ufs: amd-versal2: Use raw read/write for SLCR/CACHE registers
Update the firmware driver UFS APIs zynqmp_pm_ufs_* to directly
read/write to the pmc_iou_slcr and efuse_cache registers. Replace
these raw reads/writes with the xilinx_pm_request() API with the
correct arguments once the PM related changes are done.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ee2d1ad2e07e96f1948ab6ffe8f3c50a3b8f9be9.1742462001.git.michal.simek@amd.com
diff --git a/arch/arm/mach-versal2/include/mach/hardware.h b/arch/arm/mach-versal2/include/mach/hardware.h
index a961032..7ca2bbb 100644
--- a/arch/arm/mach-versal2/include/mach/hardware.h
+++ b/arch/arm/mach-versal2/include/mach/hardware.h
@@ -97,3 +97,9 @@
#define MIO_PIN_12 0xF1060030
#define BANK0_OUTPUT 0xF1020040
#define BANK0_TRI 0xF1060200
+
+#define PMXC_EFUSE_CACHE_BASE_ADDRESS 0xF1250000
+#define PMXC_SLCR_BASE_ADDRESS 0xF1061000
+#define PMXC_UFS_CAL_1_OFFSET 0xBE8
+#define PMXC_SRAM_CSR 0x4C
+#define PMXC_TX_RX_CFG_RDY 0x54