commit 1b107635221bafef227d863598ee6d7e19f64f57
author Jit Loon Lim <jit.loon.lim@intel.com> Fri Aug 04 10:27:12 2023 +0800
committer Jagan Teki <jagan@amarulasolutions.com> Sat Dec 09 16:39:03 2023 +0530
tree e298bd42b0451d337260acc703e1d2bae4f6f835
parent 8990e6de6ae06bf7ae5e614fe694a109c92418bd

mtd: spi-nor: Add MT25U01G part number for SPI NOR Flash

MT25QU01 OPN with 4B OPCODE support is currently not supported in
source code and the driver reuses the definition for "n25q00a"
which has the same silicon ID but is a slower part.

Adding mt25u01g definition to the source code to support a faster
read response for MT25QU01 QSPI NOR Flash device.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
[jagan: fix the id position and commit head]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

drivers/mtd/spi/spi-nor-ids.c

diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index e969421..962d404 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -318,6 +318,7 @@
 	{ INFO("n25q00",      0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 	{ INFO("n25q00a",     0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 	{ INFO("mt25ql01g",   0x21ba20, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
+	{ INFO6("mt25qu01g",  0x20bb21, 0x104400, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) },
 	{ INFO("mt25qu02g",   0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 	{ INFO("mt25ql02g",   0x20ba22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) },
 #ifdef CONFIG_SPI_FLASH_MT35XU