tree 8102d1ed2cb0ef18f642c606d4ade71219c62f64
parent 69f44b8262e30c466b83d6b514f50c1e140fbf47
author York Sun <yorksun@freescale.com> 1417547889 -0800
committer York Sun <yorksun@freescale.com> 1418663712 -0800

driver/ddr/fsl: Fix MRC_CYC calculation for DDR3

For DDR controller version 4.7 or newer, MRC_CYC (mode register set
cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD
is max(12nCK, 15ns) according to JEDEC spec.

DDR4 is not affected by this change.

Signed-off-by: York Sun <yorksun@freescale.com>