soc: soc_ti_k3: update j721e revision numbering
There is a 4 bit VARIANT number inside the JTAGID register that TI
increments any time a new variant for a chip is produced. Each
family of TI's SoCs uses a different versioning scheme based off
that VARIANT number.
CC: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c
index c8f7a57..965728e 100644
--- a/drivers/soc/soc_ti_k3.c
+++ b/drivers/soc/soc_ti_k3.c
@@ -16,9 +16,6 @@
#define AM64X 0xbb38
#define J721S2 0xbb75
-#define REV_SR1_0 0
-#define REV_SR2_0 1
-
#define JTAG_ID_VARIANT_SHIFT 28
#define JTAG_ID_VARIANT_MASK (0xf << 28)
#define JTAG_ID_PARTNO_SHIFT 12
@@ -59,25 +56,42 @@
return family;
}
+static char *j721e_rev_string_map[] = {
+ "1.0", "1.1",
+};
+
+static char *am65x_rev_string_map[] = {
+ "1.0", "2.0",
+};
+
static const char *get_rev_string(u32 idreg)
{
- const char *revision;
u32 rev;
+ u32 soc;
rev = (idreg & JTAG_ID_VARIANT_MASK) >> JTAG_ID_VARIANT_SHIFT;
+ soc = (idreg & JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
- switch (rev) {
- case REV_SR1_0:
- revision = "1.0";
- break;
- case REV_SR2_0:
- revision = "2.0";
- break;
+ switch (soc) {
+ case J721E:
+ if (rev > ARRAY_SIZE(j721e_rev_string_map))
+ goto bail;
+ return j721e_rev_string_map[rev];
+
+ case AM65X:
+ if (rev > ARRAY_SIZE(am65x_rev_string_map))
+ goto bail;
+ return am65x_rev_string_map[rev];
+
+ case AM64X:
+ case J7200:
default:
- revision = "Unknown Revision";
+ if (!rev)
+ return "1.0";
};
- return revision;
+bail:
+ return "Unknown Revision";
}
static int soc_ti_k3_get_family(struct udevice *dev, char *buf, int size)