| commit | 1a4f7cd7060233334ef95c6b04e78b04d2786327 | [log] [tgz] |
|---|---|---|
| author | Patrick Delaunay <patrick.delaunay@st.com> | Thu Apr 30 16:30:21 2020 +0200 |
| committer | Patrick Delaunay <patrick.delaunay@st.com> | Thu May 14 09:02:12 2020 +0200 |
| tree | 7ecbf62873a7a19b8327a392fcd9593b3ab7effb | |
| parent | 8e6985bbbc6c79be56e48149c27e4dee0d6a86a6 [diff] |
arm: stm32mp: activate data cache on DDR in SPL Activate cache on DDR to improve the accesses to DDR used by SPL: - CONFIG_SPL_BSS_START_ADDR - CONFIG_SYS_SPL_MALLOC_START Cache is configured only when DDR is fully initialized, to avoid speculative access and issue in get_ram_size(). Data cache is deactivated at the end of SPL, to flush the data cache and the TLB. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>