tree 0b95708c85429b59f902f501aabdcfb5cf155fb6
parent a420d7d7e993694ebd4f9b9ba8c0a2cb7d1e650e
author Jean-Jacques Hiblot <jjhiblot@ti.com> 1517324497 +0100
committer Jaehoon Chung <jh80.chung@samsung.com> 1519027134 +0900

mmc: omap_hsmmc: Reduce the max timeout for reset controller fsm

>From OMAP3 SoCs (OMAP3, OMAP4, OMAP5, AM572x, AM571x), the DAT/CMD lines
reset procedure section in TRM suggests to first poll the SRD/SRC bit
until it is set to 0x1. But looks like that bit is never set to 1 and there
is an observable delay of 1sec everytime the driver tries to reset DAT/CMD.
(The same is observed in linux kernel).

Reduce the time the driver waits for the controller to set the SRC/SRD bits
to 1 so that there is no observable delay.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>