| commit | 18d6b2d8fd86c0e3992233ece88d189e06b886e2 | [log] [tgz] |
|---|---|---|
| author | TsiChung Liew <Tsi-Chung.Liew@freescale.com> | Fri Aug 15 18:24:25 2008 +0000 |
| committer | John Rigby <jrigby@freescale.com> | Thu Aug 28 09:16:53 2008 -0600 |
| tree | ebff207846e99262f8d2fa717a2a87a96fd7adcc | |
| parent | bd05c6dac270366fe0689d14a5386c684b373327 [diff] |
ColdFire: Change the SDRAM BRD2WT timing from 3 to 7 The user manuals recommend 7. Signed-off-by: Kurt Mahan <kmahan@freescale.com> Acked-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>