commit 177fca85e47f6ef0fa5d1a88189857e2805c97f9
author Alex Porosanu <alexandru.porosanu@freescale.com> Fri Apr 29 15:17:58 2016 +0300
committer York Sun <york.sun@nxp.com> Wed May 18 08:51:46 2016 -0700
tree a187ad9403f8e304c9dd954aec3a8aad51557e08
parent 1e98bab48ab0e97116ca343b5973e0751552398a

arch/arm: add SEC JR0 offset

Freescale PPC SoCs do not hard-code security engine's Job Ring 0
address, rather a define is used. This patch adds the same
functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts)

Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

arch/arm/include/asm/arch-mx7/imx-regs.h

diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h
index a3106e7..74917f0 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -218,10 +218,13 @@
 
 #define FEC_QUIRK_ENET_MAC
 #define SNVS_LPGPR	0x68
-
-#define CONFIG_SYS_FSL_SEC_ADDR         (CAAM_IPS_BASE_ADDR)
-#define CONFIG_SYS_FSL_JR0_ADDR         (CONFIG_SYS_FSL_SEC_ADDR  + 0x1000)
-
+#define CONFIG_SYS_FSL_SEC_OFFSET       0
+#define CONFIG_SYS_FSL_SEC_ADDR         (CAAM_IPS_BASE_ADDR + \
+					 CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_OFFSET       0x1000
+#define CONFIG_SYS_FSL_JR0_ADDR         (CONFIG_SYS_FSL_SEC_ADDR + \
+					 CONFIG_SYS_FSL_JR0_OFFSET)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC   1
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/imx-common/regs-lcdif.h>
 #include <asm/types.h>