diff --git a/arch/mips/mach-jz47xx/include/mach/jz4780.h b/arch/mips/mach-jz47xx/include/mach/jz4780.h
index 4422e50..880445d 100644
--- a/arch/mips/mach-jz47xx/include/mach/jz4780.h
+++ b/arch/mips/mach-jz47xx/include/mach/jz4780.h
@@ -60,7 +60,7 @@
 
 /* PLL setup */
 #define JZ4780_SYS_EXTAL	48000000
-#define JZ4780_SYS_MEM_SPEED	(CONFIG_SYS_MHZ * 1000000)
+#define JZ4780_SYS_MEM_SPEED	(1200 * 1000000)
 #define JZ4780_SYS_MEM_DIV	3
 #define JZ4780_SYS_AUDIO_SPEED	(768 * 1000000)
 
diff --git a/arch/mips/mach-jz47xx/jz4780/pll.c b/arch/mips/mach-jz47xx/jz4780/pll.c
index 323c634..4519b47 100644
--- a/arch/mips/mach-jz47xx/jz4780/pll.c
+++ b/arch/mips/mach-jz47xx/jz4780/pll.c
@@ -399,11 +399,7 @@
 			((2 - 1) << CPM_CPCCR_L2DIV_BIT) |
 			((1 - 1) << CPM_CPCCR_CDIV_BIT);
 
-	if (CONFIG_SYS_MHZ >= 1000)
-		clk_ctrl |= (12 - 1) << CPM_CPCCR_PDIV_BIT;
-	else
-		clk_ctrl |= (6 - 1) << CPM_CPCCR_PDIV_BIT;
-
+	clk_ctrl |= (12 - 1) << CPM_CPCCR_PDIV_BIT;
 	clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl);
 
 	while (readl(cpm_regs + CPM_CPCSR) & (CPM_CPCSR_CDIV_BUSY |