| commit | 16bff1994d04ba20b01cc89dd65decd72d86c724 | [log] [tgz] |
|---|---|---|
| author | Andy Yan <andy.yan@rock-chips.com> | Tue Nov 26 21:15:39 2019 +0800 |
| committer | Kever Yang <kever.yang@rock-chips.com> | Thu Dec 05 23:53:07 2019 +0800 |
| tree | 9ebe883d2b5b3870701e0b1a3220a4bcba013b66 | |
| parent | 134eb020d0d0e9846419c642c511f0b73bd52b91 [diff] |
rockchip: px5: enable spl-fifo-mode for emmc for px5-evb We need load some parts of ATF to sram, but rockchip dwmmc controllers can't do dma to non-ddr addresses space, so set the mmc controller into fifo mode in spl. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>