diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index dd05e8b..dbe340d 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -236,6 +236,22 @@
 #define VDD_MPU_ES2_HIGH 1250
 #define VDD_MM_ES2_OD  1120
 
+/* Efuse register offsets for OMAP5 platform */
+#define OMAP5_ES2_EFUSE_BASE	0x4A002000
+#define OMAP5_ES2_PROD_REGBITS	16
+
+/* CONTROL_STD_FUSE_OPP_VDD_CORE_3 */
+#define OMAP5_ES2_PROD_CORE_OPNO_VMIN	(OMAP5_ES2_EFUSE_BASE + 0x1D8)
+
+/* CONTROL_STD_FUSE_OPP_VDD_MM_4 */
+#define OMAP5_ES2_PROD_MM_OPNO_VMIN	(OMAP5_ES2_EFUSE_BASE + 0x1A4)
+/* CONTROL_STD_FUSE_OPP_VDD_MM_5 */
+#define OMAP5_ES2_PROD_MM_OPOD_VMIN	(OMAP5_ES2_EFUSE_BASE + 0x1A8)
+/* CONTROL_STD_FUSE_OPP_VDD_MPU_6 */
+#define OMAP5_ES2_PROD_MPU_OPNO_VMIN	(OMAP5_ES2_EFUSE_BASE + 0x1C4)
+/* CONTROL_STD_FUSE_OPP_VDD_MPU_7 */
+#define OMAP5_ES2_PROD_MPU_OPHI_VMIN	(OMAP5_ES2_EFUSE_BASE + 0x1C8)
+
 /* DRA74x/75x/72x voltage settings in mv for OPP_NOM per DM */
 #define VDD_MPU_DRA7_NOM	1150
 #define VDD_CORE_DRA7_NOM	1150
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 2f005dd..b047f0d 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -224,8 +224,8 @@
 #define OMAP_ABB_GPU_TXDONE_MASK		(0x1 << 28)
 
 /* ABB efuse masks */
-#define OMAP5_ABB_FUSE_VSET_MASK		(0x1F << 24)
-#define OMAP5_ABB_FUSE_ENABLE_MASK		(0x1 << 29)
+#define OMAP5_PROD_ABB_FUSE_VSET_MASK		(0x1F << 20)
+#define OMAP5_PROD_ABB_FUSE_ENABLE_MASK		(0x1 << 25)
 #define DRA7_ABB_FUSE_VSET_MASK			(0x1F << 20)
 #define DRA7_ABB_FUSE_ENABLE_MASK		(0x1 << 25)
 #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK	(0x1 << 10)
diff --git a/arch/arm/mach-omap2/omap5/abb.c b/arch/arm/mach-omap2/omap5/abb.c
index 3bf8897..1882c49 100644
--- a/arch/arm/mach-omap2/omap5/abb.c
+++ b/arch/arm/mach-omap2/omap5/abb.c
@@ -28,8 +28,8 @@
 s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb)
 {
 	u32 vset;
-	u32 fuse_enable_mask = OMAP5_ABB_FUSE_ENABLE_MASK;
-	u32 fuse_vset_mask = OMAP5_ABB_FUSE_VSET_MASK;
+	u32 fuse_enable_mask = OMAP5_PROD_ABB_FUSE_ENABLE_MASK;
+	u32 fuse_vset_mask = OMAP5_PROD_ABB_FUSE_VSET_MASK;
 
 	if (!is_omap54xx()) {
 		/* DRA7 */
diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c
index a8a6b8a..4ad6b53 100644
--- a/arch/arm/mach-omap2/omap5/hw_data.c
+++ b/arch/arm/mach-omap2/omap5/hw_data.c
@@ -329,6 +329,15 @@
 	.mm.addr = SMPS_REG_ADDR_45_IVA,
 	.mm.pmic = &palmas,
 	.mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK,
+
+	.mpu.efuse.reg[OPP_NOM]	= OMAP5_ES2_PROD_MPU_OPNO_VMIN,
+	.mpu.efuse.reg_bits	= OMAP5_ES2_PROD_REGBITS,
+
+	.core.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_CORE_OPNO_VMIN,
+	.core.efuse.reg_bits	= OMAP5_ES2_PROD_REGBITS,
+
+	.mm.efuse.reg[OPP_NOM]	= OMAP5_ES2_PROD_MM_OPNO_VMIN,
+	.mm.efuse.reg_bits	= OMAP5_ES2_PROD_REGBITS,
 };
 
 /*