| commit | af42e2ae16d4ebd55aa55cadaefc46fdc98f37eb | [log] [tgz] |
|---|---|---|
| author | Marek Vasut <marex@denx.de> | Wed Aug 19 07:46:49 2015 +0200 |
| committer | Marek Vasut <marex@denx.de> | Sun Aug 23 11:56:21 2015 +0200 |
| tree | bfda5c57dc97c8c8f49849e572ef649ebaa2b1f5 | |
| parent | bac8895d747847ec3153d8d8ca3130b8dc498fb3 [diff] |
arm: socfpga: Fix ArriaV SoCDK PLL config Pull out the ArriaV SoCDK clock config from ancient Altera U-Boot "rel_socfpga_v2013.01.01_15.05.01_pr" and implant those values into mainline to get a booting ArriaV SoCDK. Signed-off-by: Marek Vasut <marex@denx.de>