commit 153b3e2e4adedecc37f1585ebb7bec089357781d
author Stefan Roese <sr@denx.de> Fri Oct 05 17:10:59 2007 +0200
committer Stefan Roese <sr@denx.de> Wed Oct 31 21:20:49 2007 +0100
tree 726c0998b77e26179294b8686cd005e70eb218ce
parent 136681fb621da43ac45e0c5e948b8cf66ab1240d

ppc4xx: Add PPC405EX support

Signed-off-by: Stefan Roese <sr@denx.de>

cpu/ppc4xx/cpu_init.c

diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index 351da36..afb94cc 100644
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2006
+ * (C) Copyright 2000-2007
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -112,7 +112,7 @@
 	unsigned long val;
 #endif
 
-#if defined(CONFIG_405EP)
+#if defined(CONFIG_405EP) || defined (CONFIG_405EX)
 	/*
 	 * GPIO0 setup (select GPIO or alternate function)
 	 */
@@ -128,13 +128,21 @@
 	out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
 	out32(GPIO0_TSRH, CFG_GPIO0_TSRH);	/* three-state select			*/
 	out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
+#if defined(CFG_GPIO0_ISR2H)
+	out32(GPIO0_ISR2H, CFG_GPIO0_ISR2H);
+	out32(GPIO0_ISR2L, CFG_GPIO0_ISR2L);
+#endif
+#if defined (CFG_GPIO0_TCR)
 	out32(GPIO0_TCR, CFG_GPIO0_TCR);	/* enable output driver for outputs	*/
+#endif
 
+#if defined (CONFIG_450EP)
 	/*
 	 * Set EMAC noise filter bits
 	 */
 	mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
 #endif /* CONFIG_405EP */
+#endif /* CONFIG_405EP */
 
 #if defined(CFG_440_GPIO_TABLE)
 	gpio_set_chip_configuration();
@@ -146,7 +154,7 @@
 #if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
 #if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
      defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
-     defined(CONFIG_405))
+     defined(CONFIG_405EX) || defined(CONFIG_405))
 	/*
 	 * Move the next instructions into icache, since these modify the flash
 	 * we are running from!