tree 6738dd2f648aae3e73bce28289d14b2df564ac83
parent 4c4b111530b203d0d7c8a107c6a326fcd35c1256
author Suresh Gupta <suresh.gupta@nxp.com> 1496653640 +0530
committer Jagan Teki <jagan@amarulasolutions.com> 1506334515 +0530

spi: fsl_qspi: Copy 16 byte aligned data in TX FIFO

In some of the QSPI controller version, there must be atleast
128bit data available in TX FIFO for any pop operation otherwise
error bit will be set. The code will not make any behavior change
for previous controller as the transfer data size in ipcr register
is still the same.

Patch is tested on LS1046A which do not require 16 bytes aligned and
LS1088A which require 16 bytes aligned data in TX FIFO

Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Anupam Kumar <anupam.kumar_1@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>