tree 236eb7433c2c06d3469b0bce455f1e569ef3095f
parent 1a47a48691c0ff92922f63f70eba1bd0f3699786
author Lars Povlsen <lars.povlsen@microchip.com> 1580982340 +0100
committer Daniel Schwierzeck <daniel.schwierzeck@gmail.com> 1586451359 +0200

mips: vcoreiii: Fix cache coherency issues

This patch fixes an stability issue seen on some vcoreiii targets,
which was root caused to a cache inconsistency situation.

The inconsistency was caused by having kuseg pointing to NOR area but
used as a stack/gd/heap area during initialization, while only
relatively late remapping the RAM area into kuseg position.

The fix is to initialize the DDR right after the TLB setup, and then
remapping it into position before gd/stack/heap usage.

Reported-by: Ramin Seyed-Moussavi <ramin.moussavi@yacoub.de>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Reviewed-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>