mips: vcoreiii: Fix cache coherency issues
This patch fixes an stability issue seen on some vcoreiii targets,
which was root caused to a cache inconsistency situation.
The inconsistency was caused by having kuseg pointing to NOR area but
used as a stack/gd/heap area during initialization, while only
relatively late remapping the RAM area into kuseg position.
The fix is to initialize the DDR right after the TLB setup, and then
remapping it into position before gd/stack/heap usage.
Reported-by: Ramin Seyed-Moussavi <ramin.moussavi@yacoub.de>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Reviewed-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c
index ac75d51..3ee5898 100644
--- a/arch/mips/mach-mscc/cpu.c
+++ b/arch/mips/mach-mscc/cpu.c
@@ -7,6 +7,7 @@
#include <asm/io.h>
#include <asm/types.h>
+#include <asm/mipsregs.h>
#include <mach/tlb.h>
#include <mach/ddr.h>
@@ -53,7 +54,6 @@
MMU_REGIO_RW);
#endif
-#if CONFIG_SYS_TEXT_BASE == MSCC_FLASH_TO
/*
* If U-Boot is located in NOR then we want to be able to use
* the data cache in order to boot in a decent duration
@@ -71,9 +71,10 @@
create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW,
MSCC_ATTRIB2);
- /* Enable caches by clearing the bit ERL, which is set on reset */
- write_c0_status(read_c0_status() & ~BIT(2));
-#endif /* CONFIG_SYS_TEXT_BASE */
+ /* Enable mapping (using TLB) kuseg by clearing the bit ERL,
+ * which is set on reset.
+ */
+ write_c0_status(read_c0_status() & ~ST0_ERL);
}
int mach_cpu_init(void)