commit 1463b4b4a7d0e68d790aa3d654f9f74d03e3fd56
author Andy Fleming <afleming@freescale.com> Thu Oct 30 16:50:14 2008 -0500
committer Andy Fleming <afleming@freescale.com> Mon Feb 16 18:07:43 2009 -0600
tree 2bb85a452ef20194a01d8954be714e6cc46d4e16
parent 6843a6e52fb7c8047da06ee8b9dec4a1c90a29fd

83xx: Add eSDHC support on 8379 EMDS board

Signed-off-by: Andy Fleming <afleming@freescale.com>

include/asm-ppc/immap_83xx.h

diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
index 77c09db..7b847f8 100644
--- a/include/asm-ppc/immap_83xx.h
+++ b/include/asm-ppc/immap_83xx.h
@@ -895,4 +895,6 @@
 } immap_t;
 #endif
 
+#define CONFIG_SYS_MPC83xx_ESDHC_OFFSET	(0x2e000)
+#define CONFIG_SYS_MPC83xx_ESDHC_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
 #endif				/* __IMMAP_83xx__ */

include/configs/MPC837XEMDS.h

diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 0dd6ef5..75b67b4 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -319,6 +319,9 @@
 #define CONFIG_OF_BOARD_SETUP	1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
+#define CONFIG_SYS_64BIT_STRTOUL		1
+#define CONFIG_SYS_64BIT_VSPRINTF		1
+
 /* I2C */
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
 #undef CONFIG_SOFT_I2C		/* I2C bit-banged */
@@ -502,6 +505,18 @@
 
 #undef CONFIG_WATCHDOG		/* watchdog disabled */
 
+#define CONFIG_MMC     1
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
 /*
  * Miscellaneous configurable options
  */

include/mpc83xx.h

diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 191488a..3554fdd 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -266,6 +266,7 @@
 /* SICRL bits - MPC837x specific */
 #define SICRL_USB_A			0xC0000000
 #define SICRL_USB_B			0x30000000
+#define SICRL_USB_B_SD			0x20000000
 #define SICRL_UART			0x0C000000
 #define SICRL_GPIO_A			0x02000000
 #define SICRL_GPIO_B			0x01000000
@@ -307,10 +308,12 @@
 #define SICRH_GPIO2_C			0x00002000
 #define SICRH_GPIO2_D			0x00001000
 #define SICRH_GPIO2_E			0x00000C00
+#define SICRH_GPIO2_E_SD		0x00000800
 #define SICRH_GPIO2_F			0x00000300
 #define SICRH_GPIO2_G			0x000000C0
 #define SICRH_GPIO2_H			0x00000030
 #define SICRH_SPI			0x00000003
+#define SICRH_SPI_SD			0x00000001
 #endif
 
 /* SWCRR - System Watchdog Control Register