imx8ulp_evk: Update DDR ports arbitration for DCNANO underrun
To resolve DCNANO underrun issue, change the DDR Port 0 arbitration
from round robin fashion to fixed priority level 1, while other ports
are not assigned any priority, so they will be serviced in round robin
fashion if there is no active request from Port 0.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing.c b/board/freescale/imx8ulp_evk/lpddr4_timing.c
index 1878ca5..e9edb87 100644
--- a/board/freescale/imx8ulp_evk/lpddr4_timing.c
+++ b/board/freescale/imx8ulp_evk/lpddr4_timing.c
@@ -198,8 +198,8 @@
{ 0x2e0604c8, 0x8000f00 }, /* 306 */
{ 0x2e0604cc, 0xa08 }, /* 307 */
{ 0x2e0604d0, 0x1010101 }, /* 308 */
- { 0x2e0604d4, 0x102 }, /* 309 */
- { 0x2e0604d8, 0x404 }, /* 310 */
+ { 0x2e0604d4, 0x01000102 }, /* 309 */
+ { 0x2e0604d8, 0x00000101 }, /* 310 */
{ 0x2e0604dc, 0x40400 }, /* 311 */
{ 0x2e0604e0, 0x4040000 }, /* 312 */
{ 0x2e0604e4, 0x4000000 }, /* 313 */
diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing_266.c b/board/freescale/imx8ulp_evk/lpddr4_timing_266.c
index e48cb96..9728a25 100644
--- a/board/freescale/imx8ulp_evk/lpddr4_timing_266.c
+++ b/board/freescale/imx8ulp_evk/lpddr4_timing_266.c
@@ -197,8 +197,8 @@
{ 0x2e0604c8, 0x8000f00 }, /* 306 */
{ 0x2e0604cc, 0xa08 }, /* 307 */
{ 0x2e0604d0, 0x1010101 }, /* 308 */
- { 0x2e0604d4, 0x102 }, /* 309 */
- { 0x2e0604d8, 0x404 }, /* 310 */
+ { 0x2e0604d4, 0x01000102 }, /* 309 */
+ { 0x2e0604d8, 0x00000101 }, /* 310 */
{ 0x2e0604dc, 0x40400 }, /* 311 */
{ 0x2e0604e0, 0x4040000 }, /* 312 */
{ 0x2e0604e4, 0x4000000 }, /* 313 */