tree 3aa8fc04de6bfd03c81ee07ee443bec9be07995d
parent f36e0ba2d0d86898c5646c69b113e9e28636d2ad
author Minghuan Lian <Minghuan.Lian@freescale.com> 1427433879 +0800
committer York Sun <yorksun@freescale.com> 1430756663 -0700

fsl/pci: Set CFG_READY for PCIe v3.0 and later

Freescale PCIe controllers v3.0 and later need to set bit
CFG_READY to allow all inbound configuration transactions
to be processed normally when in EP mode. However, bit
CFG_READY has been moved from PCIe configuration space to
CCSR PCIe configuration register comparing previous version.
The patch is to set this bit according to PCIe version.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>