Tegra30: Add arch-tegra30 include files
Common Tegra files are in arch-tegra, shared between T20 and T30.
Tegra30-specific headers are in arch-tegra30. Note that some of
these will be filled in as more T30 support is added (drivers,
WB/LP0 support, etc.). A couple of Tegra20 files were changed
to support common headers in arch-tegra, also.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
diff --git a/arch/arm/include/asm/arch-tegra20/funcmux.h b/arch/arm/include/asm/arch-tegra20/funcmux.h
index c986b93..1bac25e 100644
--- a/arch/arm/include/asm/arch-tegra20/funcmux.h
+++ b/arch/arm/include/asm/arch-tegra20/funcmux.h
@@ -21,8 +21,10 @@
/* Tegra20 high-level function multiplexing */
-#ifndef __FUNCMUX_H
-#define __FUNCMUX_H
+#ifndef _TEGRA20_FUNCMUX_H_
+#define _TEGRA20_FUNCMUX_H_
+
+#include <asm/arch-tegra/funcmux.h>
/* Configs supported by the func mux */
enum {
@@ -62,22 +64,4 @@
FUNCMUX_NDFLASH_ATC = 0,
FUNCMUX_NDFLASH_KBC_8_BIT,
};
-
-/**
- * Select a config for a particular peripheral.
- *
- * Each peripheral can operate through a number of configurations,
- * which are sets of pins that it uses to bring out its signals.
- * The basic config is 0, and higher numbers indicate different
- * pinmux settings to bring the peripheral out on other pins,
- *
- * This function also disables tristate for the function's pins,
- * so that they operate in normal mode.
- *
- * @param id Peripheral id
- * @param config Configuration to use (FUNCMUX_...), 0 for default
- * @return 0 if ok, -1 on error (e.g. incorrect id or config)
- */
-int funcmux_select(enum periph_id id, int config);
-
-#endif
+#endif /* _TEGRA20_FUNCMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/gp_padctrl.h b/arch/arm/include/asm/arch-tegra20/gp_padctrl.h
index 865af5b..eaaf903 100644
--- a/arch/arm/include/asm/arch-tegra20/gp_padctrl.h
+++ b/arch/arm/include/asm/arch-tegra20/gp_padctrl.h
@@ -21,8 +21,10 @@
* MA 02111-1307 USA
*/
-#ifndef _GP_PADCTRL_H_
-#define _GP_PADCTRL_H_
+#ifndef _TEGRA20_GP_PADCTRL_H_
+#define _TEGRA20_GP_PADCTRL_H_
+
+#include <asm/arch-tegra/gp_padctrl.h>
/* APB_MISC_GP and padctrl registers */
struct apb_misc_gp_ctlr {
@@ -61,13 +63,4 @@
u32 memcomp; /* 0xD4: APB_MISC_GP_MEMCOMPPADCTRL */
};
-/* bit fields definitions for APB_MISC_GP_HIDREV register */
-#define HIDREV_CHIPID_SHIFT 8
-#define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT)
-#define HIDREV_MAJORPREV_SHIFT 4
-#define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT)
-
-/* CHIPID field returned from APB_MISC_GP_HIDREV register */
-#define CHIPID_TEGRA20 0x20
-
-#endif
+#endif /* _TEGRA20_GP_PADCTRL_H_ */