| commit | aa20b3005be273426661eecd9ae6fa204a744e9a | [log] [tgz] |
|---|---|---|
| author | Swapnil Jakhade <sjakhade@cadence.com> | Fri Jan 28 13:41:44 2022 +0530 |
| committer | Tom Rini <trini@konsulko.com> | Tue Feb 08 11:00:03 2022 -0500 |
| tree | 0fe5d9dd4d0bb149f3f6fd30347d4a930b71aaea | |
| parent | 5b6b3dc7bc924bc54c02d0968455e80242dedd1f [diff] |
phy: cadence: Sierra: Add PHY PCS common register configurations Add PHY PCS common register configuration sequences for single link. Update single link PCIe register sequence accordingly. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>