drivers: pinctrl: tegra: incorporate existing code
Move all existing pinmux and funcmux code into a dedicated folder in
pinctrl to simplify further maintenance.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 547372a..b18885f 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -33,9 +33,6 @@
config TEGRA_MC
bool
-config TEGRA_PINCTRL
- bool
-
config TEGRA_PMC
bool
@@ -75,9 +72,13 @@
bool "Tegra 32-bit common options"
select BINMAN
select CPU_V7A
+ select PINCTRL
+ select PINCTRL_TEGRA
select SPL
select SPL_BOARD_INIT if SPL
select SPL_DM if SPL
+ select SPL_PINCTRL if SPL
+ select SPL_PINCTRL_TEGRA if SPL
select SPL_SKIP_LOWLEVEL_INIT_ONLY if SPL
select SPL_SYSRESET if SPL
select SUPPORT_SPL
@@ -88,7 +89,6 @@
select TEGRA_GP_PADCTRL
select TEGRA_MC
select TEGRA_NO_BPMP
- select TEGRA_PINCTRL
select TEGRA_PMC
select TEGRA_TIMER
@@ -135,6 +135,8 @@
config TEGRA210
bool "Tegra210 family"
select GICV2
+ select PINCTRL
+ select PINCTRL_TEGRA
select TIMER
select TEGRA_ARMV8_COMMON
select TEGRA_CLKRST
@@ -142,7 +144,6 @@
select TEGRA_GP_PADCTRL
select TEGRA_MC
select TEGRA_NO_BPMP
- select TEGRA_PINCTRL
select TEGRA_PMC
select TEGRA_PMC_SECURE
select TEGRA_TIMER
@@ -195,7 +196,7 @@
choice
prompt "UART to use for console"
- depends on TEGRA_PINCTRL
+ depends on PINCTRL_TEGRA
default TEGRA_ENABLE_UARTA
config TEGRA_ENABLE_UARTA
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index a5733b0..1d22dc3 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -17,7 +17,6 @@
obj-y += cache.o
obj-$(CONFIG_TEGRA_CLKRST) += clock.o
obj-$(CONFIG_$(SPL_)TEGRA_CRYPTO) += crypto.o
-obj-$(CONFIG_TEGRA_PINCTRL) += pinmux-common.o
obj-$(CONFIG_TEGRA_PMC) += powergate.o
obj-y += xusb-padctl-dummy.o
diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c
index f8b61a2..9224743 100644
--- a/arch/arm/mach-tegra/board.c
+++ b/arch/arm/mach-tegra/board.c
@@ -17,7 +17,7 @@
#if IS_ENABLED(CONFIG_TEGRA_CLKRST)
#include <asm/arch/clock.h>
#endif
-#if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
+#if CONFIG_IS_ENABLED(PINCTRL_TEGRA)
#include <asm/arch/funcmux.h>
#endif
#if IS_ENABLED(CONFIG_TEGRA_MC)
@@ -163,7 +163,7 @@
return 0;
}
-#if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
+#if CONFIG_IS_ENABLED(PINCTRL_TEGRA)
static int uart_configs[] = {
#if defined(CONFIG_TEGRA20)
#if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
@@ -235,7 +235,7 @@
void board_init_uart_f(void)
{
-#if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
+#if CONFIG_IS_ENABLED(PINCTRL_TEGRA)
int uart_ids = 0; /* bit mask of which UART ids to enable */
#ifdef CONFIG_TEGRA_ENABLE_UARTA
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 8ad76d5..adea12c 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -34,7 +34,7 @@
#if IS_ENABLED(CONFIG_TEGRA_CLKRST)
#include <asm/arch/clock.h>
#endif
-#if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
+#if CONFIG_IS_ENABLED(PINCTRL_TEGRA)
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
#endif
diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c
deleted file mode 100644
index 16b03bf..0000000
--- a/arch/arm/mach-tegra/pinmux-common.c
+++ /dev/null
@@ -1,755 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
- * Copyright (c) 2011 The Chromium OS Authors.
- */
-
-#include <common.h>
-#include <log.h>
-#include <asm/io.h>
-#include <asm/arch/pinmux.h>
-
-/* return 1 if a pingrp is in range */
-#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PMUX_PINGRP_COUNT))
-
-/* return 1 if a pmux_func is in range */
-#define pmux_func_isvalid(func) \
- (((func) >= 0) && ((func) < PMUX_FUNC_COUNT))
-
-/* return 1 if a pin_pupd_is in range */
-#define pmux_pin_pupd_isvalid(pupd) \
- (((pupd) >= PMUX_PULL_NORMAL) && ((pupd) <= PMUX_PULL_UP))
-
-/* return 1 if a pin_tristate_is in range */
-#define pmux_pin_tristate_isvalid(tristate) \
- (((tristate) >= PMUX_TRI_NORMAL) && ((tristate) <= PMUX_TRI_TRISTATE))
-
-#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
-/* return 1 if a pin_io_is in range */
-#define pmux_pin_io_isvalid(io) \
- (((io) >= PMUX_PIN_OUTPUT) && ((io) <= PMUX_PIN_INPUT))
-#endif
-
-#ifdef TEGRA_PMX_PINS_HAVE_LOCK
-/* return 1 if a pin_lock is in range */
-#define pmux_pin_lock_isvalid(lock) \
- (((lock) >= PMUX_PIN_LOCK_DISABLE) && ((lock) <= PMUX_PIN_LOCK_ENABLE))
-#endif
-
-#ifdef TEGRA_PMX_PINS_HAVE_OD
-/* return 1 if a pin_od is in range */
-#define pmux_pin_od_isvalid(od) \
- (((od) >= PMUX_PIN_OD_DISABLE) && ((od) <= PMUX_PIN_OD_ENABLE))
-#endif
-
-#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
-/* return 1 if a pin_ioreset_is in range */
-#define pmux_pin_ioreset_isvalid(ioreset) \
- (((ioreset) >= PMUX_PIN_IO_RESET_DISABLE) && \
- ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
-#endif
-
-#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
-/* return 1 if a pin_rcv_sel_is in range */
-#define pmux_pin_rcv_sel_isvalid(rcv_sel) \
- (((rcv_sel) >= PMUX_PIN_RCV_SEL_NORMAL) && \
- ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
-#endif
-
-#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
-/* return 1 if a pin_e_io_hv is in range */
-#define pmux_pin_e_io_hv_isvalid(e_io_hv) \
- (((e_io_hv) >= PMUX_PIN_E_IO_HV_NORMAL) && \
- ((e_io_hv) <= PMUX_PIN_E_IO_HV_HIGH))
-#endif
-
-#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
-#define pmux_lpmd_isvalid(lpm) \
- (((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
-#endif
-
-#if defined(TEGRA_PMX_PINS_HAVE_SCHMT) || defined(TEGRA_PMX_GRPS_HAVE_SCHMT)
-#define pmux_schmt_isvalid(schmt) \
- (((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
-#endif
-
-#if defined(TEGRA_PMX_PINS_HAVE_HSM) || defined(TEGRA_PMX_GRPS_HAVE_HSM)
-#define pmux_hsm_isvalid(hsm) \
- (((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
-#endif
-
-#define _R(offset) (u32 *)((unsigned long)NV_PA_APB_MISC_BASE + (offset))
-
-#if defined(CONFIG_TEGRA20)
-
-#define MUX_REG(grp) _R(0x80 + ((tegra_soc_pingroups[grp].ctl_id / 16) * 4))
-#define MUX_SHIFT(grp) ((tegra_soc_pingroups[grp].ctl_id % 16) * 2)
-
-#define PULL_REG(grp) _R(0xa0 + ((tegra_soc_pingroups[grp].pull_id / 16) * 4))
-#define PULL_SHIFT(grp) ((tegra_soc_pingroups[grp].pull_id % 16) * 2)
-
-#define TRI_REG(grp) _R(0x14 + (((grp) / 32) * 4))
-#define TRI_SHIFT(grp) ((grp) % 32)
-
-#else
-
-#define REG(pin) _R(0x3000 + ((pin) * 4))
-
-#define MUX_REG(pin) REG(pin)
-#define MUX_SHIFT(pin) 0
-
-#define PULL_REG(pin) REG(pin)
-#define PULL_SHIFT(pin) 2
-
-#define TRI_REG(pin) REG(pin)
-#define TRI_SHIFT(pin) 4
-
-#endif /* CONFIG_TEGRA20 */
-
-#define DRV_REG(group) _R(TEGRA_PMX_SOC_DRV_GROUP_BASE_REG + ((group) * 4))
-
-#define MIPIPADCTRL_REG(group) _R(TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG + ((group) * 4))
-
-/*
- * We could force arch-tegraNN/pinmux.h to define all of these. However,
- * that's a lot of defines, and for now it's manageable to just put a
- * special case here. It's possible this decision will change with future
- * SoCs.
- */
-#ifdef CONFIG_TEGRA210
-#define IO_SHIFT 6
-#define LOCK_SHIFT 7
-#ifdef TEGRA_PMX_PINS_HAVE_HSM
-#define HSM_SHIFT 9
-#endif
-#define E_IO_HV_SHIFT 10
-#define OD_SHIFT 11
-#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
-#define SCHMT_SHIFT 12
-#endif
-#else
-#define IO_SHIFT 5
-#define OD_SHIFT 6
-#define LOCK_SHIFT 7
-#define IO_RESET_SHIFT 8
-#define RCV_SEL_SHIFT 9
-#endif
-
-#ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING
-/* This register/field only exists on Tegra114 and later */
-#define APB_MISC_PP_PINMUX_GLOBAL_0 0x40
-#define CLAMP_INPUTS_WHEN_TRISTATED 1
-
-void pinmux_set_tristate_input_clamping(void)
-{
- u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
-
- setbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
-}
-
-void pinmux_clear_tristate_input_clamping(void)
-{
- u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
-
- clrbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
-}
-#endif
-
-void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
-{
- u32 *reg = MUX_REG(pin);
- int i, mux = -1;
- u32 val;
-
- if (func == PMUX_FUNC_DEFAULT)
- return;
-
- /* Error check on pin and func */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_func_isvalid(func));
-
- if (func >= PMUX_FUNC_RSVD1) {
- mux = (func - PMUX_FUNC_RSVD1) & 3;
- } else {
- /* Search for the appropriate function */
- for (i = 0; i < 4; i++) {
- if (tegra_soc_pingroups[pin].funcs[i] == func) {
- mux = i;
- break;
- }
- }
- }
- assert(mux != -1);
-
- val = readl(reg);
- val &= ~(3 << MUX_SHIFT(pin));
- val |= (mux << MUX_SHIFT(pin));
- writel(val, reg);
-}
-
-void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
-{
- u32 *reg = PULL_REG(pin);
- u32 val;
-
- /* Error check on pin and pupd */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_pupd_isvalid(pupd));
-
- val = readl(reg);
- val &= ~(3 << PULL_SHIFT(pin));
- val |= (pupd << PULL_SHIFT(pin));
- writel(val, reg);
-}
-
-static void pinmux_set_tristate(enum pmux_pingrp pin, int tri)
-{
- u32 *reg = TRI_REG(pin);
- u32 val;
-
- /* Error check on pin */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_tristate_isvalid(tri));
-
- val = readl(reg);
- if (tri == PMUX_TRI_TRISTATE)
- val |= (1 << TRI_SHIFT(pin));
- else
- val &= ~(1 << TRI_SHIFT(pin));
- writel(val, reg);
-}
-
-void pinmux_tristate_enable(enum pmux_pingrp pin)
-{
- pinmux_set_tristate(pin, PMUX_TRI_TRISTATE);
-}
-
-void pinmux_tristate_disable(enum pmux_pingrp pin)
-{
- pinmux_set_tristate(pin, PMUX_TRI_NORMAL);
-}
-
-#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
-void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
-{
- u32 *reg = REG(pin);
- u32 val;
-
- if (io == PMUX_PIN_NONE)
- return;
-
- /* Error check on pin and io */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_io_isvalid(io));
-
- val = readl(reg);
- if (io == PMUX_PIN_INPUT)
- val |= (io & 1) << IO_SHIFT;
- else
- val &= ~(1 << IO_SHIFT);
- writel(val, reg);
-}
-#endif
-
-#ifdef TEGRA_PMX_PINS_HAVE_LOCK
-static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
-{
- u32 *reg = REG(pin);
- u32 val;
-
- if (lock == PMUX_PIN_LOCK_DEFAULT)
- return;
-
- /* Error check on pin and lock */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_lock_isvalid(lock));
-
- val = readl(reg);
- if (lock == PMUX_PIN_LOCK_ENABLE) {
- val |= (1 << LOCK_SHIFT);
- } else {
- if (val & (1 << LOCK_SHIFT))
- printf("%s: Cannot clear LOCK bit!\n", __func__);
- val &= ~(1 << LOCK_SHIFT);
- }
- writel(val, reg);
-
- return;
-}
-#endif
-
-#ifdef TEGRA_PMX_PINS_HAVE_OD
-static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
-{
- u32 *reg = REG(pin);
- u32 val;
-
- if (od == PMUX_PIN_OD_DEFAULT)
- return;
-
- /* Error check on pin and od */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_od_isvalid(od));
-
- val = readl(reg);
- if (od == PMUX_PIN_OD_ENABLE)
- val |= (1 << OD_SHIFT);
- else
- val &= ~(1 << OD_SHIFT);
- writel(val, reg);
-
- return;
-}
-#endif
-
-#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
-static void pinmux_set_ioreset(enum pmux_pingrp pin,
- enum pmux_pin_ioreset ioreset)
-{
- u32 *reg = REG(pin);
- u32 val;
-
- if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
- return;
-
- /* Error check on pin and ioreset */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_ioreset_isvalid(ioreset));
-
- val = readl(reg);
- if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
- val |= (1 << IO_RESET_SHIFT);
- else
- val &= ~(1 << IO_RESET_SHIFT);
- writel(val, reg);
-
- return;
-}
-#endif
-
-#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
-static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
- enum pmux_pin_rcv_sel rcv_sel)
-{
- u32 *reg = REG(pin);
- u32 val;
-
- if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
- return;
-
- /* Error check on pin and rcv_sel */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
-
- val = readl(reg);
- if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
- val |= (1 << RCV_SEL_SHIFT);
- else
- val &= ~(1 << RCV_SEL_SHIFT);
- writel(val, reg);
-
- return;
-}
-#endif
-
-#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
-static void pinmux_set_e_io_hv(enum pmux_pingrp pin,
- enum pmux_pin_e_io_hv e_io_hv)
-{
- u32 *reg = REG(pin);
- u32 val;
-
- if (e_io_hv == PMUX_PIN_E_IO_HV_DEFAULT)
- return;
-
- /* Error check on pin and e_io_hv */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_e_io_hv_isvalid(e_io_hv));
-
- val = readl(reg);
- if (e_io_hv == PMUX_PIN_E_IO_HV_HIGH)
- val |= (1 << E_IO_HV_SHIFT);
- else
- val &= ~(1 << E_IO_HV_SHIFT);
- writel(val, reg);
-
- return;
-}
-#endif
-
-#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
-static void pinmux_set_schmt(enum pmux_pingrp pin, enum pmux_schmt schmt)
-{
- u32 *reg = REG(grp);
- u32 val;
-
- /* NONE means unspecified/do not change/use POR value */
- if (schmt == PMUX_SCHMT_NONE)
- return;
-
- /* Error check pad */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_schmt_isvalid(schmt));
-
- val = readl(reg);
- if (schmt == PMUX_SCHMT_ENABLE)
- val |= (1 << SCHMT_SHIFT);
- else
- val &= ~(1 << SCHMT_SHIFT);
- writel(val, reg);
-
- return;
-}
-#endif
-
-#ifdef TEGRA_PMX_PINS_HAVE_HSM
-static void pinmux_set_hsm(enum pmux_pingrp pin, enum pmux_hsm hsm)
-{
- u32 *reg = REG(grp);
- u32 val;
-
- /* NONE means unspecified/do not change/use POR value */
- if (hsm == PMUX_HSM_NONE)
- return;
-
- /* Error check pad */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_hsm_isvalid(hsm));
-
- val = readl(reg);
- if (hsm == PMUX_HSM_ENABLE)
- val |= (1 << HSM_SHIFT);
- else
- val &= ~(1 << HSM_SHIFT);
- writel(val, reg);
-
- return;
-}
-#endif
-
-static void pinmux_config_pingrp(const struct pmux_pingrp_config *config)
-{
- enum pmux_pingrp pin = config->pingrp;
-
- pinmux_set_func(pin, config->func);
- pinmux_set_pullupdown(pin, config->pull);
- pinmux_set_tristate(pin, config->tristate);
-#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
- pinmux_set_io(pin, config->io);
-#endif
-#ifdef TEGRA_PMX_PINS_HAVE_LOCK
- pinmux_set_lock(pin, config->lock);
-#endif
-#ifdef TEGRA_PMX_PINS_HAVE_OD
- pinmux_set_od(pin, config->od);
-#endif
-#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
- pinmux_set_ioreset(pin, config->ioreset);
-#endif
-#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
- pinmux_set_rcv_sel(pin, config->rcv_sel);
-#endif
-#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
- pinmux_set_e_io_hv(pin, config->e_io_hv);
-#endif
-#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
- pinmux_set_schmt(pin, config->schmt);
-#endif
-#ifdef TEGRA_PMX_PINS_HAVE_HSM
- pinmux_set_hsm(pin, config->hsm);
-#endif
-}
-
-void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
- int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- pinmux_config_pingrp(&config[i]);
-}
-
-#ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
-
-#define pmux_drvgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_DRVGRP_COUNT))
-
-#define pmux_slw_isvalid(slw) \
- (((slw) >= PMUX_SLWF_MIN) && ((slw) <= PMUX_SLWF_MAX))
-
-#define pmux_drv_isvalid(drv) \
- (((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX))
-
-#ifdef TEGRA_PMX_GRPS_HAVE_HSM
-#define HSM_SHIFT 2
-#endif
-#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
-#define SCHMT_SHIFT 3
-#endif
-#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
-#define LPMD_SHIFT 4
-#define LPMD_MASK (3 << LPMD_SHIFT)
-#endif
-/*
- * Note that the following DRV* and SLW* defines are accurate for many drive
- * groups on many SoCs. We really need a per-group data structure to solve
- * this, since the fields are in different positions/sizes in different
- * registers (for different groups).
- *
- * On Tegra30/114/124, the DRV*_SHIFT values vary.
- * On Tegra30, the SLW*_SHIFT values vary.
- * On Tegra30/114/124/210, the DRV*_MASK values vary, although the values
- * below are wide enough to cover the widest fields, and hopefully don't
- * interfere with any other fields.
- * On Tegra30, the SLW*_MASK values vary, but we can't use a value that's
- * wide enough to cover all cases, since that would cause the field to
- * overlap with other fields in the narrower cases.
- */
-#define DRVDN_SHIFT 12
-#define DRVDN_MASK (0x7F << DRVDN_SHIFT)
-#define DRVUP_SHIFT 20
-#define DRVUP_MASK (0x7F << DRVUP_SHIFT)
-#define SLWR_SHIFT 28
-#define SLWR_MASK (3 << SLWR_SHIFT)
-#define SLWF_SHIFT 30
-#define SLWF_MASK (3 << SLWF_SHIFT)
-
-static void pinmux_set_drvup_slwf(enum pmux_drvgrp grp, int slwf)
-{
- u32 *reg = DRV_REG(grp);
- u32 val;
-
- /* NONE means unspecified/do not change/use POR value */
- if (slwf == PMUX_SLWF_NONE)
- return;
-
- /* Error check on pad and slwf */
- assert(pmux_drvgrp_isvalid(grp));
- assert(pmux_slw_isvalid(slwf));
-
- val = readl(reg);
- val &= ~SLWF_MASK;
- val |= (slwf << SLWF_SHIFT);
- writel(val, reg);
-
- return;
-}
-
-static void pinmux_set_drvdn_slwr(enum pmux_drvgrp grp, int slwr)
-{
- u32 *reg = DRV_REG(grp);
- u32 val;
-
- /* NONE means unspecified/do not change/use POR value */
- if (slwr == PMUX_SLWR_NONE)
- return;
-
- /* Error check on pad and slwr */
- assert(pmux_drvgrp_isvalid(grp));
- assert(pmux_slw_isvalid(slwr));
-
- val = readl(reg);
- val &= ~SLWR_MASK;
- val |= (slwr << SLWR_SHIFT);
- writel(val, reg);
-
- return;
-}
-
-static void pinmux_set_drvup(enum pmux_drvgrp grp, int drvup)
-{
- u32 *reg = DRV_REG(grp);
- u32 val;
-
- /* NONE means unspecified/do not change/use POR value */
- if (drvup == PMUX_DRVUP_NONE)
- return;
-
- /* Error check on pad and drvup */
- assert(pmux_drvgrp_isvalid(grp));
- assert(pmux_drv_isvalid(drvup));
-
- val = readl(reg);
- val &= ~DRVUP_MASK;
- val |= (drvup << DRVUP_SHIFT);
- writel(val, reg);
-
- return;
-}
-
-static void pinmux_set_drvdn(enum pmux_drvgrp grp, int drvdn)
-{
- u32 *reg = DRV_REG(grp);
- u32 val;
-
- /* NONE means unspecified/do not change/use POR value */
- if (drvdn == PMUX_DRVDN_NONE)
- return;
-
- /* Error check on pad and drvdn */
- assert(pmux_drvgrp_isvalid(grp));
- assert(pmux_drv_isvalid(drvdn));
-
- val = readl(reg);
- val &= ~DRVDN_MASK;
- val |= (drvdn << DRVDN_SHIFT);
- writel(val, reg);
-
- return;
-}
-
-#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
-static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd)
-{
- u32 *reg = DRV_REG(grp);
- u32 val;
-
- /* NONE means unspecified/do not change/use POR value */
- if (lpmd == PMUX_LPMD_NONE)
- return;
-
- /* Error check pad and lpmd value */
- assert(pmux_drvgrp_isvalid(grp));
- assert(pmux_lpmd_isvalid(lpmd));
-
- val = readl(reg);
- val &= ~LPMD_MASK;
- val |= (lpmd << LPMD_SHIFT);
- writel(val, reg);
-
- return;
-}
-#endif
-
-#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
-static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt)
-{
- u32 *reg = DRV_REG(grp);
- u32 val;
-
- /* NONE means unspecified/do not change/use POR value */
- if (schmt == PMUX_SCHMT_NONE)
- return;
-
- /* Error check pad */
- assert(pmux_drvgrp_isvalid(grp));
- assert(pmux_schmt_isvalid(schmt));
-
- val = readl(reg);
- if (schmt == PMUX_SCHMT_ENABLE)
- val |= (1 << SCHMT_SHIFT);
- else
- val &= ~(1 << SCHMT_SHIFT);
- writel(val, reg);
-
- return;
-}
-#endif
-
-#ifdef TEGRA_PMX_GRPS_HAVE_HSM
-static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm)
-{
- u32 *reg = DRV_REG(grp);
- u32 val;
-
- /* NONE means unspecified/do not change/use POR value */
- if (hsm == PMUX_HSM_NONE)
- return;
-
- /* Error check pad */
- assert(pmux_drvgrp_isvalid(grp));
- assert(pmux_hsm_isvalid(hsm));
-
- val = readl(reg);
- if (hsm == PMUX_HSM_ENABLE)
- val |= (1 << HSM_SHIFT);
- else
- val &= ~(1 << HSM_SHIFT);
- writel(val, reg);
-
- return;
-}
-#endif
-
-static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config)
-{
- enum pmux_drvgrp grp = config->drvgrp;
-
- pinmux_set_drvup_slwf(grp, config->slwf);
- pinmux_set_drvdn_slwr(grp, config->slwr);
- pinmux_set_drvup(grp, config->drvup);
- pinmux_set_drvdn(grp, config->drvdn);
-#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
- pinmux_set_lpmd(grp, config->lpmd);
-#endif
-#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
- pinmux_set_schmt(grp, config->schmt);
-#endif
-#ifdef TEGRA_PMX_GRPS_HAVE_HSM
- pinmux_set_hsm(grp, config->hsm);
-#endif
-}
-
-void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
- int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- pinmux_config_drvgrp(&config[i]);
-}
-#endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */
-
-#ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS
-
-#define pmux_mipipadctrlgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_MIPIPADCTRLGRP_COUNT))
-
-static void pinmux_mipipadctrl_set_func(enum pmux_mipipadctrlgrp grp,
- enum pmux_func func)
-{
- u32 *reg = MIPIPADCTRL_REG(grp);
- int i, mux = -1;
- u32 val;
-
- if (func == PMUX_FUNC_DEFAULT)
- return;
-
- /* Error check grp and func */
- assert(pmux_mipipadctrlgrp_isvalid(grp));
- assert(pmux_func_isvalid(func));
-
- if (func >= PMUX_FUNC_RSVD1) {
- mux = (func - PMUX_FUNC_RSVD1) & 1;
- } else {
- /* Search for the appropriate function */
- for (i = 0; i < 2; i++) {
- if (tegra_soc_mipipadctrl_groups[grp].funcs[i]
- == func) {
- mux = i;
- break;
- }
- }
- }
- assert(mux != -1);
-
- val = readl(reg);
- val &= ~(1 << 1);
- val |= (mux << 1);
- writel(val, reg);
-}
-
-static void pinmux_config_mipipadctrlgrp(const struct pmux_mipipadctrlgrp_config *config)
-{
- enum pmux_mipipadctrlgrp grp = config->grp;
-
- pinmux_mipipadctrl_set_func(grp, config->func);
-}
-
-void pinmux_config_mipipadctrlgrp_table(
- const struct pmux_mipipadctrlgrp_config *config, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- pinmux_config_mipipadctrlgrp(&config[i]);
-}
-#endif /* TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS */
diff --git a/arch/arm/mach-tegra/tegra114/Makefile b/arch/arm/mach-tegra/tegra114/Makefile
index 0e8f32c..346d6cb 100644
--- a/arch/arm/mach-tegra/tegra114/Makefile
+++ b/arch/arm/mach-tegra/tegra114/Makefile
@@ -4,4 +4,4 @@
obj-$(CONFIG_SPL_BUILD) += cpu.o
-obj-y += clock.o funcmux.o pinmux.o
+obj-y += clock.o
diff --git a/arch/arm/mach-tegra/tegra114/funcmux.c b/arch/arm/mach-tegra/tegra114/funcmux.c
deleted file mode 100644
index 23a27c8..0000000
--- a/arch/arm/mach-tegra/tegra114/funcmux.c
+++ /dev/null
@@ -1,57 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
- */
-
-/* Tegra114 high-level function multiplexing */
-
-#include <common.h>
-#include <log.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/funcmux.h>
-#include <asm/arch/pinmux.h>
-
-int funcmux_select(enum periph_id id, int config)
-{
- int bad_config = config != FUNCMUX_DEFAULT;
-
- switch (id) {
- case PERIPH_ID_UART4:
- switch (config) {
- case FUNCMUX_UART4_GMI:
- pinmux_set_func(PMUX_PINGRP_GMI_A16_PJ7,
- PMUX_FUNC_UARTD);
- pinmux_set_func(PMUX_PINGRP_GMI_A17_PB0,
- PMUX_FUNC_UARTD);
- pinmux_set_func(PMUX_PINGRP_GMI_A18_PB1,
- PMUX_FUNC_UARTD);
- pinmux_set_func(PMUX_PINGRP_GMI_A19_PK7,
- PMUX_FUNC_UARTD);
-
- pinmux_set_io(PMUX_PINGRP_GMI_A16_PJ7, PMUX_PIN_OUTPUT);
- pinmux_set_io(PMUX_PINGRP_GMI_A17_PB0, PMUX_PIN_INPUT);
- pinmux_set_io(PMUX_PINGRP_GMI_A18_PB1, PMUX_PIN_INPUT);
- pinmux_set_io(PMUX_PINGRP_GMI_A19_PK7, PMUX_PIN_OUTPUT);
-
- pinmux_tristate_disable(PMUX_PINGRP_GMI_A16_PJ7);
- pinmux_tristate_disable(PMUX_PINGRP_GMI_A17_PB0);
- pinmux_tristate_disable(PMUX_PINGRP_GMI_A18_PB1);
- pinmux_tristate_disable(PMUX_PINGRP_GMI_A19_PK7);
- break;
- }
- break;
-
- /* Add other periph IDs here as needed */
-
- default:
- debug("%s: invalid periph_id %d", __func__, id);
- return -1;
- }
-
- if (bad_config) {
- debug("%s: invalid config %d for periph_id %d", __func__,
- config, id);
- return -1;
- }
- return 0;
-}
diff --git a/arch/arm/mach-tegra/tegra114/pinmux.c b/arch/arm/mach-tegra/tegra114/pinmux.c
deleted file mode 100644
index 1179660..0000000
--- a/arch/arm/mach-tegra/tegra114/pinmux.c
+++ /dev/null
@@ -1,292 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/pinmux.h>
-
-#define PIN(pin, f0, f1, f2, f3) \
- { \
- .funcs = { \
- PMUX_FUNC_##f0, \
- PMUX_FUNC_##f1, \
- PMUX_FUNC_##f2, \
- PMUX_FUNC_##f3, \
- }, \
- }
-
-#define PIN_RESERVED {}
-
-static const struct pmux_pingrp_desc tegra114_pingroups[] = {
- /* pin, f0, f1, f2, f3 */
- /* Offset 0x3000 */
- PIN(ULPI_DATA0_PO1, SPI3, HSI, UARTA, ULPI),
- PIN(ULPI_DATA1_PO2, SPI3, HSI, UARTA, ULPI),
- PIN(ULPI_DATA2_PO3, SPI3, HSI, UARTA, ULPI),
- PIN(ULPI_DATA3_PO4, SPI3, HSI, UARTA, ULPI),
- PIN(ULPI_DATA4_PO5, SPI2, HSI, UARTA, ULPI),
- PIN(ULPI_DATA5_PO6, SPI2, HSI, UARTA, ULPI),
- PIN(ULPI_DATA6_PO7, SPI2, HSI, UARTA, ULPI),
- PIN(ULPI_DATA7_PO0, SPI2, HSI, UARTA, ULPI),
- PIN(ULPI_CLK_PY0, SPI1, SPI5, UARTD, ULPI),
- PIN(ULPI_DIR_PY1, SPI1, SPI5, UARTD, ULPI),
- PIN(ULPI_NXT_PY2, SPI1, SPI5, UARTD, ULPI),
- PIN(ULPI_STP_PY3, SPI1, SPI5, UARTD, ULPI),
- PIN(DAP3_FS_PP0, I2S2, SPI5, DISPLAYA, DISPLAYB),
- PIN(DAP3_DIN_PP1, I2S2, SPI5, DISPLAYA, DISPLAYB),
- PIN(DAP3_DOUT_PP2, I2S2, SPI5, DISPLAYA, DISPLAYB),
- PIN(DAP3_SCLK_PP3, I2S2, SPI5, DISPLAYA, DISPLAYB),
- PIN(PV0, USB, RSVD2, RSVD3, RSVD4),
- PIN(PV1, RSVD1, RSVD2, RSVD3, RSVD4),
- PIN(SDMMC1_CLK_PZ0, SDMMC1, CLK12, RSVD3, RSVD4),
- PIN(SDMMC1_CMD_PZ1, SDMMC1, SPDIF, SPI4, UARTA),
- PIN(SDMMC1_DAT3_PY4, SDMMC1, SPDIF, SPI4, UARTA),
- PIN(SDMMC1_DAT2_PY5, SDMMC1, PWM0, SPI4, UARTA),
- PIN(SDMMC1_DAT1_PY6, SDMMC1, PWM1, SPI4, UARTA),
- PIN(SDMMC1_DAT0_PY7, SDMMC1, RSVD2, SPI4, UARTA),
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x3068 */
- PIN(CLK2_OUT_PW5, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
- PIN(CLK2_REQ_PCC5, DAP, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x3110 */
- PIN(HDMI_INT_PN7, RSVD1, RSVD2, RSVD3, RSVD4),
- PIN(DDC_SCL_PV4, I2C4, RSVD2, RSVD3, RSVD4),
- PIN(DDC_SDA_PV5, I2C4, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x3164 */
- PIN(UART2_RXD_PC3, IRDA, SPDIF, UARTA, SPI4),
- PIN(UART2_TXD_PC2, IRDA, SPDIF, UARTA, SPI4),
- PIN(UART2_RTS_N_PJ6, UARTA, UARTB, RSVD3, SPI4),
- PIN(UART2_CTS_N_PJ5, UARTA, UARTB, RSVD3, SPI4),
- PIN(UART3_TXD_PW6, UARTC, RSVD2, RSVD3, SPI4),
- PIN(UART3_RXD_PW7, UARTC, RSVD2, RSVD3, SPI4),
- PIN(UART3_CTS_N_PA1, UARTC, SDMMC1, DTV, SPI4),
- PIN(UART3_RTS_N_PC0, UARTC, PWM0, DTV, DISPLAYA),
- PIN(PU0, OWR, UARTA, RSVD3, RSVD4),
- PIN(PU1, RSVD1, UARTA, RSVD3, RSVD4),
- PIN(PU2, RSVD1, UARTA, RSVD3, RSVD4),
- PIN(PU3, PWM0, UARTA, DISPLAYA, DISPLAYB),
- PIN(PU4, PWM1, UARTA, DISPLAYA, DISPLAYB),
- PIN(PU5, PWM2, UARTA, DISPLAYA, DISPLAYB),
- PIN(PU6, PWM3, UARTA, USB, DISPLAYB),
- PIN(GEN1_I2C_SDA_PC5, I2C1, RSVD2, RSVD3, RSVD4),
- PIN(GEN1_I2C_SCL_PC4, I2C1, RSVD2, RSVD3, RSVD4),
- PIN(DAP4_FS_PP4, I2S3, RSVD2, DTV, RSVD4),
- PIN(DAP4_DIN_PP5, I2S3, RSVD2, RSVD3, RSVD4),
- PIN(DAP4_DOUT_PP6, I2S3, RSVD2, DTV, RSVD4),
- PIN(DAP4_SCLK_PP7, I2S3, RSVD2, RSVD3, RSVD4),
- PIN(CLK3_OUT_PEE0, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
- PIN(CLK3_REQ_PEE1, DEV3, RSVD2, RSVD3, RSVD4),
- PIN(GMI_WP_N_PC7, RSVD1, NAND, GMI, GMI_ALT),
- PIN(GMI_IORDY_PI5, SDMMC2, RSVD2, GMI, TRACE),
- PIN(GMI_WAIT_PI7, SPI4, NAND, GMI, DTV),
- PIN(GMI_ADV_N_PK0, RSVD1, NAND, GMI, TRACE),
- PIN(GMI_CLK_PK1, SDMMC2, NAND, GMI, TRACE),
- PIN(GMI_CS0_N_PJ0, RSVD1, NAND, GMI, USB),
- PIN(GMI_CS1_N_PJ2, RSVD1, NAND, GMI, SOC),
- PIN(GMI_CS2_N_PK3, SDMMC2, NAND, GMI, TRACE),
- PIN(GMI_CS3_N_PK4, SDMMC2, NAND, GMI, GMI_ALT),
- PIN(GMI_CS4_N_PK2, USB, NAND, GMI, TRACE),
- PIN(GMI_CS6_N_PI3, NAND, NAND_ALT, GMI, SPI4),
- PIN(GMI_CS7_N_PI6, NAND, NAND_ALT, GMI, SDMMC2),
- PIN(GMI_AD0_PG0, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD1_PG1, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD2_PG2, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD3_PG3, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD4_PG4, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD5_PG5, RSVD1, NAND, GMI, SPI4),
- PIN(GMI_AD6_PG6, RSVD1, NAND, GMI, SPI4),
- PIN(GMI_AD7_PG7, RSVD1, NAND, GMI, SPI4),
- PIN(GMI_AD8_PH0, PWM0, NAND, GMI, DTV),
- PIN(GMI_AD9_PH1, PWM1, NAND, GMI, CLDVFS),
- PIN(GMI_AD10_PH2, PWM2, NAND, GMI, CLDVFS),
- PIN(GMI_AD11_PH3, PWM3, NAND, GMI, USB),
- PIN(GMI_AD12_PH4, SDMMC2, NAND, GMI, RSVD4),
- PIN(GMI_AD13_PH5, SDMMC2, NAND, GMI, RSVD4),
- PIN(GMI_AD14_PH6, SDMMC2, NAND, GMI, DTV),
- PIN(GMI_AD15_PH7, SDMMC2, NAND, GMI, DTV),
- PIN(GMI_A16_PJ7, UARTD, TRACE, GMI, GMI_ALT),
- PIN(GMI_A17_PB0, UARTD, RSVD2, GMI, TRACE),
- PIN(GMI_A18_PB1, UARTD, RSVD2, GMI, TRACE),
- PIN(GMI_A19_PK7, UARTD, SPI4, GMI, TRACE),
- PIN(GMI_WR_N_PI0, RSVD1, NAND, GMI, SPI4),
- PIN(GMI_OE_N_PI1, RSVD1, NAND, GMI, SOC),
- PIN(GMI_DQS_P_PJ3, SDMMC2, NAND, GMI, TRACE),
- PIN(GMI_RST_N_PI4, NAND, NAND_ALT, GMI, RSVD4),
- PIN(GEN2_I2C_SCL_PT5, I2C2, RSVD2, GMI, RSVD4),
- PIN(GEN2_I2C_SDA_PT6, I2C2, RSVD2, GMI, RSVD4),
- PIN(SDMMC4_CLK_PCC4, SDMMC4, RSVD2, GMI, RSVD4),
- PIN(SDMMC4_CMD_PT7, SDMMC4, RSVD2, GMI, RSVD4),
- PIN(SDMMC4_DAT0_PAA0, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT1_PAA1, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT2_PAA2, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT3_PAA3, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT4_PAA4, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT5_PAA5, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT6_PAA6, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT7_PAA7, SDMMC4, RSVD2, GMI, RSVD4),
- PIN_RESERVED,
- /* Offset 0x3284 */
- PIN(CAM_MCLK_PCC0, VI, VI_ALT1, VI_ALT3, RSVD4),
- PIN(PCC1, I2S4, RSVD2, RSVD3, RSVD4),
- PIN(PBB0, I2S4, VI, VI_ALT1, VI_ALT3),
- PIN(CAM_I2C_SCL_PBB1, VGP1, I2C3, RSVD3, RSVD4),
- PIN(CAM_I2C_SDA_PBB2, VGP2, I2C3, RSVD3, RSVD4),
- PIN(PBB3, VGP3, DISPLAYA, DISPLAYB, RSVD4),
- PIN(PBB4, VGP4, DISPLAYA, DISPLAYB, RSVD4),
- PIN(PBB5, VGP5, DISPLAYA, DISPLAYB, RSVD4),
- PIN(PBB6, VGP6, DISPLAYA, DISPLAYB, RSVD4),
- PIN(PBB7, I2S4, RSVD2, RSVD3, RSVD4),
- PIN(PCC2, I2S4, RSVD2, RSVD3, RSVD4),
- PIN(JTAG_RTCK, RTCK, RSVD2, RSVD3, RSVD4),
- PIN(PWR_I2C_SCL_PZ6, I2CPWR, RSVD2, RSVD3, RSVD4),
- PIN(PWR_I2C_SDA_PZ7, I2CPWR, RSVD2, RSVD3, RSVD4),
- PIN(KB_ROW0_PR0, KBC, RSVD2, RSVD3, RSVD4),
- PIN(KB_ROW1_PR1, KBC, RSVD2, RSVD3, RSVD4),
- PIN(KB_ROW2_PR2, KBC, RSVD2, RSVD3, RSVD4),
- PIN(KB_ROW3_PR3, KBC, DISPLAYA, RSVD3, DISPLAYB),
- PIN(KB_ROW4_PR4, KBC, DISPLAYA, SPI2, DISPLAYB),
- PIN(KB_ROW5_PR5, KBC, DISPLAYA, SPI2, DISPLAYB),
- PIN(KB_ROW6_PR6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB),
- PIN(KB_ROW7_PR7, KBC, RSVD2, CLDVFS, UARTA),
- PIN(KB_ROW8_PS0, KBC, RSVD2, CLDVFS, UARTA),
- PIN(KB_ROW9_PS1, KBC, RSVD2, RSVD3, UARTA),
- PIN(KB_ROW10_PS2, KBC, RSVD2, RSVD3, UARTA),
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x32fc */
- PIN(KB_COL0_PQ0, KBC, USB, SPI2, EMC_DLL),
- PIN(KB_COL1_PQ1, KBC, RSVD2, SPI2, EMC_DLL),
- PIN(KB_COL2_PQ2, KBC, RSVD2, SPI2, RSVD4),
- PIN(KB_COL3_PQ3, KBC, DISPLAYA, PWM2, UARTA),
- PIN(KB_COL4_PQ4, KBC, OWR, SDMMC3, UARTA),
- PIN(KB_COL5_PQ5, KBC, RSVD2, SDMMC1, RSVD4),
- PIN(KB_COL6_PQ6, KBC, RSVD2, SPI2, RSVD4),
- PIN(KB_COL7_PQ7, KBC, RSVD2, SPI2, RSVD4),
- PIN(CLK_32K_OUT_PA0, BLINK, SOC, RSVD3, RSVD4),
- PIN(SYS_CLK_REQ_PZ5, SYSCLK, RSVD2, RSVD3, RSVD4),
- PIN(CORE_PWR_REQ, PWRON, RSVD2, RSVD3, RSVD4),
- PIN(CPU_PWR_REQ, CPU, RSVD2, RSVD3, RSVD4),
- PIN(PWR_INT_N, PMI, RSVD2, RSVD3, RSVD4),
- PIN(CLK_32K_IN, CLK, RSVD2, RSVD3, RSVD4),
- PIN(OWR, OWR, RSVD2, RSVD3, RSVD4),
- PIN(DAP1_FS_PN0, I2S0, HDA, GMI, RSVD4),
- PIN(DAP1_DIN_PN1, I2S0, HDA, GMI, RSVD4),
- PIN(DAP1_DOUT_PN2, I2S0, HDA, GMI, RSVD4),
- PIN(DAP1_SCLK_PN3, I2S0, HDA, GMI, RSVD4),
- PIN(CLK1_REQ_PEE2, DAP, DAP1, RSVD3, RSVD4),
- PIN(CLK1_OUT_PW4, EXTPERIPH1, DAP2, RSVD3, RSVD4),
- PIN(SPDIF_IN_PK6, SPDIF, USB, RSVD3, RSVD4),
- PIN(SPDIF_OUT_PK5, SPDIF, RSVD2, RSVD3, RSVD4),
- PIN(DAP2_FS_PA2, I2S1, HDA, RSVD3, RSVD4),
- PIN(DAP2_DIN_PA4, I2S1, HDA, RSVD3, RSVD4),
- PIN(DAP2_DOUT_PA5, I2S1, HDA, RSVD3, RSVD4),
- PIN(DAP2_SCLK_PA3, I2S1, HDA, RSVD3, RSVD4),
- PIN(DVFS_PWM_PX0, SPI6, CLDVFS, RSVD3, RSVD4),
- PIN(GPIO_X1_AUD_PX1, SPI6, RSVD2, RSVD3, RSVD4),
- PIN(GPIO_X3_AUD_PX3, SPI6, SPI1, RSVD3, RSVD4),
- PIN(DVFS_CLK_PX2, SPI6, CLDVFS, RSVD3, RSVD4),
- PIN(GPIO_X4_AUD_PX4, RSVD1, SPI1, SPI2, DAP2),
- PIN(GPIO_X5_AUD_PX5, RSVD1, SPI1, SPI2, RSVD4),
- PIN(GPIO_X6_AUD_PX6, SPI6, SPI1, SPI2, RSVD4),
- PIN(GPIO_X7_AUD_PX7, RSVD1, SPI1, SPI2, RSVD4),
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x3390 */
- PIN(SDMMC3_CLK_PA6, SDMMC3, RSVD2, RSVD3, SPI3),
- PIN(SDMMC3_CMD_PA7, SDMMC3, PWM3, UARTA, SPI3),
- PIN(SDMMC3_DAT0_PB7, SDMMC3, RSVD2, RSVD3, SPI3),
- PIN(SDMMC3_DAT1_PB6, SDMMC3, PWM2, UARTA, SPI3),
- PIN(SDMMC3_DAT2_PB5, SDMMC3, PWM1, DISPLAYA, SPI3),
- PIN(SDMMC3_DAT3_PB4, SDMMC3, PWM0, DISPLAYB, SPI3),
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x33e0 */
- PIN(HDMI_CEC_PEE3, CEC, SDMMC3, RSVD3, SOC),
- PIN(SDMMC1_WP_N_PV3, SDMMC1, CLK12, SPI4, UARTA),
- PIN(SDMMC3_CD_N_PV2, SDMMC3, OWR, RSVD3, RSVD4),
- PIN(GPIO_W2_AUD_PW2, SPI6, RSVD2, SPI2, I2C1),
- PIN(GPIO_W3_AUD_PW3, SPI6, SPI1, SPI2, I2C1),
- PIN(USB_VBUS_EN0_PN4, USB, RSVD2, RSVD3, RSVD4),
- PIN(USB_VBUS_EN1_PN5, USB, RSVD2, RSVD3, RSVD4),
- PIN(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, RSVD2, RSVD3, RSVD4),
- PIN(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, RSVD2, RSVD3, RSVD4),
- PIN(GMI_CLK_LB, SDMMC2, NAND, GMI, RSVD4),
- PIN(RESET_OUT_N, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
-};
-const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra114_pingroups;
diff --git a/arch/arm/mach-tegra/tegra124/Makefile b/arch/arm/mach-tegra/tegra124/Makefile
index d275daf..6ea511e 100644
--- a/arch/arm/mach-tegra/tegra124/Makefile
+++ b/arch/arm/mach-tegra/tegra124/Makefile
@@ -8,8 +8,6 @@
obj-$(CONFIG_SPL_BUILD) += cpu.o
obj-y += clock.o
-obj-y += funcmux.o
-obj-y += pinmux.o
obj-y += pmc.o
obj-y += xusb-padctl.o
obj-y += ../xusb-padctl-common.o
diff --git a/arch/arm/mach-tegra/tegra124/funcmux.c b/arch/arm/mach-tegra/tegra124/funcmux.c
deleted file mode 100644
index e7ad85f..0000000
--- a/arch/arm/mach-tegra/tegra124/funcmux.c
+++ /dev/null
@@ -1,71 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2013
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-/* Tegra124 high-level function multiplexing */
-
-#include <common.h>
-#include <log.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/funcmux.h>
-#include <asm/arch/pinmux.h>
-
-int funcmux_select(enum periph_id id, int config)
-{
- int bad_config = config != FUNCMUX_DEFAULT;
-
- switch (id) {
- case PERIPH_ID_UART4:
- switch (config) {
- case FUNCMUX_UART4_GPIO: /* TXD,RXD,CTS,RTS */
- pinmux_set_func(PMUX_PINGRP_PJ7, PMUX_FUNC_UARTD);
- pinmux_set_func(PMUX_PINGRP_PB0, PMUX_FUNC_UARTD);
- pinmux_set_func(PMUX_PINGRP_PB1, PMUX_FUNC_UARTD);
- pinmux_set_func(PMUX_PINGRP_PK7, PMUX_FUNC_UARTD);
-
- pinmux_set_io(PMUX_PINGRP_PJ7, PMUX_PIN_OUTPUT);
- pinmux_set_io(PMUX_PINGRP_PB0, PMUX_PIN_INPUT);
- pinmux_set_io(PMUX_PINGRP_PB1, PMUX_PIN_INPUT);
- pinmux_set_io(PMUX_PINGRP_PK7, PMUX_PIN_OUTPUT);
-
- pinmux_tristate_disable(PMUX_PINGRP_PJ7);
- pinmux_tristate_disable(PMUX_PINGRP_PB0);
- pinmux_tristate_disable(PMUX_PINGRP_PB1);
- pinmux_tristate_disable(PMUX_PINGRP_PK7);
- break;
- }
- break;
-
- case PERIPH_ID_UART1:
- switch (config) {
- case FUNCMUX_UART1_KBC:
- pinmux_set_func(PMUX_PINGRP_KB_ROW9_PS1,
- PMUX_FUNC_UARTA);
- pinmux_set_func(PMUX_PINGRP_KB_ROW10_PS2,
- PMUX_FUNC_UARTA);
-
- pinmux_set_io(PMUX_PINGRP_KB_ROW9_PS1, PMUX_PIN_OUTPUT);
- pinmux_set_io(PMUX_PINGRP_KB_ROW10_PS2, PMUX_PIN_INPUT);
-
- pinmux_tristate_disable(PMUX_PINGRP_KB_ROW9_PS1);
- pinmux_tristate_disable(PMUX_PINGRP_KB_ROW10_PS2);
- break;
- }
- break;
-
- /* Add other periph IDs here as needed */
-
- default:
- debug("%s: invalid periph_id %d", __func__, id);
- return -1;
- }
-
- if (bad_config) {
- debug("%s: invalid config %d for periph_id %d", __func__,
- config, id);
- return -1;
- }
- return 0;
-}
diff --git a/arch/arm/mach-tegra/tegra124/pinmux.c b/arch/arm/mach-tegra/tegra124/pinmux.c
deleted file mode 100644
index 261ce64..0000000
--- a/arch/arm/mach-tegra/tegra124/pinmux.c
+++ /dev/null
@@ -1,322 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/pinmux.h>
-
-#define PIN(pin, f0, f1, f2, f3) \
- { \
- .funcs = { \
- PMUX_FUNC_##f0, \
- PMUX_FUNC_##f1, \
- PMUX_FUNC_##f2, \
- PMUX_FUNC_##f3, \
- }, \
- }
-
-#define PIN_RESERVED {}
-
-static const struct pmux_pingrp_desc tegra124_pingroups[] = {
- /* pin, f0, f1, f2, f3 */
- /* Offset 0x3000 */
- PIN(ULPI_DATA0_PO1, SPI3, HSI, UARTA, ULPI),
- PIN(ULPI_DATA1_PO2, SPI3, HSI, UARTA, ULPI),
- PIN(ULPI_DATA2_PO3, SPI3, HSI, UARTA, ULPI),
- PIN(ULPI_DATA3_PO4, SPI3, HSI, UARTA, ULPI),
- PIN(ULPI_DATA4_PO5, SPI2, HSI, UARTA, ULPI),
- PIN(ULPI_DATA5_PO6, SPI2, HSI, UARTA, ULPI),
- PIN(ULPI_DATA6_PO7, SPI2, HSI, UARTA, ULPI),
- PIN(ULPI_DATA7_PO0, SPI2, HSI, UARTA, ULPI),
- PIN(ULPI_CLK_PY0, SPI1, SPI5, UARTD, ULPI),
- PIN(ULPI_DIR_PY1, SPI1, SPI5, UARTD, ULPI),
- PIN(ULPI_NXT_PY2, SPI1, SPI5, UARTD, ULPI),
- PIN(ULPI_STP_PY3, SPI1, SPI5, UARTD, ULPI),
- PIN(DAP3_FS_PP0, I2S2, SPI5, DISPLAYA, DISPLAYB),
- PIN(DAP3_DIN_PP1, I2S2, SPI5, DISPLAYA, DISPLAYB),
- PIN(DAP3_DOUT_PP2, I2S2, SPI5, DISPLAYA, RSVD4),
- PIN(DAP3_SCLK_PP3, I2S2, SPI5, RSVD3, DISPLAYB),
- PIN(PV0, RSVD1, RSVD2, RSVD3, RSVD4),
- PIN(PV1, RSVD1, RSVD2, RSVD3, RSVD4),
- PIN(SDMMC1_CLK_PZ0, SDMMC1, CLK12, RSVD3, RSVD4),
- PIN(SDMMC1_CMD_PZ1, SDMMC1, SPDIF, SPI4, UARTA),
- PIN(SDMMC1_DAT3_PY4, SDMMC1, SPDIF, SPI4, UARTA),
- PIN(SDMMC1_DAT2_PY5, SDMMC1, PWM0, SPI4, UARTA),
- PIN(SDMMC1_DAT1_PY6, SDMMC1, PWM1, SPI4, UARTA),
- PIN(SDMMC1_DAT0_PY7, SDMMC1, RSVD2, SPI4, UARTA),
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x3068 */
- PIN(CLK2_OUT_PW5, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
- PIN(CLK2_REQ_PCC5, DAP, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x3110 */
- PIN(HDMI_INT_PN7, RSVD1, RSVD2, RSVD3, RSVD4),
- PIN(DDC_SCL_PV4, I2C4, RSVD2, RSVD3, RSVD4),
- PIN(DDC_SDA_PV5, I2C4, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x3164 */
- PIN(UART2_RXD_PC3, IRDA, SPDIF, UARTA, SPI4),
- PIN(UART2_TXD_PC2, IRDA, SPDIF, UARTA, SPI4),
- PIN(UART2_RTS_N_PJ6, UARTA, UARTB, GMI, SPI4),
- PIN(UART2_CTS_N_PJ5, UARTA, UARTB, GMI, SPI4),
- PIN(UART3_TXD_PW6, UARTC, RSVD2, GMI, SPI4),
- PIN(UART3_RXD_PW7, UARTC, RSVD2, GMI, SPI4),
- PIN(UART3_CTS_N_PA1, UARTC, SDMMC1, DTV, GMI),
- PIN(UART3_RTS_N_PC0, UARTC, PWM0, DTV, GMI),
- PIN(PU0, OWR, UARTA, GMI, RSVD4),
- PIN(PU1, RSVD1, UARTA, GMI, RSVD4),
- PIN(PU2, RSVD1, UARTA, GMI, RSVD4),
- PIN(PU3, PWM0, UARTA, GMI, DISPLAYB),
- PIN(PU4, PWM1, UARTA, GMI, DISPLAYB),
- PIN(PU5, PWM2, UARTA, GMI, DISPLAYB),
- PIN(PU6, PWM3, UARTA, RSVD3, GMI),
- PIN(GEN1_I2C_SDA_PC5, I2C1, RSVD2, RSVD3, RSVD4),
- PIN(GEN1_I2C_SCL_PC4, I2C1, RSVD2, RSVD3, RSVD4),
- PIN(DAP4_FS_PP4, I2S3, GMI, DTV, RSVD4),
- PIN(DAP4_DIN_PP5, I2S3, GMI, RSVD3, RSVD4),
- PIN(DAP4_DOUT_PP6, I2S3, GMI, DTV, RSVD4),
- PIN(DAP4_SCLK_PP7, I2S3, GMI, RSVD3, RSVD4),
- PIN(CLK3_OUT_PEE0, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
- PIN(CLK3_REQ_PEE1, DEV3, RSVD2, RSVD3, RSVD4),
- PIN(PC7, RSVD1, RSVD2, GMI, GMI_ALT),
- PIN(PI5, SDMMC2, RSVD2, GMI, RSVD4),
- PIN(PI7, RSVD1, TRACE, GMI, DTV),
- PIN(PK0, RSVD1, SDMMC3, GMI, SOC),
- PIN(PK1, SDMMC2, TRACE, GMI, RSVD4),
- PIN(PJ0, RSVD1, RSVD2, GMI, USB),
- PIN(PJ2, RSVD1, RSVD2, GMI, SOC),
- PIN(PK3, SDMMC2, TRACE, GMI, CCLA),
- PIN(PK4, SDMMC2, RSVD2, GMI, GMI_ALT),
- PIN(PK2, RSVD1, RSVD2, GMI, RSVD4),
- PIN(PI3, RSVD1, RSVD2, GMI, SPI4),
- PIN(PI6, RSVD1, RSVD2, GMI, SDMMC2),
- PIN(PG0, RSVD1, RSVD2, GMI, RSVD4),
- PIN(PG1, RSVD1, RSVD2, GMI, RSVD4),
- PIN(PG2, RSVD1, TRACE, GMI, RSVD4),
- PIN(PG3, RSVD1, TRACE, GMI, RSVD4),
- PIN(PG4, RSVD1, TMDS, GMI, SPI4),
- PIN(PG5, RSVD1, RSVD2, GMI, SPI4),
- PIN(PG6, RSVD1, RSVD2, GMI, SPI4),
- PIN(PG7, RSVD1, RSVD2, GMI, SPI4),
- PIN(PH0, PWM0, TRACE, GMI, DTV),
- PIN(PH1, PWM1, TMDS, GMI, DISPLAYA),
- PIN(PH2, PWM2, TMDS, GMI, CLDVFS),
- PIN(PH3, PWM3, SPI4, GMI, CLDVFS),
- PIN(PH4, SDMMC2, RSVD2, GMI, RSVD4),
- PIN(PH5, SDMMC2, RSVD2, GMI, RSVD4),
- PIN(PH6, SDMMC2, TRACE, GMI, DTV),
- PIN(PH7, SDMMC2, TRACE, GMI, DTV),
- PIN(PJ7, UARTD, RSVD2, GMI, GMI_ALT),
- PIN(PB0, UARTD, RSVD2, GMI, RSVD4),
- PIN(PB1, UARTD, RSVD2, GMI, RSVD4),
- PIN(PK7, UARTD, RSVD2, GMI, RSVD4),
- PIN(PI0, RSVD1, RSVD2, GMI, RSVD4),
- PIN(PI1, RSVD1, RSVD2, GMI, RSVD4),
- PIN(PI2, SDMMC2, TRACE, GMI, RSVD4),
- PIN(PI4, SPI4, TRACE, GMI, DISPLAYA),
- PIN(GEN2_I2C_SCL_PT5, I2C2, RSVD2, GMI, RSVD4),
- PIN(GEN2_I2C_SDA_PT6, I2C2, RSVD2, GMI, RSVD4),
- PIN(SDMMC4_CLK_PCC4, SDMMC4, RSVD2, GMI, RSVD4),
- PIN(SDMMC4_CMD_PT7, SDMMC4, RSVD2, GMI, RSVD4),
- PIN(SDMMC4_DAT0_PAA0, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT1_PAA1, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT2_PAA2, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT3_PAA3, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT4_PAA4, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT5_PAA5, SDMMC4, SPI3, RSVD3, RSVD4),
- PIN(SDMMC4_DAT6_PAA6, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT7_PAA7, SDMMC4, RSVD2, GMI, RSVD4),
- PIN_RESERVED,
- /* Offset 0x3284 */
- PIN(CAM_MCLK_PCC0, VI, VI_ALT1, VI_ALT3, SDMMC2),
- PIN(PCC1, I2S4, RSVD2, RSVD3, SDMMC2),
- PIN(PBB0, VGP6, VIMCLK2, SDMMC2, VIMCLK2_ALT),
- PIN(CAM_I2C_SCL_PBB1, VGP1, I2C3, RSVD3, SDMMC2),
- PIN(CAM_I2C_SDA_PBB2, VGP2, I2C3, RSVD3, SDMMC2),
- PIN(PBB3, VGP3, DISPLAYA, DISPLAYB, SDMMC2),
- PIN(PBB4, VGP4, DISPLAYA, DISPLAYB, SDMMC2),
- PIN(PBB5, VGP5, DISPLAYA, RSVD3, SDMMC2),
- PIN(PBB6, I2S4, RSVD2, DISPLAYB, SDMMC2),
- PIN(PBB7, I2S4, RSVD2, RSVD3, SDMMC2),
- PIN(PCC2, I2S4, RSVD2, SDMMC3, SDMMC2),
- PIN(JTAG_RTCK, RTCK, RSVD2, RSVD3, RSVD4),
- PIN(PWR_I2C_SCL_PZ6, I2CPWR, RSVD2, RSVD3, RSVD4),
- PIN(PWR_I2C_SDA_PZ7, I2CPWR, RSVD2, RSVD3, RSVD4),
- PIN(KB_ROW0_PR0, KBC, RSVD2, RSVD3, RSVD4),
- PIN(KB_ROW1_PR1, KBC, RSVD2, RSVD3, RSVD4),
- PIN(KB_ROW2_PR2, KBC, RSVD2, RSVD3, RSVD4),
- PIN(KB_ROW3_PR3, KBC, DISPLAYA, SYS, DISPLAYB),
- PIN(KB_ROW4_PR4, KBC, DISPLAYA, RSVD3, DISPLAYB),
- PIN(KB_ROW5_PR5, KBC, DISPLAYA, RSVD3, DISPLAYB),
- PIN(KB_ROW6_PR6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB),
- PIN(KB_ROW7_PR7, KBC, RSVD2, CLDVFS, UARTA),
- PIN(KB_ROW8_PS0, KBC, RSVD2, CLDVFS, UARTA),
- PIN(KB_ROW9_PS1, KBC, RSVD2, RSVD3, UARTA),
- PIN(KB_ROW10_PS2, KBC, RSVD2, RSVD3, UARTA),
- PIN(KB_ROW11_PS3, KBC, RSVD2, RSVD3, IRDA),
- PIN(KB_ROW12_PS4, KBC, RSVD2, RSVD3, IRDA),
- PIN(KB_ROW13_PS5, KBC, RSVD2, SPI2, RSVD4),
- PIN(KB_ROW14_PS6, KBC, RSVD2, SPI2, RSVD4),
- PIN(KB_ROW15_PS7, KBC, SOC, RSVD3, RSVD4),
- PIN(KB_COL0_PQ0, KBC, RSVD2, SPI2, RSVD4),
- PIN(KB_COL1_PQ1, KBC, RSVD2, SPI2, RSVD4),
- PIN(KB_COL2_PQ2, KBC, RSVD2, SPI2, RSVD4),
- PIN(KB_COL3_PQ3, KBC, DISPLAYA, PWM2, UARTA),
- PIN(KB_COL4_PQ4, KBC, OWR, SDMMC3, UARTA),
- PIN(KB_COL5_PQ5, KBC, RSVD2, SDMMC3, RSVD4),
- PIN(KB_COL6_PQ6, KBC, RSVD2, SPI2, UARTD),
- PIN(KB_COL7_PQ7, KBC, RSVD2, SPI2, UARTD),
- PIN(CLK_32K_OUT_PA0, BLINK, SOC, RSVD3, RSVD4),
- PIN_RESERVED,
- /* Offset 0x3324 */
- PIN(CORE_PWR_REQ, PWRON, RSVD2, RSVD3, RSVD4),
- PIN(CPU_PWR_REQ, CPU, RSVD2, RSVD3, RSVD4),
- PIN(PWR_INT_N, PMI, RSVD2, RSVD3, RSVD4),
- PIN(CLK_32K_IN, CLK, RSVD2, RSVD3, RSVD4),
- PIN(OWR, OWR, RSVD2, RSVD3, RSVD4),
- PIN(DAP1_FS_PN0, I2S0, HDA, GMI, RSVD4),
- PIN(DAP1_DIN_PN1, I2S0, HDA, GMI, RSVD4),
- PIN(DAP1_DOUT_PN2, I2S0, HDA, GMI, SATA),
- PIN(DAP1_SCLK_PN3, I2S0, HDA, GMI, RSVD4),
- PIN(DAP_MCLK1_REQ_PEE2, DAP, DAP1, SATA, RSVD4),
- PIN(DAP_MCLK1_PW4, EXTPERIPH1, DAP2, RSVD3, RSVD4),
- PIN(SPDIF_IN_PK6, SPDIF, RSVD2, RSVD3, I2C3),
- PIN(SPDIF_OUT_PK5, SPDIF, RSVD2, RSVD3, I2C3),
- PIN(DAP2_FS_PA2, I2S1, HDA, GMI, RSVD4),
- PIN(DAP2_DIN_PA4, I2S1, HDA, GMI, RSVD4),
- PIN(DAP2_DOUT_PA5, I2S1, HDA, GMI, RSVD4),
- PIN(DAP2_SCLK_PA3, I2S1, HDA, GMI, RSVD4),
- PIN(DVFS_PWM_PX0, SPI6, CLDVFS, GMI, RSVD4),
- PIN(GPIO_X1_AUD_PX1, SPI6, RSVD2, GMI, RSVD4),
- PIN(GPIO_X3_AUD_PX3, SPI6, SPI1, GMI, RSVD4),
- PIN(DVFS_CLK_PX2, SPI6, CLDVFS, GMI, RSVD4),
- PIN(GPIO_X4_AUD_PX4, GMI, SPI1, SPI2, DAP2),
- PIN(GPIO_X5_AUD_PX5, GMI, SPI1, SPI2, RSVD4),
- PIN(GPIO_X6_AUD_PX6, SPI6, SPI1, SPI2, GMI),
- PIN(GPIO_X7_AUD_PX7, RSVD1, SPI1, SPI2, RSVD4),
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x3390 */
- PIN(SDMMC3_CLK_PA6, SDMMC3, RSVD2, RSVD3, SPI3),
- PIN(SDMMC3_CMD_PA7, SDMMC3, PWM3, UARTA, SPI3),
- PIN(SDMMC3_DAT0_PB7, SDMMC3, RSVD2, RSVD3, SPI3),
- PIN(SDMMC3_DAT1_PB6, SDMMC3, PWM2, UARTA, SPI3),
- PIN(SDMMC3_DAT2_PB5, SDMMC3, PWM1, DISPLAYA, SPI3),
- PIN(SDMMC3_DAT3_PB4, SDMMC3, PWM0, DISPLAYB, SPI3),
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x33bc */
- PIN(PEX_L0_RST_N_PDD1, PE0, RSVD2, RSVD3, RSVD4),
- PIN(PEX_L0_CLKREQ_N_PDD2, PE0, RSVD2, RSVD3, RSVD4),
- PIN(PEX_WAKE_N_PDD3, PE, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED,
- /* Offset 0x33cc */
- PIN(PEX_L1_RST_N_PDD5, PE1, RSVD2, RSVD3, RSVD4),
- PIN(PEX_L1_CLKREQ_N_PDD6, PE1, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x33e0 */
- PIN(HDMI_CEC_PEE3, CEC, RSVD2, RSVD3, RSVD4),
- PIN(SDMMC1_WP_N_PV3, SDMMC1, CLK12, SPI4, UARTA),
- PIN(SDMMC3_CD_N_PV2, SDMMC3, OWR, RSVD3, RSVD4),
- PIN(GPIO_W2_AUD_PW2, SPI6, RSVD2, SPI2, I2C1),
- PIN(GPIO_W3_AUD_PW3, SPI6, SPI1, SPI2, I2C1),
- PIN(USB_VBUS_EN0_PN4, USB, RSVD2, RSVD3, RSVD4),
- PIN(USB_VBUS_EN1_PN5, USB, RSVD2, RSVD3, RSVD4),
- PIN(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, RSVD2, RSVD3, RSVD4),
- PIN(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, RSVD2, RSVD3, RSVD4),
- PIN(GMI_CLK_LB, SDMMC2, RSVD2, GMI, RSVD4),
- PIN(RESET_OUT_N, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
- PIN(KB_ROW16_PT0, KBC, RSVD2, RSVD3, UARTC),
- PIN(KB_ROW17_PT1, KBC, RSVD2, RSVD3, UARTC),
- PIN(USB_VBUS_EN2_PFF1, USB, RSVD2, RSVD3, RSVD4),
- PIN(PFF2, SATA, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x3430 */
- PIN(DP_HPD_PFF0, DP, RSVD2, RSVD3, RSVD4),
-};
-const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra124_pingroups;
-
-#define MIPIPADCTRL_GRP(grp, f0, f1) \
- { \
- .funcs = { \
- PMUX_FUNC_##f0, \
- PMUX_FUNC_##f1, \
- }, \
- }
-
-#define MIPIPADCTRL_RESERVED {}
-
-static const struct pmux_mipipadctrlgrp_desc tegra124_mipipadctrl_groups[] = {
- /* pin, f0, f1 */
- /* Offset 0x820 */
- MIPIPADCTRL_GRP(DSI_B, CSI, DSI_B),
-};
-const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups = tegra124_mipipadctrl_groups;
diff --git a/arch/arm/mach-tegra/tegra20/Makefile b/arch/arm/mach-tegra/tegra20/Makefile
index 991cabe..c2ae98e 100644
--- a/arch/arm/mach-tegra/tegra20/Makefile
+++ b/arch/arm/mach-tegra/tegra20/Makefile
@@ -11,7 +11,7 @@
-D__LINUX_ARM_ARCH__=4
CFLAGS_REMOVE_warmboot_avp.o := $(LTO_CFLAGS)
-obj-y += clock.o funcmux.o pinmux.o
+obj-y += clock.o
obj-$(CONFIG_TEGRA_LP0) += warmboot.o warmboot_avp.o
obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
obj-$(CONFIG_TEGRA_PMU) += pmu.o
diff --git a/arch/arm/mach-tegra/tegra20/funcmux.c b/arch/arm/mach-tegra/tegra20/funcmux.c
deleted file mode 100644
index 90fe0cb..0000000
--- a/arch/arm/mach-tegra/tegra20/funcmux.c
+++ /dev/null
@@ -1,298 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- */
-
-/* Tegra20 high-level function multiplexing */
-#include <common.h>
-#include <log.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/funcmux.h>
-#include <asm/arch/pinmux.h>
-
-/*
- * The PINMUX macro is used to set up pinmux tables.
- */
-#define PINMUX(grp, mux, pupd, tri) \
- {PMUX_PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri}
-
-static const struct pmux_pingrp_config disp1_default[] = {
- PINMUX(LDI, DISPA, NORMAL, NORMAL),
- PINMUX(LHP0, DISPA, NORMAL, NORMAL),
- PINMUX(LHP1, DISPA, NORMAL, NORMAL),
- PINMUX(LHP2, DISPA, NORMAL, NORMAL),
- PINMUX(LHS, DISPA, NORMAL, NORMAL),
- PINMUX(LM0, RSVD4, NORMAL, NORMAL),
- PINMUX(LPP, DISPA, NORMAL, NORMAL),
- PINMUX(LPW0, DISPA, NORMAL, NORMAL),
- PINMUX(LPW2, DISPA, NORMAL, NORMAL),
- PINMUX(LSC0, DISPA, NORMAL, NORMAL),
- PINMUX(LSPI, DISPA, NORMAL, NORMAL),
- PINMUX(LVP1, DISPA, NORMAL, NORMAL),
- PINMUX(LVS, DISPA, NORMAL, NORMAL),
- PINMUX(SLXD, SPDIF, NORMAL, NORMAL),
-};
-
-
-int funcmux_select(enum periph_id id, int config)
-{
- int bad_config = config != FUNCMUX_DEFAULT;
-
- switch (id) {
- case PERIPH_ID_UART1:
- switch (config) {
- case FUNCMUX_UART1_IRRX_IRTX:
- pinmux_set_func(PMUX_PINGRP_IRRX, PMUX_FUNC_UARTA);
- pinmux_set_func(PMUX_PINGRP_IRTX, PMUX_FUNC_UARTA);
- pinmux_tristate_disable(PMUX_PINGRP_IRRX);
- pinmux_tristate_disable(PMUX_PINGRP_IRTX);
- break;
- case FUNCMUX_UART1_UAA_UAB:
- pinmux_set_func(PMUX_PINGRP_UAA, PMUX_FUNC_UARTA);
- pinmux_set_func(PMUX_PINGRP_UAB, PMUX_FUNC_UARTA);
- pinmux_tristate_disable(PMUX_PINGRP_UAA);
- pinmux_tristate_disable(PMUX_PINGRP_UAB);
- bad_config = 0;
- break;
- case FUNCMUX_UART1_GPU:
- pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_UARTA);
- pinmux_tristate_disable(PMUX_PINGRP_GPU);
- bad_config = 0;
- break;
- case FUNCMUX_UART1_SDIO1:
- pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_UARTA);
- pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
- bad_config = 0;
- break;
- }
- if (!bad_config) {
- /*
- * Tegra appears to boot with function UARTA pre-
- * selected on mux group SDB. If two mux groups are
- * both set to the same function, it's unclear which
- * group's pins drive the RX signals into the HW.
- * For UARTA, SDB certainly overrides group IRTX in
- * practice. To solve this, configure some alternative
- * function on SDB to avoid the conflict. Also, tri-
- * state the group to avoid driving any signal onto it
- * until we know what's connected.
- */
- pinmux_tristate_enable(PMUX_PINGRP_SDB);
- pinmux_set_func(PMUX_PINGRP_SDB, PMUX_FUNC_SDIO3);
- }
- break;
-
- case PERIPH_ID_UART2:
- if (config == FUNCMUX_UART2_UAD) {
- pinmux_set_func(PMUX_PINGRP_UAD, PMUX_FUNC_UARTB);
- pinmux_tristate_disable(PMUX_PINGRP_UAD);
- }
- break;
-
- case PERIPH_ID_UART4:
- if (config == FUNCMUX_UART4_GMC) {
- pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_UARTD);
- pinmux_tristate_disable(PMUX_PINGRP_GMC);
- }
- break;
-
- case PERIPH_ID_DVC_I2C:
- /* there is only one selection, pinmux_config is ignored */
- if (config == FUNCMUX_DVC_I2CP) {
- pinmux_set_func(PMUX_PINGRP_I2CP, PMUX_FUNC_I2C);
- pinmux_tristate_disable(PMUX_PINGRP_I2CP);
- }
- break;
-
- case PERIPH_ID_I2C1:
- /* support pinmux_config of 0 for now, */
- if (config == FUNCMUX_I2C1_RM) {
- pinmux_set_func(PMUX_PINGRP_RM, PMUX_FUNC_I2C);
- pinmux_tristate_disable(PMUX_PINGRP_RM);
- }
- break;
- case PERIPH_ID_I2C2: /* I2C2 */
- switch (config) {
- case FUNCMUX_I2C2_DDC: /* DDC pin group, select I2C2 */
- pinmux_set_func(PMUX_PINGRP_DDC, PMUX_FUNC_I2C2);
- /* PTA to HDMI */
- pinmux_set_func(PMUX_PINGRP_PTA, PMUX_FUNC_HDMI);
- pinmux_tristate_disable(PMUX_PINGRP_DDC);
- break;
- case FUNCMUX_I2C2_PTA: /* PTA pin group, select I2C2 */
- pinmux_set_func(PMUX_PINGRP_PTA, PMUX_FUNC_I2C2);
- /* set DDC_SEL to RSVDx (RSVD2 works for now) */
- pinmux_set_func(PMUX_PINGRP_DDC, PMUX_FUNC_RSVD2);
- pinmux_tristate_disable(PMUX_PINGRP_PTA);
- bad_config = 0;
- break;
- }
- break;
- case PERIPH_ID_I2C3: /* I2C3 */
- /* support pinmux_config of 0 for now */
- if (config == FUNCMUX_I2C3_DTF) {
- pinmux_set_func(PMUX_PINGRP_DTF, PMUX_FUNC_I2C3);
- pinmux_tristate_disable(PMUX_PINGRP_DTF);
- }
- break;
-
- case PERIPH_ID_SDMMC1:
- if (config == FUNCMUX_SDMMC1_SDIO1_4BIT) {
- pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_SDIO1);
- pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
- }
- break;
-
- case PERIPH_ID_SDMMC2:
- if (config == FUNCMUX_SDMMC2_DTA_DTD_8BIT) {
- pinmux_set_func(PMUX_PINGRP_DTA, PMUX_FUNC_SDIO2);
- pinmux_set_func(PMUX_PINGRP_DTD, PMUX_FUNC_SDIO2);
-
- pinmux_tristate_disable(PMUX_PINGRP_DTA);
- pinmux_tristate_disable(PMUX_PINGRP_DTD);
- }
- break;
-
- case PERIPH_ID_SDMMC3:
- switch (config) {
- case FUNCMUX_SDMMC3_SDB_SLXA_8BIT:
- pinmux_set_func(PMUX_PINGRP_SLXA, PMUX_FUNC_SDIO3);
- pinmux_set_func(PMUX_PINGRP_SLXC, PMUX_FUNC_SDIO3);
- pinmux_set_func(PMUX_PINGRP_SLXD, PMUX_FUNC_SDIO3);
- pinmux_set_func(PMUX_PINGRP_SLXK, PMUX_FUNC_SDIO3);
-
- pinmux_tristate_disable(PMUX_PINGRP_SLXA);
- pinmux_tristate_disable(PMUX_PINGRP_SLXC);
- pinmux_tristate_disable(PMUX_PINGRP_SLXD);
- pinmux_tristate_disable(PMUX_PINGRP_SLXK);
- /* fall through */
-
- case FUNCMUX_SDMMC3_SDB_4BIT:
- pinmux_set_func(PMUX_PINGRP_SDB, PMUX_FUNC_SDIO3);
- pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_SDIO3);
- pinmux_set_func(PMUX_PINGRP_SDD, PMUX_FUNC_SDIO3);
-
- pinmux_tristate_disable(PMUX_PINGRP_SDB);
- pinmux_tristate_disable(PMUX_PINGRP_SDC);
- pinmux_tristate_disable(PMUX_PINGRP_SDD);
- bad_config = 0;
- break;
- }
- break;
-
- case PERIPH_ID_SDMMC4:
- switch (config) {
- case FUNCMUX_SDMMC4_ATC_ATD_8BIT:
- pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_SDIO4);
- pinmux_set_func(PMUX_PINGRP_ATD, PMUX_FUNC_SDIO4);
-
- pinmux_tristate_disable(PMUX_PINGRP_ATC);
- pinmux_tristate_disable(PMUX_PINGRP_ATD);
- break;
-
- case FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT:
- pinmux_set_func(PMUX_PINGRP_GME, PMUX_FUNC_SDIO4);
- pinmux_tristate_disable(PMUX_PINGRP_GME);
- /* fall through */
-
- case FUNCMUX_SDMMC4_ATB_GMA_4_BIT:
- pinmux_set_func(PMUX_PINGRP_ATB, PMUX_FUNC_SDIO4);
- pinmux_set_func(PMUX_PINGRP_GMA, PMUX_FUNC_SDIO4);
-
- pinmux_tristate_disable(PMUX_PINGRP_ATB);
- pinmux_tristate_disable(PMUX_PINGRP_GMA);
- bad_config = 0;
- break;
- }
- break;
-
- case PERIPH_ID_KBC:
- if (config == FUNCMUX_DEFAULT) {
- enum pmux_pingrp grp[] = {PMUX_PINGRP_KBCA,
- PMUX_PINGRP_KBCB, PMUX_PINGRP_KBCC,
- PMUX_PINGRP_KBCD, PMUX_PINGRP_KBCE,
- PMUX_PINGRP_KBCF};
- int i;
-
- for (i = 0; i < ARRAY_SIZE(grp); i++) {
- pinmux_tristate_disable(grp[i]);
- pinmux_set_func(grp[i], PMUX_FUNC_KBC);
- pinmux_set_pullupdown(grp[i], PMUX_PULL_UP);
- }
- }
- break;
-
- case PERIPH_ID_USB2:
- if (config == FUNCMUX_USB2_ULPI) {
- pinmux_set_func(PMUX_PINGRP_UAA, PMUX_FUNC_ULPI);
- pinmux_set_func(PMUX_PINGRP_UAB, PMUX_FUNC_ULPI);
- pinmux_set_func(PMUX_PINGRP_UDA, PMUX_FUNC_ULPI);
-
- pinmux_tristate_disable(PMUX_PINGRP_UAA);
- pinmux_tristate_disable(PMUX_PINGRP_UAB);
- pinmux_tristate_disable(PMUX_PINGRP_UDA);
- }
- break;
-
- case PERIPH_ID_SPI1:
- if (config == FUNCMUX_SPI1_GMC_GMD) {
- pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH);
- pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH);
-
- pinmux_tristate_disable(PMUX_PINGRP_GMC);
- pinmux_tristate_disable(PMUX_PINGRP_GMD);
- }
- break;
-
- case PERIPH_ID_NDFLASH:
- switch (config) {
- case FUNCMUX_NDFLASH_ATC:
- pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_NAND);
- pinmux_tristate_disable(PMUX_PINGRP_ATC);
- break;
- case FUNCMUX_NDFLASH_KBC_8_BIT:
- pinmux_set_func(PMUX_PINGRP_KBCA, PMUX_FUNC_NAND);
- pinmux_set_func(PMUX_PINGRP_KBCB, PMUX_FUNC_NAND);
- pinmux_set_func(PMUX_PINGRP_KBCC, PMUX_FUNC_NAND);
- pinmux_set_func(PMUX_PINGRP_KBCD, PMUX_FUNC_NAND);
- pinmux_set_func(PMUX_PINGRP_KBCE, PMUX_FUNC_NAND);
- pinmux_set_func(PMUX_PINGRP_KBCF, PMUX_FUNC_NAND);
-
- pinmux_tristate_disable(PMUX_PINGRP_KBCA);
- pinmux_tristate_disable(PMUX_PINGRP_KBCB);
- pinmux_tristate_disable(PMUX_PINGRP_KBCC);
- pinmux_tristate_disable(PMUX_PINGRP_KBCD);
- pinmux_tristate_disable(PMUX_PINGRP_KBCE);
- pinmux_tristate_disable(PMUX_PINGRP_KBCF);
-
- bad_config = 0;
- break;
- }
- break;
- case PERIPH_ID_DISP1:
- if (config == FUNCMUX_DEFAULT) {
- int i;
-
- for (i = PMUX_PINGRP_LD0; i <= PMUX_PINGRP_LD17; i++) {
- pinmux_set_func(i, PMUX_FUNC_DISPA);
- pinmux_tristate_disable(i);
- pinmux_set_pullupdown(i, PMUX_PULL_NORMAL);
- }
- pinmux_config_pingrp_table(disp1_default,
- ARRAY_SIZE(disp1_default));
- }
- break;
-
- default:
- debug("%s: invalid periph_id %d", __func__, id);
- return -1;
- }
-
- if (bad_config) {
- debug("%s: invalid config %d for periph_id %d", __func__,
- config, id);
- return -1;
- }
-
- return 0;
-}
diff --git a/arch/arm/mach-tegra/tegra20/pinmux.c b/arch/arm/mach-tegra/tegra20/pinmux.c
deleted file mode 100644
index 0af39e7..0000000
--- a/arch/arm/mach-tegra/tegra20/pinmux.c
+++ /dev/null
@@ -1,424 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- */
-
-/* Tegra20 pin multiplexing functions */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/pinmux.h>
-
-/*
- * This defines the order of the pin mux control bits in the registers. For
- * some reason there is no correspendence between the tristate, pin mux and
- * pullup/pulldown registers.
- */
-enum pmux_ctlid {
- /* 0: APB_MISC_PP_PIN_MUX_CTL_A_0 */
- MUXCTL_UAA,
- MUXCTL_UAB,
- MUXCTL_UAC,
- MUXCTL_UAD,
- MUXCTL_UDA,
- MUXCTL_RESERVED5,
- MUXCTL_ATE,
- MUXCTL_RM,
-
- MUXCTL_ATB,
- MUXCTL_RESERVED9,
- MUXCTL_ATD,
- MUXCTL_ATC,
- MUXCTL_ATA,
- MUXCTL_KBCF,
- MUXCTL_KBCE,
- MUXCTL_SDMMC1,
-
- /* 16: APB_MISC_PP_PIN_MUX_CTL_B_0 */
- MUXCTL_GMA,
- MUXCTL_GMC,
- MUXCTL_HDINT,
- MUXCTL_SLXA,
- MUXCTL_OWC,
- MUXCTL_SLXC,
- MUXCTL_SLXD,
- MUXCTL_SLXK,
-
- MUXCTL_UCA,
- MUXCTL_UCB,
- MUXCTL_DTA,
- MUXCTL_DTB,
- MUXCTL_RESERVED28,
- MUXCTL_DTC,
- MUXCTL_DTD,
- MUXCTL_DTE,
-
- /* 32: APB_MISC_PP_PIN_MUX_CTL_C_0 */
- MUXCTL_DDC,
- MUXCTL_CDEV1,
- MUXCTL_CDEV2,
- MUXCTL_CSUS,
- MUXCTL_I2CP,
- MUXCTL_KBCA,
- MUXCTL_KBCB,
- MUXCTL_KBCC,
-
- MUXCTL_IRTX,
- MUXCTL_IRRX,
- MUXCTL_DAP1,
- MUXCTL_DAP2,
- MUXCTL_DAP3,
- MUXCTL_DAP4,
- MUXCTL_GMB,
- MUXCTL_GMD,
-
- /* 48: APB_MISC_PP_PIN_MUX_CTL_D_0 */
- MUXCTL_GME,
- MUXCTL_GPV,
- MUXCTL_GPU,
- MUXCTL_SPDO,
- MUXCTL_SPDI,
- MUXCTL_SDB,
- MUXCTL_SDC,
- MUXCTL_SDD,
-
- MUXCTL_SPIH,
- MUXCTL_SPIG,
- MUXCTL_SPIF,
- MUXCTL_SPIE,
- MUXCTL_SPID,
- MUXCTL_SPIC,
- MUXCTL_SPIB,
- MUXCTL_SPIA,
-
- /* 64: APB_MISC_PP_PIN_MUX_CTL_E_0 */
- MUXCTL_LPW0,
- MUXCTL_LPW1,
- MUXCTL_LPW2,
- MUXCTL_LSDI,
- MUXCTL_LSDA,
- MUXCTL_LSPI,
- MUXCTL_LCSN,
- MUXCTL_LDC,
-
- MUXCTL_LSCK,
- MUXCTL_LSC0,
- MUXCTL_LSC1,
- MUXCTL_LHS,
- MUXCTL_LVS,
- MUXCTL_LM0,
- MUXCTL_LM1,
- MUXCTL_LVP0,
-
- /* 80: APB_MISC_PP_PIN_MUX_CTL_F_0 */
- MUXCTL_LD0,
- MUXCTL_LD1,
- MUXCTL_LD2,
- MUXCTL_LD3,
- MUXCTL_LD4,
- MUXCTL_LD5,
- MUXCTL_LD6,
- MUXCTL_LD7,
-
- MUXCTL_LD8,
- MUXCTL_LD9,
- MUXCTL_LD10,
- MUXCTL_LD11,
- MUXCTL_LD12,
- MUXCTL_LD13,
- MUXCTL_LD14,
- MUXCTL_LD15,
-
- /* 96: APB_MISC_PP_PIN_MUX_CTL_G_0 */
- MUXCTL_LD16,
- MUXCTL_LD17,
- MUXCTL_LHP1,
- MUXCTL_LHP2,
- MUXCTL_LVP1,
- MUXCTL_LHP0,
- MUXCTL_RESERVED102,
- MUXCTL_LPP,
-
- MUXCTL_LDI,
- MUXCTL_PMC,
- MUXCTL_CRTP,
- MUXCTL_PTA,
- MUXCTL_RESERVED108,
- MUXCTL_KBCD,
- MUXCTL_GPU7,
- MUXCTL_DTF,
-
- MUXCTL_NONE = -1,
-};
-
-/*
- * And this defines the order of the pullup/pulldown controls which are again
- * in a different order
- */
-enum pmux_pullid {
- /* 0: APB_MISC_PP_PULLUPDOWN_REG_A_0 */
- PUCTL_ATA,
- PUCTL_ATB,
- PUCTL_ATC,
- PUCTL_ATD,
- PUCTL_ATE,
- PUCTL_DAP1,
- PUCTL_DAP2,
- PUCTL_DAP3,
-
- PUCTL_DAP4,
- PUCTL_DTA,
- PUCTL_DTB,
- PUCTL_DTC,
- PUCTL_DTD,
- PUCTL_DTE,
- PUCTL_DTF,
- PUCTL_GPV,
-
- /* 16: APB_MISC_PP_PULLUPDOWN_REG_B_0 */
- PUCTL_RM,
- PUCTL_I2CP,
- PUCTL_PTA,
- PUCTL_GPU7,
- PUCTL_KBCA,
- PUCTL_KBCB,
- PUCTL_KBCC,
- PUCTL_KBCD,
-
- PUCTL_SPDI,
- PUCTL_SPDO,
- PUCTL_GPSLXAU,
- PUCTL_CRTP,
- PUCTL_SLXC,
- PUCTL_SLXD,
- PUCTL_SLXK,
-
- /* 32: APB_MISC_PP_PULLUPDOWN_REG_C_0 */
- PUCTL_CDEV1,
- PUCTL_CDEV2,
- PUCTL_SPIA,
- PUCTL_SPIB,
- PUCTL_SPIC,
- PUCTL_SPID,
- PUCTL_SPIE,
- PUCTL_SPIF,
-
- PUCTL_SPIG,
- PUCTL_SPIH,
- PUCTL_IRTX,
- PUCTL_IRRX,
- PUCTL_GME,
- PUCTL_RESERVED45,
- PUCTL_XM2D,
- PUCTL_XM2C,
-
- /* 48: APB_MISC_PP_PULLUPDOWN_REG_D_0 */
- PUCTL_UAA,
- PUCTL_UAB,
- PUCTL_UAC,
- PUCTL_UAD,
- PUCTL_UCA,
- PUCTL_UCB,
- PUCTL_LD17,
- PUCTL_LD19_18,
-
- PUCTL_LD21_20,
- PUCTL_LD23_22,
- PUCTL_LS,
- PUCTL_LC,
- PUCTL_CSUS,
- PUCTL_DDRC,
- PUCTL_SDC,
- PUCTL_SDD,
-
- /* 64: APB_MISC_PP_PULLUPDOWN_REG_E_0 */
- PUCTL_KBCF,
- PUCTL_KBCE,
- PUCTL_PMCA,
- PUCTL_PMCB,
- PUCTL_PMCC,
- PUCTL_PMCD,
- PUCTL_PMCE,
- PUCTL_CK32,
-
- PUCTL_UDA,
- PUCTL_SDMMC1,
- PUCTL_GMA,
- PUCTL_GMB,
- PUCTL_GMC,
- PUCTL_GMD,
- PUCTL_DDC,
- PUCTL_OWC,
-
- PUCTL_NONE = -1
-};
-
-/* Convenient macro for defining pin group properties */
-#define PINALL(pingrp, f0, f1, f2, f3, mux, pupd) \
- { \
- .funcs = { \
- PMUX_FUNC_ ## f0, \
- PMUX_FUNC_ ## f1, \
- PMUX_FUNC_ ## f2, \
- PMUX_FUNC_ ## f3, \
- }, \
- .ctl_id = mux, \
- .pull_id = pupd \
- }
-
-/* A normal pin group where the mux name and pull-up name match */
-#define PIN(pingrp, f0, f1, f2, f3) \
- PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pingrp)
-
-/* A pin group where the pull-up name doesn't have a 1-1 mapping */
-#define PINP(pingrp, f0, f1, f2, f3, pupd) \
- PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pupd)
-
-/* A pin group number which is not used */
-#define PIN_RESERVED \
- PIN(NONE, RSVD1, RSVD2, RSVD3, RSVD4)
-
-#define DRVGRP(drvgrp) \
- PINALL(drvgrp, RSVD1, RSVD2, RSVD3, RSVD4, MUXCTL_NONE, PUCTL_NONE)
-
-static const struct pmux_pingrp_desc tegra20_pingroups[] = {
- PIN(ATA, IDE, NAND, GMI, RSVD4),
- PIN(ATB, IDE, NAND, GMI, SDIO4),
- PIN(ATC, IDE, NAND, GMI, SDIO4),
- PIN(ATD, IDE, NAND, GMI, SDIO4),
- PIN(CDEV1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC),
- PIN(CDEV2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4),
- PIN(CSUS, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK),
- PIN(DAP1, DAP1, RSVD2, GMI, SDIO2),
-
- PIN(DAP2, DAP2, TWC, RSVD3, GMI),
- PIN(DAP3, DAP3, RSVD2, RSVD3, RSVD4),
- PIN(DAP4, DAP4, RSVD2, GMI, RSVD4),
- PIN(DTA, RSVD1, SDIO2, VI, RSVD4),
- PIN(DTB, RSVD1, RSVD2, VI, SPI1),
- PIN(DTC, RSVD1, RSVD2, VI, RSVD4),
- PIN(DTD, RSVD1, SDIO2, VI, RSVD4),
- PIN(DTE, RSVD1, RSVD2, VI, SPI1),
-
- PINP(GPU, PWM, UARTA, GMI, RSVD4, GPSLXAU),
- PIN(GPV, PCIE, RSVD2, RSVD3, RSVD4),
- PIN(I2CP, I2C, RSVD2, RSVD3, RSVD4),
- PIN(IRTX, UARTA, UARTB, GMI, SPI4),
- PIN(IRRX, UARTA, UARTB, GMI, SPI4),
- PIN(KBCB, KBC, NAND, SDIO2, MIO),
- PIN(KBCA, KBC, NAND, SDIO2, EMC_TEST0_DLL),
- PINP(PMC, PWR_ON, PWR_INTR, RSVD3, RSVD4, NONE),
-
- PIN(PTA, I2C2, HDMI, GMI, RSVD4),
- PIN(RM, I2C, RSVD2, RSVD3, RSVD4),
- PIN(KBCE, KBC, NAND, OWR, RSVD4),
- PIN(KBCF, KBC, NAND, TRACE, MIO),
- PIN(GMA, UARTE, SPI3, GMI, SDIO4),
- PIN(GMC, UARTD, SPI4, GMI, SFLASH),
- PIN(SDMMC1, SDIO1, RSVD2, UARTE, UARTA),
- PIN(OWC, OWR, RSVD2, RSVD3, RSVD4),
-
- PIN(GME, RSVD1, DAP5, GMI, SDIO4),
- PIN(SDC, PWM, TWC, SDIO3, SPI3),
- PIN(SDD, UARTA, PWM, SDIO3, SPI3),
- PIN_RESERVED,
- PINP(SLXA, PCIE, SPI4, SDIO3, SPI2, CRTP),
- PIN(SLXC, SPDIF, SPI4, SDIO3, SPI2),
- PIN(SLXD, SPDIF, SPI4, SDIO3, SPI2),
- PIN(SLXK, PCIE, SPI4, SDIO3, SPI2),
-
- PIN(SPDI, SPDIF, RSVD2, I2C, SDIO2),
- PIN(SPDO, SPDIF, RSVD2, I2C, SDIO2),
- PIN(SPIA, SPI1, SPI2, SPI3, GMI),
- PIN(SPIB, SPI1, SPI2, SPI3, GMI),
- PIN(SPIC, SPI1, SPI2, SPI3, GMI),
- PIN(SPID, SPI2, SPI1, SPI2_ALT, GMI),
- PIN(SPIE, SPI2, SPI1, SPI2_ALT, GMI),
- PIN(SPIF, SPI3, SPI1, SPI2, RSVD4),
-
- PIN(SPIG, SPI3, SPI2, SPI2_ALT, I2C),
- PIN(SPIH, SPI3, SPI2, SPI2_ALT, I2C),
- PIN(UAA, SPI3, MIPI_HS, UARTA, ULPI),
- PIN(UAB, SPI2, MIPI_HS, UARTA, ULPI),
- PIN(UAC, OWR, RSVD2, RSVD3, RSVD4),
- PIN(UAD, UARTB, SPDIF, UARTA, SPI4),
- PIN(UCA, UARTC, RSVD2, GMI, RSVD4),
- PIN(UCB, UARTC, PWM, GMI, RSVD4),
-
- PIN_RESERVED,
- PIN(ATE, IDE, NAND, GMI, RSVD4),
- PIN(KBCC, KBC, NAND, TRACE, EMC_TEST1_DLL),
- PIN_RESERVED,
- PIN_RESERVED,
- PIN(GMB, IDE, NAND, GMI, GMI_INT),
- PIN(GMD, RSVD1, NAND, GMI, SFLASH),
- PIN(DDC, I2C2, RSVD2, RSVD3, RSVD4),
-
- /* 64 */
- PINP(LD0, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD1, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD2, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD3, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD4, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD5, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD6, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD7, DISPA, DISPB, XIO, RSVD4, LD17),
-
- PINP(LD8, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD9, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD10, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD11, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD12, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD13, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD14, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD15, DISPA, DISPB, XIO, RSVD4, LD17),
-
- PINP(LD16, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD17, DISPA, DISPB, RSVD3, RSVD4, LD17),
- PINP(LHP0, DISPA, DISPB, RSVD3, RSVD4, LD21_20),
- PINP(LHP1, DISPA, DISPB, RSVD3, RSVD4, LD19_18),
- PINP(LHP2, DISPA, DISPB, RSVD3, RSVD4, LD19_18),
- PINP(LVP0, DISPA, DISPB, RSVD3, RSVD4, LC),
- PINP(LVP1, DISPA, DISPB, RSVD3, RSVD4, LD21_20),
- PINP(HDINT, HDMI, RSVD2, RSVD3, RSVD4, LC),
-
- PINP(LM0, DISPA, DISPB, SPI3, RSVD4, LC),
- PINP(LM1, DISPA, DISPB, RSVD3, CRT, LC),
- PINP(LVS, DISPA, DISPB, XIO, RSVD4, LC),
- PINP(LSC0, DISPA, DISPB, XIO, RSVD4, LC),
- PINP(LSC1, DISPA, DISPB, SPI3, HDMI, LS),
- PINP(LSCK, DISPA, DISPB, SPI3, HDMI, LS),
- PINP(LDC, DISPA, DISPB, RSVD3, RSVD4, LS),
- PINP(LCSN, DISPA, DISPB, SPI3, RSVD4, LS),
-
- /* 96 */
- PINP(LSPI, DISPA, DISPB, XIO, HDMI, LC),
- PINP(LSDA, DISPA, DISPB, SPI3, HDMI, LS),
- PINP(LSDI, DISPA, DISPB, SPI3, RSVD4, LS),
- PINP(LPW0, DISPA, DISPB, SPI3, HDMI, LS),
- PINP(LPW1, DISPA, DISPB, RSVD3, RSVD4, LS),
- PINP(LPW2, DISPA, DISPB, SPI3, HDMI, LS),
- PINP(LDI, DISPA, DISPB, RSVD3, RSVD4, LD23_22),
- PINP(LHS, DISPA, DISPB, XIO, RSVD4, LC),
-
- PINP(LPP, DISPA, DISPB, RSVD3, RSVD4, LD23_22),
- PIN_RESERVED,
- PIN(KBCD, KBC, NAND, SDIO2, MIO),
- PIN(GPU7, RTCK, RSVD2, RSVD3, RSVD4),
- PIN(DTF, I2C3, RSVD2, VI, RSVD4),
- PIN(UDA, SPI1, RSVD2, UARTD, ULPI),
- PIN(CRTP, CRT, RSVD2, RSVD3, RSVD4),
- PINP(SDB, UARTA, PWM, SDIO3, SPI2, NONE),
-
- /* these pin groups only have pullup and pull down control */
- DRVGRP(CK32),
- DRVGRP(DDRC),
- DRVGRP(PMCA),
- DRVGRP(PMCB),
- DRVGRP(PMCC),
- DRVGRP(PMCD),
- DRVGRP(PMCE),
- DRVGRP(XM2C),
- DRVGRP(XM2D),
-};
-const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra20_pingroups;
diff --git a/arch/arm/mach-tegra/tegra210/Makefile b/arch/arm/mach-tegra/tegra210/Makefile
index cfcba5b..5cc718d 100644
--- a/arch/arm/mach-tegra/tegra210/Makefile
+++ b/arch/arm/mach-tegra/tegra210/Makefile
@@ -6,6 +6,5 @@
#
obj-y += clock.o
-obj-y += funcmux.o
obj-y += xusb-padctl.o
obj-y += ../xusb-padctl-common.o
diff --git a/arch/arm/mach-tegra/tegra210/funcmux.c b/arch/arm/mach-tegra/tegra210/funcmux.c
deleted file mode 100644
index 30d994a..0000000
--- a/arch/arm/mach-tegra/tegra210/funcmux.c
+++ /dev/null
@@ -1,40 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2013-2015
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-/* Tegra210 high-level function multiplexing */
-
-#include <common.h>
-#include <log.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/funcmux.h>
-#include <asm/arch/pinmux.h>
-
-int funcmux_select(enum periph_id id, int config)
-{
- int bad_config = config != FUNCMUX_DEFAULT;
-
- switch (id) {
- /*
- * Add other periph IDs here as needed.
- * Note that all pinmux/pads should have already
- * been set up in the board pinmux table in
- * pinmux-config-<board>.h for all periphs.
- * Leave this in for the odd case where a mux
- * needs to be changed on-the-fly.
- */
-
- default:
- debug("%s: invalid periph_id %d", __func__, id);
- return -1;
- }
-
- if (bad_config) {
- debug("%s: invalid config %d for periph_id %d", __func__,
- config, id);
- return -1;
- }
- return 0;
-}
diff --git a/arch/arm/mach-tegra/tegra30/Makefile b/arch/arm/mach-tegra/tegra30/Makefile
index 28dd486..ee0e6f5 100644
--- a/arch/arm/mach-tegra/tegra30/Makefile
+++ b/arch/arm/mach-tegra/tegra30/Makefile
@@ -5,4 +5,4 @@
obj-$(CONFIG_SPL_BUILD) += cpu.o
obj-$(CONFIG_$(SPL_)CMD_EBTUPDATE) += bct.o
-obj-y += clock.o funcmux.o pinmux.o
+obj-y += clock.o
diff --git a/arch/arm/mach-tegra/tegra30/funcmux.c b/arch/arm/mach-tegra/tegra30/funcmux.c
deleted file mode 100644
index c3ee787..0000000
--- a/arch/arm/mach-tegra/tegra30/funcmux.c
+++ /dev/null
@@ -1,51 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
- */
-
-/* Tegra30 high-level function multiplexing */
-
-#include <common.h>
-#include <log.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/funcmux.h>
-#include <asm/arch/pinmux.h>
-
-int funcmux_select(enum periph_id id, int config)
-{
- int bad_config = config != FUNCMUX_DEFAULT;
-
- switch (id) {
- case PERIPH_ID_UART1:
- switch (config) {
- case FUNCMUX_UART1_ULPI:
- pinmux_set_func(PMUX_PINGRP_ULPI_DATA0_PO1,
- PMUX_FUNC_UARTA);
- pinmux_set_func(PMUX_PINGRP_ULPI_DATA1_PO2,
- PMUX_FUNC_UARTA);
- pinmux_set_func(PMUX_PINGRP_ULPI_DATA2_PO3,
- PMUX_FUNC_UARTA);
- pinmux_set_func(PMUX_PINGRP_ULPI_DATA3_PO4,
- PMUX_FUNC_UARTA);
- pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA0_PO1);
- pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA1_PO2);
- pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA2_PO3);
- pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA3_PO4);
- break;
- }
- break;
-
- /* Add other periph IDs here as needed */
-
- default:
- debug("%s: invalid periph_id %d", __func__, id);
- return -1;
- }
-
- if (bad_config) {
- debug("%s: invalid config %d for periph_id %d", __func__,
- config, id);
- return -1;
- }
- return 0;
-}
diff --git a/arch/arm/mach-tegra/tegra30/pinmux.c b/arch/arm/mach-tegra/tegra30/pinmux.c
deleted file mode 100644
index d11b2aa..0000000
--- a/arch/arm/mach-tegra/tegra30/pinmux.c
+++ /dev/null
@@ -1,275 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/pinmux.h>
-
-#define PIN(pin, f0, f1, f2, f3) \
- { \
- .funcs = { \
- PMUX_FUNC_##f0, \
- PMUX_FUNC_##f1, \
- PMUX_FUNC_##f2, \
- PMUX_FUNC_##f3, \
- }, \
- }
-
-#define PIN_RESERVED {}
-
-static const struct pmux_pingrp_desc tegra30_pingroups[] = {
- /* pin, f0, f1, f2, f3 */
- /* Offset 0x3000 */
- PIN(ULPI_DATA0_PO1, SPI3, HSI, UARTA, ULPI),
- PIN(ULPI_DATA1_PO2, SPI3, HSI, UARTA, ULPI),
- PIN(ULPI_DATA2_PO3, SPI3, HSI, UARTA, ULPI),
- PIN(ULPI_DATA3_PO4, SPI3, HSI, UARTA, ULPI),
- PIN(ULPI_DATA4_PO5, SPI2, HSI, UARTA, ULPI),
- PIN(ULPI_DATA5_PO6, SPI2, HSI, UARTA, ULPI),
- PIN(ULPI_DATA6_PO7, SPI2, HSI, UARTA, ULPI),
- PIN(ULPI_DATA7_PO0, SPI2, HSI, UARTA, ULPI),
- PIN(ULPI_CLK_PY0, SPI1, RSVD2, UARTD, ULPI),
- PIN(ULPI_DIR_PY1, SPI1, RSVD2, UARTD, ULPI),
- PIN(ULPI_NXT_PY2, SPI1, RSVD2, UARTD, ULPI),
- PIN(ULPI_STP_PY3, SPI1, RSVD2, UARTD, ULPI),
- PIN(DAP3_FS_PP0, I2S2, RSVD2, DISPLAYA, DISPLAYB),
- PIN(DAP3_DIN_PP1, I2S2, RSVD2, DISPLAYA, DISPLAYB),
- PIN(DAP3_DOUT_PP2, I2S2, RSVD2, DISPLAYA, DISPLAYB),
- PIN(DAP3_SCLK_PP3, I2S2, RSVD2, DISPLAYA, DISPLAYB),
- PIN(PV0, RSVD1, RSVD2, RSVD3, RSVD4),
- PIN(PV1, RSVD1, RSVD2, RSVD3, RSVD4),
- PIN(SDMMC1_CLK_PZ0, SDMMC1, RSVD2, RSVD3, UARTA),
- PIN(SDMMC1_CMD_PZ1, SDMMC1, RSVD2, RSVD3, UARTA),
- PIN(SDMMC1_DAT3_PY4, SDMMC1, RSVD2, UARTE, UARTA),
- PIN(SDMMC1_DAT2_PY5, SDMMC1, RSVD2, UARTE, UARTA),
- PIN(SDMMC1_DAT1_PY6, SDMMC1, RSVD2, UARTE, UARTA),
- PIN(SDMMC1_DAT0_PY7, SDMMC1, RSVD2, UARTE, UARTA),
- PIN(PV2, OWR, RSVD2, RSVD3, RSVD4),
- PIN(PV3, CLK_12M_OUT, RSVD2, RSVD3, RSVD4),
- PIN(CLK2_OUT_PW5, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
- PIN(CLK2_REQ_PCC5, DAP, RSVD2, RSVD3, RSVD4),
- PIN(LCD_PWR1_PC1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_PWR2_PC6, DISPLAYA, DISPLAYB, SPI5, HDCP),
- PIN(LCD_SDIN_PZ2, DISPLAYA, DISPLAYB, SPI5, RSVD4),
- PIN(LCD_SDOUT_PN5, DISPLAYA, DISPLAYB, SPI5, HDCP),
- PIN(LCD_WR_N_PZ3, DISPLAYA, DISPLAYB, SPI5, HDCP),
- PIN(LCD_CS0_N_PN4, DISPLAYA, DISPLAYB, SPI5, RSVD4),
- PIN(LCD_DC0_PN6, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_SCK_PZ4, DISPLAYA, DISPLAYB, SPI5, HDCP),
- PIN(LCD_PWR0_PB2, DISPLAYA, DISPLAYB, SPI5, HDCP),
- PIN(LCD_PCLK_PB3, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_DE_PJ1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_HSYNC_PJ3, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_VSYNC_PJ4, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D0_PE0, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D1_PE1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D2_PE2, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D3_PE3, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D4_PE4, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D5_PE5, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D6_PE6, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D7_PE7, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D8_PF0, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D9_PF1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D10_PF2, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D11_PF3, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D12_PF4, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D13_PF5, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D14_PF6, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D15_PF7, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D16_PM0, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D17_PM1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D18_PM2, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D19_PM3, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D20_PM4, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D21_PM5, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D22_PM6, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D23_PM7, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_CS1_N_PW0, DISPLAYA, DISPLAYB, SPI5, RSVD4),
- PIN(LCD_M1_PW1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_DC1_PD2, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(HDMI_INT_PN7, HDMI, RSVD2, RSVD3, RSVD4),
- PIN(DDC_SCL_PV4, I2C4, RSVD2, RSVD3, RSVD4),
- PIN(DDC_SDA_PV5, I2C4, RSVD2, RSVD3, RSVD4),
- PIN(CRT_HSYNC_PV6, CRT, RSVD2, RSVD3, RSVD4),
- PIN(CRT_VSYNC_PV7, CRT, RSVD2, RSVD3, RSVD4),
- PIN(VI_D0_PT4, DDR, RSVD2, VI, RSVD4),
- PIN(VI_D1_PD5, DDR, SDMMC2, VI, RSVD4),
- PIN(VI_D2_PL0, DDR, SDMMC2, VI, RSVD4),
- PIN(VI_D3_PL1, DDR, SDMMC2, VI, RSVD4),
- PIN(VI_D4_PL2, DDR, SDMMC2, VI, RSVD4),
- PIN(VI_D5_PL3, DDR, SDMMC2, VI, RSVD4),
- PIN(VI_D6_PL4, DDR, SDMMC2, VI, RSVD4),
- PIN(VI_D7_PL5, DDR, SDMMC2, VI, RSVD4),
- PIN(VI_D8_PL6, DDR, SDMMC2, VI, RSVD4),
- PIN(VI_D9_PL7, DDR, SDMMC2, VI, RSVD4),
- PIN(VI_D10_PT2, DDR, RSVD2, VI, RSVD4),
- PIN(VI_D11_PT3, DDR, RSVD2, VI, RSVD4),
- PIN(VI_PCLK_PT0, RSVD1, SDMMC2, VI, RSVD4),
- PIN(VI_MCLK_PT1, VI, VI_ALT1, VI_ALT2, VI_ALT3),
- PIN(VI_VSYNC_PD6, DDR, RSVD2, VI, RSVD4),
- PIN(VI_HSYNC_PD7, DDR, RSVD2, VI, RSVD4),
- PIN(UART2_RXD_PC3, UARTB, SPDIF, UARTA, SPI4),
- PIN(UART2_TXD_PC2, UARTB, SPDIF, UARTA, SPI4),
- PIN(UART2_RTS_N_PJ6, UARTA, UARTB, GMI, SPI4),
- PIN(UART2_CTS_N_PJ5, UARTA, UARTB, GMI, SPI4),
- PIN(UART3_TXD_PW6, UARTC, RSVD2, GMI, RSVD4),
- PIN(UART3_RXD_PW7, UARTC, RSVD2, GMI, RSVD4),
- PIN(UART3_CTS_N_PA1, UARTC, RSVD2, GMI, RSVD4),
- PIN(UART3_RTS_N_PC0, UARTC, PWM0, GMI, RSVD4),
- PIN(PU0, OWR, UARTA, GMI, RSVD4),
- PIN(PU1, RSVD1, UARTA, GMI, RSVD4),
- PIN(PU2, RSVD1, UARTA, GMI, RSVD4),
- PIN(PU3, PWM0, UARTA, GMI, RSVD4),
- PIN(PU4, PWM1, UARTA, GMI, RSVD4),
- PIN(PU5, PWM2, UARTA, GMI, RSVD4),
- PIN(PU6, PWM3, UARTA, GMI, RSVD4),
- PIN(GEN1_I2C_SDA_PC5, I2C1, RSVD2, RSVD3, RSVD4),
- PIN(GEN1_I2C_SCL_PC4, I2C1, RSVD2, RSVD3, RSVD4),
- PIN(DAP4_FS_PP4, I2S3, RSVD2, GMI, RSVD4),
- PIN(DAP4_DIN_PP5, I2S3, RSVD2, GMI, RSVD4),
- PIN(DAP4_DOUT_PP6, I2S3, RSVD2, GMI, RSVD4),
- PIN(DAP4_SCLK_PP7, I2S3, RSVD2, GMI, RSVD4),
- PIN(CLK3_OUT_PEE0, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
- PIN(CLK3_REQ_PEE1, DEV3, RSVD2, RSVD3, RSVD4),
- PIN(GMI_WP_N_PC7, RSVD1, NAND, GMI, GMI_ALT),
- PIN(GMI_IORDY_PI5, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_WAIT_PI7, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_ADV_N_PK0, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_CLK_PK1, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_CS0_N_PJ0, RSVD1, NAND, GMI, DTV),
- PIN(GMI_CS1_N_PJ2, RSVD1, NAND, GMI, DTV),
- PIN(GMI_CS2_N_PK3, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_CS3_N_PK4, RSVD1, NAND, GMI, GMI_ALT),
- PIN(GMI_CS4_N_PK2, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_CS6_N_PI3, NAND, NAND_ALT, GMI, SATA),
- PIN(GMI_CS7_N_PI6, NAND, NAND_ALT, GMI, GMI_ALT),
- PIN(GMI_AD0_PG0, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD1_PG1, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD2_PG2, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD3_PG3, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD4_PG4, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD5_PG5, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD6_PG6, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD7_PG7, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD8_PH0, PWM0, NAND, GMI, RSVD4),
- PIN(GMI_AD9_PH1, PWM1, NAND, GMI, RSVD4),
- PIN(GMI_AD10_PH2, PWM2, NAND, GMI, RSVD4),
- PIN(GMI_AD11_PH3, PWM3, NAND, GMI, RSVD4),
- PIN(GMI_AD12_PH4, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD13_PH5, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD14_PH6, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD15_PH7, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_A16_PJ7, UARTD, SPI4, GMI, GMI_ALT),
- PIN(GMI_A17_PB0, UARTD, SPI4, GMI, DTV),
- PIN(GMI_A18_PB1, UARTD, SPI4, GMI, DTV),
- PIN(GMI_A19_PK7, UARTD, SPI4, GMI, RSVD4),
- PIN(GMI_WR_N_PI0, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_OE_N_PI1, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_DQS_PI2, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_RST_N_PI4, NAND, NAND_ALT, GMI, RSVD4),
- PIN(GEN2_I2C_SCL_PT5, I2C2, HDCP, GMI, RSVD4),
- PIN(GEN2_I2C_SDA_PT6, I2C2, HDCP, GMI, RSVD4),
- PIN(SDMMC4_CLK_PCC4, INVALID, NAND, GMI, SDMMC4),
- PIN(SDMMC4_CMD_PT7, I2C3, NAND, GMI, SDMMC4),
- PIN(SDMMC4_DAT0_PAA0, UARTE, SPI3, GMI, SDMMC4),
- PIN(SDMMC4_DAT1_PAA1, UARTE, SPI3, GMI, SDMMC4),
- PIN(SDMMC4_DAT2_PAA2, UARTE, SPI3, GMI, SDMMC4),
- PIN(SDMMC4_DAT3_PAA3, UARTE, SPI3, GMI, SDMMC4),
- PIN(SDMMC4_DAT4_PAA4, I2C3, I2S4, GMI, SDMMC4),
- PIN(SDMMC4_DAT5_PAA5, VGP3, I2S4, GMI, SDMMC4),
- PIN(SDMMC4_DAT6_PAA6, VGP4, I2S4, GMI, SDMMC4),
- PIN(SDMMC4_DAT7_PAA7, VGP5, I2S4, GMI, SDMMC4),
- PIN(SDMMC4_RST_N_PCC3, VGP6, RSVD2, RSVD3, SDMMC4),
- PIN(CAM_MCLK_PCC0, VI, VI_ALT1, VI_ALT3, SDMMC4),
- PIN(PCC1, I2S4, RSVD2, RSVD3, SDMMC4),
- PIN(PBB0, I2S4, RSVD2, RSVD3, SDMMC4),
- PIN(CAM_I2C_SCL_PBB1, VGP1, I2C3, RSVD3, SDMMC4),
- PIN(CAM_I2C_SDA_PBB2, VGP2, I2C3, RSVD3, SDMMC4),
- PIN(PBB3, VGP3, DISPLAYA, DISPLAYB, SDMMC4),
- PIN(PBB4, VGP4, DISPLAYA, DISPLAYB, SDMMC4),
- PIN(PBB5, VGP5, DISPLAYA, DISPLAYB, SDMMC4),
- PIN(PBB6, VGP6, DISPLAYA, DISPLAYB, SDMMC4),
- PIN(PBB7, I2S4, RSVD2, RSVD3, SDMMC4),
- PIN(PCC2, I2S4, RSVD2, RSVD3, RSVD4),
- PIN(JTAG_RTCK_PU7, RTCK, RSVD2, RSVD3, RSVD4),
- PIN(PWR_I2C_SCL_PZ6, I2CPWR, RSVD2, RSVD3, RSVD4),
- PIN(PWR_I2C_SDA_PZ7, I2CPWR, RSVD2, RSVD3, RSVD4),
- PIN(KB_ROW0_PR0, KBC, NAND, RSVD3, RSVD4),
- PIN(KB_ROW1_PR1, KBC, NAND, RSVD3, RSVD4),
- PIN(KB_ROW2_PR2, KBC, NAND, RSVD3, RSVD4),
- PIN(KB_ROW3_PR3, KBC, NAND, RSVD3, INVALID),
- PIN(KB_ROW4_PR4, KBC, NAND, TRACE, RSVD4),
- PIN(KB_ROW5_PR5, KBC, NAND, TRACE, OWR),
- PIN(KB_ROW6_PR6, KBC, NAND, SDMMC2, MIO),
- PIN(KB_ROW7_PR7, KBC, NAND, SDMMC2, MIO),
- PIN(KB_ROW8_PS0, KBC, NAND, SDMMC2, MIO),
- PIN(KB_ROW9_PS1, KBC, NAND, SDMMC2, MIO),
- PIN(KB_ROW10_PS2, KBC, NAND, SDMMC2, MIO),
- PIN(KB_ROW11_PS3, KBC, NAND, SDMMC2, MIO),
- PIN(KB_ROW12_PS4, KBC, NAND, SDMMC2, MIO),
- PIN(KB_ROW13_PS5, KBC, NAND, SDMMC2, MIO),
- PIN(KB_ROW14_PS6, KBC, NAND, SDMMC2, MIO),
- PIN(KB_ROW15_PS7, KBC, NAND, SDMMC2, MIO),
- PIN(KB_COL0_PQ0, KBC, NAND, TRACE, TEST),
- PIN(KB_COL1_PQ1, KBC, NAND, TRACE, TEST),
- PIN(KB_COL2_PQ2, KBC, NAND, TRACE, RSVD4),
- PIN(KB_COL3_PQ3, KBC, NAND, TRACE, RSVD4),
- PIN(KB_COL4_PQ4, KBC, NAND, TRACE, RSVD4),
- PIN(KB_COL5_PQ5, KBC, NAND, TRACE, RSVD4),
- PIN(KB_COL6_PQ6, KBC, NAND, TRACE, MIO),
- PIN(KB_COL7_PQ7, KBC, NAND, TRACE, MIO),
- PIN(CLK_32K_OUT_PA0, BLINK, RSVD2, RSVD3, RSVD4),
- PIN(SYS_CLK_REQ_PZ5, SYSCLK, RSVD2, RSVD3, RSVD4),
- PIN(CORE_PWR_REQ, CORE_PWR_REQ, RSVD2, RSVD3, RSVD4),
- PIN(CPU_PWR_REQ, CPU_PWR_REQ, RSVD2, RSVD3, RSVD4),
- PIN(PWR_INT_N, PWR_INT_N, RSVD2, RSVD3, RSVD4),
- PIN(CLK_32K_IN, CLK_32K_IN, RSVD2, RSVD3, RSVD4),
- PIN(OWR, OWR, CEC, RSVD3, RSVD4),
- PIN(DAP1_FS_PN0, I2S0, HDA, GMI, SDMMC2),
- PIN(DAP1_DIN_PN1, I2S0, HDA, GMI, SDMMC2),
- PIN(DAP1_DOUT_PN2, I2S0, HDA, GMI, SDMMC2),
- PIN(DAP1_SCLK_PN3, I2S0, HDA, GMI, SDMMC2),
- PIN(CLK1_REQ_PEE2, DAP, HDA, RSVD3, RSVD4),
- PIN(CLK1_OUT_PW4, EXTPERIPH1, RSVD2, RSVD3, RSVD4),
- PIN(SPDIF_IN_PK6, SPDIF, HDA, I2C1, SDMMC2),
- PIN(SPDIF_OUT_PK5, SPDIF, RSVD2, I2C1, SDMMC2),
- PIN(DAP2_FS_PA2, I2S1, HDA, RSVD3, GMI),
- PIN(DAP2_DIN_PA4, I2S1, HDA, RSVD3, GMI),
- PIN(DAP2_DOUT_PA5, I2S1, HDA, RSVD3, GMI),
- PIN(DAP2_SCLK_PA3, I2S1, HDA, RSVD3, GMI),
- PIN(SPI2_MOSI_PX0, SPI6, SPI2, SPI3, GMI),
- PIN(SPI2_MISO_PX1, SPI6, SPI2, SPI3, GMI),
- PIN(SPI2_CS0_N_PX3, SPI6, SPI2, SPI3, GMI),
- PIN(SPI2_SCK_PX2, SPI6, SPI2, SPI3, GMI),
- PIN(SPI1_MOSI_PX4, SPI2, SPI1, SPI2_ALT, GMI),
- PIN(SPI1_SCK_PX5, SPI2, SPI1, SPI2_ALT, GMI),
- PIN(SPI1_CS0_N_PX6, SPI2, SPI1, SPI2_ALT, GMI),
- PIN(SPI1_MISO_PX7, SPI3, SPI1, SPI2_ALT, RSVD4),
- PIN(SPI2_CS1_N_PW2, SPI3, SPI2, SPI2_ALT, I2C1),
- PIN(SPI2_CS2_N_PW3, SPI3, SPI2, SPI2_ALT, I2C1),
- PIN(SDMMC3_CLK_PA6, UARTA, PWM2, SDMMC3, SPI3),
- PIN(SDMMC3_CMD_PA7, UARTA, PWM3, SDMMC3, SPI2),
- PIN(SDMMC3_DAT0_PB7, RSVD1, RSVD2, SDMMC3, SPI3),
- PIN(SDMMC3_DAT1_PB6, RSVD1, RSVD2, SDMMC3, SPI3),
- PIN(SDMMC3_DAT2_PB5, RSVD1, PWM1, SDMMC3, SPI3),
- PIN(SDMMC3_DAT3_PB4, RSVD1, PWM0, SDMMC3, SPI3),
- PIN(SDMMC3_DAT4_PD1, PWM1, SPI4, SDMMC3, SPI2),
- PIN(SDMMC3_DAT5_PD0, PWM0, SPI4, SDMMC3, SPI2),
- PIN(SDMMC3_DAT6_PD3, SPDIF, SPI4, SDMMC3, SPI2),
- PIN(SDMMC3_DAT7_PD4, SPDIF, SPI4, SDMMC3, SPI2),
- PIN(PEX_L0_PRSNT_N_PDD0, PCIE, HDA, RSVD3, RSVD4),
- PIN(PEX_L0_RST_N_PDD1, PCIE, HDA, RSVD3, RSVD4),
- PIN(PEX_L0_CLKREQ_N_PDD2, PCIE, HDA, RSVD3, RSVD4),
- PIN(PEX_WAKE_N_PDD3, PCIE, HDA, RSVD3, RSVD4),
- PIN(PEX_L1_PRSNT_N_PDD4, PCIE, HDA, RSVD3, RSVD4),
- PIN(PEX_L1_RST_N_PDD5, PCIE, HDA, RSVD3, RSVD4),
- PIN(PEX_L1_CLKREQ_N_PDD6, PCIE, HDA, RSVD3, RSVD4),
- PIN(PEX_L2_PRSNT_N_PDD7, PCIE, HDA, RSVD3, RSVD4),
- PIN(PEX_L2_RST_N_PCC6, PCIE, HDA, RSVD3, RSVD4),
- PIN(PEX_L2_CLKREQ_N_PCC7, PCIE, HDA, RSVD3, RSVD4),
- PIN(HDMI_CEC_PEE3, CEC, RSVD2, RSVD3, RSVD4),
-};
-const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra30_pingroups;