clk: renesas: Add RZ/G2L & RZ/G2LC CPG driver
This driver provides clock and reset control for the Renesas R9A07G044L
(RZ/G2L) and R9A07G044C (RZ/G2LC) SoC. It consists of two parts:
* driver code which is applicable to all SoCs in the RZ/G2L family.
* static data describing the clocks and resets which are specific to the
R9A07G044{L,C} SoCs. The identifier r9a07g044 (without a final letter)
is used to indicate that both SoCs are supported.
clk_set_rate() and clk_get_rate() are implemented only for the clocks
that are actually used in u-boot.
The CPG driver is marked with DM_FLAG_PRE_RELOC to ensure that its bind
function is called before the SCIF (serial port) driver is probed. This
is required so that we can de-assert the relevant reset signal during
the serial driver probe function.
This patch is based on the corresponding Linux v6.5 driver
(commit 52e12027d50affbf60c6c9c64db8017391b0c22e).
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
index 1d8d26d..c5419e8 100644
--- a/arch/arm/mach-rmobile/Kconfig
+++ b/arch/arm/mach-rmobile/Kconfig
@@ -70,6 +70,7 @@
prompt "Renesas RZ/G2L Family ARM SoCs"
select GICV3
select RCAR_64
+ imply CLK_RZG2L
imply MULTI_DTB_FIT
imply MULTI_DTB_FIT_USER_DEFINED_AREA
imply RENESAS_SDHI
diff --git a/arch/arm/mach-rmobile/Kconfig.rzg2l b/arch/arm/mach-rmobile/Kconfig.rzg2l
index eda04df..039d6b0 100644
--- a/arch/arm/mach-rmobile/Kconfig.rzg2l
+++ b/arch/arm/mach-rmobile/Kconfig.rzg2l
@@ -5,6 +5,7 @@
config R9A07G044L
bool "Renesas R9A07G044L SoC"
+ imply CLK_R9A07G044
help
Enable support for the Renesas R9A07G044L (RZ/G2L) SoC.