mtd: nand: support GPMI NAND driver for i.MX8
enable the GPMI NAND driver for i.MX8, i.MX8 use similar controller as
i.MX8M
- register definition for i.mx8
- DMA structure must be 32bit address
Signed-off-by: Peng Fan <peng.fan@nxp.com>
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index c46fec3..c4d9d31 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -259,12 +259,12 @@
config NAND_MXS
bool "MXS NAND support"
- depends on MX23 || MX28 || MX6 || MX7 || IMX8M
+ depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
select SYS_NAND_SELF_INIT
imply CMD_NAND
select APBH_DMA
- select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8M
- select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8M
+ select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
+ select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
help
This enables NAND driver for the NAND flash controller on the
MXS processors.
diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c
index 3bf5ab2..b6e65c6 100644
--- a/drivers/mtd/nand/raw/mxs_nand.c
+++ b/drivers/mtd/nand/raw/mxs_nand.c
@@ -31,7 +31,8 @@
#define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
-#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || \
+ defined(CONFIG_IMX8M)
#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
#else
#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
@@ -55,21 +56,21 @@
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
{
- uint32_t addr = (uint32_t)info->data_buf;
+ uint32_t addr = (uintptr_t)info->data_buf;
flush_dcache_range(addr, addr + info->data_buf_size);
}
static void mxs_nand_inval_data_buf(struct mxs_nand_info *info)
{
- uint32_t addr = (uint32_t)info->data_buf;
+ uint32_t addr = (uintptr_t)info->data_buf;
invalidate_dcache_range(addr, addr + info->data_buf_size);
}
static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info)
{
- uint32_t addr = (uint32_t)info->cmd_buf;
+ uint32_t addr = (uintptr_t)info->cmd_buf;
flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE);
}
@@ -773,7 +774,7 @@
if (status[i] == 0xff) {
if (is_mx6dqp() || is_mx7() ||
- is_mx6ul() || is_imx8m())
+ is_mx6ul() || is_imx8() || is_imx8m())
if (readl(&bch_regs->hw_bch_debug1))
flag = 1;
continue;
@@ -1172,7 +1173,7 @@
/* Set erase threshold to ecc strength for mx6ul, mx6qp and mx7 */
if (is_mx6dqp() || is_mx7() ||
- is_mx6ul() || is_imx8m())
+ is_mx6ul() || is_imx8() || is_imx8m())
writel(BCH_MODE_ERASE_THRESHOLD(geo->ecc_strength),
&bch_regs->hw_bch_mode);
@@ -1311,7 +1312,7 @@
nand_info->gpmi_regs = (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
nand_info->bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
- if (is_mx6sx() || is_mx7() || is_imx8m())
+ if (is_mx6sx() || is_mx7() || is_imx8() || is_imx8m())
nand_info->max_ecc_strength_supported = 62;
else
nand_info->max_ecc_strength_supported = 40;
diff --git a/drivers/mtd/nand/raw/mxs_nand_dt.c b/drivers/mtd/nand/raw/mxs_nand_dt.c
index bd429e0..c4dc0bb 100644
--- a/drivers/mtd/nand/raw/mxs_nand_dt.c
+++ b/drivers/mtd/nand/raw/mxs_nand_dt.c
@@ -33,6 +33,10 @@
.max_ecc_strength_supported = 62,
};
+static const struct mxs_nand_dt_data mxs_nand_imx8qxp_data = {
+ .max_ecc_strength_supported = 62,
+};
+
static const struct udevice_id mxs_nand_dt_ids[] = {
{
.compatible = "fsl,imx6q-gpmi-nand",
@@ -50,6 +54,10 @@
.compatible = "fsl,imx7d-gpmi-nand",
.data = (unsigned long)&mxs_nand_imx7d_data,
},
+ {
+ .compatible = "fsl,imx8qxp-gpmi-nand",
+ .data = (unsigned long)&mxs_nand_imx8qxp_data,
+ },
{ /* sentinel */ }
};