mtd: nand: support GPMI NAND driver for i.MX8
enable the GPMI NAND driver for i.MX8, i.MX8 use similar controller as
i.MX8M
- register definition for i.mx8
- DMA structure must be 32bit address
Signed-off-by: Peng Fan <peng.fan@nxp.com>
diff --git a/arch/arm/include/asm/mach-imx/dma.h b/arch/arm/include/asm/mach-imx/dma.h
index cb73aae..247a91a 100644
--- a/arch/arm/include/asm/mach-imx/dma.h
+++ b/arch/arm/include/asm/mach-imx/dma.h
@@ -7,6 +7,7 @@
*
* Based on code from LTIB:
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2020 NXP
*/
#ifndef __DMA_H__
@@ -53,7 +54,7 @@
MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
MXS_MAX_DMA_CHANNELS,
};
-#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
+#else
enum {
MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
@@ -95,13 +96,13 @@
#define MXS_DMA_DESC_BYTES_OFFSET 16
struct mxs_dma_cmd {
- unsigned long next;
- unsigned long data;
+ u32 next;
+ u32 data;
union {
- dma_addr_t address;
- unsigned long alternate;
+ u32 address;
+ u32 alternate;
};
- unsigned long pio_words[DMA_PIO_WORDS];
+ u32 pio_words[DMA_PIO_WORDS];
};
/*
@@ -117,7 +118,7 @@
struct mxs_dma_desc {
struct mxs_dma_cmd cmd;
unsigned int flags;
- dma_addr_t address;
+ u32 address;
void *buffer;
struct list_head node;
} __aligned(MXS_DMA_ALIGNMENT);