ti: dwc3: Enable clocks in enable_basic_clocks() in hw_data.c
Commit d3cfcb3 (ARM: DRA7: Enable clocks for USB OTGSS and USB PHY)
changed the member names of prcm_regs from cm_l3init_usb_otg_ss_clkctrl
to cm_l3init_usb_otg_ss1_clkctrl and from cm_coreaon_usb_phy_core_clkctrl
to cm_coreaon_usb_phy1_core_clkctrl in order to differentiate between
the two dwc3 controllers present in dra7xx/am43xx and enabled these
clocks in enable_basic_clocks() in hw_data.c. However these clocks
continued to be enabled in board files/driver files for dwc3 host
mode functionality causing compilation break with few configs.
Fixed it here by making all the clocks enabled in enable_basic_clocks()
and removing it from board files/driver files here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index e4abb25..868415d 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -460,7 +460,7 @@
(*prcm)->cm_l4per_gpio6_clkctrl,
(*prcm)->cm_l4per_gpio7_clkctrl,
(*prcm)->cm_l4per_gpio8_clkctrl,
-#ifdef CONFIG_USB_DWC3
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
(*prcm)->cm_l3init_ocp2scp1_clkctrl,
(*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
#endif
@@ -495,7 +495,7 @@
setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);
-#ifdef CONFIG_USB_DWC3
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
/* Enable 960 MHz clock for dwc3 */
setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
OPTFCLKEN_REFCLK960M);