armv8: LS2080A: Rename LS2085A to reflect LS2080A
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list]
Reviewed-by: York Sun <yorksun@freescale.com>
diff --git a/board/freescale/ls2085a/Kconfig b/board/freescale/ls2080a/Kconfig
similarity index 66%
rename from board/freescale/ls2085a/Kconfig
rename to board/freescale/ls2080a/Kconfig
index 042f85b..0b938ff 100644
--- a/board/freescale/ls2085a/Kconfig
+++ b/board/freescale/ls2080a/Kconfig
@@ -1,7 +1,7 @@
-if TARGET_LS2085A_EMU
+if TARGET_LS2080A_EMU
config SYS_BOARD
- default "ls2085a"
+ default "ls2080a"
config SYS_VENDOR
default "freescale"
@@ -10,14 +10,14 @@
default "fsl-layerscape"
config SYS_CONFIG_NAME
- default "ls2085a_emu"
+ default "ls2080a_emu"
endif
-if TARGET_LS2085A_SIMU
+if TARGET_LS2080A_SIMU
config SYS_BOARD
- default "ls2085a"
+ default "ls2080a"
config SYS_VENDOR
default "freescale"
@@ -26,6 +26,6 @@
default "fsl-layerscape"
config SYS_CONFIG_NAME
- default "ls2085a_simu"
+ default "ls2080a_simu"
endif
diff --git a/board/freescale/ls2080a/MAINTAINERS b/board/freescale/ls2080a/MAINTAINERS
new file mode 100644
index 0000000..bb25084
--- /dev/null
+++ b/board/freescale/ls2080a/MAINTAINERS
@@ -0,0 +1,8 @@
+LS2080A BOARD
+M: York Sun <yorksun@freescale.com>
+S: Maintained
+F: board/freescale/ls2080a/
+F: include/configs/ls2080a_emu.h
+F: configs/ls2080a_emu_defconfig
+F: include/configs/ls2080a_simu.h
+F: configs/ls2080a_simu_defconfig
diff --git a/board/freescale/ls2080a/Makefile b/board/freescale/ls2080a/Makefile
new file mode 100644
index 0000000..47c7c74
--- /dev/null
+++ b/board/freescale/ls2080a/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2014-15 Freescale Semiconductor
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ls2080a.o
+obj-y += ddr.o
diff --git a/board/freescale/ls2085a/README b/board/freescale/ls2080a/README
similarity index 97%
rename from board/freescale/ls2085a/README
rename to board/freescale/ls2080a/README
index bc1d0bb..7e53f1f 100644
--- a/board/freescale/ls2085a/README
+++ b/board/freescale/ls2080a/README
@@ -1,4 +1,4 @@
-Freescale ls2085a_emu
+Freescale ls2080a_emu
This is a emulator target with limited peripherals.
diff --git a/board/freescale/ls2085a/ddr.c b/board/freescale/ls2080a/ddr.c
similarity index 98%
rename from board/freescale/ls2085a/ddr.c
rename to board/freescale/ls2080a/ddr.c
index 4884fa2..47d73ef 100644
--- a/board/freescale/ls2085a/ddr.c
+++ b/board/freescale/ls2080a/ddr.c
@@ -71,7 +71,7 @@
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
pbsp->wrlvl_ctl_3);
-
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
if (ctrl_num == CONFIG_DP_DDR_CTRL) {
/* force DDR bus width to 32 bits */
popts->data_bus_width = 1;
@@ -79,6 +79,7 @@
popts->burst_length = DDR_BL8;
popts->bstopre = 0; /* enable auto precharge */
}
+#endif
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
diff --git a/board/freescale/ls2085a/ddr.h b/board/freescale/ls2080a/ddr.h
similarity index 100%
rename from board/freescale/ls2085a/ddr.h
rename to board/freescale/ls2080a/ddr.h
diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2080a/ls2080a.c
similarity index 98%
rename from board/freescale/ls2085a/ls2085a.c
rename to board/freescale/ls2080a/ls2080a.c
index 27481e2..827fbf0 100644
--- a/board/freescale/ls2085a/ls2085a.c
+++ b/board/freescale/ls2080a/ls2080a.c
@@ -41,11 +41,13 @@
puts("\nDDR ");
print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
print_ddr_info(0);
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
if (gd->bd->bi_dram[2].size) {
puts("\nDP-DDR ");
print_size(gd->bd->bi_dram[2].size, "");
print_ddr_info(CONFIG_DP_DDR_CTRL);
}
+#endif
}
int dram_init(void)
diff --git a/board/freescale/ls2085aqds/Kconfig b/board/freescale/ls2080aqds/Kconfig
similarity index 67%
rename from board/freescale/ls2085aqds/Kconfig
rename to board/freescale/ls2080aqds/Kconfig
index 8d6acba..2f997e9 100644
--- a/board/freescale/ls2085aqds/Kconfig
+++ b/board/freescale/ls2080aqds/Kconfig
@@ -1,8 +1,8 @@
-if TARGET_LS2085AQDS
+if TARGET_LS2080AQDS
config SYS_BOARD
- default "ls2085aqds"
+ default "ls2080aqds"
config SYS_VENDOR
default "freescale"
@@ -11,6 +11,6 @@
default "fsl-layerscape"
config SYS_CONFIG_NAME
- default "ls2085aqds"
+ default "ls2080aqds"
endif
diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS
new file mode 100644
index 0000000..3d82482
--- /dev/null
+++ b/board/freescale/ls2080aqds/MAINTAINERS
@@ -0,0 +1,8 @@
+LS2080A BOARD
+M: Prabhakar Kushwaha <prabhakar@freescale.com>
+S: Maintained
+F: board/freescale/ls2080aqds/
+F: board/freescale/ls2080a/ls2080aqds.c
+F: include/configs/ls2080aqds.h
+F: configs/ls2080aqds_defconfig
+F: configs/ls2080aqds_nand_defconfig
diff --git a/board/freescale/ls2085aqds/Makefile b/board/freescale/ls2080aqds/Makefile
similarity index 83%
rename from board/freescale/ls2085aqds/Makefile
rename to board/freescale/ls2080aqds/Makefile
index da69a7d..e0da8a5 100644
--- a/board/freescale/ls2085aqds/Makefile
+++ b/board/freescale/ls2080aqds/Makefile
@@ -4,6 +4,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += ls2085aqds.o
+obj-y += ls2080aqds.o
obj-y += ddr.o
obj-y += eth.o
diff --git a/board/freescale/ls2085aqds/README b/board/freescale/ls2080aqds/README
similarity index 95%
rename from board/freescale/ls2085aqds/README
rename to board/freescale/ls2080aqds/README
index e4a6f69..a4abb7e 100644
--- a/board/freescale/ls2085aqds/README
+++ b/board/freescale/ls2080aqds/README
@@ -1,19 +1,19 @@
Overview
--------
-The LS2085A Development System (QDS) is a high-performance computing,
-evaluation, and development platform that supports the QorIQ LS2085A
-Layerscape Architecture processor. The LS2085AQDS provides validation and
-SW development platform for the Freescale LS2085A processor series, with
+The LS2080A Development System (QDS) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS2080A
+Layerscape Architecture processor. The LS2080AQDS provides validation and
+SW development platform for the Freescale LS2080A processor series, with
a complete debugging environment.
-LS2085A SoC Overview
+LS2080A SoC Overview
------------------
-The LS2085A integrated multicore processor combines eight ARM Cortex-A57
+The LS2080A integrated multicore processor combines eight ARM Cortex-A57
processor cores with high-performance data path acceleration logic and network
and peripheral bus interfaces required for networking, telecom/datacom,
wireless infrastructure, and mil/aerospace applications.
-The LS2085A SoC includes the following function and features:
+The LS2080A SoC includes the following function and features:
- Eight 64-bit ARM Cortex-A57 CPUs
- 1 MB platform cache with ECC
@@ -50,7 +50,7 @@
- Service processor (SP) provides pre-boot initialization and secure-boot
capabilities
- LS2085AQDS board Overview
+ LS2080AQDS board Overview
-----------------------
- SERDES Connections, 16 lanes supporting:
- PCI Express - 3.0
diff --git a/board/freescale/ls2085aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c
similarity index 98%
rename from board/freescale/ls2085aqds/ddr.c
rename to board/freescale/ls2080aqds/ddr.c
index 8d71ae1..ae681de 100644
--- a/board/freescale/ls2085aqds/ddr.c
+++ b/board/freescale/ls2080aqds/ddr.c
@@ -15,7 +15,9 @@
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
+#endif
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
ulong ddr_freq;
int slot;
@@ -79,7 +81,7 @@
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
pbsp->wrlvl_ctl_3);
-
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
if (ctrl_num == CONFIG_DP_DDR_CTRL) {
/* force DDR bus width to 32 bits */
popts->data_bus_width = 1;
@@ -114,6 +116,7 @@
pdimm[slot].dq_mapping[16] = 0;
pdimm[slot].dq_mapping[17] = 0;
}
+#endif
/* To work at higher than 1333MT/s */
popts->half_strength_driver_enable = 0;
/*
diff --git a/board/freescale/ls2085aqds/ddr.h b/board/freescale/ls2080aqds/ddr.h
similarity index 100%
rename from board/freescale/ls2085aqds/ddr.h
rename to board/freescale/ls2080aqds/ddr.h
diff --git a/board/freescale/ls2085aqds/eth.c b/board/freescale/ls2080aqds/eth.c
similarity index 88%
rename from board/freescale/ls2085aqds/eth.c
rename to board/freescale/ls2080aqds/eth.c
index d116cd5..0637ecf 100644
--- a/board/freescale/ls2085aqds/eth.c
+++ b/board/freescale/ls2080aqds/eth.c
@@ -18,16 +18,16 @@
#include "../common/qixis.h"
-#include "ls2085aqds_qixis.h"
+#include "ls2080aqds_qixis.h"
#ifdef CONFIG_FSL_MC_ENET
- /* - In LS2085A there are only 16 SERDES lanes, spread across 2 SERDES banks.
+ /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
* Bank 1 -> Lanes A, B, C, D, E, F, G, H
* Bank 2 -> Lanes A,B, C, D, E, F, G, H
*/
- /* Mapping of 16 SERDES lanes to LS2085A QDS board slots. A value of '0' here
+ /* Mapping of 16 SERDES lanes to LS2080A QDS board slots. A value of '0' here
* means that the mapping must be determined dynamically, or that the lane
* maps to something other than a board slot.
*/
@@ -74,16 +74,16 @@
#define SFP_TX 0
static const char * const mdio_names[] = {
- "LS2085A_QDS_MDIO0",
- "LS2085A_QDS_MDIO1",
- "LS2085A_QDS_MDIO2",
- "LS2085A_QDS_MDIO3",
- "LS2085A_QDS_MDIO4",
- "LS2085A_QDS_MDIO5",
+ "LS2080A_QDS_MDIO0",
+ "LS2080A_QDS_MDIO1",
+ "LS2080A_QDS_MDIO2",
+ "LS2080A_QDS_MDIO3",
+ "LS2080A_QDS_MDIO4",
+ "LS2080A_QDS_MDIO5",
DEFAULT_WRIOP_MDIO2_NAME,
};
-struct ls2085a_qds_mdio {
+struct ls2080a_qds_mdio {
u8 muxval;
struct mii_dev *realbus;
};
@@ -95,7 +95,7 @@
int i, j, ret;
int dpmac_id = 0, dpmac, mii_bus = 0;
unsigned short value;
- char dev[2][20] = {"LS2085A_QDS_MDIO0", "LS2085A_QDS_MDIO3"};
+ char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60};
uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
@@ -222,7 +222,7 @@
uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
- const char *dev = "LS2085A_QDS_MDIO0";
+ const char *dev = "LS2080A_QDS_MDIO0";
int ret = 0;
unsigned short value;
@@ -318,7 +318,7 @@
return;
}
-static const char *ls2085a_qds_mdio_name_for_muxval(u8 muxval)
+static const char *ls2080a_qds_mdio_name_for_muxval(u8 muxval)
{
return mdio_names[muxval];
}
@@ -326,7 +326,7 @@
struct mii_dev *mii_dev_for_muxval(u8 muxval)
{
struct mii_dev *bus;
- const char *name = ls2085a_qds_mdio_name_for_muxval(muxval);
+ const char *name = ls2080a_qds_mdio_name_for_muxval(muxval);
if (!name) {
printf("No bus for muxval %x\n", muxval);
@@ -343,7 +343,7 @@
return bus;
}
-static void ls2085a_qds_enable_SFP_TX(u8 muxval)
+static void ls2080a_qds_enable_SFP_TX(u8 muxval)
{
u8 brdcfg9;
@@ -353,7 +353,7 @@
QIXIS_WRITE(brdcfg[9], brdcfg9);
}
-static void ls2085a_qds_mux_mdio(u8 muxval)
+static void ls2080a_qds_mux_mdio(u8 muxval)
{
u8 brdcfg4;
@@ -365,54 +365,54 @@
}
}
-static int ls2085a_qds_mdio_read(struct mii_dev *bus, int addr,
+static int ls2080a_qds_mdio_read(struct mii_dev *bus, int addr,
int devad, int regnum)
{
- struct ls2085a_qds_mdio *priv = bus->priv;
+ struct ls2080a_qds_mdio *priv = bus->priv;
- ls2085a_qds_mux_mdio(priv->muxval);
+ ls2080a_qds_mux_mdio(priv->muxval);
return priv->realbus->read(priv->realbus, addr, devad, regnum);
}
-static int ls2085a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+static int ls2080a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
int regnum, u16 value)
{
- struct ls2085a_qds_mdio *priv = bus->priv;
+ struct ls2080a_qds_mdio *priv = bus->priv;
- ls2085a_qds_mux_mdio(priv->muxval);
+ ls2080a_qds_mux_mdio(priv->muxval);
return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
}
-static int ls2085a_qds_mdio_reset(struct mii_dev *bus)
+static int ls2080a_qds_mdio_reset(struct mii_dev *bus)
{
- struct ls2085a_qds_mdio *priv = bus->priv;
+ struct ls2080a_qds_mdio *priv = bus->priv;
return priv->realbus->reset(priv->realbus);
}
-static int ls2085a_qds_mdio_init(char *realbusname, u8 muxval)
+static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval)
{
- struct ls2085a_qds_mdio *pmdio;
+ struct ls2080a_qds_mdio *pmdio;
struct mii_dev *bus = mdio_alloc();
if (!bus) {
- printf("Failed to allocate ls2085a_qds MDIO bus\n");
+ printf("Failed to allocate ls2080a_qds MDIO bus\n");
return -1;
}
pmdio = malloc(sizeof(*pmdio));
if (!pmdio) {
- printf("Failed to allocate ls2085a_qds private data\n");
+ printf("Failed to allocate ls2080a_qds private data\n");
free(bus);
return -1;
}
- bus->read = ls2085a_qds_mdio_read;
- bus->write = ls2085a_qds_mdio_write;
- bus->reset = ls2085a_qds_mdio_reset;
- sprintf(bus->name, ls2085a_qds_mdio_name_for_muxval(muxval));
+ bus->read = ls2080a_qds_mdio_read;
+ bus->write = ls2080a_qds_mdio_write;
+ bus->reset = ls2080a_qds_mdio_reset;
+ sprintf(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval));
pmdio->realbus = miiphy_get_dev_by_name(realbusname);
@@ -511,7 +511,7 @@
}
}
-void ls2085a_handle_phy_interface_sgmii(int dpmac_id)
+void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
{
int lane, slot;
struct mii_dev *bus;
@@ -632,7 +632,7 @@
}
}
-void ls2085a_handle_phy_interface_qsgmii(int dpmac_id)
+void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
{
int lane = 0, slot;
struct mii_dev *bus;
@@ -706,7 +706,7 @@
qsgmii_configure_repeater(dpmac_id);
}
-void ls2085a_handle_phy_interface_xsgmii(int i)
+void ls2080a_handle_phy_interface_xsgmii(int i)
{
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
@@ -725,7 +725,7 @@
* error.
*/
wriop_set_phy_address(i, i + 4);
- ls2085a_qds_enable_SFP_TX(SFP_TX);
+ ls2080a_qds_enable_SFP_TX(SFP_TX);
break;
default:
@@ -778,25 +778,25 @@
fm_memac_mdio_init(bis, memac_mdio1_info);
/* Register the muxing front-ends to the MDIO buses */
- ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
- ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
- ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
- ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
- ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
- ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
+ ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
+ ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
+ ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
+ ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
+ ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
+ ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
- ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
+ ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
switch (wriop_get_enet_if(i)) {
case PHY_INTERFACE_MODE_QSGMII:
- ls2085a_handle_phy_interface_qsgmii(i);
+ ls2080a_handle_phy_interface_qsgmii(i);
break;
case PHY_INTERFACE_MODE_SGMII:
- ls2085a_handle_phy_interface_sgmii(i);
+ ls2080a_handle_phy_interface_sgmii(i);
break;
case PHY_INTERFACE_MODE_XGMII:
- ls2085a_handle_phy_interface_xsgmii(i);
+ ls2080a_handle_phy_interface_xsgmii(i);
break;
default:
break;
diff --git a/board/freescale/ls2085aqds/ls2085aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
similarity index 98%
rename from board/freescale/ls2085aqds/ls2085aqds.c
rename to board/freescale/ls2080aqds/ls2080aqds.c
index 36b059f..1f99072 100644
--- a/board/freescale/ls2085aqds/ls2085aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -21,7 +21,7 @@
#include <hwconfig.h>
#include "../common/qixis.h"
-#include "ls2085aqds_qixis.h"
+#include "ls2080aqds_qixis.h"
#define PIN_MUX_SEL_SDHC 0x00
#define PIN_MUX_SEL_DSPI 0x0a
@@ -226,11 +226,13 @@
puts("\nDDR ");
print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
print_ddr_info(0);
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
if (gd->bd->bi_dram[2].size) {
puts("\nDP-DDR ");
print_size(gd->bd->bi_dram[2].size, "");
print_ddr_info(CONFIG_DP_DDR_CTRL);
}
+#endif
}
int dram_init(void)
diff --git a/board/freescale/ls2085aqds/ls2085aqds_qixis.h b/board/freescale/ls2080aqds/ls2080aqds_qixis.h
similarity index 100%
rename from board/freescale/ls2085aqds/ls2085aqds_qixis.h
rename to board/freescale/ls2080aqds/ls2080aqds_qixis.h
diff --git a/board/freescale/ls2085aqds/Kconfig b/board/freescale/ls2080ardb/Kconfig
similarity index 67%
copy from board/freescale/ls2085aqds/Kconfig
copy to board/freescale/ls2080ardb/Kconfig
index 8d6acba..fe02575 100644
--- a/board/freescale/ls2085aqds/Kconfig
+++ b/board/freescale/ls2080ardb/Kconfig
@@ -1,8 +1,8 @@
-if TARGET_LS2085AQDS
+if TARGET_LS2080ARDB
config SYS_BOARD
- default "ls2085aqds"
+ default "ls2080ardb"
config SYS_VENDOR
default "freescale"
@@ -11,6 +11,6 @@
default "fsl-layerscape"
config SYS_CONFIG_NAME
- default "ls2085aqds"
+ default "ls2080ardb"
endif
diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS
new file mode 100644
index 0000000..aac8110
--- /dev/null
+++ b/board/freescale/ls2080ardb/MAINTAINERS
@@ -0,0 +1,8 @@
+LS2080A BOARD
+M: Prabhakar Kushwaha <prabhakar@freescale.com>
+S: Maintained
+F: board/freescale/ls2080ardb/
+F: board/freescale/ls2080a/ls2080ardb.c
+F: include/configs/ls2080ardb.h
+F: configs/ls2080ardb_defconfig
+F: configs/ls2080ardb_nand_defconfig
diff --git a/board/freescale/ls2085ardb/Makefile b/board/freescale/ls2080ardb/Makefile
similarity index 72%
rename from board/freescale/ls2085ardb/Makefile
rename to board/freescale/ls2080ardb/Makefile
index de383cc..6a52167 100644
--- a/board/freescale/ls2085ardb/Makefile
+++ b/board/freescale/ls2080ardb/Makefile
@@ -4,5 +4,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += ls2085ardb.o eth_ls2085rdb.o
+obj-y += ls2080ardb.o eth_ls2080rdb.o
obj-y += ddr.o
diff --git a/board/freescale/ls2085ardb/README b/board/freescale/ls2080ardb/README
similarity index 94%
rename from board/freescale/ls2085ardb/README
rename to board/freescale/ls2080ardb/README
index 2f18243..7fc2569 100644
--- a/board/freescale/ls2085ardb/README
+++ b/board/freescale/ls2080ardb/README
@@ -1,17 +1,17 @@
Overview
--------
-The LS2085A Reference Design (RDB) is a high-performance computing,
-evaluation, and development platform that supports the QorIQ LS2085A
+The LS2080A Reference Design (RDB) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS2080A
Layerscape Architecture processor.
-LS2085A SoC Overview
+LS2080A SoC Overview
------------------
-The LS2085A integrated multicore processor combines eight ARM Cortex-A57
+The LS2080A integrated multicore processor combines eight ARM Cortex-A57
processor cores with high-performance data path acceleration logic and network
and peripheral bus interfaces required for networking, telecom/datacom,
wireless infrastructure, and mil/aerospace applications.
-The LS2085A SoC includes the following function and features:
+The LS2080A SoC includes the following function and features:
- Eight 64-bit ARM Cortex-A57 CPUs
- 1 MB platform cache with ECC
@@ -48,7 +48,7 @@
- Service processor (SP) provides pre-boot initialization and secure-boot
capabilities
- LS2085ARDB board Overview
+ LS2080ARDB board Overview
-----------------------
- SERDES Connections, 16 lanes supporting:
- PCI Express - 3.0
diff --git a/board/freescale/ls2085aqds/ddr.c b/board/freescale/ls2080ardb/ddr.c
similarity index 98%
copy from board/freescale/ls2085aqds/ddr.c
copy to board/freescale/ls2080ardb/ddr.c
index 8d71ae1..ae681de 100644
--- a/board/freescale/ls2085aqds/ddr.c
+++ b/board/freescale/ls2080ardb/ddr.c
@@ -15,7 +15,9 @@
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
+#endif
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
ulong ddr_freq;
int slot;
@@ -79,7 +81,7 @@
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
pbsp->wrlvl_ctl_3);
-
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
if (ctrl_num == CONFIG_DP_DDR_CTRL) {
/* force DDR bus width to 32 bits */
popts->data_bus_width = 1;
@@ -114,6 +116,7 @@
pdimm[slot].dq_mapping[16] = 0;
pdimm[slot].dq_mapping[17] = 0;
}
+#endif
/* To work at higher than 1333MT/s */
popts->half_strength_driver_enable = 0;
/*
diff --git a/board/freescale/ls2085ardb/ddr.h b/board/freescale/ls2080ardb/ddr.h
similarity index 100%
rename from board/freescale/ls2085ardb/ddr.h
rename to board/freescale/ls2080ardb/ddr.h
diff --git a/board/freescale/ls2085ardb/eth_ls2085rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c
similarity index 97%
rename from board/freescale/ls2085ardb/eth_ls2085rdb.c
rename to board/freescale/ls2080ardb/eth_ls2080rdb.c
index d578757..db50e4e 100644
--- a/board/freescale/ls2085ardb/eth_ls2085rdb.c
+++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c
@@ -97,7 +97,7 @@
break;
default:
- printf("SerDes1 protocol 0x%x is not supported on LS2085aRDB\n",
+ printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n",
srds_s1);
break;
}
diff --git a/board/freescale/ls2085ardb/ls2085ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
similarity index 98%
rename from board/freescale/ls2085ardb/ls2085ardb.c
rename to board/freescale/ls2080ardb/ls2080ardb.c
index 761d7c8..2ae9d6c 100644
--- a/board/freescale/ls2085ardb/ls2085ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -20,7 +20,7 @@
#include <asm/arch/soc.h>
#include "../common/qixis.h"
-#include "ls2085ardb_qixis.h"
+#include "ls2080ardb_qixis.h"
#define PIN_MUX_SEL_SDHC 0x00
#define PIN_MUX_SEL_DSPI 0x0a
@@ -192,11 +192,13 @@
puts("\nDDR ");
print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
print_ddr_info(0);
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
if (gd->bd->bi_dram[2].size) {
puts("\nDP-DDR ");
print_size(gd->bd->bi_dram[2].size, "");
print_ddr_info(CONFIG_DP_DDR_CTRL);
}
+#endif
}
int dram_init(void)
diff --git a/board/freescale/ls2085ardb/ls2085ardb_qixis.h b/board/freescale/ls2080ardb/ls2080ardb_qixis.h
similarity index 100%
rename from board/freescale/ls2085ardb/ls2085ardb_qixis.h
rename to board/freescale/ls2080ardb/ls2080ardb_qixis.h
diff --git a/board/freescale/ls2085a/MAINTAINERS b/board/freescale/ls2085a/MAINTAINERS
deleted file mode 100644
index 90b4e47..0000000
--- a/board/freescale/ls2085a/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-LS2085A BOARD
-M: York Sun <yorksun@freescale.com>
-S: Maintained
-F: board/freescale/ls2085a/
-F: include/configs/ls2085a_emu.h
-F: configs/ls2085a_emu_defconfig
-F: include/configs/ls2085a_simu.h
-F: configs/ls2085a_simu_defconfig
diff --git a/board/freescale/ls2085a/Makefile b/board/freescale/ls2085a/Makefile
deleted file mode 100644
index 701b35c..0000000
--- a/board/freescale/ls2085a/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Copyright 2014 Freescale Semiconductor
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += ls2085a.o
-obj-y += ddr.o
diff --git a/board/freescale/ls2085aqds/MAINTAINERS b/board/freescale/ls2085aqds/MAINTAINERS
deleted file mode 100644
index fbed672..0000000
--- a/board/freescale/ls2085aqds/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-LS2085A BOARD
-M: Prabhakar Kushwaha <prabhakar@freescale.com>
-S: Maintained
-F: board/freescale/ls2085aqds/
-F: board/freescale/ls2085a/ls2085aqds.c
-F: include/configs/ls2085aqds.h
-F: configs/ls2085aqds_defconfig
-F: configs/ls2085aqds_nand_defconfig
diff --git a/board/freescale/ls2085ardb/Kconfig b/board/freescale/ls2085ardb/Kconfig
deleted file mode 100644
index cb40db9..0000000
--- a/board/freescale/ls2085ardb/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-
-if TARGET_LS2085ARDB
-
-config SYS_BOARD
- default "ls2085ardb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_SOC
- default "fsl-layerscape"
-
-config SYS_CONFIG_NAME
- default "ls2085ardb"
-
-endif
diff --git a/board/freescale/ls2085ardb/MAINTAINERS b/board/freescale/ls2085ardb/MAINTAINERS
deleted file mode 100644
index d5cce40..0000000
--- a/board/freescale/ls2085ardb/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-LS2085A BOARD
-M: Prabhakar Kushwaha <prabhakar@freescale.com>
-S: Maintained
-F: board/freescale/ls2085ardb/
-F: board/freescale/ls2085a/ls2085ardb.c
-F: include/configs/ls2085ardb.h
-F: configs/ls2085ardb_defconfig
-F: configs/ls2085ardb_nand_defconfig
diff --git a/board/freescale/ls2085ardb/ddr.c b/board/freescale/ls2085ardb/ddr.c
deleted file mode 100644
index 8d71ae1..0000000
--- a/board/freescale/ls2085ardb/ddr.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include "ddr.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
- int slot;
-
- if (ctrl_num > 2) {
- printf("Not supported controller number %d\n", ctrl_num);
- return;
- }
-
- for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) {
- if (pdimm[slot].n_ranks)
- break;
- }
-
- if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR)
- return;
-
- /*
- * we use identical timing for all slots. If needed, change the code
- * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
- */
- if (popts->registered_dimm_en)
- pbsp = rdimms[ctrl_num];
- else
- pbsp = udimms[ctrl_num];
-
-
- /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm[slot].n_ranks &&
- (pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found for data rate %lu MT/s\n"
- "Trying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- } else {
- panic("DIMM is not supported by this board");
- }
-found:
- debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
- "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
- pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
- pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
- pbsp->wrlvl_ctl_3);
-
- if (ctrl_num == CONFIG_DP_DDR_CTRL) {
- /* force DDR bus width to 32 bits */
- popts->data_bus_width = 1;
- popts->otf_burst_chop_en = 0;
- popts->burst_length = DDR_BL8;
- popts->bstopre = 0; /* enable auto precharge */
- /*
- * Layout optimization results byte mapping
- * Byte 0 -> Byte ECC
- * Byte 1 -> Byte 3
- * Byte 2 -> Byte 2
- * Byte 3 -> Byte 1
- * Byte ECC -> Byte 0
- */
- dq_mapping_0 = pdimm[slot].dq_mapping[0];
- dq_mapping_2 = pdimm[slot].dq_mapping[2];
- dq_mapping_3 = pdimm[slot].dq_mapping[3];
- pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8];
- pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9];
- pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6];
- pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7];
- pdimm[slot].dq_mapping[6] = dq_mapping_2;
- pdimm[slot].dq_mapping[7] = dq_mapping_3;
- pdimm[slot].dq_mapping[8] = dq_mapping_0;
- pdimm[slot].dq_mapping[9] = 0;
- pdimm[slot].dq_mapping[10] = 0;
- pdimm[slot].dq_mapping[11] = 0;
- pdimm[slot].dq_mapping[12] = 0;
- pdimm[slot].dq_mapping[13] = 0;
- pdimm[slot].dq_mapping[14] = 0;
- pdimm[slot].dq_mapping[15] = 0;
- pdimm[slot].dq_mapping[16] = 0;
- pdimm[slot].dq_mapping[17] = 0;
- }
- /* To work at higher than 1333MT/s */
- popts->half_strength_driver_enable = 0;
- /*
- * Write leveling override
- */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0x0; /* 32 clocks */
-
- /*
- * Rtt and Rtt_WR override
- */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
- if (ddr_freq < 2350) {
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
- DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
- DDR_CDR2_VREF_RANGE_2;
- } else {
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
- DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) |
- DDR_CDR2_VREF_RANGE_2;
- }
-}
-
-phys_size_t initdram(int board_type)
-{
- phys_size_t dram_size;
-
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
- return fsl_ddr_sdram_size();
-#else
- puts("Initializing DDR....using SPD\n");
-
- dram_size = fsl_ddr_sdram();
-#endif
-
- return dram_size;
-}
-
-void dram_init_banksize(void)
-{
-#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
- phys_size_t dp_ddr_size;
-#endif
-
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
- gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
- gd->bd->bi_dram[1].size = gd->ram_size -
- CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
- } else {
- gd->bd->bi_dram[0].size = gd->ram_size;
- }
-
-#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
- /* initialize DP-DDR here */
- puts("DP-DDR: ");
- /*
- * DDR controller use 0 as the base address for binding.
- * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
- */
- dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
- CONFIG_DP_DDR_CTRL,
- CONFIG_DP_DDR_NUM_CTRLS,
- CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
- NULL, NULL, NULL);
- if (dp_ddr_size) {
- gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
- gd->bd->bi_dram[2].size = dp_ddr_size;
- } else {
- puts("Not detected");
- }
-#endif
-}