ARM: dts: uniphier: sync Device Trees with upstream Linux
I periodically sync Device Trees for better maintainability.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
diff --git a/arch/arm/dts/uniphier-ph1-ld11.dtsi b/arch/arm/dts/uniphier-ph1-ld11.dtsi
index e485f90..8901a79 100644
--- a/arch/arm/dts/uniphier-ph1-ld11.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld11.dtsi
@@ -1,11 +1,14 @@
/*
* Device Tree Source for UniPhier PH1-LD11 SoC
*
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
+/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
+
/ {
compatible = "socionext,ph1-ld11";
#address-cells = <2>;
@@ -16,24 +19,41 @@
#address-cells = <2>;
#size-cells = <0>;
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+
- cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x000>;
enable-method = "spin-table";
- cpu-release-addr = <0 0x80000100>;
+ cpu-release-addr = <0 0x80000000>;
};
- cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x001>;
enable-method = "spin-table";
- cpu-release-addr = <0 0x80000100>;
+ cpu-release-addr = <0 0x80000000>;
};
};
clocks {
+ refclk: ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
uart_clk: uart_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -60,6 +80,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
+ u-boot,dm-pre-reloc;
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
@@ -183,6 +204,8 @@
reg = <0x58c00000 0x400>;
#address-cells = <2>;
#size-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_system_bus>;
};
smpctrl@59800000 {
@@ -226,9 +249,15 @@
#clock-cells = <1>;
};
- pinctrl: pinctrl@5f801000 {
- compatible = "socionext,ph1-ld11-pinctrl", "syscon";
- reg = <0x5f801000 0xe00>;
+ soc-glue@5f800000 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0x5f800000 0x2000>;
+ u-boot,dm-pre-reloc;
+
+ pinctrl: pinctrl {
+ compatible = "socionext,uniphier-ld11-pinctrl";
+ u-boot,dm-pre-reloc;
+ };
};
gic: interrupt-controller@5fe00000 {