diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index bb3b116..3b5d6da 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -1,6 +1,7 @@
 dtb-y += link.dtb \
 	chromebook_link.dtb \
-	alex.dtb
+	alex.dtb \
+	crownbay.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
new file mode 100644
index 0000000..399dafb
--- /dev/null
+++ b/arch/x86/dts/crownbay.dts
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+/include/ "coreboot.dtsi"
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	model = "Intel Crown Bay";
+	compatible = "intel,crownbay", "intel,queensbay";
+
+	config {
+		silent_console = <0>;
+	};
+
+	gpioa {
+		compatible = "intel,ich6-gpio";
+		u-boot,dm-pre-reloc;
+		reg = <0 0x20>;
+		bank-name = "A";
+	};
+
+	gpiob {
+		compatible = "intel,ich6-gpio";
+		u-boot,dm-pre-reloc;
+		reg = <0x20 0x20>;
+		bank-name = "B";
+	};
+
+	serial {
+		reg = <0x3f8 8>;
+		clock-frequency = <115200>;
+	};
+
+	chosen { };
+	memory { device_type = "memory"; reg = <0 0>; };
+
+	spi {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "intel,ich7";
+		spi-flash@0 {
+			reg = <0>;
+			compatible = "sst,25vf016b", "spi-flash";
+			memory-map = <0xffe00000 0x00200000>;
+		};
+	};
+};