dm: tegra: spi: Convert to driver model
This converts the Tegra SPI drivers to use driver model. This is tested
on:
- Tegra20 - trimslice
- Tegra30 - beaver
- Tegra124 - dalmore
(not tested on Tegra124)
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c
index 664de6e..213fa5f 100644
--- a/drivers/spi/tegra20_slink.c
+++ b/drivers/spi/tegra20_slink.c
@@ -22,14 +22,13 @@
*/
#include <common.h>
-#include <malloc.h>
+#include <dm.h>
#include <asm/io.h>
-#include <asm/gpio.h>
#include <asm/arch/clock.h>
#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra20/tegra20_slink.h>
#include <spi.h>
#include <fdtdec.h>
+#include "tegra_spi.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -87,130 +86,70 @@
u32 rx_fifo; /* SLINK_RX_FIFO_0 reg off 180h */
};
-struct tegra_spi_ctrl {
+struct tegra30_spi_priv {
struct spi_regs *regs;
unsigned int freq;
unsigned int mode;
int periph_id;
int valid;
+ int last_transaction_us;
};
struct tegra_spi_slave {
struct spi_slave slave;
- struct tegra_spi_ctrl *ctrl;
+ struct tegra30_spi_priv *ctrl;
};
-static struct tegra_spi_ctrl spi_ctrls[CONFIG_TEGRA_SLINK_CTRLS];
-
-static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
-{
- return container_of(slave, struct tegra_spi_slave, slave);
-}
-
-int tegra30_spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- if (bus >= CONFIG_TEGRA_SLINK_CTRLS || cs > 3 || !spi_ctrls[bus].valid)
- return 0;
- else
- return 1;
-}
-
-struct spi_slave *tegra30_spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
+static int tegra30_spi_ofdata_to_platdata(struct udevice *bus)
{
- struct tegra_spi_slave *spi;
+ struct tegra_spi_platdata *plat = bus->platdata;
+ const void *blob = gd->fdt_blob;
+ int node = bus->of_offset;
- debug("%s: bus: %u, cs: %u, max_hz: %u, mode: %u\n", __func__,
- bus, cs, max_hz, mode);
-
- if (!spi_cs_is_valid(bus, cs)) {
- printf("SPI error: unsupported bus %d / chip select %d\n",
- bus, cs);
- return NULL;
- }
+ plat->base = fdtdec_get_addr(blob, node, "reg");
+ plat->periph_id = clock_decode_periph_id(blob, node);
- if (max_hz > TEGRA_SPI_MAX_FREQ) {
- printf("SPI error: unsupported frequency %d Hz. Max frequency"
- " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
- return NULL;
+ if (plat->periph_id == PERIPH_ID_NONE) {
+ debug("%s: could not decode periph id %d\n", __func__,
+ plat->periph_id);
+ return -FDT_ERR_NOTFOUND;
}
- spi = spi_alloc_slave(struct tegra_spi_slave, bus, cs);
- if (!spi) {
- printf("SPI error: malloc of SPI structure failed\n");
- return NULL;
- }
- spi->ctrl = &spi_ctrls[bus];
- if (!spi->ctrl) {
- printf("SPI error: could not find controller for bus %d\n",
- bus);
- return NULL;
- }
+ /* Use 500KHz as a suitable default */
+ plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
+ 500000);
+ plat->deactivate_delay_us = fdtdec_get_int(blob, node,
+ "spi-deactivate-delay", 0);
+ debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
+ __func__, plat->base, plat->periph_id, plat->frequency,
+ plat->deactivate_delay_us);
- if (max_hz < spi->ctrl->freq) {
- debug("%s: limiting frequency from %u to %u\n", __func__,
- spi->ctrl->freq, max_hz);
- spi->ctrl->freq = max_hz;
- }
- spi->ctrl->mode = mode;
-
- return &spi->slave;
+ return 0;
}
-void tegra30_spi_free_slave(struct spi_slave *slave)
+static int tegra30_spi_probe(struct udevice *bus)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
-
- free(spi);
-}
+ struct tegra_spi_platdata *plat = dev_get_platdata(bus);
+ struct tegra30_spi_priv *priv = dev_get_priv(bus);
-int tegra30_spi_init(int *node_list, int count)
-{
- struct tegra_spi_ctrl *ctrl;
- int i;
- int node = 0;
- int found = 0;
+ priv->regs = (struct spi_regs *)plat->base;
- for (i = 0; i < count; i++) {
- ctrl = &spi_ctrls[i];
- node = node_list[i];
+ priv->last_transaction_us = timer_get_us();
+ priv->freq = plat->frequency;
+ priv->periph_id = plat->periph_id;
- ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob,
- node, "reg");
- if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) {
- debug("%s: no slink register found\n", __func__);
- continue;
- }
- ctrl->freq = fdtdec_get_int(gd->fdt_blob, node,
- "spi-max-frequency", 0);
- if (!ctrl->freq) {
- debug("%s: no slink max frequency found\n", __func__);
- continue;
- }
-
- ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
- if (ctrl->periph_id == PERIPH_ID_NONE) {
- debug("%s: could not decode periph id\n", __func__);
- continue;
- }
- ctrl->valid = 1;
- found = 1;
-
- debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
- __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
- }
- return !found;
+ return 0;
}
-int tegra30_spi_claim_bus(struct spi_slave *slave)
+static int tegra30_spi_claim_bus(struct udevice *bus)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
- struct spi_regs *regs = spi->ctrl->regs;
+ struct tegra30_spi_priv *priv = dev_get_priv(bus);
+ struct spi_regs *regs = priv->regs;
u32 reg;
/* Change SPI clock to correct frequency, PLLP_OUT0 source */
- clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH,
- spi->ctrl->freq);
+ clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
+ priv->freq);
/* Clear stale status here */
reg = SLINK_STAT_RDY | SLINK_STAT_RXF_FLUSH | SLINK_STAT_TXF_FLUSH | \
@@ -227,29 +166,46 @@
return 0;
}
-void tegra30_spi_cs_activate(struct spi_slave *slave)
+static void spi_cs_activate(struct udevice *dev)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
- struct spi_regs *regs = spi->ctrl->regs;
+ struct udevice *bus = dev->parent;
+ struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
+ struct tegra30_spi_priv *priv = dev_get_priv(bus);
+
+ /* If it's too soon to do another transaction, wait */
+ if (pdata->deactivate_delay_us &&
+ priv->last_transaction_us) {
+ ulong delay_us; /* The delay completed so far */
+ delay_us = timer_get_us() - priv->last_transaction_us;
+ if (delay_us < pdata->deactivate_delay_us)
+ udelay(pdata->deactivate_delay_us - delay_us);
+ }
/* CS is negated on Tegra, so drive a 1 to get a 0 */
- setbits_le32(®s->command, SLINK_CMD_CS_VAL);
+ setbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL);
}
-void tegra30_spi_cs_deactivate(struct spi_slave *slave)
+static void spi_cs_deactivate(struct udevice *dev)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
- struct spi_regs *regs = spi->ctrl->regs;
+ struct udevice *bus = dev->parent;
+ struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
+ struct tegra30_spi_priv *priv = dev_get_priv(bus);
/* CS is negated on Tegra, so drive a 0 to get a 1 */
- clrbits_le32(®s->command, SLINK_CMD_CS_VAL);
+ clrbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL);
+
+ /* Remember time of this transaction so we can honour the bus delay */
+ if (pdata->deactivate_delay_us)
+ priv->last_transaction_us = timer_get_us();
}
-int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
- const void *data_out, void *data_in, unsigned long flags)
+static int tegra30_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *data_out, void *data_in,
+ unsigned long flags)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
- struct spi_regs *regs = spi->ctrl->regs;
+ struct udevice *bus = dev->parent;
+ struct tegra30_spi_priv *priv = dev_get_priv(bus);
+ struct spi_regs *regs = priv->regs;
u32 reg, tmpdout, tmpdin = 0;
const u8 *dout = data_out;
u8 *din = data_in;
@@ -257,7 +213,7 @@
int ret;
debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
- __func__, slave->bus, slave->cs, dout, din, bitlen);
+ __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
if (bitlen % 8)
return -1;
num_bytes = bitlen / 8;
@@ -276,11 +232,11 @@
clrsetbits_le32(®s->command2, SLINK_CMD2_SS_EN_MASK,
SLINK_CMD2_TXEN | SLINK_CMD2_RXEN |
- (slave->cs << SLINK_CMD2_SS_EN_SHIFT));
+ (spi_chip_select(dev) << SLINK_CMD2_SS_EN_SHIFT));
debug("%s entry: COMMAND2 = %08x\n", __func__, readl(®s->command2));
if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(slave);
+ spi_cs_activate(dev);
/* handle data in 32-bit chunks */
while (num_bytes > 0) {
@@ -344,7 +300,7 @@
}
if (flags & SPI_XFER_END)
- spi_cs_deactivate(slave);
+ spi_cs_deactivate(dev);
debug("%s: transfer ended. Value=%08x, status = %08x\n",
__func__, tmpdin, readl(®s->status));
@@ -357,3 +313,54 @@
return 0;
}
+
+static int tegra30_spi_set_speed(struct udevice *bus, uint speed)
+{
+ struct tegra_spi_platdata *plat = bus->platdata;
+ struct tegra30_spi_priv *priv = dev_get_priv(bus);
+
+ if (speed > plat->frequency)
+ speed = plat->frequency;
+ priv->freq = speed;
+ debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
+
+ return 0;
+}
+
+static int tegra30_spi_set_mode(struct udevice *bus, uint mode)
+{
+ struct tegra30_spi_priv *priv = dev_get_priv(bus);
+
+ priv->mode = mode;
+ debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
+
+ return 0;
+}
+
+static const struct dm_spi_ops tegra30_spi_ops = {
+ .claim_bus = tegra30_spi_claim_bus,
+ .xfer = tegra30_spi_xfer,
+ .set_speed = tegra30_spi_set_speed,
+ .set_mode = tegra30_spi_set_mode,
+ /*
+ * cs_info is not needed, since we require all chip selects to be
+ * in the device tree explicitly
+ */
+};
+
+static const struct udevice_id tegra30_spi_ids[] = {
+ { .compatible = "nvidia,tegra20-slink" },
+ { }
+};
+
+U_BOOT_DRIVER(tegra30_spi) = {
+ .name = "tegra20_slink",
+ .id = UCLASS_SPI,
+ .of_match = tegra30_spi_ids,
+ .ops = &tegra30_spi_ops,
+ .ofdata_to_platdata = tegra30_spi_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
+ .priv_auto_alloc_size = sizeof(struct tegra30_spi_priv),
+ .per_child_auto_alloc_size = sizeof(struct spi_slave),
+ .probe = tegra30_spi_probe,
+};