Merge tag 'xilinx-for-v2025.07-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx/FPGA changes for v2025.07-rc1
AMD/Xilinx:
- Synchronize enums around tcm_mode
- Access bootmode registers via firmware interface
- Setup default values for DEBUG_UART
- Fix dfu alt buffer clearing
- Convert loadpdi command to fpga
- Fix board detection code
- Minor defconfig updates
Versal:
- Wire multi_boot register
Versal Gen 2:
- Enable missing drivers
- Wire i2c FRU decoding at start
- Wire saving variables to different locations
- Disable default DEBUG_UART
- Wire USB/UFS boot and fix access via firmware interface
- Minor fixes
ZynqMP/Kria:
- Enable mkfwumdata
- Topic board update
- Enhance binman configurations
- Kria usb update
BuR:
- Add multiple Zynq based boards
cadence_ospi:
- Enable device reset
fpga:
- Add support for loading bitstream for Altera SoCs
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 57d3dd9..bcf3f4b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -303,6 +303,13 @@
zynqmp-zc1751-xm017-dc3.dtb \
zynqmp-zc1751-xm018-dc4.dtb \
zynqmp-zc1751-xm019-dc5.dtb
+dtb-$(CONFIG_TARGET_ZYNQ_BR) += \
+ zynq-brcp1_2r.dtb \
+ zynq-brcp1_1r.dtb \
+ zynq-brcp1_1r_switch.dtb \
+ zynq-brsmarc2.dtb \
+ zynq-brcp150.dtb \
+ zynq-brcp170.dtb
zynqmp-p-a2197-00-revA-x-prc-01-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-01-revA.dtbo
zynqmp-p-a2197-00-revA-x-prc-02-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-02-revA.dtbo
diff --git a/arch/arm/dts/zynq-binman-brcp1.dtsi b/arch/arm/dts/zynq-binman-brcp1.dtsi
new file mode 100644
index 0000000..3cc8ee8
--- /dev/null
+++ b/arch/arm/dts/zynq-binman-brcp1.dtsi
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 B&R Industrial Automation GmbH
+ */
+
+ #include <config.h>
+
+/ {
+ binman {
+ bootph-all;
+ filename = "flash.bin";
+ pad-byte = <0xff>;
+ align-size = <16>;
+ align = <16>;
+
+ blob@0 {
+ filename = "spl/boot.bin";
+ offset = <0x0>;
+ };
+
+ fit {
+ description = "U-Boot BR Zynq boards";
+ offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
+
+ images {
+ uboot {
+ description = "U-Boot BR Zynq";
+ type = "firmware";
+ os = "u-boot";
+ arch = "arm";
+ compression = "none";
+ load = <CONFIG_TEXT_BASE>;
+ u-boot-nodtb {
+ };
+ };
+
+ fdt-0 {
+ description = "DTB BR Zynq";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ u-boot-dtb {
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "BR Zynq";
+ firmware = "uboot";
+ fdt = "fdt-0";
+ };
+ };
+ };
+
+ blob-ext@0 {
+ filename = "blobs/cfg.img";
+ offset = <0xC0000>;
+ size = <0x10000>;
+ optional;
+ };
+
+ blob-ext@5 {
+ filename = "blobs/cfg_opt.img";
+ offset = <0xD0000>;
+ size = <0x10000>;
+ optional;
+ };
+
+ blob-ext@1 {
+ bootph-all;
+ filename = "blobs/bitstream.bit";
+ offset = <0x100000>;
+ size = <0x200000>;
+ optional;
+ };
+
+ blob-ext@4 {
+ bootph-all;
+ filename = "blobs/bitstream_update.bit";
+ offset = <0x400000>;
+ size = <0x200000>;
+ optional;
+ };
+
+ blob-ext@2 {
+ filename = "blobs/bootar.itb";
+ offset = <0x900000>;
+ size = <0x600000>;
+ optional;
+ };
+
+ blob-ext@3 {
+ filename = "blobs/dtb.bin";
+ offset = <0xF00000>;
+ size = <0x100000>;
+ optional;
+ };
+ };
+};
diff --git a/arch/arm/dts/zynq-brcp1.dtsi b/arch/arm/dts/zynq-brcp1.dtsi
new file mode 100644
index 0000000..ebaf42d
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1.dtsi
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/include/ "zynq-7000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "BRCP1 CPU";
+ compatible = "br,cp1",
+ "xlnx,zynq-7000";
+
+ aliases {
+ i2c0 = &i2c0;
+ serial0 = &uart0;
+ spi0 = &qspi;
+ mmc0 = &sdhci0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x40000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+
+ brd_rst: board_reset {
+ compatible = "br,board-reset";
+ pin = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ se_green {
+ label = "S_E_GREEN";
+ gpios = <&ledgpio 0 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ se_red {
+ label = "S_E_RED";
+ gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ rdy_f_yellow {
+ label = "RDY_F_YELLOW";
+ gpios = <&ledgpio 2 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ re_green {
+ label = "R_E_GREEN";
+ gpios = <&ledgpio 3 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ re_red {
+ label = "R_E_RED";
+ gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ plk_se_green {
+ label = "PLK_S_E_GREEN";
+ gpios = <&ledgpio 5 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ eth_se_green {
+ label = "ETH_S_E_GREEN";
+ gpios = <&ledgpio 6 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ ledgpio: max7320@5d { /* board LED */
+ status = "okay";
+ compatible = "maxim,max7320";
+ reg = <0x5d>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ ngpios = <8>;
+ };
+
+ pmic0: da9062@58 {
+ compatible = "dlg,da9062";
+ reg = <0x58>;
+ };
+};
+
+&sdhci0 {
+ status = "okay";
+ max-frequency = <25000000>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+ spi-max-frequency = <100000000>;
+
+ spi_flash: spiflash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1";
+ spi-max-frequency = <100000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+};
+
+&gpio0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/zynq-brcp150-u-boot.dtsi b/arch/arm/dts/zynq-brcp150-u-boot.dtsi
new file mode 100644
index 0000000..1bfd5f2
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp150-u-boot.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+#include "zynq-binman-brcp1.dtsi"
+
+&i2c0 {
+ bootph-all;
+};
+
+&uart0 {
+ bootph-all;
+};
+
+&qspi {
+ bootph-all;
+};
+
+&spi_flash {
+ bootph-all;
+};
+
+&gpio0 {
+ bootph-all;
+};
+
+&brd_rst {
+ bootph-all;
+};
+
+&rs232_en {
+ bootph-all;
+};
diff --git a/arch/arm/dts/zynq-brcp150.dts b/arch/arm/dts/zynq-brcp150.dts
new file mode 100644
index 0000000..1b22d37
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp150.dts
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "BRCP150 CPU";
+ compatible = "br,cp150",
+ "xlnx,zynq-7000";
+
+ aliases {
+ i2c0 = &i2c0;
+ serial0 = &uart0;
+ spi0 = &qspi;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x20000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+
+ brd_rst: board_reset {
+ compatible = "br,board-reset";
+ pin = <&gpio0 27 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* Put this pin active high to enable RS232 debug serial */
+ rs232_en: rs232_enable {
+ compatible = "br,rs232-en";
+ pin = <&gpio0 52 GPIO_ACTIVE_HIGH>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ re_green {
+ label = "R_E_GREEN";
+ gpios = <&ledgpio 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ re_red {
+ label = "R_E_RED";
+ gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ rdy_f_red {
+ label = "RDY_F_RED";
+ gpios = <&ledgpio 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ rdy_f_yellow {
+ label = "RDY_F_YELLOW";
+ gpios = <&ledgpio 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ se_green {
+ label = "S_E_GREEN";
+ gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ se_red {
+ label = "S_E_RED";
+ gpios = <&ledgpio 5 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ plk_se_green {
+ label = "PLK_S_E_GREEN";
+ gpios = <&ledgpio 6 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ eth_se_green {
+ label = "ETH_S_E_GREEN";
+ gpios = <&ledgpio 7 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ user1_green {
+ label = "USER1_GREEN";
+ gpios = <&ledgpio 12 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ user1_red {
+ label = "USER1_RED";
+ gpios = <&ledgpio 13 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ user2_green {
+ label = "USER2_GREEN";
+ gpios = <&ledgpio 14 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ user2_red {
+ label = "USER2_RED";
+ gpios = <&ledgpio 15 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "mii";
+ phy-handle = <ðernet_phy>;
+
+ ethernet_phy: emio-phy@2 {
+ reg = <2>;
+ max-speed = <100>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ ledgpio: max7320@5d { /* board LED */
+ status = "okay";
+ compatible = "maxim,max7320";
+ reg = <0x5d>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ ngpios = <16>;
+ };
+};
+
+&sdhci0 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+ spi-max-frequency = <100000000>;
+
+ spi_flash: spiflash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1";
+ spi-max-frequency = <100000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+/* Since the gem0 clock is configured EMIO this dummy entry is needed */
+&clkc {
+ clocks = <&clkc 16>;
+ clock-names = "gem0_emio_clk";
+};
diff --git a/arch/arm/dts/zynq-brcp170-u-boot.dtsi b/arch/arm/dts/zynq-brcp170-u-boot.dtsi
new file mode 100644
index 0000000..ceea610
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp170-u-boot.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+#include "zynq-binman-brcp1.dtsi"
+
+&i2c0 {
+ bootph-all;
+};
+
+&uart0 {
+ bootph-all;
+};
+
+&qspi {
+ bootph-all;
+};
+
+&spi_flash {
+ bootph-all;
+};
+
+&gpio0 {
+ bootph-all;
+};
diff --git a/arch/arm/dts/zynq-brcp170.dts b/arch/arm/dts/zynq-brcp170.dts
new file mode 100644
index 0000000..eee19ce
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp170.dts
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "BRCP170 CPU";
+ compatible = "br,cp170",
+ "xlnx,zynq-7000";
+
+ aliases {
+ i2c0 = &i2c0;
+ serial0 = &uart0;
+ spi0 = &qspi;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x20000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ re_green {
+ label = "R_E_GREEN";
+ gpios = <&ledgpio 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ re_red {
+ label = "R_E_RED";
+ gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ rdy_f_red {
+ label = "RDY_F_RED";
+ gpios = <&ledgpio 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ rdy_f_yellow {
+ label = "RDY_F_YELLOW";
+ gpios = <&ledgpio 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ se_green {
+ label = "S_E_GREEN";
+ gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ se_red {
+ label = "S_E_RED";
+ gpios = <&ledgpio 5 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ plk_se_green {
+ label = "PLK_S_E_GREEN";
+ gpios = <&ledgpio 6 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ eth_se_green {
+ label = "ETH_S_E_GREEN";
+ gpios = <&ledgpio 7 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+
+ ethernet_phy: ethernet-phy@0 {
+ reg = <0>;
+ max-speed = <100>;
+ ti,rx-internal-delay = <7>;
+ ti,tx-internal-delay = <7>;
+ ti,fifo-depth = <0>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ ledgpio: max7320@58 { /* board LED */
+ status = "okay";
+ compatible = "maxim,max7320";
+ reg = <0x58>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ ngpios = <8>;
+ };
+};
+
+&sdhci0 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+ spi-max-frequency = <100000000>;
+
+ spi_flash: spiflash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1";
+ spi-max-frequency = <100000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+};
+
+&gpio0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi b/arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi
new file mode 100644
index 0000000..58c4558
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+#include "zynq-binman-brcp1.dtsi"
+
+&i2c0 {
+ bootph-all;
+};
+
+&uart0 {
+ bootph-all;
+};
+
+&qspi {
+ bootph-all;
+};
+
+&spi_flash {
+ bootph-all;
+};
+
+&gpio0 {
+ bootph-all;
+};
+
+&brd_rst {
+ bootph-all;
+};
diff --git a/arch/arm/dts/zynq-brcp1_1r.dts b/arch/arm/dts/zynq-brcp1_1r.dts
new file mode 100644
index 0000000..fd7ae55
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1_1r.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+#include "zynq-brcp1.dtsi"
+
+/ {
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+
+ ethernet_phy: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <7>;
+ ti,tx-internal-delay = <7>;
+ ti,fifo-depth = <0>;
+ max-speed = <1000>;
+ };
+};
diff --git a/arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi b/arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi
new file mode 120000
index 0000000..5a31a05
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi
@@ -0,0 +1 @@
+zynq-brcp1_1r-u-boot.dtsi
\ No newline at end of file
diff --git a/arch/arm/dts/zynq-brcp1_1r_switch.dts b/arch/arm/dts/zynq-brcp1_1r_switch.dts
new file mode 100644
index 0000000..a68d530
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1_1r_switch.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+#include "zynq-brcp1.dtsi"
+
+/ {
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "gmii";
+
+ fixed-link {
+ speed = <100>;
+ full-duplex;
+ };
+};
+
+/* Since the gem0 clock is configured EMIO this dummy entry is needed */
+&clkc {
+ clocks = <&clkc 16>;
+ clock-names = "gem0_emio_clk";
+};
diff --git a/arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi b/arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi
new file mode 120000
index 0000000..5a31a05
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi
@@ -0,0 +1 @@
+zynq-brcp1_1r-u-boot.dtsi
\ No newline at end of file
diff --git a/arch/arm/dts/zynq-brcp1_2r.dts b/arch/arm/dts/zynq-brcp1_2r.dts
new file mode 100644
index 0000000..353d8a1
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1_2r.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+#include "zynq-brcp1.dtsi"
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+
+ ethernet_phy: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <7>;
+ ti,tx-internal-delay = <7>;
+ ti,fifo-depth = <0>;
+ max-speed = <1000>;
+ };
+};
diff --git a/arch/arm/dts/zynq-brsmarc2-u-boot.dtsi b/arch/arm/dts/zynq-brsmarc2-u-boot.dtsi
new file mode 100644
index 0000000..58c4558
--- /dev/null
+++ b/arch/arm/dts/zynq-brsmarc2-u-boot.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+#include "zynq-binman-brcp1.dtsi"
+
+&i2c0 {
+ bootph-all;
+};
+
+&uart0 {
+ bootph-all;
+};
+
+&qspi {
+ bootph-all;
+};
+
+&spi_flash {
+ bootph-all;
+};
+
+&gpio0 {
+ bootph-all;
+};
+
+&brd_rst {
+ bootph-all;
+};
diff --git a/arch/arm/dts/zynq-brsmarc2.dts b/arch/arm/dts/zynq-brsmarc2.dts
new file mode 100644
index 0000000..32f873d
--- /dev/null
+++ b/arch/arm/dts/zynq-brsmarc2.dts
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "BRSMARC2 CPU";
+ compatible = "br,smarc2",
+ "xlnx,zynq-7000";
+
+ aliases {
+ i2c0 = &i2c0;
+ serial0 = &uart0;
+ spi0 = &qspi;
+ mmc0 = &sdhci0;
+ can0 = &can0;
+ can1 = &can1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x10000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+
+ brd_rst: board_reset {
+ compatible = "br,board-reset";
+ pin = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ plk_se_green {
+ label = "PLK_S_E_GREEN";
+ gpios = <&ledgpio 0 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ plk_se_red {
+ label = "PLK_S_E_RED";
+ gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ rdy_f_yellow {
+ label = "RDY_F_YELLOW";
+ gpios = <&ledgpio 2 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ re_green {
+ label = "R_E_GREEN";
+ gpios = <&ledgpio 3 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ re_red {
+ label = "R_E_RED";
+ gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy0>;
+
+ ethernet_phy0: ethernet-phy@1 {
+ ti,ledcr = <0x0480>;
+ ti,rgmii-rxclk-shift;
+ reg = <1>;
+ };
+};
+
+&gem1 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy1>;
+ mac-address = [ 00 00 00 00 00 00 ];
+
+ ethernet_phy1: ethernet-phy@3{
+ ti,ledcr = <0x0480>;
+ reg = <3>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ resetc: rststm@60 { /* reset controller */
+ compatible = "bur,rststm";
+ reg = <0x60>;
+ hit-gpios = <&gpio0 84 GPIO_ACTIVE_HIGH>;
+ cooling-min-state = <0>;
+ cooling-max-state = <1>; /* reset gets fired */
+ #cooling-cells = <2>; /* min followed by max */
+ };
+
+ ledgpio: max7320@5d { /* board LED */
+ status = "okay";
+ compatible = "maxim,max7320";
+ reg = <0x5d>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ ngpios = <8>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&sdhci0 {
+ status = "okay";
+ max-frequency = <25000000>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+ spi-max-frequency = <100000000>;
+
+ spi_flash: spiflash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1";
+ spi-max-frequency = <100000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+};
diff --git a/arch/arm/dts/zynq-topic-miami.dts b/arch/arm/dts/zynq-topic-miami.dts
index 8307a2e..73eea37 100644
--- a/arch/arm/dts/zynq-topic-miami.dts
+++ b/arch/arm/dts/zynq-topic-miami.dts
@@ -11,6 +11,10 @@
model = "Topic Miami Zynq Board";
compatible = "topic,miami", "xlnx,zynq-7000";
+ config {
+ u-boot,spl-payload-offset = <0x20000>;
+ };
+
aliases {
serial0 = &uart0;
spi0 = &qspi;
@@ -35,6 +39,7 @@
status = "okay";
num-cs = <1>;
flash@0 {
+ bootph-all;
compatible = "st,m25p80", "n25q256a", "jedec,spi-nor";
m25p,fast-read;
reg = <0x0>;
@@ -44,24 +49,12 @@
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
- label = "qspi-u-boot-spl";
- reg = <0x00000 0x10000>;
- };
- partition@10000 {
- label = "qspi-u-boot-img";
- reg = <0x10000 0x60000>;
+ label = "qspi-boot-bin";
+ reg = <0x00000 0x100000>;
};
- partition@70000 {
- label = "qspi-device-tree";
- reg = <0x70000 0x10000>;
- };
- partition@80000 {
- label = "qspi-linux";
- reg = <0x80000 0x400000>;
- };
- partition@480000 {
+ partition@100000 {
label = "qspi-rootfs";
- reg = <0x480000 0x1b80000>;
+ reg = <0x100000 0>;
};
};
};
@@ -74,6 +67,14 @@
&i2c1 {
status = "okay";
clock-frequency = <400000>;
+ /* GPIO expander */
+ gpioex: gpio@41 {
+ compatible = "nxp,pca9536";
+ reg = <0x41>;
+ gpio-line-names = "USB_RESET", "VTT_SHDWN_N", "V_PRESENT", "DEBUG_PRESENT";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
};
&clkc {
diff --git a/arch/arm/dts/zynqmp-binman-som.dts b/arch/arm/dts/zynqmp-binman-som.dts
index d5b63ef..a70123f 100644
--- a/arch/arm/dts/zynqmp-binman-som.dts
+++ b/arch/arm/dts/zynqmp-binman-som.dts
@@ -2,13 +2,19 @@
/*
* dts file for Xilinx ZynqMP SOMs (k24/k26)
*
- * (C) Copyright 2024, Advanced Micro Devices, Inc.
+ * (C) Copyright 2024-2025, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
#include <config.h>
+#if defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME)
+#define U_BOOT_ITB_FILENAME CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
+#else
+#define U_BOOT_ITB_FILENAME "u-boot.itb"
+#endif
+
/dts-v1/;
/ {
binman: binman {
@@ -103,9 +109,9 @@
};
};
- /* u-boot.itb generation in a static way */
+ /* Generation in a static way */
itb {
- filename = "u-boot.itb";
+ filename = U_BOOT_ITB_FILENAME;
pad-byte = <0>;
fit {
@@ -227,7 +233,7 @@
};
blob-ext@2 {
offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
- filename = "u-boot.itb";
+ filename = U_BOOT_ITB_FILENAME;
};
fdtmap {
};
diff --git a/arch/arm/dts/zynqmp-binman.dts b/arch/arm/dts/zynqmp-binman.dts
index 252c2ad..59c1388 100644
--- a/arch/arm/dts/zynqmp-binman.dts
+++ b/arch/arm/dts/zynqmp-binman.dts
@@ -2,22 +2,28 @@
/*
* dts file for Xilinx ZynqMP platforms
*
- * (C) Copyright 2024, Advanced Micro Devices, Inc.
+ * (C) Copyright 2024-2025, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
#include <config.h>
+#if defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME)
+#define U_BOOT_ITB_FILENAME CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
+#else
+#define U_BOOT_ITB_FILENAME "u-boot.itb"
+#endif
+
/dts-v1/;
/ {
binman: binman {
multiple-images;
#ifdef CONFIG_SPL
- /* u-boot.itb generation in a static way */
+ /* Generation in a static way */
itb {
- filename = "u-boot.itb";
+ filename = U_BOOT_ITB_FILENAME;
pad-byte = <0>;
fit {
@@ -196,7 +202,7 @@
};
blob-ext@2 {
offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
- filename = "u-boot.itb";
+ filename = U_BOOT_ITB_FILENAME;
};
fdtmap {
};
diff --git a/arch/arm/mach-versal-net/Kconfig b/arch/arm/mach-versal-net/Kconfig
index 54fb93a..7def7b9 100644
--- a/arch/arm/mach-versal-net/Kconfig
+++ b/arch/arm/mach-versal-net/Kconfig
@@ -45,6 +45,5 @@
default 200000000
source "board/xilinx/Kconfig"
-source "board/xilinx/versal-net/Kconfig"
endif
diff --git a/arch/arm/mach-versal/Kconfig b/arch/arm/mach-versal/Kconfig
index 629a141..5ab901c 100644
--- a/arch/arm/mach-versal/Kconfig
+++ b/arch/arm/mach-versal/Kconfig
@@ -46,6 +46,5 @@
access to DDR memory where DDR is not present.
source "board/xilinx/Kconfig"
-source "board/xilinx/versal/Kconfig"
endif
diff --git a/arch/arm/mach-versal/include/mach/hardware.h b/arch/arm/mach-versal/include/mach/hardware.h
index 9d1c2f0..b5f80a8 100644
--- a/arch/arm/mach-versal/include/mach/hardware.h
+++ b/arch/arm/mach-versal/include/mach/hardware.h
@@ -87,6 +87,8 @@
#define JTAG_MODE 0x00000000
#define BOOT_MODE_USE_ALT 0x100
#define BOOT_MODE_ALT_SHIFT 12
+#define PMC_MULTI_BOOT_REG 0xF1110004
+#define PMC_MULTI_BOOT_MASK 0x1FFF
#define FLASH_RESET_GPIO 0xc
#define WPROT_CRP 0xF126001C
diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h
index 757bd87..a6dfa55 100644
--- a/arch/arm/mach-versal/include/mach/sys_proto.h
+++ b/arch/arm/mach-versal/include/mach/sys_proto.h
@@ -5,11 +5,11 @@
#include <linux/build_bug.h>
-enum {
- TCM_LOCK,
- TCM_SPLIT,
+enum tcm_mode {
+ TCM_LOCK = 0,
+ TCM_SPLIT = 1,
};
-void initialize_tcm(bool mode);
-void tcm_init(u8 mode);
+void initialize_tcm(enum tcm_mode mode);
+void tcm_init(enum tcm_mode mode);
void mem_map_fill(void);
diff --git a/arch/arm/mach-versal/mp.c b/arch/arm/mach-versal/mp.c
index 921ca49..7423b8d 100644
--- a/arch/arm/mach-versal/mp.c
+++ b/arch/arm/mach-versal/mp.c
@@ -24,7 +24,7 @@
#define VERSAL_CRL_RST_CPU_R5_RESET_PGE_MASK 0x10
#define VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK 0x1000000
-static void set_r5_halt_mode(u8 halt, u8 mode)
+static void set_r5_halt_mode(u8 halt, enum tcm_mode mode)
{
u32 tmp;
@@ -45,7 +45,7 @@
}
}
-static void set_r5_tcm_mode(u8 mode)
+static void set_r5_tcm_mode(enum tcm_mode mode)
{
u32 tmp;
@@ -63,7 +63,7 @@
writel(tmp, &rpu_base->rpu_glbl_ctrl);
}
-static void release_r5_reset(u8 mode)
+static void release_r5_reset(enum tcm_mode mode)
{
u32 tmp;
@@ -87,9 +87,9 @@
writel(tmp, &crlapb_base->cpu_r5_ctrl);
}
-void initialize_tcm(bool mode)
+void initialize_tcm(enum tcm_mode mode)
{
- if (!mode) {
+ if (mode == TCM_LOCK) {
set_r5_tcm_mode(TCM_LOCK);
set_r5_halt_mode(HALT, TCM_LOCK);
enable_clock_r5();
@@ -102,7 +102,7 @@
}
}
-void tcm_init(u8 mode)
+void tcm_init(enum tcm_mode mode)
{
puts("WARNING: Initializing TCM overwrites TCM content\n");
initialize_tcm(mode);
diff --git a/arch/arm/mach-versal2/Kconfig b/arch/arm/mach-versal2/Kconfig
index 3f18e33..2a59515 100644
--- a/arch/arm/mach-versal2/Kconfig
+++ b/arch/arm/mach-versal2/Kconfig
@@ -50,6 +50,5 @@
default 200000000
source "board/xilinx/Kconfig"
-source "board/amd/versal2/Kconfig"
endif
diff --git a/arch/arm/mach-versal2/include/mach/hardware.h b/arch/arm/mach-versal2/include/mach/hardware.h
index 15085f9..7ca2bbb 100644
--- a/arch/arm/mach-versal2/include/mach/hardware.h
+++ b/arch/arm/mach-versal2/include/mach/hardware.h
@@ -68,6 +68,7 @@
#define USB_MODE 0x00000007
#define OSPI_MODE 0x00000008
#define SELECTMAP_MODE 0x0000000A
+#define UFS_MODE 0x0000000B
#define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */
#define JTAG_MODE 0x00000000
#define BOOT_MODE_USE_ALT 0x100
@@ -96,3 +97,9 @@
#define MIO_PIN_12 0xF1060030
#define BANK0_OUTPUT 0xF1020040
#define BANK0_TRI 0xF1060200
+
+#define PMXC_EFUSE_CACHE_BASE_ADDRESS 0xF1250000
+#define PMXC_SLCR_BASE_ADDRESS 0xF1061000
+#define PMXC_UFS_CAL_1_OFFSET 0xBE8
+#define PMXC_SRAM_CSR 0x4C
+#define PMXC_TX_RX_CFG_RDY 0x54
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index 376d1bc..c3f505f 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -58,5 +58,6 @@
source "board/xilinx/Kconfig"
source "board/xilinx/zynq/Kconfig"
+source "board/BuR/zynq/Kconfig"
endif
diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c
index 960ffac..b7a4142 100644
--- a/arch/arm/mach-zynqmp/cpu.c
+++ b/arch/arm/mach-zynqmp/cpu.c
@@ -113,7 +113,7 @@
}
#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
-void tcm_init(u8 mode)
+void tcm_init(enum tcm_mode mode)
{
int ret;
diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
index 9af3ab5..b6a41df 100644
--- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h
+++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
@@ -41,18 +41,18 @@
ZYNQMP_SILICON_V4,
};
-enum {
- TCM_LOCK,
- TCM_SPLIT,
+enum tcm_mode {
+ TCM_LOCK = 0,
+ TCM_SPLIT = 1,
};
unsigned int zynqmp_get_silicon_version(void);
-int check_tcm_mode(bool mode);
-void initialize_tcm(bool mode);
+int check_tcm_mode(enum tcm_mode mode);
+void initialize_tcm(enum tcm_mode mode);
void mem_map_fill(void);
#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
-void tcm_init(u8 mode);
+void tcm_init(enum tcm_mode mode);
#endif
#endif /* _ASM_ARCH_SYS_PROTO_H */
diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c
index 448bc53..d2a7f30 100644
--- a/arch/arm/mach-zynqmp/mp.c
+++ b/arch/arm/mach-zynqmp/mp.c
@@ -17,9 +17,6 @@
#include <linux/errno.h>
#include <linux/string.h>
-#define LOCK 0
-#define SPLIT 1
-
#define HALT 0
#define RELEASE 1
@@ -65,11 +62,11 @@
return 0;
}
-static void set_r5_halt_mode(u32 nr, u8 halt, u8 mode)
+static void set_r5_halt_mode(u32 nr, u8 halt, enum tcm_mode mode)
{
u32 tmp;
- if (mode == LOCK || nr == ZYNQMP_CORE_RPU0) {
+ if (mode == TCM_LOCK || nr == ZYNQMP_CORE_RPU0) {
tmp = readl(&rpu_base->rpu0_cfg);
if (halt == HALT)
tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;
@@ -78,7 +75,7 @@
writel(tmp, &rpu_base->rpu0_cfg);
}
- if (mode == LOCK || nr == ZYNQMP_CORE_RPU1) {
+ if (mode == TCM_LOCK || nr == ZYNQMP_CORE_RPU1) {
tmp = readl(&rpu_base->rpu1_cfg);
if (halt == HALT)
tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;
@@ -88,12 +85,12 @@
}
}
-static void set_r5_tcm_mode(u8 mode)
+static void set_r5_tcm_mode(enum tcm_mode mode)
{
u32 tmp;
tmp = readl(&rpu_base->rpu_glbl_ctrl);
- if (mode == LOCK) {
+ if (mode == TCM_LOCK) {
tmp &= ~ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
tmp |= ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK |
ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK;
@@ -106,12 +103,12 @@
writel(tmp, &rpu_base->rpu_glbl_ctrl);
}
-static void set_r5_reset(u32 nr, u8 mode)
+static void set_r5_reset(u32 nr, enum tcm_mode mode)
{
u32 tmp;
tmp = readl(&crlapb_base->rst_lpd_top);
- if (mode == LOCK) {
+ if (mode == TCM_LOCK) {
tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK |
ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK);
@@ -130,16 +127,16 @@
writel(tmp, &crlapb_base->rst_lpd_top);
}
-static void release_r5_reset(u32 nr, u8 mode)
+static void release_r5_reset(u32 nr, enum tcm_mode mode)
{
u32 tmp;
tmp = readl(&crlapb_base->rst_lpd_top);
- if (mode == LOCK || nr == ZYNQMP_CORE_RPU0)
+ if (mode == TCM_LOCK || nr == ZYNQMP_CORE_RPU0)
tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK);
- if (mode == LOCK || nr == ZYNQMP_CORE_RPU1)
+ if (mode == TCM_LOCK || nr == ZYNQMP_CORE_RPU1)
tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK);
@@ -165,9 +162,9 @@
tmp = readl(&rpu_base->rpu_glbl_ctrl);
if (tmp & ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK)
- return SPLIT;
+ return TCM_SPLIT;
- return LOCK;
+ return TCM_LOCK;
}
int cpu_disable(u32 nr)
@@ -249,27 +246,27 @@
}
}
-void initialize_tcm(bool mode)
+void initialize_tcm(enum tcm_mode mode)
{
- if (!mode) {
- set_r5_tcm_mode(LOCK);
- set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, LOCK);
+ if (mode == TCM_LOCK) {
+ set_r5_tcm_mode(TCM_LOCK);
+ set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, TCM_LOCK);
enable_clock_r5();
- release_r5_reset(ZYNQMP_CORE_RPU0, LOCK);
+ release_r5_reset(ZYNQMP_CORE_RPU0, TCM_LOCK);
} else {
- set_r5_tcm_mode(SPLIT);
- set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, SPLIT);
- set_r5_halt_mode(ZYNQMP_CORE_RPU1, HALT, SPLIT);
+ set_r5_tcm_mode(TCM_SPLIT);
+ set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, TCM_SPLIT);
+ set_r5_halt_mode(ZYNQMP_CORE_RPU1, HALT, TCM_SPLIT);
enable_clock_r5();
- release_r5_reset(ZYNQMP_CORE_RPU0, SPLIT);
- release_r5_reset(ZYNQMP_CORE_RPU1, SPLIT);
+ release_r5_reset(ZYNQMP_CORE_RPU0, TCM_SPLIT);
+ release_r5_reset(ZYNQMP_CORE_RPU1, TCM_SPLIT);
}
}
-int check_tcm_mode(bool mode)
+int check_tcm_mode(enum tcm_mode mode)
{
u32 tmp, cpu_state;
- bool mode_prev;
+ enum tcm_mode mode_prev;
tmp = readl(&rpu_base->rpu_glbl_ctrl);
mode_prev = FIELD_GET(ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK, tmp);
@@ -279,7 +276,7 @@
ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK, tmp);
cpu_state = cpu_state ? false : true;
- if ((mode_prev == SPLIT && mode == LOCK) && cpu_state)
+ if ((mode_prev == TCM_SPLIT && mode == TCM_LOCK) && cpu_state)
return -EACCES;
if (mode_prev == mode)
@@ -288,11 +285,11 @@
return 0;
}
-static void mark_r5_used(u32 nr, u8 mode)
+static void mark_r5_used(u32 nr, enum tcm_mode mode)
{
u32 mask = 0;
- if (mode == LOCK) {
+ if (mode == TCM_LOCK) {
mask = ZYNQMP_RPU0_USE_MASK | ZYNQMP_RPU1_USE_MASK;
} else {
switch (nr) {
@@ -358,30 +355,30 @@
return 1;
}
printf("R5 lockstep mode\n");
- set_r5_reset(nr, LOCK);
- set_r5_tcm_mode(LOCK);
- set_r5_halt_mode(nr, HALT, LOCK);
+ set_r5_reset(nr, TCM_LOCK);
+ set_r5_tcm_mode(TCM_LOCK);
+ set_r5_halt_mode(nr, HALT, TCM_LOCK);
set_r5_start(boot_addr);
enable_clock_r5();
- release_r5_reset(nr, LOCK);
+ release_r5_reset(nr, TCM_LOCK);
dcache_disable();
write_tcm_boot_trampoline(nr, boot_addr_uniq);
dcache_enable();
- set_r5_halt_mode(nr, RELEASE, LOCK);
- mark_r5_used(nr, LOCK);
+ set_r5_halt_mode(nr, RELEASE, TCM_LOCK);
+ mark_r5_used(nr, TCM_LOCK);
} else if (!strcmp(argv[1], "split") || !strcmp(argv[1], "1")) {
printf("R5 split mode\n");
- set_r5_reset(nr, SPLIT);
- set_r5_tcm_mode(SPLIT);
- set_r5_halt_mode(nr, HALT, SPLIT);
+ set_r5_reset(nr, TCM_SPLIT);
+ set_r5_tcm_mode(TCM_SPLIT);
+ set_r5_halt_mode(nr, HALT, TCM_SPLIT);
set_r5_start(boot_addr);
enable_clock_r5();
- release_r5_reset(nr, SPLIT);
+ release_r5_reset(nr, TCM_SPLIT);
dcache_disable();
write_tcm_boot_trampoline(nr, boot_addr_uniq);
dcache_enable();
- set_r5_halt_mode(nr, RELEASE, SPLIT);
- mark_r5_used(nr, SPLIT);
+ set_r5_halt_mode(nr, RELEASE, TCM_SPLIT);
+ mark_r5_used(nr, TCM_SPLIT);
} else {
printf("Unsupported mode\n");
return 1;
diff --git a/arch/arm/mach-zynqmp/zynqmp.c b/arch/arm/mach-zynqmp/zynqmp.c
index 3aa2185..279006b 100644
--- a/arch/arm/mach-zynqmp/zynqmp.c
+++ b/arch/arm/mach-zynqmp/zynqmp.c
@@ -146,7 +146,7 @@
static int do_zynqmp_tcm_init(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
- u8 mode;
+ enum tcm_mode mode;
if (argc != cmdtp->maxargs)
return CMD_RET_USAGE;
diff --git a/board/BuR/common/Kconfig b/board/BuR/common/Kconfig
new file mode 100644
index 0000000..490201e
--- /dev/null
+++ b/board/BuR/common/Kconfig
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# B&R Industrial Automation GmbH - http://www.br-automation.com
+
+config BR_RESETC_I2CBUS
+ int "I2C Bus address of B&R reset controller"
+ depends on SYS_VENDOR = "BuR" && DM_I2C
+ default 0
diff --git a/board/BuR/common/br_resetc.c b/board/BuR/common/br_resetc.c
index f5d09fe..dfe2c2e 100644
--- a/board/BuR/common/br_resetc.c
+++ b/board/BuR/common/br_resetc.c
@@ -52,10 +52,16 @@
{
struct udevice *i2cbus;
int rc;
+#if !defined(BR_RESETC_I2CBUS)
+ int busno = 0;
+#else
+ int busno = CONFIG_BR_RESETC_I2CBUS;
+#endif
- rc = uclass_get_device_by_seq(UCLASS_I2C, 0, &i2cbus);
+ rc = uclass_get_device_by_seq(UCLASS_I2C, busno, &i2cbus);
+
if (rc) {
- printf("Cannot find I2C bus #0!\n");
+ printf("Cannot find I2C bus #%d!\n", busno);
return -1;
}
@@ -108,9 +114,73 @@
{
int rc = 0;
u16 regw;
+ unsigned int bmode = 0;
+
+ if (!resetc.i2cdev)
+ rc = resetc_init();
+
+ if (rc != 0)
+ return rc;
+
+ board_boot_led(1);
+
+ rc = br_resetc_bmode_get(&bmode);
+ if (rc != 0)
+ return rc;
+
+ LCD_SETCURSOR(1, 8);
+
+ switch (bmode) {
+ case BMODE_PME:
+ LCD_PUTS("entering PME-Mode (netscript). ");
+ regw = 0x0C0C;
+ break;
+ case BMODE_DEFAULTAR:
+ LCD_PUTS("entering BOOT-mode. ");
+ regw = 0x0000;
+ break;
+ case BMODE_DIAG:
+ LCD_PUTS("entering DIAGNOSE-mode. ");
+ regw = 0x0F0F;
+ break;
+ case BMODE_SERVICE:
+ LCD_PUTS("entering SERVICE mode. ");
+ regw = 0xB4B4;
+ break;
+ case BMODE_RUN:
+ LCD_PUTS("loading OS... ");
+ regw = 0x0404;
+ break;
+ }
+
+ board_boot_led(0);
+
+ if (resetc.is_psoc)
+ rc = dm_i2c_write(resetc.i2cdev, RSTCTRL_SCRATCHREG0,
+ (u8 *)®w, 2);
+ else
+ rc = dm_i2c_write(resetc.i2cdev, RSTCTRL_SCRATCHREG0,
+ (u8 *)®w, 1);
+
+ if (rc != 0)
+ printf("WARN: cannot write into resetcontroller!\n");
+
+ if (resetc.is_psoc)
+ printf("Reset: PSOC controller\n");
+ else
+ printf("Reset: STM32 controller\n");
+
+ printf("Mode: %s\n", bootmodeascii[regw & 0x0F]);
+ env_set_ulong("b_mode", regw & 0x0F);
+
+ return rc;
+}
+
+int br_resetc_bmode_get(unsigned int *bmode)
+{
+ int rc = 0;
u8 regb, scr;
int cnt;
- unsigned int bmode = 0;
if (!resetc.i2cdev)
rc = resetc_init();
@@ -130,13 +200,11 @@
return -1;
}
- board_boot_led(1);
-
/* special bootmode from resetcontroller */
if (regb & 0x4) {
- bmode = BMODE_DIAG;
+ *bmode = BMODE_DIAG;
} else if (regb & 0x8) {
- bmode = BMODE_DEFAULTAR;
+ *bmode = BMODE_DEFAULTAR;
} else if (board_boot_key() != 0) {
cnt = 4;
do {
@@ -163,68 +231,23 @@
switch (cnt) {
case 0:
- bmode = BMODE_PME;
+ *bmode = BMODE_PME;
break;
case 1:
- bmode = BMODE_DEFAULTAR;
+ *bmode = BMODE_DEFAULTAR;
break;
case 2:
- bmode = BMODE_DIAG;
+ *bmode = BMODE_DIAG;
break;
case 3:
- bmode = BMODE_SERVICE;
+ *bmode = BMODE_SERVICE;
break;
}
} else if ((regb & 0x1) || scr == 0xCC) {
- bmode = BMODE_PME;
+ *bmode = BMODE_PME;
} else {
- bmode = BMODE_RUN;
- }
-
- LCD_SETCURSOR(1, 8);
-
- switch (bmode) {
- case BMODE_PME:
- LCD_PUTS("entering PME-Mode (netscript). ");
- regw = 0x0C0C;
- break;
- case BMODE_DEFAULTAR:
- LCD_PUTS("entering BOOT-mode. ");
- regw = 0x0000;
- break;
- case BMODE_DIAG:
- LCD_PUTS("entering DIAGNOSE-mode. ");
- regw = 0x0F0F;
- break;
- case BMODE_SERVICE:
- LCD_PUTS("entering SERVICE mode. ");
- regw = 0xB4B4;
- break;
- case BMODE_RUN:
- LCD_PUTS("loading OS... ");
- regw = 0x0404;
- break;
+ *bmode = BMODE_RUN;
}
- board_boot_led(0);
-
- if (resetc.is_psoc)
- rc = dm_i2c_write(resetc.i2cdev, RSTCTRL_SCRATCHREG0,
- (u8 *)®w, 2);
- else
- rc = dm_i2c_write(resetc.i2cdev, RSTCTRL_SCRATCHREG0,
- (u8 *)®w, 1);
-
- if (rc != 0)
- printf("WARN: cannot write into resetcontroller!\n");
-
- if (resetc.is_psoc)
- printf("Reset: PSOC controller\n");
- else
- printf("Reset: STM32 controller\n");
-
- printf("Mode: %s\n", bootmodeascii[regw & 0x0F]);
- env_set_ulong("b_mode", regw & 0x0F);
-
return rc;
}
diff --git a/board/BuR/common/br_resetc.h b/board/BuR/common/br_resetc.h
index 999045b..3bd5ac2 100644
--- a/board/BuR/common/br_resetc.h
+++ b/board/BuR/common/br_resetc.h
@@ -11,6 +11,7 @@
int br_resetc_regget(u8 reg, u8 *dst);
int br_resetc_regset(u8 reg, u8 val);
int br_resetc_bmode(void);
+int br_resetc_bmode_get(unsigned int *bmode);
/* reset controller register defines */
#define RSTCTRL_CTRLREG 0x01
diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c
index 7fb6173..3513f43 100644
--- a/board/BuR/common/common.c
+++ b/board/BuR/common/common.c
@@ -68,7 +68,7 @@
"if test -r ${ipaddr}; then; else setenv ipaddr 192.168.60.%d; setenv serverip 192.168.60.254; setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;",
u8buf);
else
- strncpy(defip,
+ strlcpy(defip,
"if test -r ${ipaddr}; then; else setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254; setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;",
sizeof(defip));
diff --git a/board/BuR/zynq/Kconfig b/board/BuR/zynq/Kconfig
new file mode 100644
index 0000000..b450a21
--- /dev/null
+++ b/board/BuR/zynq/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# B&R Industrial Automation GmbH - http://www.br-automation.com
+if ARCH_ZYNQ
+
+config TARGET_ZYNQ_BR
+ bool "Support BR Zynq builds"
+ depends on SYS_VENDOR = "BuR"
+ select BINMAN
+ select SPL_BINMAN_FDT
+
+endif
+
+source "board/BuR/common/Kconfig"
diff --git a/board/BuR/zynq/MAINTAINERS b/board/BuR/zynq/MAINTAINERS
new file mode 100644
index 0000000..d655cae
--- /dev/null
+++ b/board/BuR/zynq/MAINTAINERS
@@ -0,0 +1,11 @@
+ZYNQ BOARD
+M: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
+S: Maintained
+F: board/BuR/zynq/
+F: board/BuR/common/
+F: include/configs/brzynq.h
+F: arch/arm/dts/zynq-br*
+F: configs/brcp1_*
+F: configs/brcp150_defconfig
+F: configs/brcp170_defconfig
+F: configs/brsmarc2_defconfig
diff --git a/board/BuR/zynq/Makefile b/board/BuR/zynq/Makefile
new file mode 100644
index 0000000..fed40b0a
--- /dev/null
+++ b/board/BuR/zynq/Makefile
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# B&R Industrial Automation GmbH - http://www.br-automation.com
+
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/zynq-//')
+
+obj-y := ../common/common.o
+obj-y += ../common/br_resetc.o
+obj-y += common/board.o
+obj-y += $(hw-platform-y)/board.o
+
+obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o
+
+# Suppress "warning: function declaration isn't a prototype"
+CFLAGS_REMOVE_ps7_init_gpl.o := -Wstrict-prototypes
diff --git a/board/BuR/zynq/brcp150/board.c b/board/BuR/zynq/brcp150/board.c
new file mode 100644
index 0000000..456d490
--- /dev/null
+++ b/board/BuR/zynq/brcp150/board.c
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ */
diff --git a/board/BuR/zynq/brcp150/ps7_init_gpl.c b/board/BuR/zynq/brcp150/ps7_init_gpl.c
new file mode 100644
index 0000000..822bce3
--- /dev/null
+++ b/board/BuR/zynq/brcp150/ps7_init_gpl.c
@@ -0,0 +1,278 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000011U),
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00500141U),
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000801U),
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001001U),
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001003U),
+ EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000802U),
+ EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00A01403U),
+ EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000801U),
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400800U),
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01FF844DU),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x0000103FU),
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00042E1AU),
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D154D4U),
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U),
+ EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U),
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U),
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
+ EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U),
+ EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U),
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU),
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U),
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C000U),
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U),
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U),
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU),
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU),
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU),
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU),
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C5U),
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U),
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U),
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU),
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU),
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU),
+ EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U),
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U),
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U),
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x000003E0U),
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x000003E1U),
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000321U),
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001220U),
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001220U),
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000321U),
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000013E1U),
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000003E0U),
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_post_config_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+ return ps7_config(ps7_post_config_3_0);
+}
+
+int ps7_init(void)
+{
+ int ret;
+
+ ret = ps7_config(ps7_mio_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_pll_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_clock_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_ddr_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_peripherals_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ return PS7_INIT_SUCCESS;
+}
diff --git a/board/BuR/zynq/brcp170/board.c b/board/BuR/zynq/brcp170/board.c
new file mode 100644
index 0000000..456d490
--- /dev/null
+++ b/board/BuR/zynq/brcp170/board.c
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ */
diff --git a/board/BuR/zynq/brcp170/ps7_init_gpl.c b/board/BuR/zynq/brcp170/ps7_init_gpl.c
new file mode 100644
index 0000000..223d13c
--- /dev/null
+++ b/board/BuR/zynq/brcp170/ps7_init_gpl.c
@@ -0,0 +1,274 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000502U),
+ EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00501903U),
+ EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400500U),
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DF844DU),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x0000103FU),
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00042E1AU),
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D154D4U),
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U),
+ EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U),
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U),
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
+ EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U),
+ EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U),
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU),
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U),
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C000U),
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U),
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U),
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU),
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU),
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU),
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU),
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C5U),
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U),
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U),
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU),
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU),
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU),
+ EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U),
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U),
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U),
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000321U),
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001220U),
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001220U),
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000321U),
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000013E1U),
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000003E0U),
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_post_config_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+ return ps7_config(ps7_post_config_3_0);
+}
+
+int ps7_init(void)
+{
+ int ret;
+
+ ret = ps7_config(ps7_mio_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_pll_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_clock_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_ddr_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_peripherals_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ return PS7_INIT_SUCCESS;
+}
diff --git a/board/BuR/zynq/brcp1_1r/board.c b/board/BuR/zynq/brcp1_1r/board.c
new file mode 100644
index 0000000..456d490
--- /dev/null
+++ b/board/BuR/zynq/brcp1_1r/board.c
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ */
diff --git a/board/BuR/zynq/brcp1_1r/ps7_init_gpl.c b/board/BuR/zynq/brcp1_1r/ps7_init_gpl.c
new file mode 100644
index 0000000..be39db9
--- /dev/null
+++ b/board/BuR/zynq/brcp1_1r/ps7_init_gpl.c
@@ -0,0 +1,274 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA240U),
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0003C000U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000300U),
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x000FA240U),
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0003C000U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U),
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00101001U),
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001401U),
+ EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000A02U),
+ EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00A01901U),
+ EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00500800U),
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DD844DU),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000084U),
+ EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001040U),
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00040EDAU),
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D258D4U),
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U),
+ EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U),
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U),
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000666U),
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFFF0000U),
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FFF5555U),
+ EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U),
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU),
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000000U),
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000000U),
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U),
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C400U),
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U),
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U),
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU),
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU),
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU),
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU),
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C6U),
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U),
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U),
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU),
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU),
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU),
+ EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U),
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000085U),
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000800U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000800U),
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000220U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U),
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U),
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000361U),
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00000360U),
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00000361U),
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000361U),
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000012E1U),
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000002E0U),
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_post_config_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+ return ps7_config(ps7_post_config_3_0);
+}
+
+int ps7_init(void)
+{
+ int ret;
+
+ ret = ps7_config(ps7_mio_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_pll_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_clock_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_ddr_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_peripherals_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ return PS7_INIT_SUCCESS;
+}
diff --git a/board/BuR/zynq/brcp1_1r_switch/board.c b/board/BuR/zynq/brcp1_1r_switch/board.c
new file mode 100644
index 0000000..456d490
--- /dev/null
+++ b/board/BuR/zynq/brcp1_1r_switch/board.c
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ */
diff --git a/board/BuR/zynq/brcp1_1r_switch/ps7_init_gpl.c b/board/BuR/zynq/brcp1_1r_switch/ps7_init_gpl.c
new file mode 100644
index 0000000..e4fc708
--- /dev/null
+++ b/board/BuR/zynq/brcp1_1r_switch/ps7_init_gpl.c
@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U),
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000011U),
+ EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U),
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00500141U),
+ EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00500141U),
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000502U),
+ EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00501901U),
+ EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400500U),
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DD84CDU),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000084U),
+ EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001040U),
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00040EDAU),
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D258D4U),
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U),
+ EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U),
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U),
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000666U),
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFFF0000U),
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FFF5555U),
+ EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U),
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU),
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000000U),
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000000U),
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U),
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C400U),
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U),
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U),
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU),
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU),
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU),
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU),
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C6U),
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U),
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U),
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU),
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU),
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU),
+ EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U),
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000085U),
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000800U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000800U),
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000220U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U),
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U),
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000361U),
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00000360U),
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00000361U),
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000361U),
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000012E1U),
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000002E0U),
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_post_config_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+ return ps7_config(ps7_post_config_3_0);
+}
+
+int ps7_init(void)
+{
+ int ret;
+
+ ret = ps7_config(ps7_mio_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_pll_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_clock_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_ddr_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_peripherals_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ return PS7_INIT_SUCCESS;
+}
diff --git a/board/BuR/zynq/brcp1_2r/board.c b/board/BuR/zynq/brcp1_2r/board.c
new file mode 100644
index 0000000..456d490
--- /dev/null
+++ b/board/BuR/zynq/brcp1_2r/board.c
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ */
diff --git a/board/BuR/zynq/brcp1_2r/ps7_init_gpl.c b/board/BuR/zynq/brcp1_2r/ps7_init_gpl.c
new file mode 100644
index 0000000..4ebed8b
--- /dev/null
+++ b/board/BuR/zynq/brcp1_2r/ps7_init_gpl.c
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA3C0U),
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0002E000U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U),
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000502U),
+ EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00501901U),
+ EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00101400U),
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00101400U),
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00101400U),
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DD844DU),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001040U),
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004281AU),
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D258D4U),
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U),
+ EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U),
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U),
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U),
+ EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U),
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU),
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U),
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C400U),
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U),
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U),
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU),
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU),
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU),
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU),
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C6U),
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U),
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U),
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU),
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU),
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU),
+ EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U),
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U),
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U),
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000361U),
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00000360U),
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00000361U),
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000361U),
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000012E1U),
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000002E0U),
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_post_config_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+ return ps7_config(ps7_post_config_3_0);
+}
+
+int ps7_init(void)
+{
+ int ret;
+
+ ret = ps7_config(ps7_mio_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_pll_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_clock_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_ddr_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_peripherals_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ return PS7_INIT_SUCCESS;
+}
diff --git a/board/BuR/zynq/brsmarc2/board.c b/board/BuR/zynq/brsmarc2/board.c
new file mode 100644
index 0000000..7d9e13a
--- /dev/null
+++ b/board/BuR/zynq/brsmarc2/board.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ */
+#include <linux/types.h>
+#include <i2c.h>
+#include <init.h>
+#include "../../common/br_resetc.h"
+#include "../../common/bur_common.h"
+
+int board_boot_key(void)
+{
+ unsigned char u8buf = 0;
+ int rc;
+
+ rc = br_resetc_regget(RSTCTRL_ENHSTATUS, &u8buf);
+ if (rc == 0)
+ return (u8buf & 0x1);
+
+ return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+int br_board_late_init(void)
+{
+ brdefaultip_setup(0, 0x57);
+
+ return 0;
+}
+#endif
diff --git a/board/BuR/zynq/brsmarc2/ps7_init_gpl.c b/board/BuR/zynq/brsmarc2/ps7_init_gpl.c
new file mode 100644
index 0000000..51ff8bf
--- /dev/null
+++ b/board/BuR/zynq/brsmarc2/ps7_init_gpl.c
@@ -0,0 +1,276 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U),
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+ EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U),
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00500801U),
+ EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00500141U),
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000503U),
+ EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00501903U),
+ EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400500U),
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DFC4CDU),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001040U),
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00040EDAU),
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D258D4U),
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U),
+ EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U),
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U),
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FFF6666U),
+ EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U),
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU),
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U),
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C400U),
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U),
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U),
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU),
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU),
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU),
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU),
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C6U),
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U),
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U),
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU),
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU),
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU),
+ EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U),
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x000016E1U),
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x000006E0U),
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000321U),
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00000320U),
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00000320U),
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000321U),
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000340U),
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000340U),
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_post_config_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+ return ps7_config(ps7_post_config_3_0);
+}
+
+int ps7_init(void)
+{
+ int ret;
+
+ ret = ps7_config(ps7_mio_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_pll_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_clock_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_ddr_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_peripherals_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ return PS7_INIT_SUCCESS;
+}
diff --git a/board/BuR/zynq/common/board.c b/board/BuR/zynq/common/board.c
new file mode 100644
index 0000000..35e8ed8
--- /dev/null
+++ b/board/BuR/zynq/common/board.c
@@ -0,0 +1,231 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board functions for B&R brcp150, brcp170, brcp1, brsmarc2 Board
+ *
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ *
+ */
+
+#include <fdtdec.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <init.h>
+#include <i2c.h>
+#include <dm/uclass.h>
+#include <command.h>
+#include <binman.h>
+#include "../../common/br_resetc.h"
+#include "../../common/bur_common.h"
+
+#include <fdt_support.h>
+#include <spi_flash.h>
+#include <fpga.h>
+#include <zynqpl.h>
+
+#define RSTCTRL_CTRLSPEC_nPCIRST 0x1
+
+__weak int br_board_late_init(void)
+{
+ return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(FPGA)
+const char *fpga_paths[2] = { "/binman/blob-ext@4",
+ "/binman/blob-ext@1"};
+
+static int start_fpga(unsigned int bank)
+{
+ struct spi_flash *flash_dev;
+ ofnode fpga_node;
+ void *buf;
+
+ u32 flash_offset, flash_size;
+ int rc;
+
+ fpga_node = ofnode_path(fpga_paths[bank]);
+
+ if (!ofnode_valid(fpga_node)) {
+ printf("WARN: binman node not found %s\n", fpga_paths[bank]);
+ return -ENOENT;
+ }
+
+ flash_offset = ofnode_read_u32_default(fpga_node, "offset", ~0UL);
+ flash_size = ofnode_read_u32_default(fpga_node, "size", ~0UL);
+
+ if (flash_offset == ~0UL || flash_size == ~0UL) {
+ printf("WARN: invalid fpga 'offset, size' in fdt (0x%x, 0x%x)",
+ flash_offset, flash_size);
+ return -EINVAL;
+ }
+
+ printf("loading bitstream from bank #%d (0x%08x / 0x%08x)\n", bank,
+ flash_offset, flash_size);
+
+ flash_dev = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+ CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE);
+
+ if (rc) {
+ printf("WARN: cannot probe SPI-flash for bitstream!\n");
+ return -ENODEV;
+ }
+
+ buf = kmalloc(flash_size, 0);
+ if (!buf) {
+ spi_flash_free(flash_dev);
+ return -ENOMEM;
+ }
+
+ debug("using buf @ %p, flashbase: 0x%08x, len: 0x%08x\n",
+ buf, flash_offset, flash_size);
+
+ rc = spi_flash_read(flash_dev, flash_offset, flash_size, buf);
+
+ spi_flash_free(flash_dev);
+
+ if (rc) {
+ printf("WARN: cannot read bitstream from spi-flash!\n");
+ kfree(buf);
+
+ return -EIO;
+ }
+
+ rc = fpga_loadbitstream(0, buf, flash_size, BIT_FULL);
+ if (rc) {
+ printf("WARN: FPGA configuration from bank #%d failed!\n", bank);
+ kfree(buf);
+
+ return -EIO;
+ }
+
+ kfree(buf);
+
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_SPL_BUILD)
+const char *boot_gpios[] = { "br,rs232-en",
+ "br,board-reset",
+ NULL};
+
+/* spl stage */
+int board_init(void)
+{
+ struct gpio_desc gpio;
+ int node;
+ int rc;
+
+ /* peripheral RESET on PSOC reset-controller */
+ rc = br_resetc_regset(RSTCTRL_SPECGPIO_O, RSTCTRL_CTRLSPEC_nPCIRST);
+ if (rc != 0)
+ printf("ERROR: cannot write to resetc (nPCIRST)!\n");
+
+ for (int i = 0; boot_gpios[i]; i++) {
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, boot_gpios[i]);
+
+ if (node < 0) {
+ printf("INFO: %s not found!\n", boot_gpios[i]);
+ } else {
+ rc = gpio_request_by_name_nodev(offset_to_ofnode(node), "pin",
+ 0, &gpio, GPIOD_IS_OUT);
+
+ if (!rc)
+ dm_gpio_set_value(&gpio, 1);
+ else
+ printf("ERROR: failed to setup %s!\n", boot_gpios[i]);
+ }
+ }
+
+#if CONFIG_IS_ENABLED(FPGA)
+ unsigned int bmode;
+ unsigned int bank;
+
+ rc = br_resetc_bmode_get(&bmode);
+ if (rc) {
+ printf("WARN: can't get Boot Mode!\n");
+ return -ENODEV;
+ }
+
+ /* use golden FPGA image in case of special boot flow (PME, BootAR, USB, Net ...) */
+ bank = ((bmode == 0) || (bmode == 12)) ? 1 : 0;
+
+ /* bring up FPGA */
+ if (start_fpga(bank) != 0) {
+ printf("WARN: cannot start fpga from bank %d, trying bank %d!\n", bank, bank ^ 1);
+ bank ^= 1;
+ start_fpga(bank);
+ }
+#endif
+ return 0;
+}
+#else
+int board_init(void)
+{
+ return 0;
+}
+
+/*
+ * PMIC buckboost regulator workaround:
+ * The DA9062 PMIC can switch its buckboost regulator output
+ * between PFM and PWM mode for eco-purpose.
+ * In very rare situations this transition leads into a non-
+ * functional buckboost regulator with zero output.
+ * With this workaround we prevent this with turning this
+ * feature off by forcing PWM-mode if auto-mode is selected.
+ */
+static void pmic_fixup(int addr)
+{
+ u8 regs[] = { 0x9E, 0x9D, 0xA0, 0x9F };
+ struct udevice *i2cdev = NULL;
+ unsigned int i;
+ u8 val;
+ int rc;
+
+ i2c_get_chip_for_busnum(0, addr, 1, &i2cdev);
+ if (!i2cdev)
+ return;
+
+ printf("PMIC: fixup buckboost at i2c device 0x%x\n", addr);
+
+ for (i = 0; i < sizeof(regs); i++) {
+ rc = dm_i2c_read(i2cdev, regs[i], &val, 1);
+ if (rc == 0 && val == 0xC0) {
+ val = 0x80;
+ dm_i2c_write(i2cdev, regs[i], &val, 1);
+ }
+ }
+}
+
+int board_late_init(void)
+{
+ ofnode node;
+ u32 addr;
+
+ br_resetc_bmode();
+ br_board_late_init();
+
+ node = ofnode_by_compatible(ofnode_null(), "dlg,da9062");
+
+ if (!ofnode_valid(node))
+ return 0;
+
+ if (!ofnode_read_u32(node, "reg", &addr))
+ pmic_fixup(addr);
+ else
+ printf("WARN: cannot read PMIC address!");
+
+ return 0;
+}
+#endif
+
+int dram_init(void)
+{
+ if (fdtdec_setup_mem_size_base() != 0)
+ return -EINVAL;
+
+ zynq_ddrc_init();
+
+ return 0;
+}
diff --git a/board/BuR/zynq/env/brcp1.env b/board/BuR/zynq/env/brcp1.env
new file mode 100644
index 0000000..269e519
--- /dev/null
+++ b/board/BuR/zynq/env/brcp1.env
@@ -0,0 +1,109 @@
+autoload=0
+b_break=0
+fpgastatus=disabled
+/* Memory variable */
+scradr=0xC0000
+fdtbackaddr=0x4000000
+loadaddr=CONFIG_SYS_LOAD_ADDR
+
+/* PREBOOT */
+preboot=run setupaddr_spi; run brdefaultip; run cfgscr; setenv bootstart 1
+
+/* SPI layout variables */
+cfg_addr=
+ fdt get value cfgaddr_spi /binman/blob-ext@0 offset &&
+ fdt get value cfgsize_spi /binman/blob-ext@0 size
+
+fpga_addr=
+ fdt get value fpgaaddr_spi /binman/blob-ext@1 offset &&
+ fdt get value fpgasize_spi /binman/blob-ext@1 size
+
+os_addr=
+ fdt get value osaddr_spi /binman/blob-ext@2 offset &&
+ fdt get value ossize_spi /binman/blob-ext@2 size
+
+dtb_addr=
+ fdt get value dtbaddr_spi /binman/blob-ext@3 offset &&
+ fdt get value dtbsize_spi /binman/blob-ext@3 size
+
+setupaddr_spi=
+ fdt addr ${fdtcontroladdr};
+ run dtb_addr; run os_addr;
+ run fpga_addr; run cfg_addr
+
+/* IP setup */
+brdefaultip=
+ if test -r ${ipaddr}; then;
+ else
+ setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254;
+ setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0;
+ fi
+
+/* Boot orders */
+b_tgts_std=mmc0 mmc1 spi usb0 usb1 net
+b_tgts_rcy=spi usb0 usb1 net
+b_tgts_pme=net usb0 usb1 mmc spi
+
+/* Boot targets */
+b_mmc0=
+ run fpga; mmc dev 0; load mmc 0 ${loadaddr} arimg.itb &&
+ run vxargs && bootm ${loadaddr}
+
+b_mmc1=
+ run fpga; mmc dev 0; load mmc 0 ${loadaddr} arimg &&
+ run vxargs &&
+ sf read ${fdtbackaddr} ${dtbaddr_spi} ${dtbsize_spi} &&
+ fdt addr ${fdtbackaddr} &&
+ bootm ${loadaddr} - ${fdtbackaddr}
+
+b_spi=
+ run fpga; sf read ${loadaddr} ${osaddr_spi} ${ossize_spi} &&
+ run vxargs && bootm ${loadaddr}
+
+b_net=run fpga; tftp ${scradr} netscript.img && source ${scradr}
+b_usb0=usb start && load usb 0 ${scradr} usbscript.img && source ${scradr}
+b_usb1=usb start && load usb 0 ${scradr} bootscr.img && source ${scradr}
+
+/* FPGA setup */
+fpga=
+ setenv fpgastatus disabled;
+ sf read ${loadaddr} ${fpgaaddr_spi} ${fpgasize_spi} &&
+ fpga loadb 0 ${loadaddr} ${fpgasize_spi} &&
+ setenv fpgastatus okay
+
+/* Configuration preboot*/
+cfgscr=
+ sf probe &&
+ sf read ${scradr} ${cfgaddr_spi} ${cfgsize_spi} &&
+ source ${scradr}
+
+/* OS Boot */
+fdt_fixup=
+ run cfgscr; run vxfdt
+
+vxargs=
+ setenv bootargs gem(0,0)host:vxWorks h=${serverip}
+ e=${ipaddr}:${netmask} g=${gatewayip} u=vxWorksFTP pw=vxWorks f=0x1
+
+vxfdt=
+ fdt set /fpga/pci status ${fpgastatus};
+ fdt set /fpga status ${fpgastatus}
+
+/* Boot code */
+b_default=
+ run b_deftgts;
+ for target in ${b_tgts}; do
+ run b_${target};
+ if test ${b_break} = 1; then;
+ exit;
+ fi;
+ done
+
+b_deftgts=
+ if test ${b_mode} = 12; then
+ setenv b_tgts ${b_tgts_pme};
+ elif test ${b_mode} = 0; then
+ setenv b_tgts ${b_tgts_rcy};
+ else
+ setenv b_tgts ${b_tgts_std};
+ fi
diff --git a/board/BuR/zynq/env/brcp150.env b/board/BuR/zynq/env/brcp150.env
new file mode 100644
index 0000000..9c27f0f
--- /dev/null
+++ b/board/BuR/zynq/env/brcp150.env
@@ -0,0 +1,119 @@
+autoload=0
+b_break=0
+fpgastatus=disabled
+/* Memory variable */
+scradr=0xC0000
+fdtbackaddr=0x4000000
+loadaddr=CONFIG_SYS_LOAD_ADDR
+
+/* PREBOOT */
+preboot=run setupaddr_spi; run brdefaultip; run cfgscr; setenv bootstart 1
+
+/* SPI layout variables */
+cfg_addr=
+ fdt get value cfgaddr_spi /binman/blob-ext@0 offset &&
+ fdt get value cfgsize_spi /binman/blob-ext@0 size
+
+fpga_addr=
+ fdt get value fpgaaddr_spi /binman/blob-ext@1 offset &&
+ fdt get value fpgasize_spi /binman/blob-ext@1 size
+
+os_addr=
+ fdt get value osaddr_spi /binman/blob-ext@2 offset &&
+ fdt get value ossize_spi /binman/blob-ext@2 size
+
+dtb_addr=
+ fdt get value dtbaddr_spi /binman/blob-ext@3 offset &&
+ fdt get value dtbsize_spi /binman/blob-ext@3 size
+
+opt_addr=
+ fdt get value optaddr_spi /binman/blob-ext@5 offset &&
+ fdt get value optsize_spi /binman/blob-ext@5 size
+
+setupaddr_spi=
+ fdt addr ${fdtcontroladdr};
+ run dtb_addr; run os_addr;
+ run fpga_addr; run cfg_addr;
+ run opt_addr
+
+/* IP setup */
+brdefaultip=
+ if test -r ${ipaddr}; then;
+ else
+ setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254;
+ setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0;
+ fi
+
+/* Boot orders */
+b_tgts_std=mmc0 mmc1 fpga spi usb0 usb1 net
+b_tgts_rcy=spi usb0 usb1 net
+b_tgts_pme=net usb0 usb1 mmc spi
+
+/* Boot targets */
+b_mmc0=
+ mmc dev 0; load mmc 0 ${loadaddr} arimg.itb &&
+ run vxargs && bootm ${loadaddr}
+
+b_mmc1=
+ mmc dev 0; load mmc 0 ${loadaddr} arimg &&
+ run vxargs &&
+ sf read ${fdtbackaddr} ${dtbaddr_spi} ${dtbsize_spi} &&
+ fdt addr ${fdtbackaddr} &&
+ bootm ${loadaddr} - ${fdtbackaddr}
+
+b_spi=
+ sf read ${loadaddr} ${osaddr_spi} ${ossize_spi} &&
+ run vxargs && bootm ${loadaddr}
+
+b_net=tftp ${scradr} netscript.img && source ${scradr}
+b_usb0=usb start && load usb 0 ${scradr} usbscript.img && source ${scradr}
+b_usb1=usb start && load usb 0 ${scradr} bootscr.img && source ${scradr}
+
+/* FPGA setup */
+b_fpga=
+ setenv fpgastatus disabled;
+ sf read ${loadaddr} ${fpgaaddr_spi} ${fpgasize_spi} &&
+ fpga loadb 0 ${loadaddr} ${fpgasize_spi} &&
+ setenv fpgastatus okay
+
+/* Configuration preboot*/
+cfgscr=
+ sf probe &&
+ sf read ${scradr} ${cfgaddr_spi} ${cfgsize_spi} &&
+ source ${scradr}
+
+cfgoptsct=
+ sf probe &&
+ sf read ${scradr} ${optaddr_spi} ${optsize_spi} &&
+ source ${scradr}
+
+/* OS Boot */
+fdt_fixup=
+ run cfgscr; run cfgoptsct; run vxfdt
+
+vxargs=
+ setenv bootargs gem(0,0)host:vxWorks h=${serverip}
+ e=${ipaddr}:${netmask} g=${gatewayip} u=vxWorksFTP pw=vxWorks f=0x1
+
+vxfdt=
+ fdt set /fpga/pci status ${fpgastatus};
+ fdt set /fpga status ${fpgastatus}
+
+/* Boot code */
+b_default=
+ run b_deftgts;
+ for target in ${b_tgts}; do
+ run b_${target};
+ if test ${b_break} = 1; then;
+ exit;
+ fi;
+ done
+
+b_deftgts=
+ if test ${b_mode} = 12; then
+ setenv b_tgts ${b_tgts_pme};
+ elif test ${b_mode} = 0; then
+ setenv b_tgts ${b_tgts_rcy};
+ else
+ setenv b_tgts ${b_tgts_std};
+ fi
diff --git a/board/amd/versal2/Kconfig b/board/amd/versal2/Kconfig
deleted file mode 100644
index ab46af6..0000000
--- a/board/amd/versal2/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Copyright (C) 2020 - 2022, Xilinx, Inc.
-# Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
-#
-if ARCH_VERSAL2
-
-config CMD_VERSAL2
- bool "Enable Versal Gen 2 specific commands"
- default y
- depends on ZYNQMP_FIRMWARE
- help
- Select this to enable AMD Versal Gen 2 specific commands.
- Commands like versal2 loadpdi are enabled by this.
-
-endif
diff --git a/board/amd/versal2/Makefile b/board/amd/versal2/Makefile
index 3a04451..1673be4 100644
--- a/board/amd/versal2/Makefile
+++ b/board/amd/versal2/Makefile
@@ -8,4 +8,3 @@
obj-y := board.o
-obj-$(CONFIG_CMD_VERSAL2) += cmds.o
diff --git a/board/amd/versal2/board.c b/board/amd/versal2/board.c
index 5651d51..72967e6 100644
--- a/board/amd/versal2/board.c
+++ b/board/amd/versal2/board.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 - 2022, Xilinx, Inc.
- * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
+ * Copyright (C) 2022 - 2025, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -20,6 +20,7 @@
#include <asm/arch/sys_proto.h>
#include <dm/device.h>
#include <dm/uclass.h>
+#include <versalpl.h>
#include "../../xilinx/common/board.h"
#include <linux/bitfield.h>
@@ -28,10 +29,25 @@
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_FPGA_VERSALPL)
+static xilinx_desc versalpl = {
+ xilinx_versal2, csu_dma, 1, &versal_op, 0, &versal_op, NULL,
+ FPGA_LEGACY
+};
+#endif
+
int board_init(void)
{
printf("EL Level:\tEL%d\n", current_el());
+#if defined(CONFIG_FPGA_VERSALPL)
+ fpga_init();
+ fpga_add(fpga_xilinx, &versalpl);
+#endif
+
+ if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
+ xilinx_read_eeprom();
+
return 0;
}
@@ -149,7 +165,7 @@
return 0;
}
-static u8 versal_net_get_bootmode(void)
+static u8 versal2_get_bootmode(void)
{
u8 bootmode;
u32 reg = 0;
@@ -175,7 +191,7 @@
char *new_targets;
char *env_targets;
- bootmode = versal_net_get_bootmode();
+ bootmode = versal2_get_bootmode();
puts("Bootmode: ");
switch (bootmode) {
@@ -252,6 +268,16 @@
mode = "mmc";
bootseq = dev_seq(dev);
break;
+ case UFS_MODE:
+ puts("UFS_MODE\n");
+ if (uclass_get_device(UCLASS_UFS, 0, &dev)) {
+ debug("UFS driver for UFS device is not present\n");
+ break;
+ }
+ debug("ufs device found at %p\n", dev);
+
+ mode = "ufs";
+ break;
default:
printf("Invalid Boot Mode:0x%x\n", bootmode);
break;
@@ -284,6 +310,7 @@
env_targets ? env_targets : "");
env_set("boot_targets", new_targets);
+ free(new_targets);
}
return 0;
@@ -340,4 +367,36 @@
void reset_cpu(void)
{
+}
+
+#if defined(CONFIG_ENV_IS_NOWHERE)
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ u32 bootmode = versal2_get_bootmode();
+
+ if (prio)
+ return ENVL_UNKNOWN;
+
+ switch (bootmode) {
+ case EMMC_MODE:
+ case SD_MODE:
+ case SD1_LSHFT_MODE:
+ case SD_MODE1:
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
+ return ENVL_FAT;
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
+ return ENVL_EXT4;
+ return ENVL_NOWHERE;
+ case OSPI_MODE:
+ case QSPI_MODE_24BIT:
+ case QSPI_MODE_32BIT:
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
+ return ENVL_SPI_FLASH;
+ return ENVL_NOWHERE;
+ case JTAG_MODE:
+ case SELECTMAP_MODE:
+ default:
+ return ENVL_NOWHERE;
+ }
}
+#endif
diff --git a/board/amd/versal2/cmds.c b/board/amd/versal2/cmds.c
deleted file mode 100644
index 56ae39b..0000000
--- a/board/amd/versal2/cmds.c
+++ /dev/null
@@ -1,80 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2024, Advanced Micro Devices, Inc.
- *
- * Michal Simek <michal.simek@amd.com>
- */
-
-#include <cpu_func.h>
-#include <command.h>
-#include <log.h>
-#include <memalign.h>
-#include <versalpl.h>
-#include <vsprintf.h>
-#include <zynqmp_firmware.h>
-
-/**
- * do_versal2_load_pdi - Handle the "versal2 load pdi" command-line command
- * @cmdtp: Command data struct pointer
- * @flag: Command flag
- * @argc: Command-line argument count
- * @argv: Array of command-line arguments
- *
- * Processes the versal2 load pdi command
- *
- * Return: return 0 on success, Error value if command fails.
- * CMD_RET_USAGE incase of incorrect/missing parameters.
- */
-static int do_versal2_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc,
- char * const argv[])
-{
- u32 buf_lo, buf_hi;
- u32 ret_payload[PAYLOAD_ARG_CNT];
- ulong addr, *pdi_buf;
- size_t len;
- int ret;
-
- if (argc != cmdtp->maxargs) {
- debug("pdi_load: incorrect parameters passed\n");
- return CMD_RET_USAGE;
- }
-
- addr = simple_strtol(argv[1], NULL, 16);
- if (!addr) {
- debug("pdi_load: zero pdi_data address\n");
- return CMD_RET_USAGE;
- }
-
- len = hextoul(argv[2], NULL);
- if (!len) {
- debug("pdi_load: zero size\n");
- return CMD_RET_USAGE;
- }
-
- pdi_buf = (ulong *)ALIGN((ulong)addr, ARCH_DMA_MINALIGN);
- if ((ulong)addr != (ulong)pdi_buf) {
- memcpy((void *)pdi_buf, (void *)addr, len);
- debug("Pdi addr:0x%lx aligned to 0x%lx\n",
- addr, (ulong)pdi_buf);
- }
-
- flush_dcache_range((ulong)pdi_buf, (ulong)pdi_buf + len);
-
- buf_lo = lower_32_bits((ulong)pdi_buf);
- buf_hi = upper_32_bits((ulong)pdi_buf);
-
- ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
- buf_hi, 0, ret_payload);
- if (ret)
- printf("PDI load failed with err: 0x%08x\n", ret);
-
- return cmd_process_error(cmdtp, ret);
-}
-
-U_BOOT_LONGHELP(versal2,
- "loadpdi addr len - Load pdi image\n"
- "load pdi image at ddr address 'addr' with pdi image size 'len'\n");
-
-U_BOOT_CMD_WITH_SUBCMDS(versal2, "Versal Gen 2 sub-system", versal2_help_text,
- U_BOOT_SUBCMD_MKENT(loadpdi, 3, 1,
- do_versal2_load_pdi));
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index deea6c7..8ffe742 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -80,7 +80,7 @@
};
static int highest_id = -1;
-static struct xilinx_board_description *board_info;
+static struct xilinx_board_description *board_info __section(".data");
#define XILINX_I2C_DETECTION_BITS sizeof(struct fru_common_hdr)
@@ -468,6 +468,9 @@
ret |= env_set_addr("bootm_size", (void *)bootm_size);
for (id = 0; id <= highest_id; id++) {
+ if (!board_info)
+ break;
+
desc = &board_info[id];
if (desc && desc->header == EEPROM_HEADER_MAGIC) {
if (desc->manufacturer[0])
diff --git a/board/xilinx/versal-net/Kconfig b/board/xilinx/versal-net/Kconfig
deleted file mode 100644
index 2484429..0000000
--- a/board/xilinx/versal-net/Kconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Copyright (C) 2020 - 2022, Xilinx, Inc.
-# Copyright (C) 2022, Advanced Micro Devices, Inc.
-#
-
-if ARCH_VERSAL_NET
-
-config CMD_VERSAL_NET
- bool "Enable Versal NET specific commands"
- default y
- depends on ZYNQMP_FIRMWARE
- help
- Select this to enable Versal NET specific commands.
- Commands like versalnet loadpdi are enabled by this.
-
-endif
diff --git a/board/xilinx/versal-net/Makefile b/board/xilinx/versal-net/Makefile
index f9ff07c..2008d4e 100644
--- a/board/xilinx/versal-net/Makefile
+++ b/board/xilinx/versal-net/Makefile
@@ -7,4 +7,3 @@
#
obj-y := board.o
-obj-$(CONFIG_CMD_VERSAL_NET) += cmds.o
diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c
index 4d5913c..65b2a45 100644
--- a/board/xilinx/versal-net/board.c
+++ b/board/xilinx/versal-net/board.c
@@ -21,6 +21,8 @@
#include <asm/arch/sys_proto.h>
#include <dm/device.h>
#include <dm/uclass.h>
+#include <zynqmp_firmware.h>
+#include <versalpl.h>
#include "../common/board.h"
#include <linux/bitfield.h>
@@ -29,10 +31,21 @@
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_FPGA_VERSALPL)
+static xilinx_desc versalpl = {
+ xilinx_versal_net, csu_dma, 1, &versal_op, 0, &versal_op, NULL,
+ FPGA_LEGACY
+};
+#endif
+
int board_init(void)
{
printf("EL Level:\tEL%d\n", current_el());
+#if defined(CONFIG_FPGA_VERSALPL)
+ fpga_init();
+ fpga_add(fpga_xilinx, &versalpl);
+#endif
return 0;
}
@@ -184,7 +197,11 @@
u8 bootmode;
u32 reg = 0;
- reg = readl(&crp_base->boot_mode_usr);
+ if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3) {
+ reg = zynqmp_pm_get_bootmode_reg();
+ } else {
+ reg = readl(&crp_base->boot_mode_usr);
+ }
if (reg >> BOOT_MODE_ALT_SHIFT)
reg >>= BOOT_MODE_ALT_SHIFT;
diff --git a/board/xilinx/versal-net/cmds.c b/board/xilinx/versal-net/cmds.c
deleted file mode 100644
index e8b669f..0000000
--- a/board/xilinx/versal-net/cmds.c
+++ /dev/null
@@ -1,80 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2023, Advanced Micro Devices, Inc.
- *
- * Michal Simek <michal.simek@amd.com>
- */
-
-#include <cpu_func.h>
-#include <command.h>
-#include <log.h>
-#include <memalign.h>
-#include <versalpl.h>
-#include <vsprintf.h>
-#include <zynqmp_firmware.h>
-
-/**
- * do_versalnet_load_pdi - Handle the "versalnet load pdi" command-line command
- * @cmdtp: Command data struct pointer
- * @flag: Command flag
- * @argc: Command-line argument count
- * @argv: Array of command-line arguments
- *
- * Processes the Versal NET load pdi command
- *
- * Return: return 0 on success, Error value if command fails.
- * CMD_RET_USAGE incase of incorrect/missing parameters.
- */
-static int do_versalnet_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc,
- char * const argv[])
-{
- u32 buf_lo, buf_hi;
- u32 ret_payload[PAYLOAD_ARG_CNT];
- ulong addr, *pdi_buf;
- size_t len;
- int ret;
-
- if (argc != cmdtp->maxargs) {
- debug("pdi_load: incorrect parameters passed\n");
- return CMD_RET_USAGE;
- }
-
- addr = simple_strtol(argv[1], NULL, 16);
- if (!addr) {
- debug("pdi_load: zero pdi_data address\n");
- return CMD_RET_USAGE;
- }
-
- len = hextoul(argv[2], NULL);
- if (!len) {
- debug("pdi_load: zero size\n");
- return CMD_RET_USAGE;
- }
-
- pdi_buf = (ulong *)ALIGN((ulong)addr, ARCH_DMA_MINALIGN);
- if ((ulong)addr != (ulong)pdi_buf) {
- memcpy((void *)pdi_buf, (void *)addr, len);
- debug("Pdi addr:0x%lx aligned to 0x%lx\n",
- addr, (ulong)pdi_buf);
- }
-
- flush_dcache_range((ulong)pdi_buf, (ulong)pdi_buf + len);
-
- buf_lo = lower_32_bits((ulong)pdi_buf);
- buf_hi = upper_32_bits((ulong)pdi_buf);
-
- ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
- buf_hi, 0, ret_payload);
- if (ret)
- printf("PDI load failed with err: 0x%08x\n", ret);
-
- return cmd_process_error(cmdtp, ret);
-}
-
-U_BOOT_LONGHELP(versalnet,
- "loadpdi addr len - Load pdi image\n"
- "load pdi image at ddr address 'addr' with pdi image size 'len'\n");
-
-U_BOOT_CMD_WITH_SUBCMDS(versalnet, "Versal NET sub-system", versalnet_help_text,
- U_BOOT_SUBCMD_MKENT(loadpdi, 3, 1,
- do_versalnet_load_pdi));
diff --git a/board/xilinx/versal/Kconfig b/board/xilinx/versal/Kconfig
deleted file mode 100644
index c0cccc2..0000000
--- a/board/xilinx/versal/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-# Copyright (c) 2020, Xilinx, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0
-
-if ARCH_VERSAL
-
-config CMD_VERSAL
- bool "Enable Versal specific commands"
- default y
- depends on ZYNQMP_FIRMWARE
- help
- Enable Versal specific commands.
-
-endif
diff --git a/board/xilinx/versal/Makefile b/board/xilinx/versal/Makefile
index d912f2e..761e084 100644
--- a/board/xilinx/versal/Makefile
+++ b/board/xilinx/versal/Makefile
@@ -5,4 +5,3 @@
#
obj-y := board.o
-obj-$(CONFIG_CMD_VERSAL) += cmds.o
diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
index 0553073..9371c30 100644
--- a/board/xilinx/versal/board.c
+++ b/board/xilinx/versal/board.c
@@ -27,6 +27,7 @@
#include <dm/device.h>
#include <dm/uclass.h>
#include <versalpl.h>
+#include <zynqmp_firmware.h>
#include "../common/board.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -43,7 +44,11 @@
u8 bootmode;
u32 reg = 0;
- reg = readl(&crp_base->boot_mode_usr);
+ if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3) {
+ reg = zynqmp_pm_get_bootmode_reg();
+ } else {
+ reg = readl(&crp_base->boot_mode_usr);
+ }
if (reg >> BOOT_MODE_ALT_SHIFT)
reg >>= BOOT_MODE_ALT_SHIFT;
@@ -56,12 +61,18 @@
static u32 versal_multi_boot(void)
{
u8 bootmode = versal_get_bootmode();
+ u32 reg = 0;
/* Mostly workaround for QEMU CI pipeline */
if (bootmode == JTAG_MODE)
return 0;
- return readl(0xF1110004);
+ if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3)
+ reg = zynqmp_pm_get_pmc_multi_boot_reg();
+ else
+ reg = readl(PMC_MULTI_BOOT_REG);
+
+ return reg & PMC_MULTI_BOOT_MASK;
}
int board_init(void)
@@ -272,6 +283,7 @@
env_targets ? env_targets : "");
env_set("boot_targets", new_targets);
+ free(new_targets);
}
return 0;
@@ -395,7 +407,7 @@
ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
- memset(buf, 0, sizeof(buf));
+ memset(buf, 0, DFU_ALT_BUF_LEN);
multiboot = env_get_hex("multiboot", multiboot);
diff --git a/board/xilinx/versal/cmds.c b/board/xilinx/versal/cmds.c
deleted file mode 100644
index c787935..0000000
--- a/board/xilinx/versal/cmds.c
+++ /dev/null
@@ -1,101 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * (C) Copyright 2020 Xilinx, Inc.
- * Michal Simek <michal.simek@amd.com>
- */
-
-#include <cpu_func.h>
-#include <command.h>
-#include <log.h>
-#include <memalign.h>
-#include <versalpl.h>
-#include <vsprintf.h>
-#include <zynqmp_firmware.h>
-
-static int do_versal_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc,
- char * const argv[])
-{
- u32 buf_lo, buf_hi;
- u32 ret_payload[PAYLOAD_ARG_CNT];
- ulong addr, *pdi_buf;
- size_t len;
- int ret;
-
- if (argc != cmdtp->maxargs) {
- debug("pdi_load: incorrect parameters passed\n");
- return CMD_RET_USAGE;
- }
-
- addr = simple_strtol(argv[2], NULL, 16);
- if (!addr) {
- debug("pdi_load: zero pdi_data address\n");
- return CMD_RET_USAGE;
- }
-
- len = hextoul(argv[3], NULL);
- if (!len) {
- debug("pdi_load: zero size\n");
- return CMD_RET_USAGE;
- }
-
- pdi_buf = (ulong *)ALIGN((ulong)addr, ARCH_DMA_MINALIGN);
- if ((ulong)addr != (ulong)pdi_buf) {
- memcpy((void *)pdi_buf, (void *)addr, len);
- debug("Pdi addr:0x%lx aligned to 0x%lx\n",
- addr, (ulong)pdi_buf);
- }
-
- flush_dcache_range((ulong)pdi_buf, (ulong)pdi_buf + len);
-
- buf_lo = lower_32_bits((ulong)pdi_buf);
- buf_hi = upper_32_bits((ulong)pdi_buf);
-
- ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
- buf_hi, 0, ret_payload);
- if (ret)
- printf("PDI load failed with err: 0x%08x\n", ret);
-
- return ret;
-}
-
-static struct cmd_tbl cmd_versal_sub[] = {
- U_BOOT_CMD_MKENT(loadpdi, 4, 1, do_versal_load_pdi, "", ""),
-};
-
-/**
- * do_versal - Handle the "versal" command-line command
- * @cmdtp: Command data struct pointer
- * @flag: Command flag
- * @argc: Command-line argument count
- * @argv: Array of command-line arguments
- *
- * Processes the versal specific commands
- *
- * Return: return 0 on success, Error value if command fails.
- * CMD_RET_USAGE incase of incorrect/missing parameters.
- */
-static int do_versal(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
-{
- struct cmd_tbl *c;
- int ret = CMD_RET_USAGE;
-
- if (argc < 2)
- return CMD_RET_USAGE;
-
- c = find_cmd_tbl(argv[1], &cmd_versal_sub[0],
- ARRAY_SIZE(cmd_versal_sub));
- if (c)
- ret = c->cmd(c, flag, argc, argv);
-
- return cmd_process_error(c, ret);
-}
-
-U_BOOT_LONGHELP(versal,
- "loadpdi addr len - Load pdi image\n"
- "load pdi image at ddr address 'addr' with pdi image size 'len'\n");
-
-U_BOOT_CMD(versal, 4, 1, do_versal,
- "versal sub-system",
- versal_help_text
-);
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 5efef61..04dee1b 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -175,7 +175,7 @@
{
ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
- memset(buf, 0, sizeof(buf));
+ memset(buf, 0, DFU_ALT_BUF_LEN);
switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
#if defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME)
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 33205d4..735ef3c 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -668,7 +668,7 @@
ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
- memset(buf, 0, sizeof(buf));
+ memset(buf, 0, DFU_ALT_BUF_LEN);
multiboot = multi_boot();
if (multiboot < 0)
diff --git a/board/xilinx/zynqmp/zynqmp_kria.env b/board/xilinx/zynqmp/zynqmp_kria.env
index 75b604a..89f48c0 100644
--- a/board/xilinx/zynqmp/zynqmp_kria.env
+++ b/board/xilinx/zynqmp/zynqmp_kria.env
@@ -42,7 +42,7 @@
script_size_f=0x80000
scriptaddr=0x20000000
usb_boot=usb start; if usb dev ${devnum}; then devtype=usb; run scan_dev_for_boot_part; fi
-preboot=setenv boot_targets; setenv modeboot; run board_setup
+preboot=setenv boot_targets; setenv modeboot; run board_setup; usb start
usb_pgood_delay=1000
# SOM specific boot methods
diff --git a/configs/amd_versal2_mini_defconfig b/configs/amd_versal2_mini_defconfig
index b657118..d224583 100644
--- a/configs/amd_versal2_mini_defconfig
+++ b/configs/amd_versal2_mini_defconfig
@@ -13,12 +13,9 @@
CONFIG_ENV_SIZE=0x80
CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-mini"
CONFIG_SYS_LOAD_ADDR=0xBBF80000
-CONFIG_DEBUG_UART_BASE=0xf1920000
-CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_XILINX_MINI=y
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
# CONFIG_PSCI_RESET is not set
-CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00001000
# CONFIG_EXPERT is not set
@@ -71,9 +68,6 @@
# CONFIG_INPUT is not set
# CONFIG_MMC is not set
# CONFIG_POWER is not set
-CONFIG_DEBUG_UART_PL011=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_ARM_DCC=y
CONFIG_PL01X_SERIAL=y
# CONFIG_GZIP is not set
diff --git a/configs/amd_versal2_mini_emmc_defconfig b/configs/amd_versal2_mini_emmc_defconfig
index da3eebe..3afc6cb 100644
--- a/configs/amd_versal2_mini_emmc_defconfig
+++ b/configs/amd_versal2_mini_emmc_defconfig
@@ -10,11 +10,8 @@
CONFIG_ENV_SIZE=0x80
CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-mini"
CONFIG_SYS_LOAD_ADDR=0x8000000
-CONFIG_DEBUG_UART_BASE=0xf1920000
-CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_XILINX_MINI=y
# CONFIG_PSCI_RESET is not set
-CONFIG_DEBUG_UART=y
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
# CONFIG_EFI_LOADER is not set
@@ -60,9 +57,6 @@
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_DEBUG_UART_PL011=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_ARM_DCC=y
CONFIG_PL01X_SERIAL=y
CONFIG_FAT_WRITE=y
diff --git a/configs/amd_versal2_mini_ospi_defconfig b/configs/amd_versal2_mini_ospi_defconfig
index 8b9c440..54328e8 100644
--- a/configs/amd_versal2_mini_ospi_defconfig
+++ b/configs/amd_versal2_mini_ospi_defconfig
@@ -13,12 +13,9 @@
CONFIG_ENV_SIZE=0x80
CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-mini"
CONFIG_SYS_LOAD_ADDR=0xBBF80000
-CONFIG_DEBUG_UART_BASE=0xf1920000
-CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_XILINX_MINI=y
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
# CONFIG_PSCI_RESET is not set
-CONFIG_DEBUG_UART=y
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
# CONFIG_LEGACY_IMAGE_FORMAT is not set
@@ -72,9 +69,6 @@
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MT35XU=y
# CONFIG_POWER is not set
-CONFIG_DEBUG_UART_PL011=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_ARM_DCC=y
CONFIG_PL01X_SERIAL=y
CONFIG_SPI=y
diff --git a/configs/amd_versal2_mini_qspi_defconfig b/configs/amd_versal2_mini_qspi_defconfig
index e17ca86..48fb7ae 100644
--- a/configs/amd_versal2_mini_qspi_defconfig
+++ b/configs/amd_versal2_mini_qspi_defconfig
@@ -13,12 +13,9 @@
CONFIG_ENV_SIZE=0x80
CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-mini"
CONFIG_SYS_LOAD_ADDR=0xBBF80000
-CONFIG_DEBUG_UART_BASE=0xf1920000
-CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_XILINX_MINI=y
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
# CONFIG_PSCI_RESET is not set
-CONFIG_DEBUG_UART=y
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
# CONFIG_LEGACY_IMAGE_FORMAT is not set
@@ -65,9 +62,6 @@
# CONFIG_INPUT is not set
# CONFIG_MMC is not set
# CONFIG_POWER is not set
-CONFIG_DEBUG_UART_PL011=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_ARM_DCC=y
CONFIG_PL01X_SERIAL=y
CONFIG_SPI=y
diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig
index 9911caa..6ec7dd3 100644
--- a/configs/amd_versal2_virt_defconfig
+++ b/configs/amd_versal2_virt_defconfig
@@ -3,17 +3,15 @@
CONFIG_POSITION_INDEPENDENT=y
CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864
CONFIG_ARCH_VERSAL2=y
-CONFIG_TEXT_BASE=0x8000000
+CONFIG_TEXT_BASE=0x40000000
CONFIG_SYS_MALLOC_F_LEN=0x100000
+CONFIG_NR_DRAM_BANKS=36
CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-virt"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_SYS_BOOTM_LEN=0x6400000
CONFIG_SYS_LOAD_ADDR=0x8000000
-CONFIG_DEBUG_UART_BASE=0xf1920000
-CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_CMD_FRU=y
-CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00001000
CONFIG_REMAKE_ELF=y
@@ -28,6 +26,7 @@
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_CLOCKS=y
CONFIG_SYS_PROMPT="versal2> "
+CONFIG_CMD_SMBIOS=y
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_NVEDIT_EFI=y
@@ -64,8 +63,9 @@
CONFIG_CMD_UBI=y
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_BOARD=y
-CONFIG_DTB_RESELECT=y
-CONFIG_MULTI_DTB_FIT=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_LWIP=y
@@ -75,6 +75,8 @@
CONFIG_CLK_SCMI=y
CONFIG_DFU_RAM=y
CONFIG_ARM_FFA_TRANSPORT=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_VERSALPL=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_I2C_MUX=y
@@ -82,6 +84,7 @@
CONFIG_DM_MAILBOX=y
CONFIG_ZYNQMP_IPI=y
CONFIG_MISC=y
+CONFIG_NVMEM=y
CONFIG_I2C_EEPROM=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
@@ -113,11 +116,10 @@
CONFIG_XILINX_AXIEMAC=y
CONFIG_ZYNQ_GEM=y
CONFIG_POWER_DOMAIN=y
+CONFIG_ZYNQMP_POWER_DOMAIN=y
CONFIG_RESET_SCMI=y
+CONFIG_RESET_ZYNQMP=y
CONFIG_SCSI=y
-CONFIG_DEBUG_UART_PL011=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_ARM_DCC=y
CONFIG_PL01X_SERIAL=y
CONFIG_SOC_DEVICE=y
diff --git a/configs/brcp150_defconfig b/configs/brcp150_defconfig
new file mode 100644
index 0000000..d619f71
--- /dev/null
+++ b/configs/brcp150_defconfig
@@ -0,0 +1,121 @@
+CONFIG_ARM=y
+CONFIG_SYS_VENDOR="BuR"
+CONFIG_SYS_CONFIG_NAME="brzynq"
+CONFIG_SYS_L2CACHE_OFF=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SOURCE_FILE="env/brcp150"
+CONFIG_SF_DEFAULT_SPEED=100000000
+CONFIG_SF_DEFAULT_MODE=0x3
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x20000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp150"
+CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000
+# CONFIG_SPL_MMC is not set
+CONFIG_SPL_STACK_R_ADDR=0x800000
+CONFIG_SPL_STACK=0xFFFFFE00
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x20000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_LOAD_ADDR=0x2000000
+CONFIG_SPL_SIZE_LIMIT=0x20000
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x30000
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000
+CONFIG_TARGET_ZYNQ_BR=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000
+CONFIG_SPL_LOAD_FIT_FULL=y
+CONFIG_BOOTDELAY=0
+CONFIG_OF_ENV_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run b_default"
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_CLOCKS=y
+CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
+CONFIG_SPL_CPU=y
+CONFIG_SPL_FPGA=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_HUSH_PARSER=y
+CONFIG_HUSH_MODERN_PARSER=y
+CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_BOOTP_MAY_FAIL=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_NET_RETRY_COUNT=10
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
+CONFIG_MAX7320_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_ZYNQ_HISPD_BROKEN=y
+CONFIG_DM_MTD=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HX_T=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_ZBIT=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_PHY_TI_GENERIC=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y
+# CONFIG_SHA256 is not set
+CONFIG_SPL_CRC32=y
+# CONFIG_SPL_SHA1 is not set
diff --git a/configs/brcp170_defconfig b/configs/brcp170_defconfig
new file mode 100644
index 0000000..06cd64a
--- /dev/null
+++ b/configs/brcp170_defconfig
@@ -0,0 +1,120 @@
+CONFIG_ARM=y
+CONFIG_SYS_VENDOR="BuR"
+CONFIG_SYS_CONFIG_NAME="brzynq"
+CONFIG_SYS_L2CACHE_OFF=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SOURCE_FILE="env/brcp1"
+CONFIG_SF_DEFAULT_SPEED=100000000
+CONFIG_SF_DEFAULT_MODE=0x3
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x20000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp170"
+CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000
+# CONFIG_SPL_MMC is not set
+CONFIG_SPL_STACK_R_ADDR=0x800000
+CONFIG_SPL_STACK=0xFFFFFE00
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x20000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_LOAD_ADDR=0x2000000
+CONFIG_SPL_SIZE_LIMIT=0x20000
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x30000
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000
+CONFIG_TARGET_ZYNQ_BR=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000
+CONFIG_SPL_LOAD_FIT_FULL=y
+CONFIG_BOOTDELAY=0
+CONFIG_OF_ENV_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run b_default"
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_CLOCKS=y
+CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
+CONFIG_SPL_CPU=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_HUSH_PARSER=y
+CONFIG_HUSH_MODERN_PARSER=y
+CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_BOOTP_MAY_FAIL=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_NET_RETRY_COUNT=10
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
+CONFIG_MAX7320_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_ZYNQ_HISPD_BROKEN=y
+CONFIG_DM_MTD=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HX_T=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_ZBIT=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_PHY_TI_GENERIC=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y
+# CONFIG_SHA256 is not set
+CONFIG_SPL_CRC32=y
+# CONFIG_SPL_SHA1 is not set
diff --git a/configs/brcp1_1r_defconfig b/configs/brcp1_1r_defconfig
new file mode 100644
index 0000000..ed2eb86
--- /dev/null
+++ b/configs/brcp1_1r_defconfig
@@ -0,0 +1,120 @@
+CONFIG_ARM=y
+CONFIG_SYS_VENDOR="BuR"
+CONFIG_SYS_CONFIG_NAME="brzynq"
+CONFIG_SYS_L2CACHE_OFF=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SOURCE_FILE="env/brcp1"
+CONFIG_SF_DEFAULT_SPEED=100000000
+CONFIG_SF_DEFAULT_MODE=0x3
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x20000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp1_1r"
+CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000
+# CONFIG_SPL_MMC is not set
+CONFIG_SPL_STACK_R_ADDR=0x800000
+CONFIG_SPL_STACK=0xFFFFFE00
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x20000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_LOAD_ADDR=0x2000000
+CONFIG_SPL_SIZE_LIMIT=0x20000
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x30000
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000
+CONFIG_TARGET_ZYNQ_BR=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000
+CONFIG_SPL_LOAD_FIT_FULL=y
+CONFIG_BOOTDELAY=0
+CONFIG_OF_ENV_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run b_default"
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_CLOCKS=y
+CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
+CONFIG_SPL_CPU=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_HUSH_PARSER=y
+CONFIG_HUSH_MODERN_PARSER=y
+CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_BOOTP_MAY_FAIL=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_NET_RETRY_COUNT=10
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
+CONFIG_MAX7320_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_ZYNQ_HISPD_BROKEN=y
+CONFIG_DM_MTD=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HX_T=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_ZBIT=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y
+# CONFIG_SHA256 is not set
+CONFIG_SPL_CRC32=y
+# CONFIG_SPL_SHA1 is not set
diff --git a/configs/brcp1_1r_switch_defconfig b/configs/brcp1_1r_switch_defconfig
new file mode 100644
index 0000000..38427da
--- /dev/null
+++ b/configs/brcp1_1r_switch_defconfig
@@ -0,0 +1,121 @@
+CONFIG_ARM=y
+CONFIG_SYS_VENDOR="BuR"
+CONFIG_SYS_CONFIG_NAME="brzynq"
+CONFIG_SYS_L2CACHE_OFF=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SOURCE_FILE="env/brcp1"
+CONFIG_SF_DEFAULT_SPEED=100000000
+CONFIG_SF_DEFAULT_MODE=0x3
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x20000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp1_1r_switch"
+CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000
+# CONFIG_SPL_MMC is not set
+CONFIG_SPL_STACK_R_ADDR=0x800000
+CONFIG_SPL_STACK=0xFFFFFE00
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x20000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_LOAD_ADDR=0x2000000
+CONFIG_SPL_SIZE_LIMIT=0x20000
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x30000
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000
+CONFIG_TARGET_ZYNQ_BR=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000
+CONFIG_SPL_LOAD_FIT_FULL=y
+CONFIG_BOOTDELAY=0
+CONFIG_OF_ENV_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run b_default"
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_CLOCKS=y
+CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
+CONFIG_SPL_CPU=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_HUSH_PARSER=y
+CONFIG_HUSH_MODERN_PARSER=y
+CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_BOOTP_MAY_FAIL=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_NET_RETRY_COUNT=10
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
+CONFIG_MAX7320_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_ZYNQ_HISPD_BROKEN=y
+CONFIG_DM_MTD=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HX_T=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_ZBIT=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_FIXED=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y
+# CONFIG_SHA256 is not set
+CONFIG_SPL_CRC32=y
+# CONFIG_SPL_SHA1 is not set
diff --git a/configs/brcp1_2r_defconfig b/configs/brcp1_2r_defconfig
new file mode 100644
index 0000000..2bc8eab
--- /dev/null
+++ b/configs/brcp1_2r_defconfig
@@ -0,0 +1,120 @@
+CONFIG_ARM=y
+CONFIG_SYS_VENDOR="BuR"
+CONFIG_SYS_CONFIG_NAME="brzynq"
+CONFIG_SYS_L2CACHE_OFF=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SOURCE_FILE="env/brcp1"
+CONFIG_SF_DEFAULT_SPEED=100000000
+CONFIG_SF_DEFAULT_MODE=0x3
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x20000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp1_2r"
+CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000
+# CONFIG_SPL_MMC is not set
+CONFIG_SPL_STACK_R_ADDR=0x800000
+CONFIG_SPL_STACK=0xFFFFFE00
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x20000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_LOAD_ADDR=0x2000000
+CONFIG_SPL_SIZE_LIMIT=0x20000
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x30000
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000
+CONFIG_TARGET_ZYNQ_BR=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000
+CONFIG_SPL_LOAD_FIT_FULL=y
+CONFIG_BOOTDELAY=0
+CONFIG_OF_ENV_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run b_default"
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_CLOCKS=y
+CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
+CONFIG_SPL_CPU=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_HUSH_PARSER=y
+CONFIG_HUSH_MODERN_PARSER=y
+CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_BOOTP_MAY_FAIL=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_NET_RETRY_COUNT=10
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
+CONFIG_MAX7320_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_ZYNQ_HISPD_BROKEN=y
+CONFIG_DM_MTD=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HX_T=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_ZBIT=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y
+# CONFIG_SHA256 is not set
+CONFIG_SPL_CRC32=y
+# CONFIG_SPL_SHA1 is not set
diff --git a/configs/brsmarc2_defconfig b/configs/brsmarc2_defconfig
new file mode 100644
index 0000000..0b57042
--- /dev/null
+++ b/configs/brsmarc2_defconfig
@@ -0,0 +1,120 @@
+CONFIG_ARM=y
+CONFIG_SYS_VENDOR="BuR"
+CONFIG_SYS_CONFIG_NAME="brzynq"
+CONFIG_SYS_L2CACHE_OFF=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SOURCE_FILE="env/brcp1"
+CONFIG_SF_DEFAULT_SPEED=100000000
+CONFIG_SF_DEFAULT_MODE=0x3
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x20000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-brsmarc2"
+CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000
+# CONFIG_SPL_MMC is not set
+CONFIG_SPL_STACK_R_ADDR=0x800000
+CONFIG_SPL_STACK=0xFFFFFE00
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x20000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_LOAD_ADDR=0x2000000
+CONFIG_SPL_SIZE_LIMIT=0x20000
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x30000
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000
+CONFIG_TARGET_ZYNQ_BR=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000
+CONFIG_SPL_LOAD_FIT_FULL=y
+CONFIG_BOOTDELAY=0
+CONFIG_OF_ENV_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run b_default"
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_CLOCKS=y
+CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
+CONFIG_SPL_CPU=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_HUSH_PARSER=y
+CONFIG_HUSH_MODERN_PARSER=y
+CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_BOOTP_MAY_FAIL=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_NET_RETRY_COUNT=10
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
+CONFIG_MAX7320_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_ZYNQ_HISPD_BROKEN=y
+CONFIG_DM_MTD=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HX_T=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_ZBIT=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y
+# CONFIG_SHA256 is not set
+CONFIG_SPL_CRC32=y
+# CONFIG_SPL_SHA1 is not set
diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig
index 6bfcaab..1be8d89 100644
--- a/configs/topic_miami_defconfig
+++ b/configs/topic_miami_defconfig
@@ -28,9 +28,9 @@
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=0
-CONFIG_BOOTCOMMAND="if mmcinfo; then if fatload mmc 0 0x1900000 ${bootscript}; then source 0x1900000; fi; fi; run $modeboot"
CONFIG_USE_PREBOOT=y
CONFIG_SYS_PBSIZE=2077
+# CONFIG_BOARD_LATE_INIT is not set
CONFIG_CLOCKS=y
CONFIG_SPL_MAX_SIZE=0x30000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
@@ -41,15 +41,25 @@
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SYS_PROMPT="zynq-uboot> "
CONFIG_SYS_MAXARGS=32
+# CONFIG_CMD_BOOTEFI is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_SPL is not set
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_THOR_RESET_OFF=y
+# CONFIG_CMD_SAVEENV is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DFU=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
+# CONFIG_CMD_EFICONFIG is not set
+CONFIG_CMD_SQUASHFS=y
+CONFIG_MTDIDS_DEFAULT="nor0=spi0.0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:0x100000(qspi-boot-bin),-(qspi-rootfs)"
+CONFIG_CMD_UBI=y
CONFIG_OF_EMBED=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
@@ -57,14 +67,18 @@
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_RAM=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x600000
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQPL=y
+CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_BLOCK=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_MTD_UBI_BEB_LIMIT=0
+CONFIG_UBI_BLOCK=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_ARM_DCC=y
CONFIG_ZYNQ_SERIAL=y
@@ -80,3 +94,4 @@
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_SYS_TIMER_COUNTS_DOWN=y
+CONFIG_LZ4=y
diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig
index e1cdc18..af9ce49 100644
--- a/configs/xilinx_versal_mini_ospi_defconfig
+++ b/configs/xilinx_versal_mini_ospi_defconfig
@@ -7,7 +7,7 @@
CONFIG_SYS_MALLOC_F_LEN=0x500
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xFFFFFE00
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xFFFE1000
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_ENV_SIZE=0x80
# CONFIG_DM_GPIO is not set
diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig
index 1604b59..a82ccdc 100644
--- a/configs/xilinx_versal_net_virt_defconfig
+++ b/configs/xilinx_versal_net_virt_defconfig
@@ -74,6 +74,8 @@
CONFIG_CLK_VERSAL=y
CONFIG_DFU_RAM=y
CONFIG_ARM_FFA_TRANSPORT=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_VERSALPL=y
CONFIG_ZYNQ_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
@@ -121,7 +123,6 @@
CONFIG_RESET_ZYNQMP=y
CONFIG_ARM_DCC=y
CONFIG_PL01X_SERIAL=y
-CONFIG_XILINX_UARTLITE=y
CONFIG_SOC_DEVICE=y
CONFIG_SOC_XILINX_VERSAL_NET=y
CONFIG_SPI=y
diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig
index baa4b8e..ba4519c 100644
--- a/configs/xilinx_versal_virt_defconfig
+++ b/configs/xilinx_versal_virt_defconfig
@@ -133,7 +133,6 @@
CONFIG_RESET_ZYNQMP=y
CONFIG_ARM_DCC=y
CONFIG_PL01X_SERIAL=y
-CONFIG_XILINX_UARTLITE=y
CONFIG_SOC_XILINX_VERSAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig
index 1f8e8c3..ae79f10 100644
--- a/configs/xilinx_zynqmp_kria_defconfig
+++ b/configs/xilinx_zynqmp_kria_defconfig
@@ -187,7 +187,6 @@
CONFIG_RTC_ZYNQMP=y
CONFIG_SCSI=y
CONFIG_ARM_DCC=y
-CONFIG_XILINX_UARTLITE=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_SOC_XILINX_ZYNQMP=y
CONFIG_SPI=y
@@ -228,3 +227,4 @@
CONFIG_MBEDTLS_LIB=y
CONFIG_TPM=y
CONFIG_SPL_GZIP=y
+CONFIG_TOOLS_MKFWUMDATA=y
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index abd1e1b..29aa589 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -199,7 +199,6 @@
CONFIG_RTC_ZYNQMP=y
CONFIG_SCSI=y
CONFIG_ARM_DCC=y
-CONFIG_XILINX_UARTLITE=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_SOC_XILINX_ZYNQMP=y
CONFIG_SPI=y
diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c
index 4b1b80d..2940181 100644
--- a/drivers/firmware/firmware-zynqmp.c
+++ b/drivers/firmware/firmware-zynqmp.c
@@ -5,6 +5,8 @@
* Copyright (C) 2018-2019 Xilinx, Inc.
*/
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
#include <cpu_func.h>
#include <dm.h>
#include <dm/device_compat.h>
@@ -169,6 +171,32 @@
return pm_api_version;
};
+#if defined(CONFIG_ARCH_VERSAL2)
+int zynqmp_pm_ufs_get_txrx_cfgrdy(u32 *value)
+{
+ *value = readl(PMXC_SLCR_BASE_ADDRESS + PMXC_TX_RX_CFG_RDY);
+ return 0;
+}
+
+int zynqmp_pm_ufs_sram_csr_read(u32 *value)
+{
+ *value = readl(PMXC_SLCR_BASE_ADDRESS + PMXC_SRAM_CSR);
+ return 0;
+}
+
+int zynqmp_pm_ufs_sram_csr_write(u32 *value)
+{
+ writel(*value, PMXC_SLCR_BASE_ADDRESS + PMXC_SRAM_CSR);
+ return 0;
+}
+
+int zynqmp_pm_ufs_cal_reg(u32 *value)
+{
+ *value = readl(PMXC_EFUSE_CACHE_BASE_ADDRESS + PMXC_UFS_CAL_1_OFFSET);
+ return 0;
+}
+#endif
+
int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config, u32 value)
{
int ret;
@@ -195,6 +223,52 @@
return ret;
}
+u32 zynqmp_pm_get_bootmode_reg(void)
+{
+ int ret;
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+
+ ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_READ_REG);
+ if (ret) {
+ printf("%s: IOCTL_READ_REG is not supported failed with error code: %d\n"
+ , __func__, ret);
+ return 0;
+ }
+
+ ret = xilinx_pm_request(PM_IOCTL, CRP_BOOT_MODE_REG_NODE, IOCTL_READ_REG,
+ CRP_BOOT_MODE_REG_OFFSET, 0, ret_payload);
+ if (ret) {
+ printf("%s: node 0x%x: get_bootmode 0x%x failed\n",
+ __func__, CRP_BOOT_MODE_REG_NODE, CRP_BOOT_MODE_REG_OFFSET);
+ return 0;
+ }
+
+ return ret_payload[1];
+}
+
+u32 zynqmp_pm_get_pmc_multi_boot_reg(void)
+{
+ int ret;
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+
+ ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_READ_REG);
+ if (ret) {
+ printf("%s: IOCTL_READ_REG is not supported failed with error code: %d\n"
+ , __func__, ret);
+ return 0;
+ }
+
+ ret = xilinx_pm_request(PM_IOCTL, PM_REG_PMC_GLOBAL_NODE, IOCTL_READ_REG,
+ PMC_MULTI_BOOT_MODE_REG_OFFSET, 0, ret_payload);
+ if (ret) {
+ printf("%s: node 0x%x: get_bootmode 0x%x failed\n",
+ __func__, PM_REG_PMC_GLOBAL_NODE, PMC_MULTI_BOOT_MODE_REG_OFFSET);
+ return 0;
+ }
+
+ return ret_payload[1];
+}
+
int zynqmp_pm_feature(const u32 api_id)
{
int ret;
diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c
index ae06f01..64fda3a 100644
--- a/drivers/fpga/altera.c
+++ b/drivers/fpga/altera.c
@@ -12,6 +12,10 @@
/*
* Altera FPGA support
*/
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \
+ IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include <asm/arch/misc.h>
+#endif
#include <errno.h>
#include <ACEX1K.h>
#include <log.h>
@@ -47,6 +51,43 @@
#endif
};
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \
+ IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)
+int fpga_is_partial_data(int devnum, size_t img_len)
+{
+ /*
+ * The FPGA data (full or partial) is checked by
+ * the SDM hardware, for Intel SDM Mailbox based
+ * devices. Hence always return full bitstream.
+ *
+ * For Cyclone V and Arria 10 family, the bitstream
+ * type parameter is not handled by the driver.
+ */
+ return 0;
+}
+
+int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
+ bitstream_type bstype)
+{
+ int ret_val;
+ int flags = 0;
+
+ ret_val = fpga_load(devnum, (void *)fpgadata, size, bstype, flags);
+
+ /*
+ * Enable the HPS to FPGA bridges when FPGA load is completed
+ * successfully. This is to ensure the FPGA is accessible
+ * by the HPS.
+ */
+ if (!ret_val) {
+ printf("Enable FPGA bridges\n");
+ do_bridge_reset(1, ~0);
+ }
+
+ return ret_val;
+}
+#endif
+
static int altera_validate(Altera_desc *desc, const char *fn)
{
if (!desc) {
diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c
index 1957e8d..d691f13 100644
--- a/drivers/fpga/versalpl.c
+++ b/drivers/fpga/versalpl.c
@@ -41,8 +41,15 @@
buf_lo = lower_32_bits(bin_buf);
buf_hi = upper_32_bits(bin_buf);
- ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
- buf_hi, 0, ret_payload);
+
+ if (desc->family == xilinx_versal2) {
+ ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_hi,
+ buf_lo, 0, ret_payload);
+ } else {
+ ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
+ buf_hi, 0, ret_payload);
+ }
+
if (ret)
printf("PL FPGA LOAD failed with err: 0x%08x\n", ret);
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 8413052..589b526 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -519,6 +519,8 @@
default 0x0 if DEBUG_UART_SANDBOX
default 0xff000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQMP
default 0xe0000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQ
+ default 0xff000000 if DEBUG_UART_PL011 && ARCH_VERSAL
+ default 0xf1920000 if DEBUG_UART_PL011 && (ARCH_VERSAL_NET || ARCH_VERSAL2)
help
This is the base address of your UART for memory-mapped UARTs.
@@ -554,6 +556,7 @@
default 0 if DEBUG_MVEBU_A3700_UART
default 100000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQMP
default 50000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQ
+ default 100000000 if DEBUG_UART_PL011 && (ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2)
help
The UART input clock determines the speed of the internal UART
circuitry. The baud rate is derived from this by dividing the input
diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c
index 816916d..fbeb0c6 100644
--- a/drivers/spi/cadence_ospi_versal.c
+++ b/drivers/spi/cadence_ospi_versal.c
@@ -204,3 +204,22 @@
~VERSAL_OSPI_LINEAR_MODE, VERSAL_AXI_MUX_SEL);
}
}
+
+int cadence_device_reset(struct udevice *bus)
+{
+ struct cadence_spi_priv *priv = dev_get_priv(bus);
+ u32 reg;
+
+ reg = readl(priv->regbase + CQSPI_REG_CONFIG);
+ reg |= CQSPI_REG_CONFIG_RESET_CFG_FLD_MASK;
+ writel(reg, priv->regbase + CQSPI_REG_CONFIG);
+
+ writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, priv->regbase + CQSPI_REG_CONFIG);
+ udelay(5);
+ writel(reg | CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, priv->regbase + CQSPI_REG_CONFIG);
+ udelay(150);
+ writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, priv->regbase + CQSPI_REG_CONFIG);
+ udelay(1200);
+
+ return 0;
+}
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 623904e..a78c00d 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -33,6 +33,11 @@
return 0;
}
+__weak int cadence_device_reset(struct udevice *dev)
+{
+ return 0;
+}
+
__weak int cadence_qspi_flash_reset(struct udevice *dev)
{
return 0;
@@ -251,6 +256,9 @@
priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz);
+ if (device_is_compatible(bus, "amd,versal2-ospi"))
+ return cadence_device_reset(bus);
+
/* Reset ospi flash device */
return cadence_qspi_flash_reset(bus);
@@ -452,6 +460,7 @@
static const struct udevice_id cadence_spi_ids[] = {
{ .compatible = "cdns,qspi-nor" },
{ .compatible = "ti,am654-ospi" },
+ { .compatible = "amd,versal2-ospi" },
{ }
};
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index 1f9125c..731b652 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -45,6 +45,8 @@
#define CQSPI_REG_CONFIG_CLK_POL BIT(1)
#define CQSPI_REG_CONFIG_CLK_PHA BIT(2)
#define CQSPI_REG_CONFIG_PHY_ENABLE_MASK BIT(3)
+#define CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK BIT(5)
+#define CQSPI_REG_CONFIG_RESET_CFG_FLD_MASK BIT(6)
#define CQSPI_REG_CONFIG_DIRECT BIT(7)
#define CQSPI_REG_CONFIG_DECODE BIT(9)
#define CQSPI_REG_CONFIG_ENBL_DMA BIT(15)
@@ -310,5 +312,6 @@
int cadence_qspi_flash_reset(struct udevice *dev);
ofnode cadence_qspi_get_subnode(struct udevice *dev);
void cadence_qspi_apb_enable_linear_mode(bool enable);
+int cadence_device_reset(struct udevice *dev);
#endif /* __CADENCE_QSPI_H__ */
diff --git a/drivers/ufs/ufs-amd-versal2.c b/drivers/ufs/ufs-amd-versal2.c
index bfd844e..1c5ed53 100644
--- a/drivers/ufs/ufs-amd-versal2.c
+++ b/drivers/ufs/ufs-amd-versal2.c
@@ -19,8 +19,6 @@
#include "ufshcd-dwc.h"
#include "ufshci-dwc.h"
-#define VERSAL2_UFS_DEVICE_ID 4
-
#define SRAM_CSR_INIT_DONE_MASK BIT(0)
#define SRAM_CSR_EXT_LD_DONE_MASK BIT(1)
#define SRAM_CSR_BYPASS_MASK BIT(2)
@@ -32,19 +30,12 @@
#define TIMEOUT_MICROSEC 1000000L
-#define IOCTL_UFS_TXRX_CFGRDY_GET 40
-#define IOCTL_UFS_SRAM_CSR_SEL 41
-
-#define PM_UFS_SRAM_CSR_WRITE 0
-#define PM_UFS_SRAM_CSR_READ 1
-
struct ufs_versal2_priv {
struct ufs_hba *hba;
struct reset_ctl *rstc;
struct reset_ctl *rstphy;
u32 phy_mode;
u32 host_clk;
- u32 pd_dev_id;
u8 attcompval0;
u8 attcompval1;
u8 ctlecompval0;
@@ -102,41 +93,6 @@
return 0;
}
-int versal2_pm_ufs_get_txrx_cfgrdy(u32 node_id, u32 *value)
-{
- u32 ret_payload[PAYLOAD_ARG_CNT];
- int ret;
-
- if (!value)
- return -EINVAL;
-
- ret = xilinx_pm_request(PM_IOCTL, node_id, IOCTL_UFS_TXRX_CFGRDY_GET,
- 0, 0, ret_payload);
- *value = ret_payload[1];
-
- return ret;
-}
-
-int versal2_pm_ufs_sram_csr_sel(u32 node_id, u32 type, u32 *value)
-{
- u32 ret_payload[PAYLOAD_ARG_CNT];
- int ret;
-
- if (!value)
- return -EINVAL;
-
- if (type == PM_UFS_SRAM_CSR_READ) {
- ret = xilinx_pm_request(PM_IOCTL, node_id, IOCTL_UFS_SRAM_CSR_SEL,
- type, 0, ret_payload);
- *value = ret_payload[1];
- } else {
- ret = xilinx_pm_request(PM_IOCTL, node_id, IOCTL_UFS_SRAM_CSR_SEL,
- type, *value, 0);
- }
-
- return ret;
-}
-
static int ufs_versal2_enable_phy(struct ufs_hba *hba)
{
u32 offset, reg;
@@ -281,7 +237,7 @@
time_left = TIMEOUT_MICROSEC;
do {
time_left--;
- ret = versal2_pm_ufs_get_txrx_cfgrdy(priv->pd_dev_id, ®);
+ ret = zynqmp_pm_ufs_get_txrx_cfgrdy(®);
if (ret)
return ret;
@@ -312,8 +268,7 @@
time_left = TIMEOUT_MICROSEC;
do {
time_left--;
- ret = versal2_pm_ufs_sram_csr_sel(priv->pd_dev_id,
- PM_UFS_SRAM_CSR_READ, ®);
+ ret = zynqmp_pm_ufs_sram_csr_read(®);
if (ret)
return ret;
@@ -341,10 +296,10 @@
struct ufs_versal2_priv *priv = dev_get_priv(hba->dev);
struct clk clk;
unsigned long core_clk_rate = 0;
+ u32 cal;
int ret = 0;
priv->phy_mode = UFSHCD_DWC_PHY_MODE_ROM;
- priv->pd_dev_id = VERSAL2_UFS_DEVICE_ID;
ret = clk_get_by_name(hba->dev, "core_clk", &clk);
if (ret) {
@@ -371,6 +326,15 @@
return PTR_ERR(priv->rstphy);
}
+ ret = zynqmp_pm_ufs_cal_reg(&cal);
+ if (ret)
+ return ret;
+
+ priv->attcompval0 = (u8)cal;
+ priv->attcompval1 = (u8)(cal >> 8);
+ priv->ctlecompval0 = (u8)(cal >> 16);
+ priv->ctlecompval1 = (u8)(cal >> 24);
+
return ret;
}
@@ -397,8 +361,7 @@
return ret;
}
- ret = versal2_pm_ufs_sram_csr_sel(priv->pd_dev_id,
- PM_UFS_SRAM_CSR_READ, &sram_csr);
+ ret = zynqmp_pm_ufs_sram_csr_read(&sram_csr);
if (ret)
return ret;
@@ -410,8 +373,7 @@
return -EINVAL;
}
- ret = versal2_pm_ufs_sram_csr_sel(priv->pd_dev_id,
- PM_UFS_SRAM_CSR_WRITE, &sram_csr);
+ ret = zynqmp_pm_ufs_sram_csr_write(&sram_csr);
if (ret)
return ret;
diff --git a/env/Kconfig b/env/Kconfig
index 4438f0b..9507aee 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -485,7 +485,7 @@
string "Device and partition for where to store the environemt in FAT"
depends on ENV_IS_IN_FAT
default "0:1" if TI_COMMON_CMD_OPTIONS
- default "0:auto" if ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET
+ default "0:auto" if ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2
default ":auto" if ARCH_SUNXI
default "0" if ARCH_AT91
help
diff --git a/include/configs/amd_versal2.h b/include/configs/amd_versal2.h
index 6a40bbd..1ade6ad 100644
--- a/include/configs/amd_versal2.h
+++ b/include/configs/amd_versal2.h
@@ -105,6 +105,14 @@
#define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \
"jtag "
+#define BOOT_TARGET_DEVICES_UFS(func) func(UFS, ufs, 0)
+
+#define BOOTENV_DEV_UFS(devtypeu, devtypel, instance) \
+ "bootcmd_" #devtypel "=" #devtypel " init " #instance "; scsi scan;\0"
+
+#define BOOTENV_DEV_NAME_UFS(devtypeu, devtypel, instance) \
+ "ufs "
+
#define BOOT_TARGET_DEVICES_DFU_USB(func) func(DFU_USB, dfu_usb, 0)
#define BOOTENV_DEV_DFU_USB(devtypeu, devtypel, instance) \
@@ -117,11 +125,19 @@
#define BOOTENV_DEV_NAME_DFU_USB(devtypeu, devtypel, instance) \
""
+#if defined(CONFIG_USB_STORAGE)
+#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) func(USB, usb, 1)
+#else
+#define BOOT_TARGET_DEVICES_USB(func)
+#endif
+
#define BOOT_TARGET_DEVICES(func) \
BOOT_TARGET_DEVICES_JTAG(func) \
BOOT_TARGET_DEVICES_MMC(func) \
+ BOOT_TARGET_DEVICES_UFS(func) \
BOOT_TARGET_DEVICES_XSPI(func) \
BOOT_TARGET_DEVICES_DFU_USB(func) \
+ BOOT_TARGET_DEVICES_USB(func) \
BOOT_TARGET_DEVICES_PXE(func) \
BOOT_TARGET_DEVICES_DHCP(func)
diff --git a/include/configs/brzynq.h b/include/configs/brzynq.h
new file mode 100644
index 0000000..e2ebb2f
--- /dev/null
+++ b/include/configs/brzynq.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Config file for BR Zynq board
+ *
+ * Copyright (C) 2024
+ * B&R Industrial Automation GmbH - http://www.br-automation.com/
+ */
+
+#ifndef __CONFIG_BRZYNQ_H__
+#define __CONFIG_BRZYNQ_H__
+
+/* Increase PHY_ANEG_TIMEOUT since the FPGA needs some setup time */
+#if IS_ENABLED(CONFIG_SPL_FPGA)
+#define PHY_ANEG_TIMEOUT 8000
+#endif
+
+/* Use top mapped SRAM */
+#define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000
+#define CFG_SYS_INIT_RAM_SIZE 0x2000
+
+#endif /* __CONFIG_BRZYNQ_H__ */
diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h
index 0627617..5530d36 100644
--- a/include/configs/topic_miami.h
+++ b/include/configs/topic_miami.h
@@ -9,75 +9,67 @@
#ifndef __CONFIG_TOPIC_MIAMI_H
#define __CONFIG_TOPIC_MIAMI_H
-/* Speed up boot time by ignoring the environment which we never used */
+#ifndef CONFIG_XPL_BUILD
-#include "zynq-common.h"
+#ifdef CONFIG_CMD_MMC
+#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
+#else
+#define BOOT_TARGET_DEVICES_MMC(func)
+#endif
-/* Fixup settings */
+#ifdef CONFIG_CMD_USB
+#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
+#else
+#define BOOT_TARGET_DEVICES_USB(func)
+#endif
-/* Setup proper boot sequences for Miami boards */
+#if defined(CONFIG_ZYNQ_QSPI)
+# define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na)
+#else
+# define BOOT_TARGET_DEVICES_QSPI(func)
+#endif
-#if defined(CONFIG_USB_HOST)
-# define EXTRA_ENV_USB \
- "usbreset=i2c dev 1 && i2c mw 41 1 ff && i2c mw 41 3 fe && "\
- "i2c mw 41 1 fe && i2c mw 41 1 ff\0" \
- "usbboot=run usbreset && if usb start; then " \
- "echo Booting from USB... && " \
- "if load usb 0 0x1900000 ${bootscript}; then "\
- "source 0x1900000; fi; " \
- "load usb 0 ${kernel_addr} ${kernel_image} && " \
- "load usb 0 ${devicetree_addr} ${devicetree_image} && " \
- "load usb 0 ${ramdisk_load_address} ${ramdisk_image} && " \
- "bootm ${kernel_addr} ${ramdisk_load_address} "\
- "${devicetree_addr}; " \
- "fi\0"
- /* Note that addresses here should match the addresses in the env */
-# define DFU_ALT_INFO \
- "dfu_alt_info=" \
- "uImage ram 0x2080000 0x500000;" \
- "devicetree.dtb ram 0x2000000 0x20000;" \
- "uramdisk.image.gz ram 0x4000000 0x10000000\0" \
- "dfu_ram=run usbreset && dfu 0 ram 0\0" \
- "thor_ram=run usbreset && thordown 0 ram 0\0"
+#ifdef CONFIG_CMD_UBIFS
+# define BOOT_TARGET_DEVICES_UBIFS(func) func(UBIFS, ubifs, 0, qspi-rootfs, qspi-rootfs)
#else
-# define EXTRA_ENV_USB
+# define BOOT_TARGET_DEVICES_UBIFS(func)
#endif
+#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \
+ "bootcmd_qspi=sf probe && " \
+ "sf read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \
+ "echo QSPI: Trying to boot script at ${scriptaddr} && " \
+ "source ${scriptaddr}; echo QSPI: SCRIPT FAILED: continuing...;\0"
+
-#undef CFG_EXTRA_ENV_SETTINGS
+#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \
+ "qspi "
+
+#define BOOT_TARGET_DEVICES(func) \
+ BOOT_TARGET_DEVICES_MMC(func) \
+ BOOT_TARGET_DEVICES_UBIFS(func) \
+ BOOT_TARGET_DEVICES_QSPI(func)
+
+#include <config_distro_bootcmd.h>
+
+#endif /* CONFIG_XPL_BUILD */
+
+/* Default environment */
+#ifndef CFG_EXTRA_ENV_SETTINGS
#define CFG_EXTRA_ENV_SETTINGS \
- "kernel_image=uImage\0" \
- "kernel_addr=0x2080000\0" \
- "ramdisk_image=uramdisk.image.gz\0" \
- "ramdisk_load_address=0x4000000\0" \
- "devicetree_image=devicetree.dtb\0" \
- "devicetree_addr=0x2000000\0" \
- "bitstream_image=fpga.bin\0" \
- "bootscript=autorun.scr\0" \
- "loadbit_addr=0x100000\0" \
- "loadbootenv_addr=0x2000000\0" \
- "kernel_size=0x440000\0" \
- "devicetree_size=0x10000\0" \
- "boot_size=0xF00000\0" \
- "fdt_high=0x20000000\0" \
- "initrd_high=0x20000000\0" \
- "mmc_loadbit=echo Loading bitstream from SD/MMC/eMMC to RAM.. && " \
- "mmcinfo && " \
- "load mmc 0 ${loadbit_addr} ${bitstream_image} && " \
- "fpga load 0 ${loadbit_addr} ${filesize}\0" \
- "qspiboot=echo Booting from QSPI flash... && " \
- "sf probe && " \
- "sf read ${devicetree_addr} 0xA0000 ${devicetree_size} && " \
- "sf read ${kernel_addr} 0xC0000 ${kernel_size} && " \
- "bootm ${kernel_addr} - ${devicetree_addr}\0" \
- "sdboot=if mmcinfo; then " \
- "setenv bootargs console=ttyPS0,115200 " \
- "root=/dev/mmcblk0p2 rw rootfstype=ext4 " \
- "rootwait quiet ; " \
- "load mmc 0 ${kernel_addr} ${kernel_image}&& " \
- "load mmc 0 ${devicetree_addr} ${devicetree_image}&& " \
- "bootm ${kernel_addr} - ${devicetree_addr}; " \
- "fi\0" \
- EXTRA_ENV_USB \
- DFU_ALT_INFO
+ "scriptaddr=0x3000000\0" \
+ "script_offset_f=0xf0000\0" \
+ "script_size_f=0x10000\0" \
+ "fdt_addr_r=0x1f00000\0" \
+ "pxefile_addr_r=0x2000000\0" \
+ "kernel_addr_r=0x2000000\0" \
+ "ramdisk_addr_r=0x3100000\0" \
+ BOOTENV
+#endif
+
+#include "zynq-common.h"
+
+/* Detect RAM size */
+#define CFG_SYS_SDRAM_BASE 0
+#define CFG_SYS_SDRAM_SIZE 0x40000000
#endif /* __CONFIG_TOPIC_MIAMI_H */
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 93ae589..94273d0 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -46,7 +46,10 @@
#ifdef CONFIG_XPL_BUILD
#define BOOTENV
-#else
+#endif
+
+/* Only use this section if no BOOTENV has been configured yet */
+#ifndef BOOTENV
#ifdef CONFIG_CMD_MMC
#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
@@ -167,7 +170,8 @@
BOOT_TARGET_DEVICES_DHCP(func)
#include <config_distro_bootcmd.h>
-#endif /* CONFIG_XPL_BUILD */
+
+#endif /* BOOTENV */
/* Default environment */
#ifndef CFG_EXTRA_ENV_SETTINGS
diff --git a/include/xilinx.h b/include/xilinx.h
index e4e2979..c54d6dc 100644
--- a/include/xilinx.h
+++ b/include/xilinx.h
@@ -34,6 +34,8 @@
xilinx_zynq, /* Zynq Family */
xilinx_zynqmp, /* ZynqMP Family */
xilinx_versal, /* Versal Family */
+ xilinx_versal_net, /* Versal NET Family */
+ xilinx_versal2, /* Versal Gen 2 Family */
max_xilinx_type /* insert all new types before this */
} xilinx_family; /* end, typedef xilinx_family */
diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h
index 73198a6..dc06abc 100644
--- a/include/zynqmp_firmware.h
+++ b/include/zynqmp_firmware.h
@@ -457,6 +457,12 @@
int zynqmp_mmio_read(const u32 address, u32 *value);
int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
int zynqmp_pm_feature(const u32 api_id);
+u32 zynqmp_pm_get_bootmode_reg(void);
+int zynqmp_pm_ufs_get_txrx_cfgrdy(u32 *value);
+int zynqmp_pm_ufs_sram_csr_read(u32 *value);
+int zynqmp_pm_ufs_sram_csr_write(u32 *value);
+int zynqmp_pm_ufs_cal_reg(u32 *value);
+u32 zynqmp_pm_get_pmc_multi_boot_reg(void);
/* Type of Config Object */
#define PM_CONFIG_OBJECT_TYPE_BASE 0x1U
@@ -500,4 +506,10 @@
u32 *buf;
};
+#define CRP_BOOT_MODE_REG_NODE 0x30000001
+#define CRP_BOOT_MODE_REG_OFFSET 0x200
+
+#define PM_REG_PMC_GLOBAL_NODE 0x30000004
+#define PMC_MULTI_BOOT_MODE_REG_OFFSET 0x4
+
#endif /* _ZYNQMP_FIRMWARE_H_ */