diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index f6554d5..f7fbb28 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -187,10 +187,26 @@
 config WDT_MPC8xxx
 	bool "MPC8xxx watchdog timer support"
 	depends on WDT && MPC8xx
-	select HW_WATCHDOG
 	help
 	  Select this to enable mpc8xxx watchdog timer
 
+config WDT_MPC8xxx_BME
+	bool "Enable MPC8xx Bus Monitoring"
+	depends on WDT_MPC8xxx && MPC8xx
+	help
+	  Select this to enable mpc8xx Bus Monitor.
+
+config WDT_MPC8xxx_BMT
+	int "MPC8xx Bus Monitor Timing" if WDT_MPC8xxx_BME
+	range 0 255
+	default 255
+	depends on WDT_MPC8xxx
+	help
+	  Bus monitor timing. Defines the timeout period, in 8 system clock
+	  resolution, for the bus monitor.
+
+	  Maximum timeout is 2,040 clocks (255 x 8).
+
 config WDT_MT7620
 	bool "MediaTek MT7620 watchdog timer support"
 	depends on WDT && SOC_MT7620
diff --git a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c
index ffca3ec..9a29938 100644
--- a/drivers/watchdog/mpc8xxx_wdt.c
+++ b/drivers/watchdog/mpc8xxx_wdt.c
@@ -7,32 +7,61 @@
 #include <env.h>
 #include <dm.h>
 #include <wdt.h>
-#include <mpc8xx.h>
-#include <asm/cpm_8xx.h>
+#include <clock_legacy.h>
 #include <asm/io.h>
 
-void hw_watchdog_reset(void)
+struct mpc8xxx_wdt {
+	__be32 res0;
+	__be32 swcrr;	/* System watchdog control register */
+#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */
+#define SWCRR_BME  0x00000080 /* Bus monitor enable (mpc8xx) */
+#define SWCRR_SWF  0x00000008 /* Software Watchdog Freeze (mpc8xx). */
+#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */
+#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit.*/
+#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */
+	__be32 swcnr;	/* System watchdog count register */
+	u8 res1[2];
+	__be16 swsrr;	/* System watchdog service register */
+	u8 res2[0xf0];
+};
+
+struct mpc8xxx_wdt_priv {
+	struct mpc8xxx_wdt __iomem *base;
+};
+
+static int mpc8xxx_wdt_reset(struct udevice *dev)
 {
-	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+	struct mpc8xxx_wdt_priv *priv = dev_get_priv(dev);
+
+	out_be16(&priv->base->swsrr, 0x556c);	/* write magic1 */
+	out_be16(&priv->base->swsrr, 0xaa39);	/* write magic2 */
 
-	out_be16(&immap->im_siu_conf.sc_swsr, 0x556c);	/* write magic1 */
-	out_be16(&immap->im_siu_conf.sc_swsr, 0xaa39);	/* write magic2 */
+	return 0;
 }
 
 static int mpc8xxx_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
 {
-	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
-	u32 val = CONFIG_SYS_SYPCR;
+	struct mpc8xxx_wdt_priv *priv = dev_get_priv(dev);
 	const char *mode = env_get("watchdog_mode");
+	ulong prescaler = dev_get_driver_data(dev);
+	u16 swtc = min_t(u16, timeout * get_board_sys_clk() / 1000 / prescaler, U16_MAX);
+	u32 val;
+
+	mpc8xxx_wdt_reset(dev);
 
 	if (strcmp(mode, "off") == 0)
-		val = val & ~(SYPCR_SWE | SYPCR_SWRI);
+		val = (swtc << 16) | SWCRR_SWPR;
 	else if (strcmp(mode, "nmi") == 0)
-		val = (val & ~SYPCR_SWRI) | SYPCR_SWE;
+		val = (swtc << 16) | SWCRR_SWPR | SWCRR_SWEN;
+	else
+		val = (swtc << 16) | SWCRR_SWPR | SWCRR_SWEN | SWCRR_SWRI;
+
+	if (IS_ENABLED(CONFIG_WDT_MPC8xxx_BME))
+		val |= (CONFIG_WDT_MPC8xxx_BMT << 8) | SWCRR_BME;
 
-	out_be32(&immap->im_siu_conf.sc_sypcr, val);
+	out_be32(&priv->base->swcrr, val);
 
-	if (!(in_be32(&immap->im_siu_conf.sc_sypcr) & SYPCR_SWE))
+	if (!(in_be32(&priv->base->swcrr) & SWCRR_SWEN))
 		return -EBUSY;
 	return 0;
 
@@ -40,18 +69,23 @@
 
 static int mpc8xxx_wdt_stop(struct udevice *dev)
 {
-	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+	struct mpc8xxx_wdt_priv *priv = dev_get_priv(dev);
 
-	out_be32(&immap->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR & ~SYPCR_SWE);
+	clrbits_be32(&priv->base->swcrr, SWCRR_SWEN);
 
-	if (in_be32(&immap->im_siu_conf.sc_sypcr) & SYPCR_SWE)
+	if (in_be32(&priv->base->swcrr) & SWCRR_SWEN)
 		return -EBUSY;
 	return 0;
 }
 
-static int mpc8xxx_wdt_reset(struct udevice *dev)
+static int mpc8xxx_wdt_of_to_plat(struct udevice *dev)
 {
-	hw_watchdog_reset();
+	struct mpc8xxx_wdt_priv *priv = dev_get_priv(dev);
+
+	priv->base = (void __iomem *)devfdt_remap_addr(dev);
+
+	if (!priv->base)
+		return -EINVAL;
 
 	return 0;
 }
@@ -63,7 +97,7 @@
 };
 
 static const struct udevice_id mpc8xxx_wdt_ids[] = {
-	{ .compatible = "fsl,pq1-wdt" },
+	{ .compatible = "fsl,pq1-wdt", .data = 0x800 },
 	{}
 };
 
@@ -72,4 +106,6 @@
 	.id = UCLASS_WDT,
 	.of_match = mpc8xxx_wdt_ids,
 	.ops = &mpc8xxx_wdt_ops,
+	.of_to_plat = mpc8xxx_wdt_of_to_plat,
+	.priv_auto	= sizeof(struct mpc8xxx_wdt_priv),
 };