commit 0fdd27e90c2b679079c7f186d16ca1f3a88772fc
author Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> Fri May 30 00:53:38 2008 +0900
committer Shinya Kuribayashi <shinya.kuribayashi@necel.com> Fri May 30 00:53:38 2008 +0900
tree c8659df110945904985611ce85a326ca1e2364cf
parent 179f9748dd5ed2078c8b2d3879b0ca0e3ad5f472

[MIPS] <asm/mipsregs.h>: Update coprocessor register access macros

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>

board/qemu-mips/qemu-mips.c

diff --git a/board/qemu-mips/qemu-mips.c b/board/qemu-mips/qemu-mips.c
index 6869074..6e6eab2 100644
--- a/board/qemu-mips/qemu-mips.c
+++ b/board/qemu-mips/qemu-mips.c
@@ -38,7 +38,7 @@
 	u32 proc_id;
 	u32 config1;
 
-	proc_id = read_32bit_cp0_register(CP0_PRID);
+	proc_id = read_c0_prid();
 	printf("Board: Qemu -M mips CPU: ");
 	switch (proc_id) {
 	case 0x00018000:
@@ -51,7 +51,7 @@
 		printf("4KEc");
 		break;
 	case 0x00019300:
-		config1 = read_mips32_cp0_config1();
+		config1 = read_c0_config1();
 		if (config1 & 1)
 			printf("24Kf");
 		else
@@ -64,7 +64,7 @@
 		printf("R4000");
 		break;
 	case 0x00018100:
-		config1 = read_mips32_cp0_config1();
+		config1 = read_c0_config1();
 		if (config1 & 1)
 			printf("5Kf");
 		else