tree ad81fad00ca9ee6e4a872f8dc20873402aabbca3
parent 870d0719b5355eefd8637d437a45431a27a27827
author Marek Vasut <marek.vasut+renesas@gmail.com> 1619545973 +0200
committer Marek Vasut <marek.vasut+renesas@gmail.com> 1624558937 +0200

clk: renesas: Handle R8A779A0 V3U clock types in Gen3 clock code

On R8A779A0 V3U SoC, PLL1 and PLL5 use a divider value
from cpg_pll_configs table while PLL{20,21,30,31,4} use
different control offset. Introduce new types to handle
this and handle those types in the Gen3 clock code.

Based on "clk: renesas: Add support for R8A779A0 V3U PLLn"
by Hai Pham <hai.pham.ud@renesas.com>

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>