Merge tag 'efi-2020-01-rc5' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-01-rc5
A type error in the implementation of the efidebug command is fixed.
diff --git a/MAINTAINERS b/MAINTAINERS
index 332fd9d..8d588b7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -150,7 +150,9 @@
ARM BROADCOM BCM283X
M: Matthias Brugger <mbrugger@suse.com>
S: Maintained
+F: arch/arm/dts/bcm283*
F: arch/arm/mach-bcm283x/
+F: board/raspberrypi/
F: drivers/gpio/bcm2835_gpio.c
F: drivers/mmc/bcm2835_sdhci.c
F: drivers/mmc/bcm2835_sdhost.c
@@ -158,6 +160,7 @@
F: drivers/serial/serial_bcm283x_pl011.c
F: drivers/video/bcm2835.c
F: include/dm/platform_data/serial_bcm283x_mu.h
+F: include/dt-bindings/pinctrl/bcm2835.h
F: drivers/pinctrl/broadcom/
ARM BROADCOM BCMSTB
diff --git a/Makefile b/Makefile
index 8024baa..556cebd 100644
--- a/Makefile
+++ b/Makefile
@@ -1306,7 +1306,6 @@
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
u-boot-ivt.img: MKIMAGEOUTPUT = u-boot-ivt.img.log
-CLEAN_FILES += u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log
endif
MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img)
@@ -1406,7 +1405,6 @@
lpc32xx-full.bin: lpc32xx-boot-0.bin lpc32xx-boot-1.bin u-boot.img FORCE
$(call if_changed,cat)
-CLEAN_FILES += lpc32xx-*
endif
OBJCOPYFLAGS_u-boot-with-tpl.bin = -I binary -O binary \
@@ -1694,7 +1692,7 @@
# make sure no implicit rule kicks in
$(sort $(u-boot-init) $(u-boot-main)): $(u-boot-dirs) ;
-# Handle descending into subdirectories listed in $(vmlinux-dirs)
+# Handle descending into subdirectories listed in $(u-boot-dirs)
# Preset locale variables to speed up the build process. Limit locale
# tweaks to this spot to avoid wrong language settings when running
# make menuconfig etc.
@@ -1931,7 +1929,10 @@
$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h tools/version.h \
- boot* u-boot* MLO* SPL System.map fit-dtb.blob*
+ boot* u-boot* MLO* SPL System.map fit-dtb.blob* \
+ u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log \
+ lpc32xx-* bl31.c bl31.elf bl31_*.bin image.map tispl.bin* \
+ idbloader.img
# Directories & files removed with 'make mrproper'
MRPROPER_DIRS += include/config include/generated spl tpl \
@@ -1965,8 +1966,7 @@
-o -name modules.builtin -o -name '.tmp_*.o.*' \
-o -name 'dsdt.aml' -o -name 'dsdt.asl.tmp' -o -name 'dsdt.c' \
-o -name '*.efi' -o -name '*.gcno' -o -name '*.so' \) \
- -type f -print | xargs rm -f \
- bl31.c bl31.elf bl31_*.bin image.map tispl.bin*
+ -type f -print | xargs rm -f
# mrproper - Delete all generated files, including .config
#
diff --git a/README b/README
index 107e67f..91dfb24 100644
--- a/README
+++ b/README
@@ -3082,14 +3082,16 @@
instruction cache) is still performed.
- CONFIG_SPL_BUILD
- Modifies the behaviour of start.S when compiling a loader
- that is executed before the actual U-Boot. E.g. when
- compiling a NAND SPL.
+ Set when the currently-running compilation is for an artifact
+ that will end up in the SPL (as opposed to the TPL or U-Boot
+ proper). Code that needs stage-specific behavior should check
+ this.
- CONFIG_TPL_BUILD
- Modifies the behaviour of start.S when compiling a loader
- that is executed after the SPL and before the actual U-Boot.
- It is loaded by the SPL.
+ Set when the currently-running compilation is for an artifact
+ that will end up in the TPL (as opposed to the SPL or U-Boot
+ proper). Code that needs stage-specific behavior should check
+ this.
- CONFIG_SYS_MPC85XX_NO_RESETVEC
Only for 85xx systems. If this variable is specified, the section
@@ -3306,7 +3308,7 @@
If you have modified U-Boot sources (for instance added a new board
or support for new devices, a new CPU, etc.) you are expected to
provide feedback to the other developers. The feedback normally takes
-the form of a "patch", i. e. a context diff against a certain (latest
+the form of a "patch", i.e. a context diff against a certain (latest
official or latest in the git repository) version of U-Boot sources.
But before you submit such a patch, please verify that your modifi-
diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c
index 6dc2ca8..f4ba3ad 100644
--- a/arch/arm/cpu/armv7m/cache.c
+++ b/arch/arm/cpu/armv7m/cache.c
@@ -332,6 +332,11 @@
isb(); /* subsequent instructions fetch see cache disable effect */
}
#else
+void invalidate_icache_all(void)
+{
+ return;
+}
+
void icache_enable(void)
{
return;
diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c
index 11f9b4d..4dcda70 100644
--- a/arch/arm/cpu/armv8/sec_firmware.c
+++ b/arch/arm/cpu/armv8/sec_firmware.c
@@ -354,7 +354,7 @@
return true;
#endif
if (sec_firmware_addr & SEC_FIRMWARE_RUNNING) {
- return true;
+ return true;
}
return false;
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d8846df..3dc9c4d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -835,7 +835,8 @@
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb \
- mt8516-pumpkin.dtb
+ mt8516-pumpkin.dtb \
+ mt8518-ap1-emmc.dtb
dtb-$(CONFIG_TARGET_GE_BX50V3) += imx6q-bx50v3.dtb
dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb
diff --git a/arch/arm/dts/mt8518-ap1-emmc.dts b/arch/arm/dts/mt8518-ap1-emmc.dts
new file mode 100644
index 0000000..f017ee4
--- /dev/null
+++ b/arch/arm/dts/mt8518-ap1-emmc.dts
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ *
+ */
+
+/dts-v1/;
+
+#include <config.h>
+#include "mt8518.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ model = "MT8518 AP1 EMMC";
+
+ chosen {
+ stdout-path = &uart0;
+ tick-timer = &timer0;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x10000000>;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_default>;
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ cap-mmc-hw-reset;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ non-removable;
+ status = "okay";
+};
+
+&pinctrl {
+ mmc0_pins_default: mmc0default {
+ mux {
+ function = "msdc";
+ groups = "msdc0";
+ };
+
+ conf-cmd-data {
+ pins = "MSDC0_CMD", "MSDC0_DAT0", "MSDC0_DAT1",
+ "MSDC0_DAT2", "MSDC0_DAT3", "MSDC0_DAT4",
+ "MSDC0_DAT5", "MSDC0_DAT6", "MSDC0_DAT7";
+ input-enable;
+ bias-pull-up;
+ };
+
+ conf-clk {
+ pins = "MSDC0_CLK";
+ bias-pull-down;
+ };
+
+ conf-rst {
+ pins = "MSDC0_RSTB";
+ bias-pull-up;
+ };
+ };
+
+ uart0_pins: uart0 {
+ mux {
+ function = "uart";
+ groups = "uart0_0_rxd_txd";
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/mt8518.dtsi b/arch/arm/dts/mt8518.dtsi
new file mode 100644
index 0000000..c2d17fd
--- /dev/null
+++ b/arch/arm/dts/mt8518.dtsi
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ *
+ */
+
+#include <dt-bindings/clock/mt8518-clk.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "mediatek,mt8518";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+
+
+ topckgen: clock-controller@10000000 {
+ compatible = "mediatek,mt8518-topckgen";
+ reg = <0x10000000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ gic: interrupt-controller@0c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0xc000000 0x40000>, /* GICD */
+ <0xc100000 0x200000>; /* GICR */
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ sysirq: interrupt-controller@10200a80 {
+ compatible = "mediatek,sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0x10200a80 0x50>;
+ };
+
+ timer0: apxgpt@10008000 {
+ compatible = "mediatek,timer";
+ reg = <0x10008000 0x1000>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_CLK26M_D2>,
+ <&topckgen CLK_TOP_CLK32K>,
+ <&topckgen CLK_TOP_APXGPT>;
+ clock-names = "clk13m",
+ "clk32k",
+ "bus";
+ };
+
+ watchdog0: watchdog@10007000 {
+ compatible = "mediatek,wdt";
+ reg = <0x10007000 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_FALLING>;
+ #reset-cells = <1>;
+ status = "disabled";
+ timeout-sec = <60>;
+ reset-on-timeout;
+ };
+
+ pinctrl: pinctrl@10005000 {
+ compatible = "mediatek,mt8518-pinctrl";
+ reg = <0x10005000 0x1000>;
+ gpio: gpio-controller {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ mmc0: mmc@11120000 {
+ compatible = "mediatek,mt8516-mmc";
+ reg = <0x11120000 0x1000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MSDC0>,
+ <&topckgen CLK_TOP_MSDC0>,
+ <&topckgen CLK_TOP_MSDC0_B>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ uart0: serial@11005000 {
+ compatible = "mediatek,hsuart";
+ reg = <0x11005000 0x1000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_UART0_SEL>,
+ <&topckgen CLK_TOP_UART0>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+};
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index adc5092..8a81c07 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -14,6 +14,7 @@
bool "OMAPL138 LCDK"
select SOC_DA8XX
select SUPPORT_SPL
+ select SPL_BOARD_INIT
config TARGET_LEGOEV3
bool "LEGO MINDSTORMS EV3"
diff --git a/arch/arm/mach-davinci/include/mach/sdmmc_defs.h b/arch/arm/mach-davinci/include/mach/sdmmc_defs.h
index 5755c45..46f6391 100644
--- a/arch/arm/mach-davinci/include/mach/sdmmc_defs.h
+++ b/arch/arm/mach-davinci/include/mach/sdmmc_defs.h
@@ -149,15 +149,9 @@
uint input_clk; /* Input clock to MMC controller */
uint host_caps; /* Host capabilities */
uint voltages; /* Host supported voltages */
- uint version; /* MMC Controller version */
struct mmc_config cfg;
};
-enum {
- MMC_CTLR_VERSION_1 = 0, /* DM644x and DM355 */
- MMC_CTLR_VERSION_2, /* DA830 */
-};
-
int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host);
#endif /* _SDMMC_DEFS_H */
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index 25ef765..ad453a6 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -38,10 +38,20 @@
Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth combo
chip and several DDR3 and DDR4 options.
+config TARGET_MT8518
+ bool "MediaTek MT8518 SoC"
+ select ARM64
+ help
+ The MediaTek MT8518 is a ARM64-based SoC with a quad-core Cortex-A53.
+ including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM,
+ Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth combo
+ chip and several DDR3 and DDR4 options.
+
endchoice
source "board/mediatek/mt7623/Kconfig"
source "board/mediatek/mt7629/Kconfig"
+source "board/mediatek/mt8518/Kconfig"
source "board/mediatek/pumpkin/Kconfig"
endif
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index ea414dc..b9b2355 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -6,3 +6,4 @@
obj-$(CONFIG_TARGET_MT7623) += mt7623/
obj-$(CONFIG_TARGET_MT7629) += mt7629/
obj-$(CONFIG_TARGET_MT8516) += mt8516/
+obj-$(CONFIG_TARGET_MT8518) += mt8518/
diff --git a/arch/arm/mach-mediatek/mt8518/Makefile b/arch/arm/mach-mediatek/mt8518/Makefile
new file mode 100644
index 0000000..007eb4a
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8518/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += init.o
+obj-y += lowlevel_init.o
diff --git a/arch/arm/mach-mediatek/mt8518/init.c b/arch/arm/mach-mediatek/mt8518/init.c
new file mode 100644
index 0000000..5a97c8c
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8518/init.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Configuration for MediaTek MT8518 SoC
+ *
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <ram.h>
+#include <asm/arch/misc.h>
+#include <asm/armv8/mmu.h>
+#include <asm/sections.h>
+#include <dm/uclass.h>
+#include <dt-bindings/clock/mt8518-clk.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ int ret;
+
+ ret = fdtdec_setup_memory_banksize();
+ if (ret)
+ return ret;
+
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = gd->ram_base;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ psci_system_reset();
+}
+
+int print_cpuinfo(void)
+{
+ printf("CPU: MediaTek MT8518\n");
+ return 0;
+}
+
+static struct mm_region mt8518_mem_map[] = {
+ {
+ /* DDR */
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x20000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
+ }, {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x20000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ 0,
+ }
+};
+
+struct mm_region *mem_map = mt8518_mem_map;
diff --git a/arch/arm/mach-mediatek/mt8518/lowlevel_init.S b/arch/arm/mach-mediatek/mt8518/lowlevel_init.S
new file mode 100644
index 0000000..ad39212
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8518/lowlevel_init.S
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ */
+
+/*
+ * Switch from AArch64 EL2 to AArch32 EL2
+ * @param inputs:
+ * x0: argument, zero
+ * x1: machine nr
+ * x2: fdt address
+ * x3: input argument
+ * x4: kernel entry point
+ * @param outputs for secure firmware:
+ * x0: function id
+ * x1: kernel entry point
+ * x2: machine nr
+ * x3: fdt address
+*/
+.global armv8_el2_to_aarch32
+armv8_el2_to_aarch32:
+ mov x3, x2
+ mov x2, x1
+ mov x1, x4
+ mov x4, #0
+ /* Define in src\bsp\trustzone\atf\v1.2\ */
+ /* mt8xxx\plat\mediatek\common\sip_svc.h */
+ /* MTK_SIP_KERNEL_BOOT_AARCH64 for U-BOOT-64 to KERNEL*/
+ ldr x0, =0xC2000200
+ SMC #0
+ ret
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 4936994..d8d68ba 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -312,7 +312,7 @@
Rockchip SoCs have similar boot process, prefer to use TPL for DRAM
init and back to bootrom, and SPL as Trust ATF/U-Boot loader. TPL
common board is a basic TPL board init which can be shared for most
- of SoCs to avoid copy-pase for different SoCs.
+ of SoCs to avoid copy-paste for different SoCs.
config ROCKCHIP_BOOT_MODE_REG
hex "Rockchip boot mode flag register address"
diff --git a/arch/arm/mach-rockchip/bootrom.c b/arch/arm/mach-rockchip/bootrom.c
index 9ccb45e..10614c9 100644
--- a/arch/arm/mach-rockchip/bootrom.c
+++ b/arch/arm/mach-rockchip/bootrom.c
@@ -39,8 +39,8 @@
* to check it and back to bootrom at very early bootstage(before
* some basic configurations(such as interrupts) been
* changed by TPL/SPL, as the bootrom download operation
- * relys on many default settings(such as interrupts) by
- * it's self.
+ * relies on many default settings(such as interrupts) by
+ * itself.
*/
static bool check_back_to_brom_dnl_flag(void)
{
diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig
index 01af3f1..868e85f 100644
--- a/arch/arm/mach-rockchip/rk3399/Kconfig
+++ b/arch/arm/mach-rockchip/rk3399/Kconfig
@@ -6,9 +6,9 @@
config TARGET_EVB_RK3399
bool "RK3399 evaluation board"
help
- RK3399evb is a evaluation board for Rockchp rk3399,
- with full function and phisical connectors support like type-C ports,
- usb2.0 host ports, LVDS, JTAG, MAC, SDcard, HDMI, USB-2-serial...
+ RK3399evb is a evaluation board for Rockchip RK3399,
+ with full function and physical connectors support like Type-C ports,
+ USB.0 host ports, LVDS, JTAG, MAC, SD card, HDMI, USB-to-serial...
config TARGET_PUMA_RK3399
bool "Theobroma Systems RK3399-Q7 (Puma)"
diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c
index fa8e096..c147d58 100644
--- a/arch/arm/mach-rockchip/spl-boot-order.c
+++ b/arch/arm/mach-rockchip/spl-boot-order.c
@@ -35,7 +35,7 @@
/*
* This should eventually move into the SPL code, once SPL becomes
* aware of the block-device layer. Until then (and to avoid unneeded
- * delays in getting this feature out, it lives at the board-level).
+ * delays in getting this feature out), it lives at the board-level.
*/
if (!uclass_get_device_by_of_offset(UCLASS_MMC, node, &parent)) {
struct udevice *dev;
diff --git a/board/davinci/da8xxevm/omapl138_lcdk.c b/board/davinci/da8xxevm/omapl138_lcdk.c
index 27a51d6..608a7f2 100644
--- a/board/davinci/da8xxevm/omapl138_lcdk.c
+++ b/board/davinci/da8xxevm/omapl138_lcdk.c
@@ -342,7 +342,6 @@
.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
.host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
- .version = MMC_CTLR_VERSION_2,
};
int board_mmc_init(bd_t *bis)
@@ -367,4 +366,13 @@
.name = "ns16550_serial",
.platdata = &serial_pdata,
};
+
+U_BOOT_DEVICE(omapl138_mmc) = {
+ .name = "davinci_mmc",
+};
+
+void spl_board_init(void)
+{
+ davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins));
+}
#endif
diff --git a/board/mediatek/mt8518/Kconfig b/board/mediatek/mt8518/Kconfig
new file mode 100644
index 0000000..1971c4d
--- /dev/null
+++ b/board/mediatek/mt8518/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_MT8518
+
+config SYS_BOARD
+ default "mt8518"
+
+config SYS_CONFIG_NAME
+ default "mt8518"
+
+
+config MTK_BROM_HEADER_INFO
+ string
+ default "media=nor"
+
+endif
diff --git a/board/mediatek/mt8518/MAINTAINERS b/board/mediatek/mt8518/MAINTAINERS
new file mode 100644
index 0000000..c915194
--- /dev/null
+++ b/board/mediatek/mt8518/MAINTAINERS
@@ -0,0 +1,6 @@
+MT8518
+M: Mingming lee <mingming.lee@mediatek.com>
+S: Maintained
+F: board/mediatek/mt8518
+F: include/configs/mt8518.h
+F: configs/mt8518_ap1_emmc_defconfig
diff --git a/board/mediatek/mt8518/Makefile b/board/mediatek/mt8518/Makefile
new file mode 100644
index 0000000..0884b32
--- /dev/null
+++ b/board/mediatek/mt8518/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += mt8518_ap1.o
diff --git a/board/mediatek/mt8518/mt8518_ap1.c b/board/mediatek/mt8518/mt8518_ap1.c
new file mode 100644
index 0000000..9710907
--- /dev/null
+++ b/board/mediatek/mt8518/mt8518_ap1.c
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ */
+
+#include <common.h>
+#include <dm.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ debug("gd->fdt_blob is %p\n", gd->fdt_blob);
+ return 0;
+}
diff --git a/board/rockchip/evb_rk3399/README b/board/rockchip/evb_rk3399/README
index ea3258c..da7ae89 100644
--- a/board/rockchip/evb_rk3399/README
+++ b/board/rockchip/evb_rk3399/README
@@ -9,7 +9,7 @@
* DRAM: 4GB-128MB dual-channel
* eMMC: support eMMC 5.0/5.1, suport HS400, HS200, DDR50
* SD/MMC: support SD 3.0, MMC 4.51
-* USB: USB3.0 typc-C port *2 with dwc3 controller
+* USB: USB3.0 type-C port *2 with dwc3 controller
* USB2.0 EHCI host port *2
* Display: RGB/HDMI/DP/MIPI/EDP
diff --git a/cmd/Makefile b/cmd/Makefile
index 2d723ea..f823d16 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -15,7 +15,7 @@
obj-$(CONFIG_CMD_AB_SELECT) += ab_select.o
obj-$(CONFIG_CMD_ADC) += adc.o
obj-$(CONFIG_CMD_ARMFLASH) += armflash.o
-obj-y += blk_common.o
+obj-$(CONFIG_HAVE_BLOCK_DEVICE) += blk_common.o
obj-$(CONFIG_CMD_SOURCE) += source.o
obj-$(CONFIG_CMD_BCB) += bcb.o
obj-$(CONFIG_CMD_BDI) += bdinfo.o
diff --git a/cmd/blk_common.c b/cmd/blk_common.c
index cee25a0..c5514cf 100644
--- a/cmd/blk_common.c
+++ b/cmd/blk_common.c
@@ -11,7 +11,6 @@
#include <common.h>
#include <blk.h>
-#ifdef CONFIG_HAVE_BLOCK_DEVICE
int blk_common_cmd(int argc, char * const argv[], enum if_type if_type,
int *cur_devnump)
{
@@ -96,4 +95,3 @@
}
}
}
-#endif
diff --git a/cmd/pxe.c b/cmd/pxe.c
index 2059975..768e50a 100644
--- a/cmd/pxe.c
+++ b/cmd/pxe.c
@@ -663,6 +663,7 @@
strncpy(bootm_argv[2], env_get("ramdisk_addr_r"), 18);
strcat(bootm_argv[2], ":");
strncat(bootm_argv[2], env_get("filesize"), 9);
+ bootm_argc = 3;
}
if (get_relfile_envaddr(cmdtp, label->kernel, "kernel_addr_r") < 0) {
diff --git a/common/bootm_os.c b/common/bootm_os.c
index de0709f..d89ddc3 100644
--- a/common/bootm_os.c
+++ b/common/bootm_os.c
@@ -319,8 +319,8 @@
puts("## vxWorks terminated\n");
}
-int do_bootm_vxworks(int flag, int argc, char * const argv[],
- bootm_headers_t *images)
+static int do_bootm_vxworks_legacy(int flag, int argc, char * const argv[],
+ bootm_headers_t *images)
{
if (flag != BOOTM_STATE_OS_GO)
return 0;
@@ -336,6 +336,41 @@
return 1;
}
+
+int do_bootm_vxworks(int flag, int argc, char * const argv[],
+ bootm_headers_t *images)
+{
+ char *bootargs;
+ int pos;
+ unsigned long vxflags;
+ bool std_dtb = false;
+
+ /* get bootargs env */
+ bootargs = env_get("bootargs");
+
+ if (bootargs != NULL) {
+ for (pos = 0; pos < strlen(bootargs); pos++) {
+ /* find f=0xnumber flag */
+ if ((bootargs[pos] == '=') && (pos >= 1) &&
+ (bootargs[pos - 1] == 'f')) {
+ vxflags = simple_strtoul(&bootargs[pos + 1],
+ NULL, 16);
+ if (vxflags & VXWORKS_SYSFLG_STD_DTB)
+ std_dtb = true;
+ }
+ }
+ }
+
+ if (std_dtb) {
+ if (flag & BOOTM_STATE_OS_PREP)
+ printf(" Using standard DTB\n");
+ return do_bootm_linux(flag, argc, argv, images);
+ } else {
+ if (flag & BOOTM_STATE_OS_PREP)
+ printf(" !!! WARNING !!! Using legacy DTB\n");
+ return do_bootm_vxworks_legacy(flag, argc, argv, images);
+ }
+}
#endif
#if defined(CONFIG_CMD_ELF)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 1f12283..e11faae 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -268,7 +268,7 @@
default y
help
If this option is enabled, SPL will print the banner with version
- info. Disabling this option could be useful to reduce TPL boot time
+ info. Disabling this option could be useful to reduce SPL boot time
(e.g. approx. 6 ms faster, when output on i.MX6 with 115200 baud).
config TPL_BANNER_PRINT
@@ -276,8 +276,8 @@
depends on TPL
default y
help
- If this option is enabled, SPL will not print the banner with version
- info. Disabling this option could be useful to reduce SPL boot time
+ If this option is enabled, TPL will print the banner with version
+ info. Disabling this option could be useful to reduce TPL boot time
(e.g. approx. 6 ms faster, when output on i.MX6 with 115200 baud).
config SPL_EARLY_BSS
diff --git a/common/spl/spl_ymodem.c b/common/spl/spl_ymodem.c
index c02c056..8500ee8 100644
--- a/common/spl/spl_ymodem.c
+++ b/common/spl/spl_ymodem.c
@@ -37,7 +37,7 @@
static ulong ymodem_read_fit(struct spl_load_info *load, ulong offset,
ulong size, void *addr)
{
- int res, err;
+ int res, err, buf_offset;
struct ymodem_fit_info *info = load->priv;
char *buf = info->buf;
@@ -51,7 +51,11 @@
if (info->image_read > offset) {
res = info->image_read - offset;
- memcpy(addr, &buf[BUF_SIZE - res], res);
+ if (info->image_read % BUF_SIZE)
+ buf_offset = (info->image_read % BUF_SIZE);
+ else
+ buf_offset = BUF_SIZE;
+ memcpy(addr, &buf[buf_offset - res], res);
addr = addr + res;
}
diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index c0ce181..8c6a8e1 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -62,6 +62,8 @@
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_CORTINA=y
+CONFIG_SYS_CORTINA_FW_IN_NAND=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index dd11797..4a0eac0 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -59,6 +59,8 @@
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_CORTINA=y
+CONFIG_SYS_CORTINA_FW_IN_MMC=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
diff --git a/configs/T2080RDB_SECURE_BOOT_defconfig b/configs/T2080RDB_SECURE_BOOT_defconfig
index 5c256f8..65522f7 100644
--- a/configs/T2080RDB_SECURE_BOOT_defconfig
+++ b/configs/T2080RDB_SECURE_BOOT_defconfig
@@ -43,6 +43,7 @@
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_CORTINA=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index bfc9799..4ea7379 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -62,6 +62,8 @@
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_CORTINA=y
+CONFIG_SYS_CORTINA_FW_IN_SPIFLASH=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
diff --git a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
index d29c147..8f6a5ce 100644
--- a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
@@ -35,6 +35,8 @@
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_CORTINA=y
+CONFIG_SYS_CORTINA_FW_IN_REMOTE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index dd9c63a..ac40aa7 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -47,6 +47,7 @@
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_CORTINA=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
diff --git a/configs/T4160RDB_defconfig b/configs/T4160RDB_defconfig
index 986539a..b0a661b 100644
--- a/configs/T4160RDB_defconfig
+++ b/configs/T4160RDB_defconfig
@@ -36,6 +36,7 @@
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
+CONFIG_PHY_CORTINA=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index 4653052..1173f9f 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -52,6 +52,7 @@
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
+CONFIG_PHY_CORTINA=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index 37b459e..83c69b6 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -40,6 +40,7 @@
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
+CONFIG_PHY_CORTINA=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig
index d231c23..bc42a54 100644
--- a/configs/ls2080ardb_SECURE_BOOT_defconfig
+++ b/configs/ls2080ardb_SECURE_BOOT_defconfig
@@ -42,6 +42,7 @@
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_CORTINA=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_PCI=y
diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig
index 4840304..be06206 100644
--- a/configs/ls2080ardb_defconfig
+++ b/configs/ls2080ardb_defconfig
@@ -45,6 +45,7 @@
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_CORTINA=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_PCI=y
diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index 49bdd58..bd5a953 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -54,6 +54,7 @@
CONFIG_SYS_FLASH_CFI=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_CORTINA=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_PCI=y
diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig
index 01288a7..d8204f1 100644
--- a/configs/ls2081ardb_defconfig
+++ b/configs/ls2081ardb_defconfig
@@ -41,6 +41,7 @@
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_CORTINA=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_PCI=y
diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
index 8894df5..c6327e4 100644
--- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
@@ -37,6 +37,7 @@
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_CORTINA=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_PCI=y
diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig
index d230000..ae77006 100644
--- a/configs/ls2088ardb_qspi_defconfig
+++ b/configs/ls2088ardb_qspi_defconfig
@@ -43,6 +43,7 @@
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_CORTINA=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_PCI=y
diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
index db253d1..c5339e5 100644
--- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
@@ -52,6 +52,7 @@
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_CORTINA=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_PCI=y
diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig
index 1730c9a..ed7ef43 100644
--- a/configs/ls2088ardb_tfa_defconfig
+++ b/configs/ls2088ardb_tfa_defconfig
@@ -59,6 +59,7 @@
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_CORTINA=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_PCI=y
diff --git a/configs/mt8518_ap1_emmc_defconfig b/configs/mt8518_ap1_emmc_defconfig
new file mode 100644
index 0000000..c2865a2
--- /dev/null
+++ b/configs/mt8518_ap1_emmc_defconfig
@@ -0,0 +1,44 @@
+CONFIG_ARM=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_SYS_TEXT_BASE=0x40008000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_TARGET_MT8518=y
+CONFIG_SYS_PROMPT="MT8518> "
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x4E60000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_OF_LIBFDT=y
+# CONFIG_FDT_DEBUG is not set
+CONFIG_LZMA=y
+CONFIG_LZ4=y
+CONFIG_LZO=y
+CONFIG_GZIP=y
+CONFIG_BZIP2=y
+CONFIG_CMD_BOOTMENU=y
+CONFIG_MENU_SHOW=y
+CONFIG_DEFAULT_FDT_FILE="mt8518-ap1-emmc.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="mt8518-ap1-emmc"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MT8518=y
+CONFIG_RAM=y
+CONFIG_BAUDRATE=921600
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM=y
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_SERIAL=y
+CONFIG_MTK_SERIAL=y
+CONFIG_WDT=y
+CONFIG_WDT_MTK=y
+CONFIG_CLK=y
+CONFIG_TIMER=y
+CONFIG_MTK_TIMER=y
+CONFIG_CMD_MMC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MTK=y
+CONFIG_MMC_HS200_SUPPORT=y
+# CONFIG_ENV_IS_IN_MMC is not set
diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index add152e..59a2ca2 100644
--- a/configs/omapl138_lcdk_defconfig
+++ b/configs/omapl138_lcdk_defconfig
@@ -7,6 +7,7 @@
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_ENV_SIZE=0x10000
@@ -21,6 +22,7 @@
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xb5
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
@@ -44,6 +46,8 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_OF_TRANSLATE=y
CONFIG_DM_GPIO=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_I2C=y
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index ffe0436..22fa0e1 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -21,6 +21,7 @@
CONFIG_CMD_BOOTZ=y
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
# CONFIG_CMD_FDT is not set
CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/xilinx_zynqmp_zcu216_revA_defconfig b/configs/xilinx_zynqmp_zcu216_revA_defconfig
index 331a8f2..264867f 100644
--- a/configs/xilinx_zynqmp_zcu216_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu216_revA_defconfig
@@ -33,7 +33,7 @@
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu111-revA"
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu216-revA"
CONFIG_ENV_IS_IN_FAT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/doc/README.SPL b/doc/README.SPL
index 6eed83f..3c931ec 100644
--- a/doc/README.SPL
+++ b/doc/README.SPL
@@ -75,7 +75,7 @@
- the nodes with one pre-relocation property:
'u-boot,dm-pre-reloc' or 'u-boot,dm-spl'
-ftgrep is also used to remove:
+fdtgrep is also used to remove:
- the properties defined in CONFIG_OF_SPL_REMOVE_PROPS
- all the pre-relocation properties
('u-boot,dm-pre-reloc', 'u-boot,dm-spl' and 'u-boot,dm-tpl')
diff --git a/doc/README.TPL b/doc/README.TPL
index c94129f..72027fd 100644
--- a/doc/README.TPL
+++ b/doc/README.TPL
@@ -31,7 +31,7 @@
The SPL options are shared by SPL and TPL, the board config file should
determine which SPL options to choose based on whether CONFIG_TPL_BUILD
-is set. Source files can be compiled for TPL with options choosed in the
+is set. Source files can be compiled for TPL with options chosen in the
board config file.
TPL use a small device tree (u-boot-tpl.dtb), containing only the nodes with
diff --git a/doc/README.vxworks b/doc/README.vxworks
index 3e08711..12a0d74 100644
--- a/doc/README.vxworks
+++ b/doc/README.vxworks
@@ -2,6 +2,7 @@
#
# Copyright (C) 2013, Miao Yan <miao.yan@windriver.com>
# Copyright (C) 2015-2018, Bin Meng <bmeng.cn@gmail.com>
+# Copyright (C) 2019, Lihua Zhao <lihua.zhao@windriver.com>
VxWorks Support
===============
@@ -24,6 +25,15 @@
mechanism (for PowerPC and ARM), thus requiring boot interface changes.
This section will describe the new interface.
+Since VxWorks 7 SR0640 release, VxWorks starts using Linux compatible standard
+DTB for some boards. With that, the exact same bootm flow as used by Linux is
+used, which includes board-specific DTB fix up. To keep backward compatibility,
+only when the least significant bit of flags in bootargs is set, the standard
+DTB will be used. Otherwise it falls back to the legacy bootm flow.
+
+For legacy bootm flow, make sure the least significant bit of flags in bootargs
+is cleared. The calling convention is described below:
+
For PowerPC, the calling convention of the new VxWorks entry point conforms to
the ePAPR standard, which is shown below (see ePAPR for more details):
@@ -33,6 +43,9 @@
void (*kernel_entry)(void *fdt_addr)
+When using the Linux compatible standard DTB, the calling convention of VxWorks
+entry point is exactly the same as the Linux kernel.
+
When booting a VxWorks 7 kernel (uImage format), the parameters passed to bootm
is like below:
diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt
index f8e27ed..18d2aed 100644
--- a/doc/uImage.FIT/source_file_format.txt
+++ b/doc/uImage.FIT/source_file_format.txt
@@ -262,7 +262,7 @@
- loadables : Unit name containing a list of additional binaries to be
loaded at their given locations. "loadables" is a comma-separated list
of strings. U-Boot will load each binary at its given start-address and
- may optionaly invoke additional post-processing steps on this binary based
+ may optionally invoke additional post-processing steps on this binary based
on its component image node type.
- compatible : The root compatible string of the U-Boot device tree that
this configuration shall automatically match when CONFIG_FIT_BEST_MATCH is
diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index 3feb0aa..94ab5c6 100644
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -6,7 +6,7 @@
obj-$(CONFIG_$(SPL_)BLK) += blk-uclass.o
ifndef CONFIG_$(SPL_)BLK
-obj-y += blk_legacy.o
+obj-$(CONFIG_HAVE_BLOCK_DEVICE) += blk_legacy.o
endif
ifndef CONFIG_SPL_BUILD
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index a47a5bd..e92bcd4 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -6,3 +6,4 @@
obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
+obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o
diff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c
new file mode 100644
index 0000000..76f7b3b
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8518.c
@@ -0,0 +1,1558 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT8518 SoC
+ *
+ * Copyright (C) 2019 BayLibre, SAS
+ * Author: Chen Zhong <chen.zhong@mediatek.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/mt8518-clk.h>
+
+#include "clk-mtk.h"
+
+#define MT8518_PLL_FMAX (3000UL * MHZ)
+#define MT8518_CON0_RST_BAR BIT(27)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _pcw_reg, _pcw_shift) { \
+ .id = _id, \
+ .reg = _reg, \
+ .pwr_reg = _pwr_reg, \
+ .en_mask = _en_mask, \
+ .rst_bar_mask = MT8518_CON0_RST_BAR, \
+ .fmax = MT8518_PLL_FMAX, \
+ .flags = _flags, \
+ .pcwbits = _pcwbits, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x00000001,
+ 0, 21, 0x0104, 24, 0x0104, 0),
+ PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x00000001,
+ HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0),
+ PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001,
+ HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0),
+ PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x00000001,
+ 0, 21, 0x0164, 24, 0x0164, 0),
+ PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001,
+ 0, 31, 0x0180, 1, 0x0184, 0),
+ PLL(CLK_APMIXED_APLL2, 0x01A0, 0x01B0, 0x00000001,
+ 0, 31, 0x01A0, 1, 0x01A4, 0),
+ PLL(CLK_APMIXED_TVDPLL, 0x01C0, 0x01D0, 0x00000001,
+ 0, 21, 0x01C4, 24, 0x01C4, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000),
+ FIXED_CLK(CLK_TOP_FQ_TRNG_OUT0, CLK_TOP_CLK_NULL, 500000000),
+ FIXED_CLK(CLK_TOP_FQ_TRNG_OUT1, CLK_TOP_CLK_NULL, 500000000),
+ FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000),
+};
+
+static const struct mtk_fixed_factor top_fixed_divs[] = {
+ FACTOR2(CLK_TOP_DMPLL, CLK_XTAL, 1, 1),
+ FACTOR0(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4),
+ FACTOR0(CLK_TOP_MAINPLL_D8, CLK_APMIXED_MAINPLL, 1, 8),
+ FACTOR0(CLK_TOP_MAINPLL_D16, CLK_APMIXED_MAINPLL, 1, 16),
+ FACTOR0(CLK_TOP_MAINPLL_D11, CLK_APMIXED_MAINPLL, 1, 11),
+ FACTOR0(CLK_TOP_MAINPLL_D22, CLK_APMIXED_MAINPLL, 1, 22),
+ FACTOR0(CLK_TOP_MAINPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
+ FACTOR0(CLK_TOP_MAINPLL_D6, CLK_APMIXED_MAINPLL, 1, 6),
+ FACTOR0(CLK_TOP_MAINPLL_D12, CLK_APMIXED_MAINPLL, 1, 12),
+ FACTOR0(CLK_TOP_MAINPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
+ FACTOR0(CLK_TOP_MAINPLL_D10, CLK_APMIXED_MAINPLL, 1, 10),
+ FACTOR0(CLK_TOP_MAINPLL_D20, CLK_APMIXED_MAINPLL, 1, 20),
+ FACTOR0(CLK_TOP_MAINPLL_D40, CLK_APMIXED_MAINPLL, 1, 40),
+ FACTOR0(CLK_TOP_MAINPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
+ FACTOR0(CLK_TOP_MAINPLL_D14, CLK_APMIXED_MAINPLL, 1, 14),
+ FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
+ FACTOR0(CLK_TOP_UNIVPLL_D4, CLK_APMIXED_UNIVPLL, 1, 4),
+ FACTOR0(CLK_TOP_UNIVPLL_D8, CLK_APMIXED_UNIVPLL, 1, 8),
+ FACTOR0(CLK_TOP_UNIVPLL_D16, CLK_APMIXED_UNIVPLL, 1, 16),
+ FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
+ FACTOR0(CLK_TOP_UNIVPLL_D6, CLK_APMIXED_UNIVPLL, 1, 6),
+ FACTOR0(CLK_TOP_UNIVPLL_D12, CLK_APMIXED_UNIVPLL, 1, 12),
+ FACTOR0(CLK_TOP_UNIVPLL_D24, CLK_APMIXED_UNIVPLL, 1, 24),
+ FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5),
+ FACTOR0(CLK_TOP_UNIVPLL_D20, CLK_APMIXED_UNIVPLL, 1, 20),
+ FACTOR0(CLK_TOP_UNIVPLL_D10, CLK_APMIXED_UNIVPLL, 1, 10),
+ FACTOR0(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2),
+ FACTOR0(CLK_TOP_USB20_48M, CLK_APMIXED_UNIVPLL, 1, 26),
+ FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1),
+ FACTOR1(CLK_TOP_APLL1_D4, CLK_TOP_APLL1, 1, 4),
+ FACTOR0(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1),
+ FACTOR1(CLK_TOP_APLL2_D2, CLK_TOP_APLL2, 1, 2),
+ FACTOR1(CLK_TOP_APLL2_D3, CLK_TOP_APLL2, 1, 3),
+ FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_APLL2, 1, 4),
+ FACTOR1(CLK_TOP_APLL2_D8, CLK_TOP_APLL2, 1, 8),
+ FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1),
+ FACTOR2(CLK_TOP_CLK26M_D2, CLK_XTAL, 1, 2),
+ FACTOR2(CLK_TOP_CLK26M_D4, CLK_XTAL, 1, 4),
+ FACTOR2(CLK_TOP_CLK26M_D8, CLK_XTAL, 1, 8),
+ FACTOR2(CLK_TOP_CLK26M_D793, CLK_XTAL, 1, 793),
+ FACTOR0(CLK_TOP_TVDPLL, CLK_APMIXED_TVDPLL, 1, 1),
+ FACTOR1(CLK_TOP_TVDPLL_D2, CLK_TOP_TVDPLL, 1, 2),
+ FACTOR1(CLK_TOP_TVDPLL_D4, CLK_TOP_TVDPLL, 1, 4),
+ FACTOR1(CLK_TOP_TVDPLL_D8, CLK_TOP_TVDPLL, 1, 8),
+ FACTOR1(CLK_TOP_TVDPLL_D16, CLK_TOP_TVDPLL, 1, 16),
+ FACTOR1(CLK_TOP_USB20_CLK480M, CLK_TOP_CLK_NULL, 1, 1),
+ FACTOR1(CLK_TOP_RG_APLL1_D2, CLK_TOP_APLL1_SRC_SEL, 1, 2),
+ FACTOR1(CLK_TOP_RG_APLL1_D4, CLK_TOP_APLL1_SRC_SEL, 1, 4),
+ FACTOR1(CLK_TOP_RG_APLL1_D8, CLK_TOP_APLL1_SRC_SEL, 1, 8),
+ FACTOR1(CLK_TOP_RG_APLL1_D16, CLK_TOP_APLL1_SRC_SEL, 1, 16),
+ FACTOR1(CLK_TOP_RG_APLL1_D3, CLK_TOP_APLL1_SRC_SEL, 1, 3),
+ FACTOR1(CLK_TOP_RG_APLL2_D2, CLK_TOP_APLL2_SRC_SEL, 1, 2),
+ FACTOR1(CLK_TOP_RG_APLL2_D4, CLK_TOP_APLL2_SRC_SEL, 1, 4),
+ FACTOR1(CLK_TOP_RG_APLL2_D8, CLK_TOP_APLL2_SRC_SEL, 1, 8),
+ FACTOR1(CLK_TOP_RG_APLL2_D16, CLK_TOP_APLL2_SRC_SEL, 1, 16),
+ FACTOR1(CLK_TOP_RG_APLL2_D3, CLK_TOP_APLL2_SRC_SEL, 1, 3),
+ FACTOR1(CLK_TOP_NFI1X_INFRA_BCLK, CLK_TOP_NFI2X_SEL, 1, 2),
+ FACTOR1(CLK_TOP_AHB_INFRA_D2, CLK_TOP_AXIBUS_SEL, 1, 2),
+};
+
+static const int uart0_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D24
+};
+
+static const int emi1x_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_DMPLL
+};
+
+static const int emi_ddrphy_parents[] = {
+ CLK_TOP_EMI1X_SEL,
+ CLK_TOP_EMI1X_SEL
+};
+
+static const int msdc1_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D6,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D8,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MMPLL_D2,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D12
+};
+
+static const int pwm_mm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D12
+};
+
+static const int pmicspi_parents[] = {
+ CLK_TOP_UNIVPLL_D20,
+ CLK_TOP_USB20_48M,
+ CLK_TOP_UNIVPLL_D16,
+ CLK_TOP_CLK26M,
+ CLK_TOP_CLK26M_D2
+};
+
+static const int nfi2x_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D4,
+ CLK_TOP_MAINPLL_D5,
+ CLK_TOP_MAINPLL_D6,
+ CLK_TOP_MAINPLL_D7,
+ CLK_TOP_MAINPLL_D8,
+ CLK_TOP_MAINPLL_D10,
+ CLK_TOP_MAINPLL_D12
+};
+
+static const int ddrphycfg_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D16
+};
+
+static const int smi_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D4,
+ CLK_TOP_MAINPLL_D7,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D14
+};
+
+static const int usb_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D16,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D20
+};
+
+static const int spinor_parents[] = {
+ CLK_TOP_CLK26M_D2,
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D40,
+ CLK_TOP_UNIVPLL_D24,
+ CLK_TOP_UNIVPLL_D20,
+ CLK_TOP_MAINPLL_D20,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_UNIVPLL_D12
+};
+
+static const int eth_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D40,
+ CLK_TOP_UNIVPLL_D24,
+ CLK_TOP_UNIVPLL_D20,
+ CLK_TOP_MAINPLL_D20
+};
+
+static const int aud1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL1_SRC_SEL
+};
+
+static const int aud2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL2_SRC_SEL
+};
+
+static const int i2c_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_USB20_48M,
+ CLK_TOP_UNIVPLL_D12,
+ CLK_TOP_UNIVPLL_D10,
+ CLK_TOP_UNIVPLL_D8
+};
+
+static const int aud_i2s0_m_parents[] = {
+ CLK_TOP_AUD1,
+ CLK_TOP_AUD2
+};
+
+static const int aud_spdifin_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D2,
+ CLK_TOP_TVDPLL
+};
+
+static const int dbg_atclk_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D5,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D5
+};
+
+static const int png_sys_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_MAINPLL_D7,
+ CLK_TOP_MAINPLL_D6,
+ CLK_TOP_MAINPLL_D5,
+ CLK_TOP_UNIVPLL_D3
+};
+
+static const int sej_13m_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_CLK26M_D2
+};
+
+static const int imgrz_sys_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D6,
+ CLK_TOP_MAINPLL_D7,
+ CLK_TOP_MAINPLL_D5,
+ CLK_TOP_UNIVPLL_D4,
+ CLK_TOP_UNIVPLL_D10,
+ CLK_TOP_UNIVPLL_D5,
+ CLK_TOP_UNIVPLL_D6
+};
+
+static const int graph_eclk_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D6,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_UNIVPLL_D16,
+ CLK_TOP_MAINPLL_D7,
+ CLK_TOP_UNIVPLL_D4,
+ CLK_TOP_UNIVPLL_D10,
+ CLK_TOP_UNIVPLL_D24,
+ CLK_TOP_MAINPLL_D8
+};
+
+static const int fdbi_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_MAINPLL_D14,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_UNIVPLL_D10,
+ CLK_TOP_UNIVPLL_D12,
+ CLK_TOP_UNIVPLL_D16,
+ CLK_TOP_UNIVPLL_D24,
+ CLK_TOP_TVDPLL_D2,
+ CLK_TOP_TVDPLL_D4,
+ CLK_TOP_TVDPLL_D8,
+ CLK_TOP_TVDPLL_D16
+};
+
+static const int faudio_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D24,
+ CLK_TOP_APLL1_D4,
+ CLK_TOP_APLL2_D4
+};
+
+static const int fa2sys_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL1_SRC_SEL,
+ CLK_TOP_RG_APLL1_D2,
+ CLK_TOP_RG_APLL1_D4,
+ CLK_TOP_RG_APLL1_D8,
+ CLK_TOP_RG_APLL1_D16,
+ CLK_TOP_CLK26M_D2,
+ CLK_TOP_RG_APLL1_D3
+};
+
+static const int fa1sys_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL2_SRC_SEL,
+ CLK_TOP_RG_APLL2_D2,
+ CLK_TOP_RG_APLL2_D4,
+ CLK_TOP_RG_APLL2_D8,
+ CLK_TOP_RG_APLL2_D16,
+ CLK_TOP_CLK26M_D2,
+ CLK_TOP_RG_APLL2_D3
+};
+
+static const int fasm_m_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D12,
+ CLK_TOP_UNIVPLL_D6,
+ CLK_TOP_MAINPLL_D7
+};
+
+static const int fecc_ck_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D6,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D4,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D3,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D3
+};
+
+static const int pe2_mac_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D11,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_UNIVPLL_D12,
+ CLK_TOP_UNIVPLL_D10
+};
+
+static const int cmsys_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D5,
+ CLK_TOP_UNIVPLL_D6,
+ CLK_TOP_MAINPLL_D5,
+ CLK_TOP_APLL2,
+ CLK_TOP_APLL2_D2,
+ CLK_TOP_APLL2_D4,
+ CLK_TOP_APLL2_D3
+};
+
+static const int gcpu_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D4,
+ CLK_TOP_MAINPLL_D5,
+ CLK_TOP_MAINPLL_D6,
+ CLK_TOP_MAINPLL_D7,
+ CLK_TOP_UNIVPLL_D4,
+ CLK_TOP_UNIVPLL_D10,
+ CLK_TOP_UNIVPLL_D3
+};
+
+static const int spis_ck_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D12,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D6,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D5,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D4,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D4,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D3
+};
+
+static const int apll1_ref_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL
+};
+
+static const int int_32k_parents[] = {
+ CLK_TOP_CLK32K,
+ CLK_TOP_CLK26M_D793
+};
+
+static const int apll1_src_parents[] = {
+ CLK_TOP_APLL1,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL
+};
+
+static const int apll2_src_parents[] = {
+ CLK_TOP_APLL2,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL
+};
+
+static const int faud_intbus_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D11,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D10,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_RG_APLL2_D8,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M_D2,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_RG_APLL1_D8,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D20
+};
+
+static const int axibus_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D11,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D10,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M_D2,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_APLL2_D8
+};
+
+static const int hapll1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL1_SRC_SEL,
+ CLK_TOP_RG_APLL1_D2,
+ CLK_TOP_RG_APLL1_D4,
+ CLK_TOP_RG_APLL1_D8,
+ CLK_TOP_RG_APLL1_D16,
+ CLK_TOP_CLK26M_D2,
+ CLK_TOP_CLK26M_D8,
+ CLK_TOP_RG_APLL1_D3
+};
+
+static const int hapll2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL2_SRC_SEL,
+ CLK_TOP_RG_APLL2_D2,
+ CLK_TOP_RG_APLL2_D4,
+ CLK_TOP_RG_APLL2_D8,
+ CLK_TOP_RG_APLL2_D16,
+ CLK_TOP_CLK26M_D2,
+ CLK_TOP_CLK26M_D4,
+ CLK_TOP_RG_APLL2_D3
+};
+
+static const int spinfi_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D24,
+ CLK_TOP_UNIVPLL_D20,
+ CLK_TOP_MAINPLL_D22,
+ CLK_TOP_UNIVPLL_D16,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_UNIVPLL_D12,
+ CLK_TOP_UNIVPLL_D10,
+ CLK_TOP_MAINPLL_D11
+};
+
+static const int msdc0_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D6,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D8,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_APMIXED_MMPLL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MMPLL_D2
+};
+
+static const int msdc0_clk50_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D6,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D8,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D6
+};
+
+static const int msdc2_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D6,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D8,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MMPLL_D2,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_APMIXED_MMPLL
+};
+
+static const int disp_dpi_ck_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_TVDPLL_D2,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_TVDPLL_D4,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_TVDPLL_D8,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_TVDPLL_D16
+};
+
+static const struct mtk_composite top_muxes[] = {
+ /* CLK_MUX_SEL0 */
+ MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
+ MUX(CLK_TOP_EMI1X_SEL, emi1x_parents, 0x000, 1, 1),
+ MUX(CLK_TOP_EMI_DDRPHY_SEL, emi_ddrphy_parents, 0x000, 2, 1),
+ MUX(CLK_TOP_MSDC1_SEL, msdc1_parents, 0x000, 4, 8),
+ MUX(CLK_TOP_PWM_MM_SEL, pwm_mm_parents, 0x000, 18, 1),
+ MUX(CLK_TOP_UART1_SEL, uart0_parents, 0x000, 19, 1),
+ MUX(CLK_TOP_SPM_52M_SEL, uart0_parents, 0x000, 22, 1),
+ MUX(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x000, 23, 3),
+ /* CLK_MUX_SEL1 */
+ MUX(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0x004, 0, 3),
+ MUX(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x004, 15, 1),
+ MUX(CLK_TOP_SMI_SEL, smi_parents, 0x004, 16, 4),
+ MUX(CLK_TOP_USB_SEL, usb_parents, 0x004, 20, 3),
+ /* CLK_MUX_SEL8 */
+ MUX(CLK_TOP_SPINOR_SEL, spinor_parents, 0x040, 0, 3),
+ MUX(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3),
+ MUX(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1),
+ MUX(CLK_TOP_AUD2_SEL, aud2_parents, 0x040, 23, 1),
+ MUX(CLK_TOP_I2C_SEL, i2c_parents, 0x040, 28, 3),
+ /* CLK_SEL_9 */
+ MUX(CLK_TOP_AUD_I2S0_M_SEL, aud_i2s0_m_parents, 0x044, 12, 1),
+ MUX(CLK_TOP_AUD_I2S3_M_SEL, aud_i2s0_m_parents, 0x044, 15, 1),
+ MUX(CLK_TOP_AUD_I2S4_M_SEL, aud_i2s0_m_parents, 0x044, 16, 1),
+ MUX(CLK_TOP_AUD_I2S6_M_SEL, aud_i2s0_m_parents, 0x044, 18, 1),
+ /* CLK_MUX_SEL13 */
+ MUX(CLK_TOP_PWM_SEL, pwm_mm_parents, 0x07c, 0, 1),
+ MUX(CLK_TOP_AUD_SPDIFIN_SEL, aud_spdifin_parents, 0x07c, 2, 2),
+ MUX(CLK_TOP_UART2_SEL, uart0_parents, 0x07c, 4, 1),
+ MUX(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, 0x07c, 7, 3),
+ MUX(CLK_TOP_PNG_SYS_SEL, png_sys_parents, 0x07c, 16, 3),
+ MUX(CLK_TOP_SEJ_13M_SEL, sej_13m_parents, 0x07c, 22, 1),
+ /* CLK_MUX_SEL14 */
+ MUX(CLK_TOP_IMGRZ_SYS_SEL, imgrz_sys_parents, 0xc0, 0, 3),
+ MUX(CLK_TOP_GRAPH_ECLK_SEL, graph_eclk_parents, 0xc0, 8, 4),
+ MUX(CLK_TOP_FDBI_SEL, fdbi_parents, 0xc0, 12, 4),
+ MUX(CLK_TOP_FAUDIO_SEL, faudio_parents, 0xc0, 16, 2),
+ MUX(CLK_TOP_FA2SYS_SEL, fa2sys_parents, 0xc0, 24, 3),
+ MUX(CLK_TOP_FA1SYS_SEL, fa1sys_parents, 0xc0, 27, 3),
+ MUX(CLK_TOP_FASM_M_SEL, fasm_m_parents, 0xc0, 30, 2),
+ /* CLK_MUX_SEL15 */
+ MUX(CLK_TOP_FASM_H_SEL, fasm_m_parents, 0xC4, 0, 2),
+ MUX(CLK_TOP_FASM_L_SEL, fasm_m_parents, 0xC4, 2, 2),
+ MUX(CLK_TOP_FECC_CK_SEL, fecc_ck_parents, 0xC4, 18, 6),
+ MUX(CLK_TOP_PE2_MAC_SEL, pe2_mac_parents, 0xC4, 24, 3),
+ MUX(CLK_TOP_CMSYS_SEL, cmsys_parents, 0xC4, 28, 3),
+ /* CLK_MUX_SEL16 */
+ MUX(CLK_TOP_GCPU_SEL, gcpu_parents, 0xC8, 0, 3),
+ MUX(CLK_TOP_SPIS_CK_SEL, spis_ck_parents, 0xC8, 4, 8),
+ /* CLK_MUX_SEL17 */
+ MUX(CLK_TOP_APLL1_REF_SEL, apll1_ref_parents, 0xCC, 6, 3),
+ MUX(CLK_TOP_APLL2_REF_SEL, apll1_ref_parents, 0xCC, 9, 3),
+ MUX(CLK_TOP_INT_32K_SEL, int_32k_parents, 0xCC, 12, 1),
+ MUX(CLK_TOP_APLL1_SRC_SEL, apll1_src_parents, 0xCC, 13, 2),
+ MUX(CLK_TOP_APLL2_SRC_SEL, apll2_src_parents, 0xCC, 15, 2),
+ /* CLK_MUX_SEL19 */
+ MUX(CLK_TOP_FAUD_INTBUS_SEL, faud_intbus_parents, 0xD4, 8, 8),
+ MUX(CLK_TOP_AXIBUS_SEL, axibus_parents, 0xD4, 24, 8),
+ /* CLK_MUX_SEL21 */
+ MUX(CLK_TOP_HAPLL1_SEL, hapll1_parents, 0xDC, 0, 4),
+ MUX(CLK_TOP_HAPLL2_SEL, hapll2_parents, 0xDC, 4, 4),
+ MUX(CLK_TOP_SPINFI_SEL, spinfi_parents, 0xDC, 8, 4),
+ /* CLK_MUX_SEL22 */
+ MUX(CLK_TOP_MSDC0_SEL, msdc0_parents, 0xF4, 0, 8),
+ MUX(CLK_TOP_MSDC0_CLK50_SEL, msdc0_clk50_parents, 0xF4, 8, 6),
+ MUX(CLK_TOP_MSDC2_SEL, msdc2_parents, 0xF4, 15, 8),
+ MUX(CLK_TOP_MSDC2_CLK50_SEL, msdc0_clk50_parents, 0xF4, 23, 6),
+ /* CLK_MUX_SEL23 */
+ MUX(CLK_TOP_DISP_DPI_CK_SEL, disp_dpi_ck_parents, 0xF8, 0, 6),
+ MUX(CLK_TOP_SPI1_SEL, spis_ck_parents, 0xF8, 6, 8),
+ MUX(CLK_TOP_SPI2_SEL, spis_ck_parents, 0xF8, 14, 8),
+ MUX(CLK_TOP_SPI3_SEL, spis_ck_parents, 0xF8, 22, 8),
+};
+
+static const struct mtk_gate_regs top0_cg_regs = {
+ .set_ofs = 0x50,
+ .clr_ofs = 0x80,
+ .sta_ofs = 0x20,
+};
+
+static const struct mtk_gate_regs top1_cg_regs = {
+ .set_ofs = 0x54,
+ .clr_ofs = 0x84,
+ .sta_ofs = 0x24,
+};
+
+static const struct mtk_gate_regs top2_cg_regs = {
+ .set_ofs = 0x6c,
+ .clr_ofs = 0x9c,
+ .sta_ofs = 0x3c,
+};
+
+static const struct mtk_gate_regs top3_cg_regs = {
+ .set_ofs = 0x44,
+ .clr_ofs = 0x44,
+ .sta_ofs = 0x44,
+};
+
+static const struct mtk_gate_regs top4_cg_regs = {
+ .set_ofs = 0xa0,
+ .clr_ofs = 0xb0,
+ .sta_ofs = 0x70,
+};
+
+static const struct mtk_gate_regs top5_cg_regs = {
+ .set_ofs = 0x120,
+ .clr_ofs = 0x140,
+ .sta_ofs = 0xe0,
+};
+
+static const struct mtk_gate_regs top6_cg_regs = {
+ .set_ofs = 0x128,
+ .clr_ofs = 0x148,
+ .sta_ofs = 0xe8,
+};
+
+static const struct mtk_gate_regs top7_cg_regs = {
+ .set_ofs = 0x12c,
+ .clr_ofs = 0x14c,
+ .sta_ofs = 0xec,
+};
+
+#define GATE_TOP0(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top0_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP1(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top1_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP2(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top2_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP2_I(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top2_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP3(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top3_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP4(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top4_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP5(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top5_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP5_I(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top5_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP6(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top6_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP7(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top7_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+static const struct mtk_gate top_clks[] = {
+ /* TOP0 */
+ GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
+ GATE_TOP0(CLK_TOP_SMI, CLK_TOP_SMI_SEL, 9),
+ GATE_TOP0(CLK_TOP_SPI2, CLK_TOP_SPI2_SEL, 10),
+ GATE_TOP0(CLK_TOP_SPI3, CLK_TOP_SPI3_SEL, 11),
+ GATE_TOP0(CLK_TOP_SPINFI, CLK_TOP_SPINFI_SEL, 12),
+ GATE_TOP0(CLK_TOP_26M_DEBUG, CLK_TOP_CLK26M, 16),
+ GATE_TOP0(CLK_TOP_USB_48M_DEBUG, CLK_TOP_USB20_48M, 17),
+ GATE_TOP0(CLK_TOP_52M_DEBUG, CLK_TOP_UNIVPLL_D24, 18),
+ GATE_TOP0(CLK_TOP_32K_DEBUG, CLK_TOP_INT_32K_SEL, 19),
+ /* TOP1 */
+ GATE_TOP1(CLK_TOP_THERM, CLK_TOP_AXIBUS_SEL, 1),
+ GATE_TOP1(CLK_TOP_APDMA, CLK_TOP_AXIBUS_SEL, 2),
+ GATE_TOP1(CLK_TOP_I2C0, CLK_TOP_AHB_INFRA_D2, 3),
+ GATE_TOP1(CLK_TOP_I2C1, CLK_TOP_AHB_INFRA_D2, 4),
+ GATE_TOP1(CLK_TOP_AUXADC1, CLK_TOP_CLK26M, 5),
+ GATE_TOP1(CLK_TOP_NFI, CLK_TOP_NFI1X_INFRA_BCLK, 6),
+ GATE_TOP1(CLK_TOP_NFIECC, CLK_TOP_AXIBUS_SEL, 7),
+ GATE_TOP1(CLK_TOP_DEBUGSYS, CLK_TOP_DBG_ATCLK_SEL, 8),
+ GATE_TOP1(CLK_TOP_PWM, CLK_TOP_AXIBUS_SEL, 9),
+ GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
+ GATE_TOP1(CLK_TOP_UART1, CLK_TOP_UART1_SEL, 11),
+ GATE_TOP1(CLK_TOP_USB, CLK_TOP_USB_B, 13),
+ GATE_TOP1(CLK_TOP_FLASHIF_26M, CLK_TOP_CLK26M, 14),
+ GATE_TOP1(CLK_TOP_AUXADC2, CLK_TOP_CLK26M, 15),
+ GATE_TOP1(CLK_TOP_I2C2, CLK_TOP_AHB_INFRA_D2, 16),
+ GATE_TOP1(CLK_TOP_MSDC0, CLK_TOP_MSDC0_SEL, 17),
+ GATE_TOP1(CLK_TOP_MSDC1, CLK_TOP_MSDC1_SEL, 18),
+ GATE_TOP1(CLK_TOP_NFI2X, CLK_TOP_NFI2X_SEL, 19),
+ GATE_TOP1(CLK_TOP_MEMSLP_DLYER, CLK_TOP_CLK26M, 22),
+ GATE_TOP1(CLK_TOP_SPI, CLK_TOP_SPI1_SEL, 23),
+ GATE_TOP1(CLK_TOP_APXGPT, CLK_TOP_CLK26M, 24),
+ GATE_TOP1(CLK_TOP_PMICWRAP_MD, CLK_TOP_CLK26M, 27),
+ GATE_TOP1(CLK_TOP_PMICWRAP_CONN, CLK_TOP_PMICSPI_SEL, 28),
+ GATE_TOP1(CLK_TOP_PMIC_SYSCK, CLK_TOP_CLK26M, 29),
+ GATE_TOP1(CLK_TOP_AUX_ADC, CLK_TOP_CLK26M, 30),
+ GATE_TOP1(CLK_TOP_AUX_TP, CLK_TOP_CLK26M, 31),
+ /* TOP2 */
+ GATE_TOP2(CLK_TOP_RBIST, CLK_TOP_UNIVPLL_D12, 1),
+ GATE_TOP2(CLK_TOP_NFI_BUS, CLK_TOP_AXIBUS_SEL, 2),
+ GATE_TOP2(CLK_TOP_GCE, CLK_TOP_AXIBUS_SEL, 4),
+ GATE_TOP2(CLK_TOP_TRNG, CLK_TOP_AXIBUS_SEL, 5),
+ GATE_TOP2(CLK_TOP_PWM_B, CLK_TOP_PWM_SEL, 8),
+ GATE_TOP2(CLK_TOP_PWM1_FB, CLK_TOP_PWM_SEL, 9),
+ GATE_TOP2(CLK_TOP_PWM2_FB, CLK_TOP_PWM_SEL, 10),
+ GATE_TOP2(CLK_TOP_PWM3_FB, CLK_TOP_PWM_SEL, 11),
+ GATE_TOP2(CLK_TOP_PWM4_FB, CLK_TOP_PWM_SEL, 12),
+ GATE_TOP2(CLK_TOP_PWM5_FB, CLK_TOP_PWM_SEL, 13),
+ GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, CLK_TOP_AXIBUS_SEL, 15),
+ GATE_TOP2(CLK_TOP_CQDMA, CLK_TOP_AXIBUS_SEL, 17),
+ GATE_TOP2(CLK_TOP_66M_ETH, CLK_TOP_AXIBUS_SEL, 19),
+ GATE_TOP2(CLK_TOP_133M_ETH, CLK_TOP_AXIBUS_SEL, 20),
+ GATE_TOP2(CLK_TOP_FLASHIF_AXI, CLK_TOP_SPI1_SEL, 23),
+ GATE_TOP2(CLK_TOP_USBIF, CLK_TOP_AXIBUS_SEL, 24),
+ GATE_TOP2(CLK_TOP_UART2, CLK_TOP_RG_UART2, 25),
+ GATE_TOP2(CLK_TOP_GCPU_B, CLK_TOP_AXIBUS_SEL, 27),
+ GATE_TOP2_I(CLK_TOP_MSDC0_B, CLK_TOP_MSDC0, 28),
+ GATE_TOP2_I(CLK_TOP_MSDC1_B, CLK_TOP_MSDC1, 29),
+ GATE_TOP2_I(CLK_TOP_MSDC2_B, CLK_TOP_MSDC2, 30),
+ GATE_TOP2(CLK_TOP_USB_B, CLK_TOP_USB_SEL, 31),
+ /* TOP3 */
+ GATE_TOP3(CLK_TOP_APLL12_DIV0, CLK_TOP_APLL12_CK_DIV0, 0),
+ GATE_TOP3(CLK_TOP_APLL12_DIV3, CLK_TOP_APLL12_CK_DIV3, 3),
+ GATE_TOP3(CLK_TOP_APLL12_DIV4, CLK_TOP_APLL12_CK_DIV4, 4),
+ GATE_TOP3(CLK_TOP_APLL12_DIV6, CLK_TOP_APLL12_CK_DIV6, 8),
+ /* TOP4 */
+ GATE_TOP4(CLK_TOP_SPINOR, CLK_TOP_SPINOR_SEL, 0),
+ GATE_TOP4(CLK_TOP_MSDC2, CLK_TOP_MSDC2_SEL, 1),
+ GATE_TOP4(CLK_TOP_ETH, CLK_TOP_ETH_SEL, 2),
+ GATE_TOP4(CLK_TOP_AUD1, CLK_TOP_AUD1_SEL, 8),
+ GATE_TOP4(CLK_TOP_AUD2, CLK_TOP_AUD2_SEL, 9),
+ GATE_TOP4(CLK_TOP_I2C, CLK_TOP_I2C_SEL, 12),
+ GATE_TOP4(CLK_TOP_PWM_INFRA, CLK_TOP_PWM_SEL, 13),
+ GATE_TOP4(CLK_TOP_AUD_SPDIF_IN, CLK_TOP_AUD_SPDIFIN_SEL, 14),
+ GATE_TOP4(CLK_TOP_RG_UART2, CLK_TOP_UART2_SEL, 15),
+ GATE_TOP4(CLK_TOP_DBG_AT, CLK_TOP_DBG_ATCLK_SEL, 17),
+ /* TOP5 */
+ GATE_TOP5_I(CLK_TOP_IMGRZ_SYS, CLK_TOP_IMGRZ_SYS_SEL, 0),
+ GATE_TOP5_I(CLK_TOP_PNG_SYS, CLK_TOP_PNG_SYS_SEL, 1),
+ GATE_TOP5_I(CLK_TOP_GRAPH_E, CLK_TOP_GRAPH_ECLK_SEL, 2),
+ GATE_TOP5_I(CLK_TOP_FDBI, CLK_TOP_FDBI_SEL, 3),
+ GATE_TOP5_I(CLK_TOP_FAUDIO, CLK_TOP_FAUDIO_SEL, 4),
+ GATE_TOP5_I(CLK_TOP_FAUD_INTBUS, CLK_TOP_FAUD_INTBUS_SEL, 5),
+ GATE_TOP5_I(CLK_TOP_HAPLL1, CLK_TOP_HAPLL1_SEL, 6),
+ GATE_TOP5_I(CLK_TOP_HAPLL2, CLK_TOP_HAPLL2_SEL, 7),
+ GATE_TOP5_I(CLK_TOP_FA2SYS, CLK_TOP_FA2SYS_SEL, 8),
+ GATE_TOP5_I(CLK_TOP_FA1SYS, CLK_TOP_FA1SYS_SEL, 9),
+ GATE_TOP5_I(CLK_TOP_FASM_L, CLK_TOP_FASM_L_SEL, 10),
+ GATE_TOP5_I(CLK_TOP_FASM_M, CLK_TOP_FASM_M_SEL, 11),
+ GATE_TOP5_I(CLK_TOP_FASM_H, CLK_TOP_FASM_H_SEL, 12),
+ GATE_TOP5_I(CLK_TOP_FECC, CLK_TOP_FECC_CK_SEL, 23),
+ GATE_TOP5_I(CLK_TOP_PE2_MAC, CLK_TOP_PE2_MAC_SEL, 24),
+ GATE_TOP5_I(CLK_TOP_CMSYS, CLK_TOP_CMSYS_SEL, 25),
+ GATE_TOP5_I(CLK_TOP_GCPU, CLK_TOP_GCPU_SEL, 26),
+ GATE_TOP5(CLK_TOP_SPIS, CLK_TOP_SPIS_CK_SEL, 27),
+ /* TOP6 */
+ GATE_TOP6(CLK_TOP_I2C3, CLK_TOP_AHB_INFRA_D2, 0),
+ GATE_TOP6(CLK_TOP_SPI_SLV_B, CLK_TOP_SPIS_CK_SEL, 1),
+ GATE_TOP6(CLK_TOP_SPI_SLV_BUS, CLK_TOP_AXIBUS_SEL, 2),
+ GATE_TOP6(CLK_TOP_PCIE_MAC_BUS, CLK_TOP_AXIBUS_SEL, 3),
+ GATE_TOP6(CLK_TOP_CMSYS_BUS, CLK_TOP_AXIBUS_SEL, 4),
+ GATE_TOP6(CLK_TOP_ECC_B, CLK_TOP_AXIBUS_SEL, 5),
+ GATE_TOP6(CLK_TOP_PCIE_PHY_BUS, CLK_TOP_CLK26M, 6),
+ GATE_TOP6(CLK_TOP_PCIE_AUX, CLK_TOP_CLK26M, 7),
+ /* TOP7 */
+ GATE_TOP7(CLK_TOP_DISP_DPI, CLK_TOP_DISP_DPI_CK_SEL, 0),
+};
+
+static const struct mtk_clk_tree mt8518_clk_tree = {
+ .xtal_rate = 26 * MHZ,
+ .xtal2_rate = 26 * MHZ,
+ .fdivs_offs = CLK_TOP_DMPLL,
+ .muxes_offs = CLK_TOP_UART0_SEL,
+ .plls = apmixed_plls,
+ .fclks = top_fixed_clks,
+ .fdivs = top_fixed_divs,
+ .muxes = top_muxes,
+};
+
+static int mt8518_apmixedsys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_init(dev, &mt8518_clk_tree);
+}
+
+static int mt8518_topckgen_probe(struct udevice *dev)
+{
+ return mtk_common_clk_init(dev, &mt8518_clk_tree);
+}
+
+static int mt8518_topckgen_cg_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt8518_clk_tree, top_clks);
+}
+
+static const struct udevice_id mt8518_apmixed_compat[] = {
+ { .compatible = "mediatek,mt8518-apmixedsys", },
+ { }
+};
+
+static const struct udevice_id mt8518_topckgen_compat[] = {
+ { .compatible = "mediatek,mt8518-topckgen", },
+ { }
+};
+
+static const struct udevice_id mt8518_topckgen_cg_compat[] = {
+ { .compatible = "mediatek,mt8518-topckgen-cg", },
+ { }
+};
+
+U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+ .name = "mt8518-apmixedsys",
+ .id = UCLASS_CLK,
+ .of_match = mt8518_apmixed_compat,
+ .probe = mt8518_apmixedsys_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_apmixedsys_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen) = {
+ .name = "mt8518-topckgen",
+ .id = UCLASS_CLK,
+ .of_match = mt8518_topckgen_compat,
+ .probe = mt8518_topckgen_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_topckgen_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
+ .name = "mt8518-topckgen-cg",
+ .id = UCLASS_CLK,
+ .of_match = mt8518_topckgen_cg_compat,
+ .probe = mt8518_topckgen_cg_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c
index e9e55c9..a974744 100644
--- a/drivers/core/regmap.c
+++ b/drivers/core/regmap.c
@@ -134,7 +134,7 @@
ret = init_range(node, map->ranges, addr_len, size_len, index);
if (ret)
- return ret;
+ goto err;
if (ofnode_read_bool(node, "little-endian"))
map->endianness = REGMAP_LITTLE_ENDIAN;
@@ -147,6 +147,10 @@
*mapp = map;
+ return 0;
+err:
+ regmap_uninit(map);
+
return ret;
}
@@ -158,6 +162,7 @@
int addr_len, size_len, both_len;
int len;
int index;
+ int ret;
addr_len = ofnode_read_simple_addr_cells(ofnode_get_parent(node));
if (addr_len < 0) {
@@ -200,10 +205,9 @@
for (range = map->ranges, index = 0; count > 0;
count--, range++, index++) {
- int ret = init_range(node, range, addr_len, size_len, index);
-
+ ret = init_range(node, range, addr_len, size_len, index);
if (ret)
- return ret;
+ goto err;
}
if (ofnode_read_bool(node, "little-endian"))
@@ -218,6 +222,10 @@
*mapp = map;
return 0;
+err:
+ regmap_uninit(map);
+
+ return ret;
}
#endif
diff --git a/drivers/mmc/davinci_mmc.c b/drivers/mmc/davinci_mmc.c
index 0d63279..c3f7b57 100644
--- a/drivers/mmc/davinci_mmc.c
+++ b/drivers/mmc/davinci_mmc.c
@@ -26,22 +26,12 @@
#define clear_bit(addr, val) set_val((addr), (get_val(addr) & ~(val)))
#ifdef CONFIG_DM_MMC
-struct davinci_of_data {
- const char *name;
- u8 version;
-};
-
/* Davinci MMC board definitions */
struct davinci_mmc_priv {
struct davinci_mmc_regs *reg_base; /* Register base address */
uint input_clk; /* Input clock to MMC controller */
- uint version; /* MMC Controller version */
struct gpio_desc cd_gpio; /* Card Detect GPIO */
struct gpio_desc wp_gpio; /* Write Protect GPIO */
-};
-
-struct davinci_mmc_plat
-{
struct mmc_config cfg;
struct mmc mmc;
};
@@ -173,7 +163,7 @@
/* Clear status registers */
mmcstatus = get_val(®s->mmcst0);
- fifo_words = (host->version == MMC_CTLR_VERSION_2) ? 16 : 8;
+ fifo_words = 16;
fifo_bytes = fifo_words << 2;
/* Wait for any previous busy signal to be cleared */
@@ -211,8 +201,7 @@
set_val(®s->mmcfifoctl,
(MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST));
- if (host->version == MMC_CTLR_VERSION_2)
- cmddata |= MMCCMD_DMATRIG;
+ cmddata |= MMCCMD_DMATRIG;
cmddata |= MMCCMD_WDATX;
if (data->flags == MMC_DATA_READ) {
@@ -491,21 +480,18 @@
static int davinci_mmc_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct davinci_mmc_plat *plat = dev_get_platdata(dev);
struct davinci_mmc_priv *priv = dev_get_priv(dev);
- struct mmc_config *cfg = &plat->cfg;
- struct davinci_of_data *data =
- (struct davinci_of_data *)dev_get_driver_data(dev);
+ struct mmc_config *cfg = &priv->cfg;
+#ifdef CONFIG_SPL_BUILD
+ int ret;
+#endif
+
cfg->f_min = 200000;
cfg->f_max = 25000000;
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
cfg->host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
cfg->b_max = DAVINCI_MAX_BLOCKS;
-
- if (data) {
- cfg->name = data->name;
- priv->version = data->version;
- }
+ cfg->name = "da830-mmc";
priv->reg_base = (struct davinci_mmc_regs *)dev_read_addr(dev);
priv->input_clk = clk_get(DAVINCI_MMCSD_CLKID);
@@ -516,40 +502,34 @@
gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
#endif
- upriv->mmc = &plat->mmc;
+ upriv->mmc = &priv->mmc;
+
+#ifdef CONFIG_SPL_BUILD
+ /*
+ * FIXME This is a temporary workaround to enable the driver model in
+ * SPL on omapl138-lcdk. For some reason the bind() callback is not
+ * being called in SPL for MMC which breaks the mmc boot - the hack
+ * is to call mmc_bind() from probe(). We also don't have full DT
+ * support in SPL, hence the hard-coded base register address.
+ */
+ priv->reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE;
+ ret = mmc_bind(dev, &priv->mmc, &priv->cfg);
+ if (ret)
+ return ret;
+#endif
return davinci_dm_mmc_init(dev);
}
static int davinci_mmc_bind(struct udevice *dev)
{
- struct davinci_mmc_plat *plat = dev_get_platdata(dev);
+ struct davinci_mmc_priv *priv = dev_get_priv(dev);
- return mmc_bind(dev, &plat->mmc, &plat->cfg);
+ return mmc_bind(dev, &priv->mmc, &priv->cfg);
}
-
-const struct davinci_of_data davinci_mmc_host_info[] = {
- {
- .name = "dm6441-mmc",
- .version = MMC_CTLR_VERSION_1,
- },
- {
- .name = "da830-mmc",
- .version = MMC_CTLR_VERSION_2,
- },
- {},
-};
-
static const struct udevice_id davinci_mmc_ids[] = {
- {
- .compatible = "ti,dm6441-mmc",
- .data = (ulong) &davinci_mmc_host_info[MMC_CTLR_VERSION_1]
- },
- {
- .compatible = "ti,da830-mmc",
- .data = (ulong) &davinci_mmc_host_info[MMC_CTLR_VERSION_2]
- },
+ { .compatible = "ti,da830-mmc" },
{},
};
@@ -562,7 +542,6 @@
#endif
.probe = davinci_mmc_probe,
.ops = &davinci_mmc_ops,
- .platdata_auto_alloc_size = sizeof(struct davinci_mmc_plat),
.priv_auto_alloc_size = sizeof(struct davinci_mmc_priv),
};
#endif
diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index ffd647f..eaa584a 100644
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c
@@ -125,6 +125,9 @@
#define MSDC_PAD_TUNE_DATWRDLY_M 0x1f
#define MSDC_PAD_TUNE_DATWRDLY_S 0
+#define PAD_CMD_TUNE_RX_DLY3 0x3E
+#define PAD_CMD_TUNE_RX_DLY3_S 1
+
/* EMMC50_CFG0 */
#define EMMC50_CFG_CFCSTS_SEL BIT(4)
@@ -209,7 +212,8 @@
u32 eco_ver;
u32 reserved6[27];
u32 pad_ds_tune;
- u32 reserved7[31];
+ u32 pad_cmd_tune;
+ u32 reserved7[30];
u32 emmc50_cfg0;
u32 reserved8[7];
u32 sdc_fifo_cfg;
@@ -240,6 +244,7 @@
struct msdc_tune_para {
u32 iocon;
u32 pad_tune;
+ u32 pad_cmd_tune;
};
struct msdc_host {
@@ -364,6 +369,8 @@
case MMC_CMD_WRITE_SINGLE_BLOCK:
case MMC_CMD_READ_SINGLE_BLOCK:
case SD_CMD_APP_SEND_SCR:
+ case MMC_CMD_SEND_TUNING_BLOCK:
+ case MMC_CMD_SEND_TUNING_BLOCK_HS200:
dtype = 1;
break;
case SD_CMD_SWITCH_FUNC: /* same as MMC_CMD_SWITCH */
@@ -469,6 +476,14 @@
if (!msdc_cmd_is_ready(host))
return -EIO;
+ if ((readl(&host->base->msdc_fifocs) &
+ MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S ||
+ (readl(&host->base->msdc_fifocs) &
+ MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S) {
+ pr_err("TX/RX FIFO non-empty before start of IO. Reset\n");
+ msdc_reset_hw(host);
+ }
+
msdc_fifo_clr(host);
host->last_resp_type = cmd->resp_type;
@@ -652,14 +667,22 @@
struct mmc_data *data)
{
struct msdc_host *host = dev_get_priv(dev);
- int ret;
+ int cmd_ret, data_ret;
- ret = msdc_start_command(host, cmd, data);
- if (ret)
- return ret;
+ cmd_ret = msdc_start_command(host, cmd, data);
+ if (cmd_ret &&
+ !(cmd_ret == -EIO &&
+ (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
+ cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)))
+ return cmd_ret;
- if (data)
- return msdc_start_data(host, data);
+ if (data) {
+ data_ret = msdc_start_data(host, data);
+ if (cmd_ret)
+ return cmd_ret;
+ else
+ return data_ret;
+ }
return 0;
}
@@ -941,6 +964,56 @@
return delay_phase;
}
+static int hs400_tune_response(struct udevice *dev, u32 opcode)
+{
+ struct msdc_plat *plat = dev_get_platdata(dev);
+ struct msdc_host *host = dev_get_priv(dev);
+ struct mmc *mmc = &plat->mmc;
+ u32 cmd_delay = 0;
+ struct msdc_delay_phase final_cmd_delay = { 0, };
+ u8 final_delay;
+ void __iomem *tune_reg = &host->base->pad_cmd_tune;
+ int cmd_err;
+ int i, j;
+
+ setbits_le32(&host->base->pad_cmd_tune, BIT(0));
+
+ if (mmc->selected_mode == MMC_HS_200 ||
+ mmc->selected_mode == UHS_SDR104)
+ clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
+ host->hs200_cmd_int_delay <<
+ MSDC_PAD_TUNE_CMDRRDLY_S);
+
+ if (host->r_smpl)
+ clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
+ else
+ setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
+
+ for (i = 0; i < PAD_DELAY_MAX; i++) {
+ clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
+ i << PAD_CMD_TUNE_RX_DLY3_S);
+
+ for (j = 0; j < 3; j++) {
+ mmc_send_tuning(mmc, opcode, &cmd_err);
+ if (!cmd_err) {
+ cmd_delay |= (1 << i);
+ } else {
+ cmd_delay &= ~(1 << i);
+ break;
+ }
+ }
+ }
+
+ final_cmd_delay = get_best_delay(host, cmd_delay);
+ clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
+ final_cmd_delay.final_phase <<
+ PAD_CMD_TUNE_RX_DLY3_S);
+ final_delay = final_cmd_delay.final_phase;
+
+ dev_err(dev, "Final cmd pad delay: %x\n", final_delay);
+ return final_delay == 0xff ? -EIO : 0;
+}
+
static int msdc_tune_response(struct udevice *dev, u32 opcode)
{
struct msdc_plat *plat = dev_get_platdata(dev);
@@ -1132,34 +1205,138 @@
return final_delay == 0xff ? -EIO : 0;
}
+/*
+ * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
+ * together, which can save the tuning time.
+ */
+static int msdc_tune_together(struct udevice *dev, u32 opcode)
+{
+ struct msdc_plat *plat = dev_get_platdata(dev);
+ struct msdc_host *host = dev_get_priv(dev);
+ struct mmc *mmc = &plat->mmc;
+ u32 rise_delay = 0, fall_delay = 0;
+ struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
+ u8 final_delay, final_maxlen;
+ void __iomem *tune_reg = &host->base->pad_tune;
+ int i, ret;
+
+ if (host->dev_comp->pad_tune0)
+ tune_reg = &host->base->pad_tune0;
+
+ clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
+ clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
+
+ for (i = 0; i < PAD_DELAY_MAX; i++) {
+ clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
+ i << MSDC_PAD_TUNE_CMDRDLY_S);
+ clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
+ i << MSDC_PAD_TUNE_DATRRDLY_S);
+
+ ret = mmc_send_tuning(mmc, opcode, NULL);
+ if (!ret)
+ rise_delay |= (1 << i);
+ }
+
+ final_rise_delay = get_best_delay(host, rise_delay);
+ if (final_rise_delay.maxlen >= 12 ||
+ (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
+ goto skip_fall;
+
+ setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
+ setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
+
+ for (i = 0; i < PAD_DELAY_MAX; i++) {
+ clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
+ i << MSDC_PAD_TUNE_CMDRDLY_S);
+ clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
+ i << MSDC_PAD_TUNE_DATRRDLY_S);
+
+ ret = mmc_send_tuning(mmc, opcode, NULL);
+ if (!ret)
+ fall_delay |= (1 << i);
+ }
+
+ final_fall_delay = get_best_delay(host, fall_delay);
+
+skip_fall:
+ final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
+ if (final_maxlen == final_rise_delay.maxlen) {
+ clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
+ clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
+ clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
+ final_rise_delay.final_phase <<
+ MSDC_PAD_TUNE_CMDRDLY_S);
+ clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
+ final_rise_delay.final_phase <<
+ MSDC_PAD_TUNE_DATRRDLY_S);
+ final_delay = final_rise_delay.final_phase;
+ } else {
+ setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
+ setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
+ clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
+ final_fall_delay.final_phase <<
+ MSDC_PAD_TUNE_CMDRDLY_S);
+ clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
+ final_fall_delay.final_phase <<
+ MSDC_PAD_TUNE_DATRRDLY_S);
+ final_delay = final_fall_delay.final_phase;
+ }
+
+ dev_err(dev, "Final pad delay: %x\n", final_delay);
+
+ return final_delay == 0xff ? -EIO : 0;
+}
+
static int msdc_execute_tuning(struct udevice *dev, uint opcode)
{
struct msdc_plat *plat = dev_get_platdata(dev);
struct msdc_host *host = dev_get_priv(dev);
struct mmc *mmc = &plat->mmc;
- int ret;
+ int ret = 0;
+
+ if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
+ ret = msdc_tune_together(dev, opcode);
+ if (ret == -EIO) {
+ dev_err(dev, "Tune fail!\n");
+ return ret;
+ }
+
+ if (mmc->selected_mode == MMC_HS_400) {
+ clrbits_le32(&host->base->msdc_iocon,
+ MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
+ clrsetbits_le32(&host->base->pad_tune,
+ MSDC_PAD_TUNE_DATRRDLY_M, 0);
- if (mmc->selected_mode == MMC_HS_400) {
- writel(host->hs400_ds_delay, &host->base->pad_ds_tune);
- /* for hs400 mode it must be set to 0 */
- clrbits_le32(&host->base->patch_bit2, MSDC_PB2_CFGCRCSTS);
- host->hs400_mode = true;
+ writel(host->hs400_ds_delay, &host->base->pad_ds_tune);
+ /* for hs400 mode it must be set to 0 */
+ clrbits_le32(&host->base->patch_bit2,
+ MSDC_PB2_CFGCRCSTS);
+ host->hs400_mode = true;
+ }
+ goto tune_done;
}
- ret = msdc_tune_response(dev, opcode);
+ if (mmc->selected_mode == MMC_HS_400)
+ ret = hs400_tune_response(dev, opcode);
+ else
+ ret = msdc_tune_response(dev, opcode);
if (ret == -EIO) {
dev_err(dev, "Tune response fail!\n");
return ret;
}
- if (!host->hs400_mode) {
+ if (mmc->selected_mode != MMC_HS_400) {
ret = msdc_tune_data(dev, opcode);
- if (ret == -EIO)
+ if (ret == -EIO) {
dev_err(dev, "Tune data fail!\n");
+ return ret;
+ }
}
+tune_done:
host->saved_tune_para.iocon = readl(&host->base->msdc_iocon);
host->saved_tune_para.pad_tune = readl(&host->base->pad_tune);
+ host->saved_tune_para.pad_cmd_tune = readl(&host->base->pad_cmd_tune);
return ret;
}
diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c
index 89ac822..dd04d67 100644
--- a/drivers/mtd/mtdcore.c
+++ b/drivers/mtd/mtdcore.c
@@ -76,8 +76,6 @@
.resume = mtd_cls_resume,
};
#else
-struct mtd_info *mtd_table[MAX_MTD_DEVICES];
-
#define MAX_IDR_ID 64
struct idr_layer {
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 30bd8e7..bcea8a0 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -100,6 +100,28 @@
config PHY_CORTINA
bool "Cortina Ethernet PHYs support"
+choice
+ prompt "Location of the Cortina firmware"
+ default SYS_CORTINA_FW_IN_NOR
+ depends on PHY_CORTINA
+
+config SYS_CORTINA_FW_IN_MMC
+ bool "Cortina firmware in MMC"
+
+config SYS_CORTINA_FW_IN_NAND
+ bool "Cortina firmware in NAND flash"
+
+config SYS_CORTINA_FW_IN_NOR
+ bool "Cortina firmware in NOR flash"
+
+config SYS_CORTINA_FW_IN_REMOTE
+ bool "Cortina firmware in remote device"
+
+config SYS_CORTINA_FW_IN_SPIFLASH
+ bool "Cortina firmware in SPI flash"
+
+endchoice
+
config PHY_DAVICOM
bool "Davicom Ethernet PHYs support"
diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c
index 93d5361..5762562 100644
--- a/drivers/net/ti/cpsw.c
+++ b/drivers/net/ti/cpsw.c
@@ -1224,6 +1224,9 @@
int ret;
data = calloc(1, sizeof(struct cpsw_platform_data));
+ if (!data)
+ return -ENOMEM;
+
pdata->priv_pdata = data;
pdata->iobase = dev_read_addr(dev);
data->version = CPSW_CTRL_VERSION_2;
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 219473a..da8b826 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -4,12 +4,12 @@
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
ifneq ($(CONFIG_DM_PCI),)
-obj-y += pci_rom.o
+obj-$(CONFIG_DM_VIDEO) += pci_rom.o
obj-$(CONFIG_PCI) += pci-uclass.o pci_auto.o
obj-$(CONFIG_DM_PCI_COMPAT) += pci_compat.o
obj-$(CONFIG_PCI_SANDBOX) += pci_sandbox.o
obj-$(CONFIG_SANDBOX) += pci-emul-uclass.o
-obj-$(CONFIG_X86) += pci_x86.o
+obj-$(CONFIG_X86) += pci_x86.o pci_rom.o
else
obj-$(CONFIG_PCI) += pci.o pci_auto_old.o
endif
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 9930ca1..22ee623 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -16,4 +16,8 @@
bool "MT8516 SoC pinctrl driver"
select PINCTRL_MTK
+config PINCTRL_MT8518
+ bool "MT8518 SoC pinctrl driver"
+ select PINCTRL_MTK
+
endif
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
index c4f2908..0ab7b15 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -6,3 +6,4 @@
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
+obj-$(CONFIG_PINCTRL_MT8518) += pinctrl-mt8518.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8518.c b/drivers/pinctrl/mediatek/pinctrl-mt8518.c
new file mode 100644
index 0000000..8d2cd94
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8518.c
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ */
+
+#include <dm.h>
+
+#include "pinctrl-mtk-common.h"
+
+#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 16, false)
+
+static const struct mtk_pin_field_calc mt8518_pin_mode_range[] = {
+ PIN_FIELD_CALC(0, 119, 0x300, 0x10, 0, 3, 15, false),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_dir_range[] = {
+ PIN_FIELD(0, 119, 0x0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_di_range[] = {
+ PIN_FIELD(0, 119, 0x200, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_do_range[] = {
+ PIN_FIELD(0, 119, 0x100, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_ies_range[] = {
+ PIN_FIELD(0, 2, 0x900, 0x10, 0, 1),
+ PIN_FIELD(3, 3, 0x920, 0x10, 9, 1),
+ PIN_FIELD(4, 4, 0x920, 0x10, 8, 1),
+ PIN_FIELD(5, 5, 0x920, 0x10, 7, 1),
+ PIN_FIELD(6, 6, 0x920, 0x10, 6, 1),
+ PIN_FIELD(7, 7, 0x920, 0x10, 10, 1),
+ PIN_FIELD(8, 8, 0x920, 0x10, 1, 1),
+ PIN_FIELD(9, 9, 0x920, 0x10, 0, 1),
+ PIN_FIELD(10, 10, 0x920, 0x10, 5, 1),
+ PIN_FIELD(11, 11, 0x920, 0x10, 4, 1),
+ PIN_FIELD(12, 12, 0x920, 0x10, 3, 1),
+ PIN_FIELD(13, 13, 0x920, 0x10, 2, 1),
+ PIN_FIELD(14, 14, 0x900, 0x10, 1, 1),
+ PIN_FIELD(15, 15, 0x900, 0x10, 2, 1),
+ PIN_FIELD(16, 16, 0x900, 0x10, 3, 1),
+ PIN_FIELD(17, 20, 0x900, 0x10, 4, 1),
+ PIN_FIELD(21, 22, 0x900, 0x10, 5, 1),
+ PIN_FIELD(23, 27, 0x910, 0x10, 15, 1),
+ PIN_FIELD(28, 28, 0x900, 0x10, 6, 1),
+ PIN_FIELD(29, 29, 0x930, 0x10, 2, 1),
+ PIN_FIELD(30, 30, 0x930, 0x10, 1, 1),
+ PIN_FIELD(31, 31, 0x930, 0x10, 6, 1),
+ PIN_FIELD(32, 32, 0x930, 0x10, 5, 1),
+ PIN_FIELD(33, 33, 0x930, 0x10, 4, 1),
+ PIN_FIELD(34, 35, 0x930, 0x10, 3, 1),
+ PIN_FIELD(36, 39, 0x900, 0x10, 7, 1),
+ PIN_FIELD(40, 41, 0x900, 0x10, 8, 1),
+ PIN_FIELD(42, 44, 0x900, 0x10, 9, 1),
+ PIN_FIELD(45, 47, 0x900, 0x10, 10, 1),
+ PIN_FIELD(48, 51, 0x900, 0x10, 11, 1),
+ PIN_FIELD(52, 55, 0x900, 0x10, 12, 1),
+ PIN_FIELD(56, 56, 0x900, 0x10, 13, 1),
+ PIN_FIELD(57, 57, 0x900, 0x10, 14, 1),
+ PIN_FIELD(58, 58, 0x900, 0x10, 15, 1),
+ PIN_FIELD(59, 60, 0x910, 0x10, 0, 1),
+
+ PIN_FIELD(61, 61, 0x910, 0x10, 1, 1),
+ PIN_FIELD(62, 62, 0x910, 0x10, 2, 1),
+ PIN_FIELD(63, 69, 0x910, 0x10, 3, 1),
+ PIN_FIELD(70, 70, 0x910, 0x10, 4, 1),
+ PIN_FIELD(71, 76, 0x910, 0x10, 5, 1),
+ PIN_FIELD(77, 80, 0x910, 0x10, 6, 1),
+ PIN_FIELD(81, 87, 0x910, 0x10, 7, 1),
+ PIN_FIELD(88, 97, 0x910, 0x10, 8, 1),
+ PIN_FIELD(98, 103, 0x910, 0x10, 9, 1),
+ PIN_FIELD(104, 107, 0x910, 0x10, 10, 1),
+ PIN_FIELD(108, 109, 0x910, 0x10, 11, 1),
+ PIN_FIELD(110, 111, 0x910, 0x10, 12, 1),
+ PIN_FIELD(112, 113, 0x910, 0x10, 13, 1),
+ PIN_FIELD(114, 114, 0x920, 0x10, 12, 1),
+ PIN_FIELD(115, 115, 0x920, 0x10, 11, 1),
+ PIN_FIELD(116, 116, 0x930, 0x10, 0, 1),
+ PIN_FIELD(117, 117, 0x920, 0x10, 15, 1),
+ PIN_FIELD(118, 118, 0x920, 0x10, 14, 1),
+ PIN_FIELD(119, 119, 0x920, 0x10, 13, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_smt_range[] = {
+ PIN_FIELD(0, 2, 0xA00, 0x10, 0, 1),
+ PIN_FIELD(3, 3, 0xA20, 0x10, 9, 1),
+ PIN_FIELD(4, 4, 0xA20, 0x10, 8, 1),
+ PIN_FIELD(5, 5, 0xA20, 0x10, 7, 1),
+ PIN_FIELD(6, 6, 0xA20, 0x10, 6, 1),
+ PIN_FIELD(7, 7, 0xA20, 0x10, 10, 1),
+ PIN_FIELD(8, 8, 0xA20, 0x10, 1, 1),
+ PIN_FIELD(9, 9, 0xA20, 0x10, 0, 1),
+ PIN_FIELD(10, 10, 0xA20, 0x10, 5, 1),
+ PIN_FIELD(11, 11, 0xA20, 0x10, 4, 1),
+ PIN_FIELD(12, 12, 0xA20, 0x10, 3, 1),
+ PIN_FIELD(13, 13, 0xA20, 0x10, 2, 1),
+ PIN_FIELD(14, 14, 0xA00, 0x10, 1, 1),
+ PIN_FIELD(15, 15, 0xA00, 0x10, 2, 1),
+ PIN_FIELD(16, 16, 0xA00, 0x10, 3, 1),
+ PIN_FIELD(17, 20, 0xA00, 0x10, 4, 1),
+ PIN_FIELD(21, 22, 0xA00, 0x10, 5, 1),
+ PIN_FIELD(23, 27, 0xA10, 0x10, 15, 1),
+ PIN_FIELD(28, 28, 0xA00, 0x10, 6, 1),
+ PIN_FIELD(29, 29, 0xA30, 0x10, 2, 1),
+ PIN_FIELD(30, 30, 0xA30, 0x10, 1, 1),
+ PIN_FIELD(31, 31, 0xA30, 0x10, 6, 1),
+ PIN_FIELD(32, 32, 0xA30, 0x10, 5, 1),
+ PIN_FIELD(33, 33, 0xA30, 0x10, 4, 1),
+ PIN_FIELD(34, 35, 0xA30, 0x10, 3, 1),
+ PIN_FIELD(36, 39, 0xA00, 0x10, 7, 1),
+ PIN_FIELD(40, 41, 0xA00, 0x10, 8, 1),
+ PIN_FIELD(42, 44, 0xA00, 0x10, 9, 1),
+ PIN_FIELD(45, 47, 0xA00, 0x10, 10, 1),
+ PIN_FIELD(48, 51, 0xA00, 0x10, 11, 1),
+ PIN_FIELD(52, 55, 0xA00, 0x10, 12, 1),
+ PIN_FIELD(56, 56, 0xA00, 0x10, 13, 1),
+ PIN_FIELD(57, 57, 0xA00, 0x10, 14, 1),
+ PIN_FIELD(58, 58, 0xA00, 0x10, 15, 1),
+ PIN_FIELD(59, 60, 0xA10, 0x10, 0, 1),
+
+ PIN_FIELD(61, 61, 0xA10, 0x10, 1, 1),
+ PIN_FIELD(62, 62, 0xA10, 0x10, 2, 1),
+ PIN_FIELD(63, 69, 0xA10, 0x10, 3, 1),
+ PIN_FIELD(70, 70, 0xA10, 0x10, 4, 1),
+ PIN_FIELD(71, 76, 0xA10, 0x10, 5, 1),
+ PIN_FIELD(77, 80, 0xA10, 0x10, 6, 1),
+ PIN_FIELD(81, 87, 0xA10, 0x10, 7, 1),
+ PIN_FIELD(88, 97, 0xA10, 0x10, 8, 1),
+ PIN_FIELD(98, 103, 0xA10, 0x10, 9, 1),
+ PIN_FIELD(104, 107, 0xA10, 0x10, 10, 1),
+ PIN_FIELD(108, 109, 0xA10, 0x10, 11, 1),
+ PIN_FIELD(110, 111, 0xA10, 0x10, 12, 1),
+ PIN_FIELD(112, 113, 0xA10, 0x10, 13, 1),
+ PIN_FIELD(114, 114, 0xA20, 0x10, 12, 1),
+ PIN_FIELD(115, 115, 0xA20, 0x10, 11, 1),
+ PIN_FIELD(116, 116, 0xA30, 0x10, 0, 1),
+ PIN_FIELD(117, 117, 0xA20, 0x10, 15, 1),
+ PIN_FIELD(118, 118, 0xA20, 0x10, 14, 1),
+ PIN_FIELD(119, 119, 0xA20, 0x10, 13, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_pullen_range[] = {
+ PIN_FIELD(14, 15, 0x500, 0x10, 14, 1),
+ PIN_FIELD(16, 28, 0x510, 0x10, 0, 1),
+ PIN_FIELD(36, 47, 0x520, 0x10, 4, 1),
+ PIN_FIELD(48, 63, 0x530, 0x10, 0, 1),
+ PIN_FIELD(64, 79, 0x540, 0x10, 0, 1),
+ PIN_FIELD(80, 95, 0x550, 0x10, 0, 1),
+ PIN_FIELD(96, 111, 0x560, 0x10, 0, 1),
+ PIN_FIELD(112, 113, 0x570, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_pullsel_range[] = {
+ PIN_FIELD(14, 15, 0x600, 0x10, 14, 1),
+ PIN_FIELD(16, 28, 0x610, 0x10, 0, 1),
+ PIN_FIELD(36, 47, 0x620, 0x10, 4, 1),
+ PIN_FIELD(48, 63, 0x630, 0x10, 0, 1),
+ PIN_FIELD(64, 79, 0x640, 0x10, 0, 1),
+ PIN_FIELD(80, 95, 0x650, 0x10, 0, 1),
+ PIN_FIELD(96, 111, 0x660, 0x10, 0, 1),
+ PIN_FIELD(112, 113, 0x670, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_drv_range[] = {
+ PIN_FIELD(0, 2, 0xd70, 0x10, 8, 4),
+ PIN_FIELD(3, 6, 0xd70, 0x10, 0, 4),
+ PIN_FIELD(7, 7, 0xd70, 0x10, 4, 4),
+ PIN_FIELD(8, 8, 0xd60, 0x10, 8, 4),
+ PIN_FIELD(9, 9, 0xd60, 0x10, 12, 4),
+ PIN_FIELD(10, 13, 0xd70, 0x10, 0, 4),
+ PIN_FIELD(14, 14, 0xd50, 0x10, 8, 4),
+ PIN_FIELD(15, 15, 0xd20, 0x10, 4, 4),
+ PIN_FIELD(16, 16, 0xd50, 0x10, 8, 4),
+ PIN_FIELD(17, 20, 0xd20, 0x10, 12, 4),
+ PIN_FIELD(23, 27, 0xd30, 0x10, 8, 4),
+ PIN_FIELD(28, 28, 0xd10, 0x10, 0, 4),
+ PIN_FIELD(29, 29, 0xd40, 0x10, 12, 4),
+ PIN_FIELD(30, 30, 0xd50, 0x10, 0, 4),
+ PIN_FIELD(31, 35, 0xd50, 0x10, 4, 4),
+ PIN_FIELD(36, 41, 0xd00, 0x10, 0, 4),
+ PIN_FIELD(42, 47, 0xd00, 0x10, 4, 4),
+ PIN_FIELD(48, 51, 0xd00, 0x10, 8, 4),
+ PIN_FIELD(52, 55, 0xd10, 0x10, 12, 4),
+ PIN_FIELD(56, 56, 0xdb0, 0x10, 4, 4),
+ PIN_FIELD(57, 58, 0xd00, 0x10, 8, 4),
+ PIN_FIELD(59, 62, 0xd00, 0x10, 12, 4),
+ PIN_FIELD(63, 68, 0xd90, 0x10, 12, 4),
+ PIN_FIELD(69, 69, 0xda0, 0x10, 0, 4),
+ PIN_FIELD(70, 70, 0xda0, 0x10, 12, 4),
+ PIN_FIELD(71, 73, 0xd80, 0x10, 12, 4),
+ PIN_FIELD(74, 76, 0xd90, 0x10, 0, 4),
+ PIN_FIELD(77, 80, 0xd20, 0x10, 0, 4),
+ PIN_FIELD(81, 87, 0xd80, 0x10, 8, 4),
+ PIN_FIELD(88, 97, 0xd30, 0x10, 0, 4),
+ PIN_FIELD(98, 103, 0xd10, 0x10, 4, 4),
+ PIN_FIELD(104, 105, 0xd40, 0x10, 8, 4),
+ PIN_FIELD(106, 107, 0xd10, 0x10, 8, 4),
+ PIN_FIELD(114, 114, 0xd50, 0x10, 12, 4),
+ PIN_FIELD(115, 115, 0xd60, 0x10, 0, 4),
+ PIN_FIELD(116, 119, 0xd60, 0x10, 4, 4),
+};
+
+static const struct mtk_pin_reg_calc mt8518_reg_cals[] = {
+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8518_pin_mode_range),
+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8518_pin_dir_range),
+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8518_pin_di_range),
+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8518_pin_do_range),
+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8518_pin_ies_range),
+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8518_pin_smt_range),
+ [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt8518_pin_pullsel_range),
+ [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt8518_pin_pullen_range),
+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8518_pin_drv_range),
+};
+
+static const struct mtk_pin_desc mt8518_pins[] = {
+ MTK_PIN(0, "NFI_NCEB0", DRV_GRP4),
+ MTK_PIN(1, "NFI_NREB", DRV_GRP4),
+ MTK_PIN(2, "NFI_NRNB", DRV_GRP4),
+ MTK_PIN(3, "MSDC0_DAT7", DRV_GRP4),
+ MTK_PIN(4, "MSDC0_DAT6", DRV_GRP4),
+ MTK_PIN(5, "MSDC0_DAT5", DRV_GRP4),
+ MTK_PIN(6, "MSDC0_DAT4", DRV_GRP4),
+ MTK_PIN(7, "MSDC0_RSTB", DRV_GRP4),
+ MTK_PIN(8, "MSDC0_CMD", DRV_GRP4),
+ MTK_PIN(9, "MSDC0_CLK", DRV_GRP4),
+ MTK_PIN(10, "MSDC0_DAT3", DRV_GRP4),
+ MTK_PIN(11, "MSDC0_DAT2", DRV_GRP4),
+ MTK_PIN(12, "MSDC0_DAT1", DRV_GRP4),
+ MTK_PIN(13, "MSDC0_DAT0", DRV_GRP4),
+ MTK_PIN(14, "RTC32K_CK", DRV_GRP2),
+ MTK_PIN(15, "WATCHDOG", DRV_GRP2),
+ MTK_PIN(16, "SUSPEND", DRV_GRP2),
+ MTK_PIN(17, "JTMS", DRV_GRP2),
+ MTK_PIN(18, "JTCK", DRV_GRP2),
+ MTK_PIN(19, "JTDI", DRV_GRP2),
+ MTK_PIN(20, "JTDO", DRV_GRP2),
+ MTK_PIN(21, "SDA3", DRV_GRP2),
+ MTK_PIN(22, "SCL3", DRV_GRP2),
+ MTK_PIN(23, "PWRAP_SPI_CLK", DRV_GRP2),
+ MTK_PIN(24, "PWRAP_SPI_CSN", DRV_GRP2),
+ MTK_PIN(25, "PWRAP_SPI_MOSI", DRV_GRP2),
+ MTK_PIN(26, "PWRAP_SPI_MISO", DRV_GRP2),
+ MTK_PIN(27, "PWRAP_INT", DRV_GRP2),
+ MTK_PIN(28, "EINT22", DRV_GRP2),
+ MTK_PIN(29, "MSDC2_CMD", DRV_GRP4),
+ MTK_PIN(30, "MSDC2_CLK", DRV_GRP4),
+ MTK_PIN(31, "MSDC2_DAT0", DRV_GRP4),
+ MTK_PIN(32, "MSDC2_DAT1", DRV_GRP4),
+ MTK_PIN(33, "MSDC2_DAT2", DRV_GRP4),
+ MTK_PIN(34, "MSDC2_DAT3", DRV_GRP4),
+ MTK_PIN(35, "MSDC2_DS", DRV_GRP4),
+ MTK_PIN(36, "EINT0", DRV_GRP0),
+ MTK_PIN(37, "EINT1", DRV_GRP0),
+ MTK_PIN(38, "EINT2", DRV_GRP0),
+ MTK_PIN(39, "EINT3", DRV_GRP0),
+ MTK_PIN(40, "EINT4", DRV_GRP0),
+ MTK_PIN(41, "EINT5", DRV_GRP0),
+ MTK_PIN(42, "EINT6", DRV_GRP0),
+ MTK_PIN(43, "EINT7", DRV_GRP0),
+ MTK_PIN(44, "EINT8", DRV_GRP0),
+ MTK_PIN(45, "EINT9", DRV_GRP0),
+ MTK_PIN(46, "EINT10", DRV_GRP0),
+ MTK_PIN(47, "EINT11", DRV_GRP0),
+ MTK_PIN(48, "EINT12", DRV_GRP0),
+ MTK_PIN(49, "EINT13", DRV_GRP0),
+ MTK_PIN(50, "EINT14", DRV_GRP0),
+ MTK_PIN(51, "EINT15", DRV_GRP0),
+ MTK_PIN(52, "URXD1", DRV_GRP0),
+ MTK_PIN(53, "UTXD1", DRV_GRP0),
+ MTK_PIN(54, "URTS1", DRV_GRP0),
+ MTK_PIN(55, "UCTS1", DRV_GRP0),
+ MTK_PIN(56, "IR", DRV_GRP0),
+ MTK_PIN(57, "EINT16", DRV_GRP0),
+ MTK_PIN(58, "EINT17", DRV_GRP0),
+ MTK_PIN(59, "EINT18", DRV_GRP0),
+ MTK_PIN(60, "EINT19", DRV_GRP0),
+ MTK_PIN(61, "EINT20", DRV_GRP0),
+ MTK_PIN(62, "EINT21", DRV_GRP0),
+ MTK_PIN(63, "I2SO_MCLK", DRV_GRP0),
+ MTK_PIN(64, "I2SO_BCK", DRV_GRP0),
+ MTK_PIN(65, "I2SO_LRCK", DRV_GRP0),
+ MTK_PIN(66, "I2SO_D0", DRV_GRP0),
+ MTK_PIN(67, "I2SO_D1", DRV_GRP0),
+ MTK_PIN(68, "I2SO_D2", DRV_GRP0),
+ MTK_PIN(69, "I2SO_D3", DRV_GRP0),
+ MTK_PIN(70, "SPDIF_IN0", DRV_GRP0),
+ MTK_PIN(71, "DMIC_CLK0", DRV_GRP0),
+ MTK_PIN(72, "DMIC_CLK1", DRV_GRP0),
+ MTK_PIN(73, "DMIC_DAT0", DRV_GRP0),
+ MTK_PIN(74, "DMIC_DAT1", DRV_GRP0),
+ MTK_PIN(75, "DMIC_DAT2", DRV_GRP0),
+ MTK_PIN(76, "DMIC_DAT3", DRV_GRP0),
+ MTK_PIN(77, "TDM_MCLK", DRV_GRP0),
+ MTK_PIN(78, "TDM_BCK", DRV_GRP0),
+ MTK_PIN(79, "TDM_LRCK", DRV_GRP0),
+ MTK_PIN(80, "TDM_DI", DRV_GRP0),
+ MTK_PIN(81, "I2SIN_D0", DRV_GRP0),
+ MTK_PIN(82, "I2SIN_D1", DRV_GRP0),
+ MTK_PIN(83, "I2SIN_D2", DRV_GRP0),
+ MTK_PIN(84, "I2SIN_D3", DRV_GRP0),
+ MTK_PIN(85, "I2SIN_MCLK", DRV_GRP0),
+ MTK_PIN(86, "I2SIN_BCK", DRV_GRP0),
+ MTK_PIN(87, "I2SIN_LRCK", DRV_GRP0),
+ MTK_PIN(88, "SPI1_CS", DRV_GRP0),
+ MTK_PIN(89, "SPI1_CK", DRV_GRP0),
+ MTK_PIN(90, "SPI1_MI", DRV_GRP0),
+ MTK_PIN(91, "SPI1_MO", DRV_GRP0),
+ MTK_PIN(92, "SPI2_CS", DRV_GRP0),
+ MTK_PIN(93, "SPI2_CK", DRV_GRP0),
+ MTK_PIN(94, "SPI2_MI0", DRV_GRP0),
+ MTK_PIN(95, "SPI2_MI1", DRV_GRP0),
+ MTK_PIN(96, "SPI2_MI2", DRV_GRP0),
+ MTK_PIN(97, "SPI2_MI3", DRV_GRP0),
+ MTK_PIN(98, "SW_RESET_DSP", DRV_GRP0),
+ MTK_PIN(99, "GPIO1", DRV_GRP0),
+ MTK_PIN(100, "GPIO2", DRV_GRP0),
+ MTK_PIN(101, "GPIO3", DRV_GRP0),
+ MTK_PIN(102, "GPIO4", DRV_GRP0),
+ MTK_PIN(103, "RTC32K_DSP", DRV_GRP0),
+ MTK_PIN(104, "URXD0", DRV_GRP2),
+ MTK_PIN(105, "UTXD0", DRV_GRP2),
+ MTK_PIN(106, "URXD2", DRV_GRP2),
+ MTK_PIN(107, "UTXD2", DRV_GRP2),
+ MTK_PIN(108, "SDA1", DRV_GRP4),
+ MTK_PIN(109, "SCL1", DRV_GRP4),
+ MTK_PIN(110, "SDA0", DRV_GRP4),
+ MTK_PIN(111, "SCL0", DRV_GRP4),
+ MTK_PIN(112, "SDA2", DRV_GRP4),
+ MTK_PIN(113, "SCL2", DRV_GRP4),
+ MTK_PIN(114, "MSDC1_CMD", DRV_GRP4),
+ MTK_PIN(115, "MSDC1_CLK", DRV_GRP4),
+ MTK_PIN(116, "MSDC1_DAT0", DRV_GRP4),
+ MTK_PIN(117, "MSDC1_DAT1", DRV_GRP4),
+ MTK_PIN(118, "MSDC1_DAT2", DRV_GRP4),
+ MTK_PIN(119, "MSDC1_DAT3", DRV_GRP4),
+};
+
+/* List all groups consisting of these pins dedicated to the enablement of
+ * certain hardware block and the corresponding mode for all of the pins.
+ * The hardware probably has multiple combinations of these pinouts.
+ */
+
+/* UART */
+static int mt8518_uart0_0_rxd_txd_pins[] = { 104, 105, };
+static int mt8518_uart0_0_rxd_txd_funcs[] = { 1, 1, };
+static int mt8518_uart1_0_rxd_txd_pins[] = { 52, 53, };
+static int mt8518_uart1_0_rxd_txd_funcs[] = { 1, 1, };
+static int mt8518_uart2_0_rxd_txd_pins[] = { 106, 107, };
+static int mt8518_uart2_0_rxd_txd_funcs[] = { 1, 1, };
+
+/* Joint those groups owning the same capability in user point of view which
+ * allows that people tend to use through the device tree.
+ */
+static const char *const mt8518_uart_groups[] = { "uart0_0_rxd_txd",
+ "uart1_0_rxd_txd",
+ "uart2_0_rxd_txd", };
+
+/* MMC0 */
+static int mt8518_msdc0_pins[] = { 3, 4, 5, 6, 7, 8, 9, 10, 11,
+ 12, 13, };
+static int mt8518_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+
+static const struct mtk_group_desc mt8518_groups[] = {
+ PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8518_uart0_0_rxd_txd),
+ PINCTRL_PIN_GROUP("uart1_0_rxd_txd", mt8518_uart1_0_rxd_txd),
+ PINCTRL_PIN_GROUP("uart2_0_rxd_txd", mt8518_uart2_0_rxd_txd),
+
+ PINCTRL_PIN_GROUP("msdc0", mt8518_msdc0),
+};
+
+static const char *const mt8518_msdc_groups[] = { "msdc0" };
+
+static const struct mtk_function_desc mt8518_functions[] = {
+ {"uart", mt8518_uart_groups, ARRAY_SIZE(mt8518_uart_groups)},
+ {"msdc", mt8518_msdc_groups, ARRAY_SIZE(mt8518_msdc_groups)},
+};
+
+static struct mtk_pinctrl_soc mt8518_data = {
+ .name = "mt8518_pinctrl",
+ .reg_cal = mt8518_reg_cals,
+ .pins = mt8518_pins,
+ .npins = ARRAY_SIZE(mt8518_pins),
+ .grps = mt8518_groups,
+ .ngrps = ARRAY_SIZE(mt8518_groups),
+ .funcs = mt8518_functions,
+ .nfuncs = ARRAY_SIZE(mt8518_functions),
+};
+
+static int mtk_pinctrl_mt8518_probe(struct udevice *dev)
+{
+ return mtk_pinctrl_common_probe(dev, &mt8518_data);
+}
+
+static const struct udevice_id mt8518_pctrl_match[] = {
+ { .compatible = "mediatek,mt8518-pinctrl" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(mt8518_pinctrl) = {
+ .name = "mt8518_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = mt8518_pctrl_match,
+ .ops = &mtk_pinctrl_ops,
+ .probe = mtk_pinctrl_mt8518_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_pinctrl_priv),
+};
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index d36a010..ece7d87 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -145,7 +145,7 @@
config TPL_DM_SERIAL
bool "Enable Driver Model for serial drivers in TPL"
- depends on DM_SERIAL
+ depends on DM_SERIAL && TPL_DM
default y if TPL && DM_SERIAL
help
Enable driver model for serial in TPL. This replaces
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index dcdaede..0f5f1fa 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -29,29 +29,31 @@
#if CONFIG_IS_ENABLED(SERIAL_PRESENT)
static int serial_check_stdout(const void *blob, struct udevice **devp)
{
- int node;
+ int node = -1;
+ const char *str, *p, *name;
+ int namelen;
/* Check for a chosen console */
- node = fdtdec_get_chosen_node(blob, "stdout-path");
- if (node < 0) {
- const char *str, *p, *name;
+ str = fdtdec_get_chosen_prop(blob, "stdout-path");
+ if (str) {
+ p = strchr(str, ':');
+ namelen = p ? p - str : strlen(str);
+ node = fdt_path_offset_namelen(blob, str, namelen);
- /*
- * Deal with things like
- * stdout-path = "serial0:115200n8";
- *
- * We need to look up the alias and then follow it to the
- * correct node.
- */
- str = fdtdec_get_chosen_prop(blob, "stdout-path");
- if (str) {
- p = strchr(str, ':');
- name = fdt_get_alias_namelen(blob, str,
- p ? p - str : strlen(str));
+ if (node < 0) {
+ /*
+ * Deal with things like
+ * stdout-path = "serial0:115200n8";
+ *
+ * We need to look up the alias and then follow it to
+ * the correct node.
+ */
+ name = fdt_get_alias_namelen(blob, str, namelen);
if (name)
node = fdt_path_offset(blob, name);
}
}
+
if (node < 0)
node = fdt_path_offset(blob, "console");
if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node, devp))
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index b64bafd..8c0b81a 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -502,7 +502,6 @@
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after
* env, so we got 0x110000.
*/
-#define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
#define CONFIG_CORTINA_FW_ADDR 0x120000
@@ -512,12 +511,10 @@
* about 1MB (2048 blocks), Env is stored after the image, and the env size is
* 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
*/
-#define CONFIG_SYS_CORTINA_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
#define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0)
#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_CORTINA_FW_IN_NAND
#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
@@ -528,11 +525,9 @@
* slave SRIO or PCIE outbound window->master inbound window->
* master LAW->the ucode address in master's memory space.
*/
-#define CONFIG_SYS_CORTINA_FW_IN_REMOTE
#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
#define CONFIG_CORTINA_FW_ADDR 0xFFE10000
#else
-#define CONFIG_SYS_CORTINA_FW_IN_NOR
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#define CONFIG_CORTINA_FW_ADDR 0xEFE00000
#endif
@@ -541,7 +536,6 @@
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_PHY_CORTINA
#define CONFIG_PHY_REALTEK
#define CONFIG_CORTINA_FW_LENGTH 0x40000
#define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index fc2aed3..493da70 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -548,8 +548,6 @@
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_VITESSE
-#define CONFIG_PHY_CORTINA
-#define CONFIG_SYS_CORTINA_FW_IN_NOR
#define CONFIG_CORTINA_FW_ADDR 0xefe00000
#define CONFIG_CORTINA_FW_LENGTH 0x40000
#define CONFIG_PHY_TERANETICS
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index c5d57cf..926239a 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -560,8 +560,6 @@
/* MAC/PHY configuration */
#ifdef CONFIG_FSL_MC_ENET
-#define CONFIG_PHY_CORTINA
-#define CONFIG_SYS_CORTINA_FW_IN_NOR
#ifdef CONFIG_QSPI_BOOT
#define CONFIG_CORTINA_FW_ADDR 0x20980000
#else
diff --git a/include/configs/mt8518.h b/include/configs/mt8518.h
new file mode 100644
index 0000000..a7fe83a
--- /dev/null
+++ b/include/configs/mt8518.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Configuration for MediaTek MT8518 SoC
+ *
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ */
+
+#ifndef __MT8518_H
+#define __MT8518_H
+
+#include <linux/sizes.h>
+
+/* Machine ID */
+#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M
+
+#define CONFIG_CPU_ARMV8
+
+#define COUNTER_FREQUENCY 13000000
+
+/* DRAM definition */
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CONFIG_SYS_SDRAM_SIZE 0x20000000
+
+#define CONFIG_SYS_LOAD_ADDR 0x41000000
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+#define CONFIG_SYS_MALLOC_LEN SZ_32M
+#define CONFIG_SYS_BOOTM_LEN SZ_64M
+
+/* Uboot definition */
+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + \
+ SZ_2M - \
+ GENERATED_GBL_DATA_SIZE)
+
+/* ENV Setting */
+#if defined(CONFIG_MMC_MTK)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_OVERWRITE
+
+/* MMC offset in block unit,and block size is 0x200 */
+#define ENV_BOOT_READ_IMAGE \
+ "boot_rd_img=mmc dev 0" \
+ ";mmc read ${loadaddr} 0x27400 0x4000" \
+ ";iminfo ${loadaddr}\0"
+#endif
+
+/* Console configuration */
+#define ENV_DEVICE_SETTINGS \
+ "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0"
+
+#define ENV_BOOT_CMD \
+ "mtk_boot=run boot_rd_img;bootm;\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0x6c000000\0" \
+ ENV_DEVICE_SETTINGS \
+ ENV_BOOT_READ_IMAGE \
+ ENV_BOOT_CMD \
+ "bootcmd=run mtk_boot;\0" \
+
+#endif
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index fc5c87c..2c499d8 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -23,7 +23,7 @@
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
#define CONFIG_SYS_HZ 1000
-#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
/*
* Memory Info
diff --git a/include/dt-bindings/clock/mt8518-clk.h b/include/dt-bindings/clock/mt8518-clk.h
new file mode 100644
index 0000000..43b7247
--- /dev/null
+++ b/include/dt-bindings/clock/mt8518-clk.h
@@ -0,0 +1,249 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8518_H
+#define _DT_BINDINGS_CLK_MT8518_H
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_ARMPLL 0
+#define CLK_APMIXED_MAINPLL 1
+#define CLK_APMIXED_UNIVPLL 2
+#define CLK_APMIXED_MMPLL 3
+#define CLK_APMIXED_APLL1 4
+#define CLK_APMIXED_APLL2 5
+#define CLK_APMIXED_TVDPLL 6
+#define CLK_APMIXED_NR_CLK 7
+
+/* TOPCKGEN */
+
+#define CLK_TOP_CLK_NULL 0
+#define CLK_TOP_FQ_TRNG_OUT0 1
+#define CLK_TOP_FQ_TRNG_OUT1 2
+#define CLK_TOP_CLK32K 3
+#define CLK_TOP_DMPLL 4
+#define CLK_TOP_MAINPLL_D4 5
+#define CLK_TOP_MAINPLL_D8 6
+#define CLK_TOP_MAINPLL_D16 7
+#define CLK_TOP_MAINPLL_D11 8
+#define CLK_TOP_MAINPLL_D22 9
+#define CLK_TOP_MAINPLL_D3 10
+#define CLK_TOP_MAINPLL_D6 11
+#define CLK_TOP_MAINPLL_D12 12
+#define CLK_TOP_MAINPLL_D5 13
+#define CLK_TOP_MAINPLL_D10 14
+#define CLK_TOP_MAINPLL_D20 15
+#define CLK_TOP_MAINPLL_D40 16
+#define CLK_TOP_MAINPLL_D7 17
+#define CLK_TOP_MAINPLL_D14 18
+#define CLK_TOP_UNIVPLL_D2 19
+#define CLK_TOP_UNIVPLL_D4 20
+#define CLK_TOP_UNIVPLL_D8 21
+#define CLK_TOP_UNIVPLL_D16 22
+#define CLK_TOP_UNIVPLL_D3 23
+#define CLK_TOP_UNIVPLL_D6 24
+#define CLK_TOP_UNIVPLL_D12 25
+#define CLK_TOP_UNIVPLL_D24 26
+#define CLK_TOP_UNIVPLL_D5 27
+#define CLK_TOP_UNIVPLL_D20 28
+#define CLK_TOP_UNIVPLL_D10 29
+#define CLK_TOP_MMPLL_D2 30
+#define CLK_TOP_USB20_48M 31
+#define CLK_TOP_APLL1 32
+#define CLK_TOP_APLL1_D4 33
+#define CLK_TOP_APLL2 34
+#define CLK_TOP_APLL2_D2 35
+#define CLK_TOP_APLL2_D3 36
+#define CLK_TOP_APLL2_D4 37
+#define CLK_TOP_APLL2_D8 38
+#define CLK_TOP_CLK26M 39
+#define CLK_TOP_CLK26M_D2 40
+#define CLK_TOP_CLK26M_D4 41
+#define CLK_TOP_CLK26M_D8 42
+#define CLK_TOP_CLK26M_D793 43
+#define CLK_TOP_TVDPLL 44
+#define CLK_TOP_TVDPLL_D2 45
+#define CLK_TOP_TVDPLL_D4 46
+#define CLK_TOP_TVDPLL_D8 47
+#define CLK_TOP_TVDPLL_D16 48
+#define CLK_TOP_USB20_CLK480M 49
+#define CLK_TOP_RG_APLL1_D2 50
+#define CLK_TOP_RG_APLL1_D4 51
+#define CLK_TOP_RG_APLL1_D8 52
+#define CLK_TOP_RG_APLL1_D16 53
+#define CLK_TOP_RG_APLL1_D3 54
+#define CLK_TOP_RG_APLL2_D2 55
+#define CLK_TOP_RG_APLL2_D4 56
+#define CLK_TOP_RG_APLL2_D8 57
+#define CLK_TOP_RG_APLL2_D16 58
+#define CLK_TOP_RG_APLL2_D3 59
+#define CLK_TOP_NFI1X_INFRA_BCLK 60
+#define CLK_TOP_AHB_INFRA_D2 61
+#define CLK_TOP_UART0_SEL 62
+#define CLK_TOP_EMI1X_SEL 63
+#define CLK_TOP_EMI_DDRPHY_SEL 64
+#define CLK_TOP_MSDC1_SEL 65
+#define CLK_TOP_PWM_MM_SEL 66
+#define CLK_TOP_UART1_SEL 67
+#define CLK_TOP_SPM_52M_SEL 68
+#define CLK_TOP_PMICSPI_SEL 69
+#define CLK_TOP_NFI2X_SEL 70
+#define CLK_TOP_DDRPHYCFG_SEL 71
+#define CLK_TOP_SMI_SEL 72
+#define CLK_TOP_USB_SEL 73
+#define CLK_TOP_SPINOR_SEL 74
+#define CLK_TOP_ETH_SEL 75
+#define CLK_TOP_AUD1_SEL 76
+#define CLK_TOP_AUD2_SEL 77
+#define CLK_TOP_I2C_SEL 78
+#define CLK_TOP_AUD_I2S0_M_SEL 79
+#define CLK_TOP_AUD_I2S3_M_SEL 80
+#define CLK_TOP_AUD_I2S4_M_SEL 81
+#define CLK_TOP_AUD_I2S6_M_SEL 82
+#define CLK_TOP_PWM_SEL 83
+#define CLK_TOP_AUD_SPDIFIN_SEL 84
+#define CLK_TOP_UART2_SEL 85
+#define CLK_TOP_DBG_ATCLK_SEL 86
+#define CLK_TOP_PNG_SYS_SEL 87
+#define CLK_TOP_SEJ_13M_SEL 88
+#define CLK_TOP_IMGRZ_SYS_SEL 89
+#define CLK_TOP_GRAPH_ECLK_SEL 90
+#define CLK_TOP_FDBI_SEL 91
+#define CLK_TOP_FAUDIO_SEL 92
+#define CLK_TOP_FA2SYS_SEL 93
+#define CLK_TOP_FA1SYS_SEL 94
+#define CLK_TOP_FASM_M_SEL 95
+#define CLK_TOP_FASM_H_SEL 96
+#define CLK_TOP_FASM_L_SEL 97
+#define CLK_TOP_FECC_CK_SEL 98
+#define CLK_TOP_PE2_MAC_SEL 99
+#define CLK_TOP_CMSYS_SEL 100
+#define CLK_TOP_GCPU_SEL 101
+#define CLK_TOP_SPIS_CK_SEL 102
+#define CLK_TOP_APLL1_REF_SEL 103
+#define CLK_TOP_APLL2_REF_SEL 104
+#define CLK_TOP_INT_32K_SEL 105
+#define CLK_TOP_APLL1_SRC_SEL 106
+#define CLK_TOP_APLL2_SRC_SEL 107
+#define CLK_TOP_FAUD_INTBUS_SEL 108
+#define CLK_TOP_AXIBUS_SEL 109
+#define CLK_TOP_HAPLL1_SEL 110
+#define CLK_TOP_HAPLL2_SEL 111
+#define CLK_TOP_SPINFI_SEL 112
+#define CLK_TOP_MSDC0_SEL 113
+#define CLK_TOP_MSDC0_CLK50_SEL 114
+#define CLK_TOP_MSDC2_SEL 115
+#define CLK_TOP_MSDC2_CLK50_SEL 116
+#define CLK_TOP_DISP_DPI_CK_SEL 117
+#define CLK_TOP_SPI1_SEL 118
+#define CLK_TOP_SPI2_SEL 119
+#define CLK_TOP_SPI3_SEL 120
+#define CLK_TOP_APLL12_CK_DIV0 121
+#define CLK_TOP_APLL12_CK_DIV3 122
+#define CLK_TOP_APLL12_CK_DIV4 123
+#define CLK_TOP_APLL12_CK_DIV6 124
+
+/* TOPCKGEN Gates */
+#define CLK_TOP_PWM_MM 0
+#define CLK_TOP_SMI 1
+#define CLK_TOP_SPI2 2
+#define CLK_TOP_SPI3 3
+#define CLK_TOP_SPINFI 4
+#define CLK_TOP_26M_DEBUG 5
+#define CLK_TOP_USB_48M_DEBUG 6
+#define CLK_TOP_52M_DEBUG 7
+#define CLK_TOP_32K_DEBUG 8
+#define CLK_TOP_THERM 9
+#define CLK_TOP_APDMA 10
+#define CLK_TOP_I2C0 11
+#define CLK_TOP_I2C1 12
+#define CLK_TOP_AUXADC1 13
+#define CLK_TOP_NFI 14
+#define CLK_TOP_NFIECC 15
+#define CLK_TOP_DEBUGSYS 16
+#define CLK_TOP_PWM 17
+#define CLK_TOP_UART0 18
+#define CLK_TOP_UART1 19
+#define CLK_TOP_USB 20
+#define CLK_TOP_FLASHIF_26M 21
+#define CLK_TOP_AUXADC2 22
+#define CLK_TOP_I2C2 23
+#define CLK_TOP_MSDC0 24
+#define CLK_TOP_MSDC1 25
+#define CLK_TOP_NFI2X 26
+#define CLK_TOP_MEMSLP_DLYER 27
+#define CLK_TOP_SPI 28
+#define CLK_TOP_APXGPT 29
+#define CLK_TOP_PMICWRAP_MD 30
+#define CLK_TOP_PMICWRAP_CONN 31
+#define CLK_TOP_PMIC_SYSCK 32
+#define CLK_TOP_AUX_ADC 33
+#define CLK_TOP_AUX_TP 34
+#define CLK_TOP_RBIST 35
+#define CLK_TOP_NFI_BUS 36
+#define CLK_TOP_GCE 37
+#define CLK_TOP_TRNG 38
+#define CLK_TOP_PWM_B 39
+#define CLK_TOP_PWM1_FB 40
+#define CLK_TOP_PWM2_FB 41
+#define CLK_TOP_PWM3_FB 42
+#define CLK_TOP_PWM4_FB 43
+#define CLK_TOP_PWM5_FB 44
+#define CLK_TOP_FLASHIF_FREERUN 45
+#define CLK_TOP_CQDMA 46
+#define CLK_TOP_66M_ETH 47
+#define CLK_TOP_133M_ETH 48
+#define CLK_TOP_FLASHIF_AXI 49
+#define CLK_TOP_USBIF 50
+#define CLK_TOP_UART2 51
+#define CLK_TOP_GCPU_B 52
+#define CLK_TOP_MSDC0_B 53
+#define CLK_TOP_MSDC1_B 54
+#define CLK_TOP_MSDC2_B 55
+#define CLK_TOP_USB_B 56
+#define CLK_TOP_SPINOR 57
+#define CLK_TOP_MSDC2 58
+#define CLK_TOP_ETH 59
+#define CLK_TOP_AUD1 60
+#define CLK_TOP_AUD2 61
+#define CLK_TOP_I2C 62
+#define CLK_TOP_PWM_INFRA 63
+#define CLK_TOP_AUD_SPDIF_IN 64
+#define CLK_TOP_RG_UART2 65
+#define CLK_TOP_DBG_AT 66
+#define CLK_TOP_APLL12_DIV0 67
+#define CLK_TOP_APLL12_DIV3 68
+#define CLK_TOP_APLL12_DIV4 69
+#define CLK_TOP_APLL12_DIV6 70
+#define CLK_TOP_IMGRZ_SYS 71
+#define CLK_TOP_PNG_SYS 72
+#define CLK_TOP_GRAPH_E 73
+#define CLK_TOP_FDBI 74
+#define CLK_TOP_FAUDIO 75
+#define CLK_TOP_FAUD_INTBUS 76
+#define CLK_TOP_HAPLL1 77
+#define CLK_TOP_HAPLL2 78
+#define CLK_TOP_FA2SYS 79
+#define CLK_TOP_FA1SYS 80
+#define CLK_TOP_FASM_L 81
+#define CLK_TOP_FASM_M 82
+#define CLK_TOP_FASM_H 83
+#define CLK_TOP_FECC 84
+#define CLK_TOP_PE2_MAC 85
+#define CLK_TOP_CMSYS 86
+#define CLK_TOP_GCPU 87
+#define CLK_TOP_SPIS 88
+#define CLK_TOP_I2C3 89
+#define CLK_TOP_SPI_SLV_B 90
+#define CLK_TOP_SPI_SLV_BUS 91
+#define CLK_TOP_PCIE_MAC_BUS 92
+#define CLK_TOP_CMSYS_BUS 93
+#define CLK_TOP_ECC_B 94
+#define CLK_TOP_PCIE_PHY_BUS 95
+#define CLK_TOP_PCIE_AUX 96
+#define CLK_TOP_DISP_DPI 97
+#define CLK_TOP_NR_CLK 98
+
+#endif /* _DT_BINDINGS_CLK_MT8518_H */
diff --git a/include/vxworks.h b/include/vxworks.h
index 1a29509..d90d862 100644
--- a/include/vxworks.h
+++ b/include/vxworks.h
@@ -9,6 +9,9 @@
#include <efi_api.h>
+/* Use Linux compatible standard DTB */
+#define VXWORKS_SYSFLG_STD_DTB 0x1
+
/*
* Physical address of memory base for VxWorks x86
* This is LOCAL_MEM_LOCAL_ADRS in the VxWorks kernel configuration.
diff --git a/lib/Kconfig b/lib/Kconfig
index b8a8509..55dedcb 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -96,7 +96,7 @@
set to 1000.
config SPL_USE_TINY_PRINTF
- bool "Enable tiny printf() version"
+ bool "Enable tiny printf() version in SPL"
depends on SPL
default y
help
@@ -108,7 +108,7 @@
The supported format specifiers are %c, %s, %u/%d and %x.
config TPL_USE_TINY_PRINTF
- bool "Enable tiny printf() version"
+ bool "Enable tiny printf() version in TPL"
depends on TPL
default y if SPL_USE_TINY_PRINTF
help
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index f3ed80e..73dd48c 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -1918,11 +1918,6 @@
CONFIG_SYS_CMXFCR_VALUE3
CONFIG_SYS_CORE_SRAM
CONFIG_SYS_CORE_SRAM_SIZE
-CONFIG_SYS_CORTINA_FW_IN_MMC
-CONFIG_SYS_CORTINA_FW_IN_NAND
-CONFIG_SYS_CORTINA_FW_IN_NOR
-CONFIG_SYS_CORTINA_FW_IN_REMOTE
-CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
CONFIG_SYS_CPC_REINIT_F
CONFIG_SYS_CPLD_AMASK
CONFIG_SYS_CPLD_BASE
diff --git a/tools/binman/README b/tools/binman/README
index 20a8094..a6a3ee4 100644
--- a/tools/binman/README
+++ b/tools/binman/README
@@ -73,7 +73,7 @@
and brought in as needed
- Provides for a standard image description available in the build and at
run-time
-- SoC-specific image-signing tools can be accomodated
+- SoC-specific image-signing tools can be accommodated
- Avoids cluttering the U-Boot build system with image-building code
- The image description is automatically available at run-time in U-Boot,
SPL. It can be made available to other software also
diff --git a/tools/binman/README.entries b/tools/binman/README.entries
index 1099433..0576e63 100644
--- a/tools/binman/README.entries
+++ b/tools/binman/README.entries
@@ -519,7 +519,7 @@
This file contains code used by the SoC that is required to make it work.
The Management Engine is like a background task that runs things that are
-not clearly documented, but may include keyboard, deplay and network
+not clearly documented, but may include keyboard, display and network
access. For platform that use ME it is not possible to disable it. U-Boot
does not directly execute code in the ME binary.
@@ -593,7 +593,7 @@
Properties / Entry arguments:
- filename: Filename of u-boot-br.bin (default 'u-boot-br.bin')
-This enrty is valid for PowerPC mpc85xx cpus. This entry holds
+This entry is valid for PowerPC mpc85xx cpus. This entry holds
'bootpg + resetvec' code for PowerPC mpc85xx CPUs which needs to be
placed at offset 'RESET_VECTOR_ADDRESS - 0xffc'.