board: gateworks: venice: add imx8mp-venice-gw740x support
The GW74xx is based on the i.MX 8M Plus SoC featuring:
- LPDDR4 DRAM
- eMMC FLASH
- Gateworks System Controller
- PCIe Gen 3.0 switch (build option)
- USB 3.0 HUB
- USB Type-C front panel connector
- GPS
- 3-axis accelerometer
- CAN bus
- 6x GbE RJ45 front-panel jacks
- 1x IMX8M FEC RGMII GbE (with Passive PoE)
- 5x IMX8M EQOS RGMII 6 port GbE Switch
(1x with 802.3af class 5 Active PoE)
- RS232/RS485/RS422 serial transceiver
- MIPI header (DSI/CSI/GPIO/PWM/I2S)
- DigI/O header (UART/GPIO/I2C/ADC)
- 802.11ac WiFi
- Bluetooth BLE
- 3x MiniPCIe sockets with PCI/USB
- 1x M.2 Socket with USB2.0, PCIe, and dual-SIM
- PMIC
- Wide range DC input supply (8V to 60V DC)
Do the following to add support for this and future imx8mp-venice boards:
- add dts
- add DRAM config
- add PMIC config
- add IMX8MP support in spl.c and venice.c
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c
index b1828f4..4290a69 100644
--- a/board/gateworks/venice/venice.c
+++ b/board/gateworks/venice/venice.c
@@ -6,6 +6,7 @@
#include <init.h>
#include <led.h>
#include <miiphy.h>
+#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include "eeprom.h"
@@ -39,18 +40,36 @@
return -1;
}
-#if (IS_ENABLED(CONFIG_FEC_MXC))
+#if (IS_ENABLED(CONFIG_NET))
static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+#ifndef CONFIG_IMX8MP
/* Use 125M anatop REF_CLK1 for ENET1, not from external */
clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
+#else
+ /* Enable RGMII TX clk output */
+ setbits_le32(&gpr->gpr[1], BIT(22));
+#endif
return 0;
}
+static int setup_eqos(void)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ /* set INTF as RGMII, enable RGMII TXC clock */
+ clrsetbits_le32(&gpr->gpr[1],
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
+ setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
+
+ return set_clk_eqos(ENET_125MHZ);
+}
+
int board_phy_config(struct phy_device *phydev)
{
unsigned short val;
@@ -87,7 +106,7 @@
return 0;
}
-#endif // IS_ENABLED(CONFIG_FEC_MXC)
+#endif // IS_ENABLED(CONFIG_NET)
int board_init(void)
{
@@ -95,6 +114,8 @@
if (IS_ENABLED(CONFIG_FEC_MXC))
setup_fec();
+ if (IS_ENABLED(CONFIG_DWC_ETH_QOS))
+ setup_eqos();
return 0;
}