diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c
index 6fcef63..be70d30 100644
--- a/arch/arm/mach-rockchip/px30/px30.c
+++ b/arch/arm/mach-rockchip/px30/px30.c
@@ -51,6 +51,57 @@
 
 #define QOS_PRIORITY_LEVEL(h, l)	((((h) & 3) << 8) | ((l) & 3))
 
+/* GRF_GPIO1AL_IOMUX */
+enum {
+	GPIO1A3_SHIFT		= 12,
+	GPIO1A3_MASK		= 0xf << GPIO1A3_SHIFT,
+	GPIO1A3_GPIO		= 0,
+	GPIO1A3_FLASH_D3,
+	GPIO1A3_EMMC_D3,
+	GPIO1A3_SFC_SIO3,
+
+	GPIO1A2_SHIFT		= 8,
+	GPIO1A2_MASK		= 0xf << GPIO1A2_SHIFT,
+	GPIO1A2_GPIO		= 0,
+	GPIO1A2_FLASH_D2,
+	GPIO1A2_EMMC_D2,
+	GPIO1A2_SFC_SIO2,
+
+	GPIO1A1_SHIFT		= 4,
+	GPIO1A1_MASK		= 0xf << GPIO1A1_SHIFT,
+	GPIO1A1_GPIO		= 0,
+	GPIO1A1_FLASH_D1,
+	GPIO1A1_EMMC_D1,
+	GPIO1A1_SFC_SIO1,
+
+	GPIO1A0_SHIFT		= 0,
+	GPIO1A0_MASK		= 0xf << GPIO1A0_SHIFT,
+	GPIO1A0_GPIO		= 0,
+	GPIO1A0_FLASH_D0,
+	GPIO1A0_EMMC_D0,
+	GPIO1A0_SFC_SIO0,
+};
+
+/* GRF_GPIO1AH_IOMUX */
+enum {
+	GPIO1A4_SHIFT		= 0,
+	GPIO1A4_MASK		= 0xf << GPIO1A4_SHIFT,
+	GPIO1A4_GPIO		= 0,
+	GPIO1A4_FLASH_D4,
+	GPIO1A4_EMMC_D4,
+	GPIO1A4_SFC_CSN0,
+};
+
+/* GRF_GPIO1BL_IOMUX */
+enum {
+	GPIO1B1_SHIFT		= 4,
+	GPIO1B1_MASK		= 0xf << GPIO1B1_SHIFT,
+	GPIO1B1_GPIO		= 0,
+	GPIO1B1_FLASH_RDY,
+	GPIO1B1_EMMC_CLKOUT,
+	GPIO1B1_SFC_CLK,
+};
+
 /* GRF_GPIO1BH_IOMUX */
 enum {
 	GPIO1B7_SHIFT		= 12,
@@ -193,6 +244,19 @@
 		     GPIO1D4_SDMMC_D2 << GPIO1D4_SHIFT);
 #endif
 
+#ifdef CONFIG_ROCKCHIP_SFC
+	rk_clrsetreg(&grf->gpio1al_iomux,
+		     GPIO1A3_MASK | GPIO1A2_MASK | GPIO1A1_MASK | GPIO1A0_MASK,
+		     GPIO1A3_SFC_SIO3 << GPIO1A3_SHIFT |
+		     GPIO1A2_SFC_SIO2 << GPIO1A2_SHIFT |
+		     GPIO1A1_SFC_SIO1 << GPIO1A1_SHIFT |
+		     GPIO1A0_SFC_SIO0 << GPIO1A0_SHIFT);
+	rk_clrsetreg(&grf->gpio1ah_iomux, GPIO1A4_MASK,
+		     GPIO1A4_SFC_CSN0 << GPIO1A4_SHIFT);
+	rk_clrsetreg(&grf->gpio1bl_iomux, GPIO1B1_MASK,
+		     GPIO1B1_SFC_CLK << GPIO1B1_SHIFT);
+#endif
+
 #endif
 
 	/* Enable PD_VO (default disable at reset) */