mips: mscc: Add generic PHY MIIM utility functions
The PHY MIIM utility functions can/will be used for board detection
purposes.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
diff --git a/arch/mips/mach-mscc/include/mach/common.h b/arch/mips/mach-mscc/include/mach/common.h
index 931ecd7..92a0555 100644
--- a/arch/mips/mach-mscc/include/mach/common.h
+++ b/arch/mips/mach-mscc/include/mach/common.h
@@ -9,10 +9,12 @@
#if defined(CONFIG_SOC_OCELOT)
#include <mach/ocelot/ocelot.h>
#include <mach/ocelot/ocelot_devcpu_gcb.h>
+#include <mach/ocelot/ocelot_devcpu_gcb_miim_regs.h>
#include <mach/ocelot/ocelot_icpu_cfg.h>
#elif defined(CONFIG_SOC_LUTON)
#include <mach/luton/luton.h>
#include <mach/luton/luton_devcpu_gcb.h>
+#include <mach/luton/luton_devcpu_gcb_miim_regs.h>
#include <mach/luton/luton_icpu_cfg.h>
#else
#error Unsupported platform
@@ -25,4 +27,22 @@
#define VCOREIII_TIMER_DIVIDER 25 /* Clock tick ~ 0.1 us */
+/* Common utility functions */
+
+int mscc_phy_rd_wr(u8 read,
+ u32 miim_controller,
+ u8 miim_addr,
+ u8 addr,
+ u16 *value);
+
+int mscc_phy_rd(u32 miim_controller,
+ u8 miim_addr,
+ u8 addr,
+ u16 *value);
+
+int mscc_phy_wr(u32 miim_controller,
+ u8 miim_addr,
+ u8 addr,
+ u16 value);
+
#endif /* __ASM_MACH_COMMON_H */
diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h
new file mode 100644
index 0000000..2303734
--- /dev/null
+++ b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Microsemi Ocelot Switch driver
+ *
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef _MSCC_LUTON_MIIM_REGS_H_
+#define _MSCC_LUTON_MIIM_REGS_H_
+
+#define MIIM_MII_STATUS(gi) (0xa0 + (gi * 36))
+#define MIIM_MII_CMD(gi) (0xa8 + (gi * 36))
+#define MIIM_MII_DATA(gi) (0xac + (gi * 36))
+
+#define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) (x ? BIT(3) : 0)
+
+#define MSCC_F_MII_CMD_MIIM_CMD_VLD(x) (x ? BIT(31) : 0)
+#define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & (x << 25))
+#define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & (x << 20))
+#define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & (x << 4))
+#define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & (x << 1))
+
+#define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS GENMASK(17, 16)
+#define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) ((x >> 0) & GENMASK(15, 0))
+
+#endif
diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h
new file mode 100644
index 0000000..4ad9221
--- /dev/null
+++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef _MSCC_OCELOT_DEVCPU_GCB_MIIM_REGS_H_
+#define _MSCC_OCELOT_DEVCPU_GCB_MIIM_REGS_H_
+
+#define MIIM_MII_STATUS(gi) (0x9c + (gi * 36))
+#define MIIM_MII_CMD(gi) (0xa4 + (gi * 36))
+#define MIIM_MII_DATA(gi) (0xa8 + (gi * 36))
+
+#define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) ((x) ? BIT(3) : 0)
+
+#define MSCC_F_MII_CMD_MIIM_CMD_VLD(x) ((x) ? BIT(31) : 0)
+#define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & ((x) << 25))
+#define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & ((x) << 20))
+#define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & ((x) << 4))
+#define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & ((x) << 1))
+#define MSCC_F_MII_CMD_MIIM_CMD_SCAN(x) ((x) ? BIT(0) : 0)
+
+#define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS GENMASK(17, 16)
+#define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) (((x) >> 0) & GENMASK(15, 0))
+
+#endif