tree f5e7c0f371867fc03adafc3da8fe2916b245e468
parent 8c3d61a2ac8caa4efb4a154ff2a6a487d4c54230
author Felix Radensky <felix@embedded-sol.com> 1254088572 +0200
committer Stefan Roese <sr@denx.de> 1254484408 +0200

ppc4xx: Reorganize DDR2 ECC handling

Reorganize DDR2 ECC handling to use common code for
SPD DIMMs and soldered SDRAM. Also, use common code
to display SDRAM info (ECC, CAS latency) for SPD and
soldered SDRAM variants.

Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Signed-off-by: Stefan Roese <sr@denx.de>