armv8/fsl_lsch3: Change arch to fsl-layerscape
There are two LS series processors are built on ARMv8 Layersacpe
architecture currently, LS2085A and LS1043A. They are based on
ARMv8 core although use different chassis, so create fsl-layerscape
to refactor the common code for the LS series processors which also
paves the way for adding LS1043A platform.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/clock.h b/arch/arm/include/asm/arch-fsl-layerscape/clock.h
new file mode 100644
index 0000000..6935913
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/clock.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#ifndef __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
+#define __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
+
+#include <common.h>
+
+enum mxc_clock {
+ MXC_ARM_CLK = 0,
+ MXC_BUS_CLK,
+ MXC_UART_CLK,
+ MXC_ESDHC_CLK,
+ MXC_I2C_CLK,
+ MXC_DSPI_CLK,
+};
+
+unsigned int mxc_get_clock(enum mxc_clock clk);
+
+#endif /* __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
new file mode 100644
index 0000000..dd7203f
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright 2015, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
+#define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
+
+#include <fsl_ddrc_version.h>
+
+#ifdef CONFIG_SYS_FSL_DDR4
+#define CONFIG_SYS_FSL_DDRC_GEN4
+#else
+#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
+#endif
+#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
+#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
+
+#if defined(CONFIG_LS2085A)
+#define CONFIG_MAX_CPUS 16
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
+#define CONFIG_NUM_DDR_CONTROLLERS 3
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
+#define SRDS_MAX_LANES 8
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_SRDS_2
+#define CONFIG_SYS_PAGE_SIZE 0x10000
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#ifndef L1_CACHE_BYTES
+#define L1_CACHE_SHIFT 6
+#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
+#endif
+
+#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
+#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
+
+/* DDR */
+#define CONFIG_SYS_FSL_DDR_LE
+#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
+
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+#define CONFIG_SYS_FSL_CCSR_SCFG_LE
+#define CONFIG_SYS_FSL_ESDHC_LE
+#define CONFIG_SYS_FSL_IFC_LE
+
+#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE 0x06000000
+#define GICR_BASE 0x06100000
+
+/* SMMU Defintions */
+#define SMMU_BASE 0x05000000 /* GR0 Base */
+
+/* Cache Coherent Interconnect */
+#define CCI_MN_BASE 0x04000000
+#define CCI_MN_RNF_NODEID_LIST 0x180
+#define CCI_MN_DVM_DOMAIN_CTL 0x200
+#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
+
+#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
+#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
+#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
+#define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
+#define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
+#define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
+
+#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
+#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
+#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
+
+/* TZ Protection Controller Definitions */
+#define TZPC_BASE 0x02200000
+#define TZPCR0SIZE_BASE (TZPC_BASE)
+#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
+#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
+#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
+#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
+#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
+#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
+#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
+#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
+#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
+
+#define CONFIG_SYS_FSL_ERRATUM_A008336
+#define CONFIG_SYS_FSL_ERRATUM_A008511
+#define CONFIG_SYS_FSL_ERRATUM_A008514
+#define CONFIG_SYS_FSL_ERRATUM_A008585
+#define CONFIG_SYS_FSL_ERRATUM_A008751
+#else
+#error SoC not defined
+#endif
+
+#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
new file mode 100644
index 0000000..b7b8e5d
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -0,0 +1,165 @@
+/*
+ * Copyright 2014-2015, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _FSL_LAYERSCAPE_CPU_H
+#define _FSL_LAYERSCAPE_CPU_H
+
+static struct cpu_type cpu_type_list[] = {
+ CPU_TYPE_ENTRY(LS2085, LS2085, 8),
+ CPU_TYPE_ENTRY(LS2080, LS2080, 8),
+ CPU_TYPE_ENTRY(LS2045, LS2045, 4),
+};
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+
+#define SECTION_SHIFT_L0 39UL
+#define SECTION_SHIFT_L1 30UL
+#define SECTION_SHIFT_L2 21UL
+#define BLOCK_SIZE_L0 0x8000000000
+#define BLOCK_SIZE_L1 0x40000000
+#define BLOCK_SIZE_L2 0x200000
+#define NUM_OF_ENTRY 512
+#define TCR_EL2_PS_40BIT (2 << 16)
+
+#define LAYERSCAPE_VA_BITS (40)
+#define LAYERSCAPE_TCR (TCR_TG0_4K | \
+ TCR_EL2_PS_40BIT | \
+ TCR_SHARED_NON | \
+ TCR_ORGN_NC | \
+ TCR_IRGN_NC | \
+ TCR_T0SZ(LAYERSCAPE_VA_BITS))
+#define LAYERSCAPE_TCR_FINAL (TCR_TG0_4K | \
+ TCR_EL2_PS_40BIT | \
+ TCR_SHARED_OUTER | \
+ TCR_ORGN_WBWA | \
+ TCR_IRGN_WBWA | \
+ TCR_T0SZ(LAYERSCAPE_VA_BITS))
+
+#ifdef CONFIG_FSL_LSCH3
+#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
+#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
+#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
+#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
+#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
+#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
+#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
+#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
+#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
+#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
+#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
+#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
+#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000
+#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000
+#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000
+#define CONFIG_SYS_FSL_MC_BASE 0x80c000000
+#define CONFIG_SYS_FSL_MC_SIZE 0x4000000
+#define CONFIG_SYS_FSL_NI_BASE 0x810000000
+#define CONFIG_SYS_FSL_NI_SIZE 0x8000000
+#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000
+#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000
+#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000
+#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000
+#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000
+#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000
+#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000
+#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000
+#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
+#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
+#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
+#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
+#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
+#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000
+#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
+#endif
+
+struct sys_mmu_table {
+ u64 virt_addr;
+ u64 phys_addr;
+ u64 size;
+ u64 memory_type;
+ u64 share;
+};
+
+struct table_info {
+ u64 *ptr;
+ u64 table_base;
+ u64 entry_size;
+};
+
+static const struct sys_mmu_table early_mmu_table[] = {
+#ifdef CONFIG_FSL_LSCH3
+ { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+ CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
+ /* For IFC Region #1, only the first 4MB is cache-enabled */
+ { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
+ CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
+ CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
+ CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
+ MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
+ CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+ CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+ { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+ CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+ CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+#endif
+};
+
+static const struct sys_mmu_table final_mmu_table[] = {
+#ifdef CONFIG_FSL_LSCH3
+ { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+ CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+ CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+ { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
+ CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
+ CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+ CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
+ CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
+ CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ /* For QBMAN portal, only the first 64MB is cache-enabled */
+ { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
+ CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
+ CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
+ CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
+ MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
+ CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
+ CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
+ CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+#ifdef CONFIG_LS2085A
+ { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
+ CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+#endif
+ { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
+ CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
+ CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
+ CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+ CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+#endif
+};
+#endif
+
+int fsl_qoriq_core_to_cluster(unsigned int core);
+u32 cpu_mask(void);
+#endif /* _FSL_LAYERSCAPE_CPU_H */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fdt.h b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h
new file mode 100644
index 0000000..4da73ab
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_
+#define _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_
+
+void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt);
+void append_mmu_masters(void *blob, const char *smmu_path,
+ const char *master_name, u32 *stream_ids, int count);
+void fdt_fixup_smmu_pcie(void *blob);
+#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
new file mode 100644
index 0000000..730c2b2
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSL_SERDES_H__
+#define __FSL_SERDES_H__
+
+#include <config.h>
+
+#if defined(CONFIG_LS2085A)
+enum srds_prtcl {
+ NONE = 0,
+ PCIE1,
+ PCIE2,
+ PCIE3,
+ PCIE4,
+ SATA1,
+ SATA2,
+ XAUI1,
+ XAUI2,
+ XFI1,
+ XFI2,
+ XFI3,
+ XFI4,
+ XFI5,
+ XFI6,
+ XFI7,
+ XFI8,
+ SGMII1,
+ SGMII2,
+ SGMII3,
+ SGMII4,
+ SGMII5,
+ SGMII6,
+ SGMII7,
+ SGMII8,
+ SGMII9,
+ SGMII10,
+ SGMII11,
+ SGMII12,
+ SGMII13,
+ SGMII14,
+ SGMII15,
+ SGMII16,
+ QSGMII_A, /* A indicates MACs 1-4 */
+ QSGMII_B, /* B indicates MACs 5-8 */
+ QSGMII_C, /* C indicates MACs 9-12 */
+ QSGMII_D, /* D indicates MACs 12-16 */
+ SERDES_PRCTL_COUNT
+};
+
+enum srds {
+ FSL_SRDS_1 = 0,
+ FSL_SRDS_2 = 1,
+};
+#endif
+
+int is_serdes_configured(enum srds_prtcl device);
+void fsl_serdes_init(void);
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
+int is_serdes_prtcl_valid(int serdes, u32 prtcl);
+
+#endif /* __FSL_SERDES_H__ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
new file mode 100644
index 0000000..6a70d44
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -0,0 +1,268 @@
+/*
+ * LayerScape Internal Memory Map
+ *
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ARCH_FSL_LSCH3_IMMAP_H_
+#define __ARCH_FSL_LSCH3_IMMAP_H_
+
+#define CONFIG_SYS_IMMR 0x01000000
+#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
+#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
+#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
+#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
+#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
+#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
+#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
+#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
+#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
+#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
+#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
+#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000
+#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
+ 0x18A0)
+
+#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
+#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
+#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
+#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
+
+/* SP (Cortex-A5) related */
+#define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000)
+#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR)
+#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR)
+#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \
+ (CONFIG_SYS_FSL_SP_ADDR + 0x0008)
+#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \
+ (CONFIG_SYS_FSL_SP_ADDR + 0x1000)
+
+#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
+#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
+#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
+#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL
+
+#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
+#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
+#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
+#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
+
+#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
+
+/* TZ Address Space Controller Definitions */
+#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
+#define TZASC2_BASE 0x01110000 /* as per CCSR map. */
+#define TZASC3_BASE 0x01120000 /* as per CCSR map. */
+#define TZASC4_BASE 0x01130000 /* as per CCSR map. */
+#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
+#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
+#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
+#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
+#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
+#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
+#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
+#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
+#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
+
+/* PCIe */
+#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
+#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
+#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
+#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
+#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
+#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
+#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
+
+/* Device Configuration */
+#define DCFG_BASE 0x01e00000
+#define DCFG_PORSR1 0x000
+#define DCFG_PORSR1_RCW_SRC 0xff800000
+#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000
+#define DCFG_RCWSR13 0x130
+#define DCFG_RCWSR13_DSPI (0 << 8)
+
+#define DCFG_DCSR_BASE 0X700100000ULL
+#define DCFG_DCSR_PORCR1 0x000
+
+/* Supplemental Configuration */
+#define SCFG_BASE 0x01fc0000
+#define SCFG_USB3PRM1CR 0x000
+
+#define TP_ITYP_AV 0x00000001 /* Initiator available */
+#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
+#define TP_ITYP_TYPE_ARM 0x0
+#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
+#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
+#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
+#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
+#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
+#define TY_ITYP_VER_A7 0x1
+#define TY_ITYP_VER_A53 0x2
+#define TY_ITYP_VER_A57 0x3
+
+#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
+#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
+#define TP_INIT_PER_CLUSTER 4
+/* This is chassis generation 3 */
+
+struct sys_info {
+ unsigned long freq_processor[CONFIG_MAX_CPUS];
+ unsigned long freq_systembus;
+ unsigned long freq_ddrbus;
+ unsigned long freq_ddrbus2;
+ unsigned long freq_localbus;
+ unsigned long freq_qe;
+#ifdef CONFIG_SYS_DPAA_FMAN
+ unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
+#endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ unsigned long freq_qman;
+#endif
+#ifdef CONFIG_SYS_DPAA_PME
+ unsigned long freq_pme;
+#endif
+};
+
+/* Global Utilities Block */
+struct ccsr_gur {
+ u32 porsr1; /* POR status 1 */
+ u32 porsr2; /* POR status 2 */
+ u8 res_008[0x20-0x8];
+ u32 gpporcr1; /* General-purpose POR configuration */
+ u32 gpporcr2; /* General-purpose POR configuration 2 */
+ u32 dcfg_fusesr; /* Fuse status register */
+ u32 gpporcr3;
+ u32 gpporcr4;
+ u8 res_034[0x70-0x34];
+ u32 devdisr; /* Device disable control */
+ u32 devdisr2; /* Device disable control 2 */
+ u32 devdisr3; /* Device disable control 3 */
+ u32 devdisr4; /* Device disable control 4 */
+ u32 devdisr5; /* Device disable control 5 */
+ u32 devdisr6; /* Device disable control 6 */
+ u32 devdisr7; /* Device disable control 7 */
+#define FSL_CHASSIS3_DEVDISR2_DPMAC1 0x00000001
+#define FSL_CHASSIS3_DEVDISR2_DPMAC2 0x00000002
+#define FSL_CHASSIS3_DEVDISR2_DPMAC3 0x00000004
+#define FSL_CHASSIS3_DEVDISR2_DPMAC4 0x00000008
+#define FSL_CHASSIS3_DEVDISR2_DPMAC5 0x00000010
+#define FSL_CHASSIS3_DEVDISR2_DPMAC6 0x00000020
+#define FSL_CHASSIS3_DEVDISR2_DPMAC7 0x00000040
+#define FSL_CHASSIS3_DEVDISR2_DPMAC8 0x00000080
+#define FSL_CHASSIS3_DEVDISR2_DPMAC9 0x00000100
+#define FSL_CHASSIS3_DEVDISR2_DPMAC10 0x00000200
+#define FSL_CHASSIS3_DEVDISR2_DPMAC11 0x00000400
+#define FSL_CHASSIS3_DEVDISR2_DPMAC12 0x00000800
+#define FSL_CHASSIS3_DEVDISR2_DPMAC13 0x00001000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC14 0x00002000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC15 0x00004000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC16 0x00008000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC17 0x00010000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC18 0x00020000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC19 0x00040000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC20 0x00080000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC21 0x00100000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC22 0x00200000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC23 0x00400000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC24 0x00800000
+ u8 res_08c[0x90-0x8c];
+ u32 coredisru; /* uppper portion for support of 64 cores */
+ u32 coredisrl; /* lower portion for support of 64 cores */
+ u8 res_098[0xa0-0x98];
+ u32 pvr; /* Processor version */
+ u32 svr; /* System version */
+ u32 mvr; /* Manufacturing version */
+ u8 res_0ac[0x100-0xac];
+ u32 rcwsr[32]; /* Reset control word status */
+
+#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2
+#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f
+#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10
+#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f
+#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18
+#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f
+#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000
+#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16
+#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000
+#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24
+
+ u8 res_180[0x200-0x180];
+ u32 scratchrw[32]; /* Scratch Read/Write */
+ u8 res_280[0x300-0x280];
+ u32 scratchw1r[4]; /* Scratch Read (Write once) */
+ u8 res_310[0x400-0x310];
+ u32 bootlocptrl; /* Boot location pointer low-order addr */
+ u32 bootlocptrh; /* Boot location pointer high-order addr */
+ u8 res_408[0x500-0x408];
+ u8 res_500[0x740-0x500]; /* add more registers when needed */
+ u32 tp_ityp[64]; /* Topology Initiator Type Register */
+ struct {
+ u32 upper;
+ u32 lower;
+ } tp_cluster[3]; /* Core Cluster n Topology Register */
+ u8 res_858[0x1000-0x858];
+};
+
+
+struct ccsr_clk_cluster_group {
+ struct {
+ u8 res_00[0x10];
+ u32 csr;
+ u8 res_14[0x20-0x14];
+ } hwncsr[3];
+ u8 res_60[0x80-0x60];
+ struct {
+ u32 gsr;
+ u8 res_84[0xa0-0x84];
+ } pllngsr[3];
+ u8 res_e0[0x100-0xe0];
+};
+
+struct ccsr_clk_ctrl {
+ struct {
+ u32 csr; /* core cluster n clock control status */
+ u8 res_04[0x20-0x04];
+ } clkcncsr[8];
+};
+
+struct ccsr_reset {
+ u32 rstcr; /* 0x000 */
+ u32 rstcrsp; /* 0x004 */
+ u8 res_008[0x10-0x08]; /* 0x008 */
+ u32 rstrqmr1; /* 0x010 */
+ u32 rstrqmr2; /* 0x014 */
+ u32 rstrqsr1; /* 0x018 */
+ u32 rstrqsr2; /* 0x01c */
+ u32 rstrqwdtmrl; /* 0x020 */
+ u32 rstrqwdtmru; /* 0x024 */
+ u8 res_028[0x30-0x28]; /* 0x028 */
+ u32 rstrqwdtsrl; /* 0x030 */
+ u32 rstrqwdtsru; /* 0x034 */
+ u8 res_038[0x60-0x38]; /* 0x038 */
+ u32 brrl; /* 0x060 */
+ u32 brru; /* 0x064 */
+ u8 res_068[0x80-0x68]; /* 0x068 */
+ u32 pirset; /* 0x080 */
+ u32 pirclr; /* 0x084 */
+ u8 res_088[0x90-0x88]; /* 0x088 */
+ u32 brcorenbr; /* 0x090 */
+ u8 res_094[0x100-0x94]; /* 0x094 */
+ u32 rcw_reqr; /* 0x100 */
+ u32 rcw_completion; /* 0x104 */
+ u8 res_108[0x110-0x108]; /* 0x108 */
+ u32 pbi_reqr; /* 0x110 */
+ u32 pbi_completion; /* 0x114 */
+ u8 res_118[0xa00-0x118]; /* 0x118 */
+ u32 qmbm_warmrst; /* 0xa00 */
+ u32 soc_warmrst; /* 0xa04 */
+ u8 res_a08[0xbf8-0xa08]; /* 0xa08 */
+ u32 ip_rev1; /* 0xbf8 */
+ u32 ip_rev2; /* 0xbfc */
+};
+#endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h b/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h
new file mode 100644
index 0000000..57e417b
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#ifndef __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__
+#define __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__
+
+#define I2C_QUIRK_REG /* enable 8-bit driver */
+
+#ifdef CONFIG_FSL_LPUART
+#ifdef CONFIG_LPUART_32B_REG
+struct lpuart_fsl {
+ u32 baud;
+ u32 stat;
+ u32 ctrl;
+ u32 data;
+ u32 match;
+ u32 modir;
+ u32 fifo;
+ u32 water;
+};
+#else
+struct lpuart_fsl {
+ u8 ubdh;
+ u8 ubdl;
+ u8 uc1;
+ u8 uc2;
+ u8 us1;
+ u8 us2;
+ u8 uc3;
+ u8 ud;
+ u8 uma1;
+ u8 uma2;
+ u8 uc4;
+ u8 uc5;
+ u8 ued;
+ u8 umodem;
+ u8 uir;
+ u8 reserved;
+ u8 upfifo;
+ u8 ucfifo;
+ u8 usfifo;
+ u8 utwfifo;
+ u8 utcfifo;
+ u8 urwfifo;
+ u8 urcfifo;
+ u8 rsvd[28];
+};
+#endif
+#endif /* CONFIG_FSL_LPUART */
+
+#endif /* __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ls2085a_stream_id.h b/arch/arm/include/asm/arch-fsl-layerscape/ls2085a_stream_id.h
new file mode 100644
index 0000000..5c94530
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ls2085a_stream_id.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+#ifndef __FSL_STREAM_ID_H
+#define __FSL_STREAM_ID_H
+
+/* Stream IDs on ls2085a devices are not hardwired and are
+ * programmed by sw. There are a limited number of stream IDs
+ * available, and the partitioning of them is scenario dependent.
+ * This header defines the partitioning between legacy, PCI,
+ * and DPAA2 devices.
+ *
+ * This partitiong can be customized in this file depending
+ * on the specific hardware config-- e.g. perhaps not all
+ * PEX controllers are in use.
+ *
+ * On LS2085 stream IDs are programmed in AMQ registers (32-bits) for
+ * each of the different bus masters. The relationship between
+ * the AMQ registers and stream IDs is defined in the table below:
+ * AMQ bit streamID bit
+ * ---------------------------
+ * PL[18] 9
+ * BMT[17] 8
+ * VA[16] 7
+ * [15] -
+ * ICID[14:7] -
+ * ICID[6:0] 6-0
+ * ----------------------------
+ */
+
+#define AMQ_PL_MASK (0x1 << 18) /* priviledge bit */
+#define AMQ_BMT_MASK (0x1 << 17) /* bypass bit */
+
+#define FSL_INVALID_STREAM_ID 0
+
+#define FSL_BYPASS_AMQ (AMQ_PL_MASK | AMQ_BMT_MASK)
+
+/* legacy devices */
+#define FSL_USB1_STREAM_ID 1
+#define FSL_USB2_STREAM_ID 2
+#define FSL_SDMMC_STREAM_ID 3
+#define FSL_SATA1_STREAM_ID 4
+#define FSL_SATA2_STREAM_ID 5
+#define FSL_DMA_STREAM_ID 6
+
+/* PCI - programmed in PEXn_LUT by OS */
+/* 4 IDs per controller */
+#define FSL_PEX1_STREAM_ID_START 7
+#define FSL_PEX1_STREAM_ID_END 10
+#define FSL_PEX2_STREAM_ID_START 11
+#define FSL_PEX2_STREAM_ID_END 14
+#define FSL_PEX3_STREAM_ID_START 15
+#define FSL_PEX3_STREAM_ID_END 18
+#define FSL_PEX4_STREAM_ID_START 19
+#define FSL_PEX4_STREAM_ID_END 22
+
+/* DPAA2 - set in MC DPC and alloced by MC */
+#define FSL_DPAA2_STREAM_ID_START 23
+#define FSL_DPAA2_STREAM_ID_END 63
+
+#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mmu.h b/arch/arm/include/asm/arch-fsl-layerscape/mmu.h
new file mode 100644
index 0000000..d54eacd
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/mmu.h
@@ -0,0 +1,10 @@
+/*
+ * Copyright 2015, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_
+#define _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_
+#include <asm/arch-armv8/mmu.h>
+#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
new file mode 100644
index 0000000..e46e076
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2014-2015, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _FSL_LAYERSCAPE_MP_H
+#define _FSL_LAYERSCAPE_MP_H
+
+/*
+* Each spin table element is defined as
+* struct {
+* uint64_t entry_addr;
+* uint64_t status;
+* uint64_t lpid;
+* };
+* we pad this struct to 64 bytes so each entry is in its own cacheline
+* the actual spin table is an array of these structures
+*/
+#define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX 0
+#define SPIN_TABLE_ELEM_STATUS_IDX 1
+#define SPIN_TABLE_ELEM_LPID_IDX 2
+#define WORDS_PER_SPIN_TABLE_ENTRY 8 /* pad to 64 bytes */
+#define SPIN_TABLE_ELEM_SIZE 64
+
+#define id_to_core(x) ((x & 3) | (x >> 6))
+#ifndef __ASSEMBLY__
+extern u64 __spin_table[];
+extern u64 __real_cntfrq;
+extern u64 *secondary_boot_code;
+extern size_t __secondary_boot_code_size;
+int fsl_layerscape_wake_seconday_cores(void);
+void *get_spin_tbl_addr(void);
+phys_addr_t determine_mp_bootpg(void);
+void secondary_boot_func(void);
+int is_core_online(u64 cpu_id);
+#endif
+#endif /* _FSL_LAYERSCAPE_MP_H */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
new file mode 100644
index 0000000..f131f57
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
+#define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
+
+#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
+#define gur_in32(a) in_le32(a)
+#define gur_out32(a, v) out_le32(a, v)
+#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
+#define gur_in32(a) in_be32(a)
+#define gur_out32(a, v) out_be32(a, v)
+#endif
+
+#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
+#define scfg_in32(a) in_le32(a)
+#define scfg_out32(a, v) out_le32(a, v)
+#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
+#define scfg_in32(a) in_be32(a)
+#define scfg_out32(a, v) out_be32(a, v)
+#endif
+
+struct cpu_type {
+ char name[15];
+ u32 soc_ver;
+ u32 num_cores;
+};
+
+#define CPU_TYPE_ENTRY(n, v, nc) \
+ { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
+
+#define SVR_WO_E 0xFFFFFE
+#define SVR_LS2045 0x870120
+#define SVR_LS2080 0x870110
+#define SVR_LS2085 0x870100
+
+#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
+#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
+#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
+#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
+
+void fsl_lsch3_early_init_f(void);
+void cpu_name(char *name);
+#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/speed.h b/arch/arm/include/asm/arch-fsl-layerscape/speed.h
new file mode 100644
index 0000000..de795f6
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/speed.h
@@ -0,0 +1,10 @@
+/*
+ * Copyright 2014-2015, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _FSL_LAYERSCAPE_SPEED_H
+#define _FSL_LAYERSCAPE_SPEED_H
+void get_sys_info(struct sys_info *sys_info);
+#endif /* _FSL_LAYERSCAPE_SPEED_H */