commit 0d4cee110b8a21479a49ed93592143177d2c7977
author Becky Bruce <beckyb@kernel.crashing.org> Thu Jun 17 11:37:20 2010 -0500
committer Kumar Gala <galak@kernel.crashing.org> Fri Jul 16 10:55:09 2010 -0500
tree 60b51af79796f061d119f2839d101f9584964dfc
parent dfe6e23895cdb989e2b42d1fc6fdc644ffd5a0e4

83xx/85xx/86xx: LBC register cleanup

Currently, 83xx, 86xx, and 85xx have a lot of duplicated code
dedicated to defining and manipulating the LBC registers.  Merge
this into a single spot.

To do this, we have to decide on a common name for the data structure
that holds the lbc registers - it will now be known as fsl_lbc_t, and we
adopt a common name for the immap layouts that include the lbc - this was
previously known as either im_lbc or lbus; use the former.

In addition, create accessors for the BR/OR regs that use in/out_be32
and use those instead of the mismash of access methods currently in play.

I have done a successful ppc build all and tested a board or two from
each processor family.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

nand_spl/nand_boot_fsl_elbc.c

diff --git a/nand_spl/nand_boot_fsl_elbc.c b/nand_spl/nand_boot_fsl_elbc.c
index ff47d55..9547d44 100644
--- a/nand_spl/nand_boot_fsl_elbc.c
+++ b/nand_spl/nand_boot_fsl_elbc.c
@@ -32,7 +32,7 @@
 
 static void nand_wait(void)
 {
-	fsl_lbus_t *regs = (fsl_lbus_t *)(CONFIG_SYS_IMMR + 0x5000);
+	fsl_lbc_t *regs = LBC_BASE_ADDR;
 
 	for (;;) {
 		uint32_t status = in_be32(&regs->ltesr);
@@ -49,7 +49,7 @@
 
 static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
 {
-	fsl_lbus_t *regs = (fsl_lbus_t *)(CONFIG_SYS_IMMR + 0x5000);
+	fsl_lbc_t *regs = LBC_BASE_ADDR;
 	uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
 	int large = in_be32(&regs->bank[0].or) & OR_FCM_PGS;
 	int block_shift = large ? 17 : 14;