imx: Add iMX91 support

iMX91 is reduced part from iMX93 with part number: i.MX9131/11/01
It removed A55_1, M33, MIPI DSI, LVDS, etc.

i.MX9131:
  - Support 2.4GT/s DDR and HWFFC at 1.2GT/s
i.MX9121:
  - A55 at 800Mhz and DDR at 1600MTS, with low drive mode.
i.MX9111:
  - Support 1.6GT/s DDR and HWFFC at 800MT/s
i.MX9101:
  - Support 800Mhz ARM clock
  - Support 1.6GT/s DDR and HWFFC at 800MT/s
  - No parallel display, eQOS, flexcan

Updated Clock/Container/CPU and etc for i.MX91

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index 2465e31..4554e21 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -16,6 +16,12 @@
 	select IMX9
 	select ARMV8_SPL_EXCEPTION_VECTORS
 
+config IMX91
+	bool
+	select IMX9
+	select ARMV8_SPL_EXCEPTION_VECTORS
+
+
 config SYS_SOC
 	default "imx9"
 
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index c00be19..e65cabe 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -30,6 +30,7 @@
 	INT_PLL_RATE(1400000000U, 1, 175, 3), /* 1.4Ghz */
 	INT_PLL_RATE(1000000000U, 1, 166, 4), /* 1000Mhz */
 	INT_PLL_RATE(900000000U, 1, 150, 4), /* 900Mhz */
+	INT_PLL_RATE(800000000U, 1, 200, 6), /* 800Mhz */
 };
 
 static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = {
@@ -37,12 +38,14 @@
 	FRAC_PLL_RATE(933000000U, 1, 155, 4, 1, 2), /* 933Mhz */
 	FRAC_PLL_RATE(800000000U, 1, 200, 6, 0, 1), /* 800Mhz */
 	FRAC_PLL_RATE(700000000U, 1, 145, 5, 5, 6), /* 700Mhz */
+	FRAC_PLL_RATE(600000000U, 1, 200, 8, 0, 1), /* 600Mhz */
 	FRAC_PLL_RATE(484000000U, 1, 121, 6, 0, 1),
 	FRAC_PLL_RATE(445333333U, 1, 167, 9, 0, 1),
 	FRAC_PLL_RATE(466000000U, 1, 155, 8, 1, 3), /* 466Mhz */
 	FRAC_PLL_RATE(400000000U, 1, 200, 12, 0, 1), /* 400Mhz */
 	FRAC_PLL_RATE(300000000U, 1, 150, 12, 0, 1),
 	FRAC_PLL_RATE(233000000U, 1, 174, 18, 3, 4), /* 233Mhz */
+	FRAC_PLL_RATE(200000000U, 1, 200, 24, 0, 1), /* 200Mhz */
 };
 
 /* return in khz */
@@ -723,7 +726,7 @@
 	/* SWO TRACE to 133M */
 	{SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
 	/* M33 systetick to 24M */
-	{M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1},
+	{M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1, CLK_SOC_IMX93},
 	/* NIC to 250M */
 	{NIC_CLK_ROOT, SYS_PLL_PFD0, 4},
 	/* NIC_APB to 133M */
@@ -753,13 +756,17 @@
 	 * WAKEUP_AXI to 312.5M, because of FEC only can support to 320M for
 	 * generating MII clock at 2.5M
 	 */
-	{WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2},
+	{WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2, CLK_SOC_IMX93},
+	/* Wakeup AXI 250M*/
+	{WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD0, 4, CLK_SOC_IMX91},
 	/* SWO TRACE to 133M */
 	{SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
 	/* M33 systetick to 24M */
-	{M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1},
+	{M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1, CLK_SOC_IMX93},
 	/* NIC to 400M */
-	{NIC_CLK_ROOT, SYS_PLL_PFD1, 2},
+	{NIC_CLK_ROOT, SYS_PLL_PFD1, 2, CLK_SOC_IMX93},
+	/* NIC to 333M */
+	{NIC_CLK_ROOT, SYS_PLL_PFD0, 3, CLK_SOC_IMX91},
 	/* NIC_APB to 133M */
 	{NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}
 };
@@ -769,8 +776,12 @@
 	int i;
 
 	for (i = 0; i < ARRAY_SIZE(imx_clk_ld_settings); i++) {
-		ccm_clk_root_cfg(imx_clk_ld_settings[i].clk_root,
-				 imx_clk_ld_settings[i].src, imx_clk_ld_settings[i].div);
+		if (imx_clk_ld_settings[i].soc == CLK_SOC_ALL ||
+		    (is_imx91() && imx_clk_ld_settings[i].soc == CLK_SOC_IMX91) ||
+		    (is_imx93() && imx_clk_ld_settings[i].soc == CLK_SOC_IMX93)) {
+			ccm_clk_root_cfg(imx_clk_ld_settings[i].clk_root,
+					 imx_clk_ld_settings[i].src, imx_clk_ld_settings[i].div);
+		}
 	}
 }
 
@@ -779,8 +790,12 @@
 	int i;
 
 	for (i = 0; i < ARRAY_SIZE(imx_clk_settings); i++) {
-		ccm_clk_root_cfg(imx_clk_settings[i].clk_root,
-				 imx_clk_settings[i].src, imx_clk_settings[i].div);
+		if (imx_clk_settings[i].soc == CLK_SOC_ALL ||
+		    (is_imx91() && imx_clk_settings[i].soc == CLK_SOC_IMX91) ||
+		    (is_imx93() && imx_clk_settings[i].soc == CLK_SOC_IMX93)) {
+			ccm_clk_root_cfg(imx_clk_settings[i].clk_root,
+					 imx_clk_settings[i].src, imx_clk_settings[i].div);
+		}
 	}
 }
 
@@ -857,7 +872,7 @@
 	return ccm_clk_root_get_rate(WAKEUP_AXI_CLK_ROOT);
 }
 
-#if defined(CONFIG_IMX93) && defined(CONFIG_DWC_ETH_QOS)
+#if (CONFIG_IS_ENABLED(IMX93) || CONFIG_IS_ENABLED(IMX91)) && CONFIG_IS_ENABLED(DWC_ETH_QOS)
 static int imx93_eqos_interface_init(struct udevice *dev, phy_interface_t interface_type)
 {
 	struct blk_ctrl_wakeupmix_regs *bctrl =
@@ -901,12 +916,12 @@
 
 int board_interface_eth_init(struct udevice *dev, phy_interface_t interface_type)
 {
-	if (IS_ENABLED(CONFIG_IMX93) &&
+	if ((IS_ENABLED(CONFIG_IMX93) || IS_ENABLED(CONFIG_IMX91)) &&
 	    IS_ENABLED(CONFIG_DWC_ETH_QOS) &&
 	    device_is_compatible(dev, "nxp,imx93-dwmac-eqos"))
 		return imx93_eqos_interface_init(dev, interface_type);
 
-	if (IS_ENABLED(CONFIG_IMX93) &&
+	if ((IS_ENABLED(CONFIG_IMX93) || IS_ENABLED(CONFIG_IMX91)) &&
 	    IS_ENABLED(CONFIG_FEC_MXC) &&
 	    device_is_compatible(dev, "fsl,imx93-fec"))
 		return 0;
diff --git a/arch/arm/mach-imx/imx9/container.cfg b/arch/arm/mach-imx/imx9/container.cfg
index 72fe791..91a9731 100644
--- a/arch/arm/mach-imx/imx9/container.cfg
+++ b/arch/arm/mach-imx/imx9/container.cfg
@@ -6,6 +6,10 @@
 BOOT_FROM SD 0x400
 SOC_TYPE IMX9
 CONTAINER
+#ifdef CONFIG_IMX91
+IMAGE A55 bl31.bin 0x204C0000
+#else
 IMAGE A55 bl31.bin 0x204E0000
+#endif
 IMAGE A55 u-boot.bin CONFIG_TEXT_BASE
-IMAGE A55 tee.bin 0x96000000
\ No newline at end of file
+IMAGE A55 tee.bin 0x96000000
diff --git a/arch/arm/mach-imx/imx9/imximage.cfg b/arch/arm/mach-imx/imx9/imximage.cfg
index d327d6a..118dfb3 100644
--- a/arch/arm/mach-imx/imx9/imximage.cfg
+++ b/arch/arm/mach-imx/imx9/imximage.cfg
@@ -5,6 +5,10 @@
 
 BOOT_FROM SD 0x400
 SOC_TYPE IMX9
+#ifdef CONFIG_IMX91
+APPEND mx91a0-ahab-container.img
+#else
 APPEND mx93a1-ahab-container.img
+#endif
 CONTAINER
-IMAGE A55 u-boot-spl-ddr.bin 0x2049A000
\ No newline at end of file
+IMAGE A55 u-boot-spl-ddr.bin CONFIG_SPL_TEXT_BASE
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index d30a3b0..bb13ca7 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -118,6 +118,8 @@
 
 	if (is_imx93())
 		max_speed = MHZ(1700);
+	else if (is_imx91())
+		max_speed = MHZ(1400);
 
 	/* In case the fuse of speed grade not programmed */
 	if (speed > max_speed)
@@ -196,6 +198,29 @@
 	bool npu_disable = !!(val & BIT(13));
 	bool core1_disable = !!(val & BIT(15));
 	u32 pack_9x9_fused = BIT(4) | BIT(5) | BIT(17) | BIT(19) | BIT(24);
+	u32 nxp_recog = (val & GENMASK(23, 16)) >> 16;
+
+	/* For iMX91 */
+	if (type == MXC_CPU_IMX91) {
+		switch (nxp_recog) {
+		case 0x9:
+		case 0xA:
+			type = MXC_CPU_IMX9111;
+			break;
+		case 0xD:
+		case 0xE:
+			type = MXC_CPU_IMX9121;
+			break;
+		case 0xF:
+		case 0x10:
+			type = MXC_CPU_IMX9101;
+			break;
+		default:
+			break;	/* 9131 as default */
+		}
+
+		return type;
+	}
 
 	/* Low performance 93 part */
 	if (((val >> 6) & 0x3F) == 0xE && npu_disable)
@@ -217,8 +242,14 @@
 u32 get_cpu_rev(void)
 {
 	u32 rev = (gd->arch.soc_rev >> 24) - 0xa0;
+	u32 type;
+
+	if ((gd->arch.soc_rev & 0xFFFF) == 0x9300)
+		type = MXC_CPU_IMX93;
+	else
+		type = MXC_CPU_IMX91;
 
-	return (get_cpu_variant_type(MXC_CPU_IMX93) << 12) |
+	return (get_cpu_variant_type(type) << 12) |
 		(CHIP_REV_1_0 + rev);
 }
 
@@ -539,7 +570,8 @@
 
 	cpurev = get_cpu_rev();
 
-	printf("CPU:   i.MX93 rev%d.%d\n", (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0);
+	printf("CPU:   i.MX%s rev%d.%d\n", is_imx93() ? "93" : "91",
+	       (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0);
 
 	return 0;
 }
@@ -893,7 +925,9 @@
 void soc_power_init(void)
 {
 	mix_power_init(MIX_PD_MEDIAMIX);
-	mix_power_init(MIX_PD_MLMIX);
+
+	if (is_imx93())
+		mix_power_init(MIX_PD_MLMIX);
 
 	disable_isolation();
 }
@@ -919,6 +953,9 @@
 			(struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR;
 	u32 val, i;
 
+	if (is_imx91())
+		return -ENODEV;
+
 	if (m33_is_rom_kicked())
 		return -EPERM;
 
@@ -1007,7 +1044,7 @@
 	u32 speed = get_cpu_speed_grade_hz();
 	enum imx9_soc_voltage_mode voltage = VOLT_OVER_DRIVE;
 
-	if (is_imx93()) {
+	if (is_imx93() || is_imx91()) {
 		if (speed == 1700000000)
 			voltage = VOLT_OVER_DRIVE;
 		else if (speed == 1400000000)