| commit | 9af122bf4e405e95a03779777abdb1a097dc8b2e | [log] [tgz] |
|---|---|---|
| author | Fabio Estevam <fabio.estevam@freescale.com> | Tue Mar 13 07:26:48 2012 +0000 |
| committer | Stefano Babic <sbabic@denx.de> | Tue Mar 27 09:41:16 2012 +0200 |
| tree | 120ab774df6120121c3124f4e029bb4b7feff53f | |
| parent | df86a00482afb477f839c10df83a7e8e3a0eddbc [diff] |
mx6: Fix reset cause for Power On Reset case After booting mx6qsabrelite from POR the following is reported: CPU: Freescale i.MX61 family rev1.0 at 792 MHz Reset cause: unknown reset This is because both the POR and WDOG bits are set after reset. Fix this by also checking both bits in the POR case. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>