Add support for Freescale M5271 processor
diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c
index 32a524f..302832b 100644
--- a/cpu/mcf52x2/cpu.c
+++ b/cpu/mcf52x2/cpu.c
@@ -25,6 +25,11 @@
#include <watchdog.h>
#include <command.h>
+#ifdef CONFIG_M5271
+#include <asm/immap_5271.h>
+#include <asm/m5271.h>
+#endif
+
#ifdef CONFIG_M5272
#include <asm/immap_5272.h>
#include <asm/m5272.h>
@@ -38,6 +43,41 @@
#include <asm/m5249.h>
#endif
+#ifdef CONFIG_M5271
+int checkcpu (void)
+{
+ puts ("CPU: MOTOROLA Coldfire MCF5271\n");
+ return 0;
+}
+
+int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) {
+ mbar_writeByte(MCF_RCM_RCR,
+ MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
+ return 0;
+};
+
+#if defined(CONFIG_WATCHDOG)
+void watchdog_reset (void)
+{
+ mbar_writeShort(MCF_WTM_WSR, 0x5555);
+ mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
+}
+
+int watchdog_disable (void)
+{
+ mbar_writeShort(MCF_WTM_WCR, 0);
+ return (0);
+}
+
+int watchdog_init (void)
+{
+ mbar_writeShort(MCF_WTM_WCNTR, CONFIG_WATCHDOG_TIMEOUT);
+ mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
+ return (0);
+}
+#endif /* #ifdef CONFIG_WATCHDOG */
+
+#endif
#ifdef CONFIG_M5272
int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) {
diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index 350c431..d33adc2 100644
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
@@ -24,6 +24,11 @@
#include <common.h>
#include <watchdog.h>
+#ifdef CONFIG_M5271
+#include <asm/m5271.h>
+#include <asm/immap_5271.h>
+#endif
+
#ifdef CONFIG_M5272
#include <asm/m5272.h>
#include <asm/immap_5272.h>
@@ -38,6 +43,38 @@
#include <asm/m5249.h>
#endif
+#if defined(CONFIG_M5271)
+void cpu_init_f (void)
+{
+#ifndef CONFIG_WATCHDOG
+ /* Disable the watchdog if we aren't using it */
+ mbar_writeShort(MCF_WTM_WCR, 0);
+#endif
+
+ /* Set clockspeed to 100MHz */
+ mbar_writeShort(MCF_FMPLL_SYNCR,
+ MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
+ while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK);
+
+ /* Enable UART pins */
+ mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
+ MCF_GPIO_PAR_UART_U0RXD |
+ MCF_GPIO_PAR_UART_U1RXD_UART1 |
+ MCF_GPIO_PAR_UART_U1TXD_UART1);
+
+ /* Enable Ethernet pins */
+ mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C);
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r (void)
+{
+ return (0);
+}
+#endif
+
#if defined(CONFIG_M5272)
/*
* Breath some life into the CPU...
diff --git a/cpu/mcf52x2/fec.c b/cpu/mcf52x2/fec.c
index a5c50af..f207dd6 100644
--- a/cpu/mcf52x2/fec.c
+++ b/cpu/mcf52x2/fec.c
@@ -25,6 +25,11 @@
#include <malloc.h>
#include <asm/fec.h>
+#ifdef CONFIG_M5271
+#include <asm/m5271.h>
+#include <asm/immap_5271.h>
+#endif
+
#ifdef CONFIG_M5272
#include <asm/m5272.h>
#include <asm/immap_5272.h>
@@ -41,7 +46,7 @@
#ifdef CONFIG_M5272
#define FEC_ADDR (CFG_MBAR + 0x840)
#endif
-#ifdef CONFIG_M5282
+#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
#define FEC_ADDR (CFG_MBAR + 0x1000)
#endif
@@ -240,10 +245,22 @@
#endif
#undef ea
+#ifdef CONFIG_M5271
+ /* Clear multicast address hash table
+ */
+ fecp->fec_ghash_table_high = 0;
+ fecp->fec_ghash_table_low = 0;
+
+ /* Clear individual address hash table
+ */
+ fecp->fec_ihash_table_high = 0;
+ fecp->fec_ihash_table_low = 0;
+#else
/* Clear multicast address hash table
*/
fecp->fec_hash_table_high = 0;
fecp->fec_hash_table_low = 0;
+#endif
/* Set maximum receive buffer size.
*/
@@ -295,6 +312,9 @@
fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;
#else /* Half duplex mode */
fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
+#ifdef CONFIG_M5271
+ fecp->fec_r_cntrl |= (PKT_MAXBUF_SIZE << 16); /* set max frame length */
+#endif
fecp->fec_x_cntrl = 0;
#endif
/* Set MII speed */
diff --git a/cpu/mcf52x2/interrupts.c b/cpu/mcf52x2/interrupts.c
index 868df39..116747a 100644
--- a/cpu/mcf52x2/interrupts.c
+++ b/cpu/mcf52x2/interrupts.c
@@ -27,6 +27,11 @@
#include <watchdog.h>
#include <asm/processor.h>
+#ifdef CONFIG_M5271
+#include <asm/m5271.h>
+#include <asm/immap_5271.h>
+#endif
+
#ifdef CONFIG_M5272
#include <asm/m5272.h>
#include <asm/immap_5272.h>
@@ -171,7 +176,7 @@
}
#endif
-#ifdef CONFIG_M5282
+#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
int interrupt_init (void)
{
return 0;
diff --git a/cpu/mcf52x2/serial.c b/cpu/mcf52x2/serial.c
index c730922..641f0d9 100644
--- a/cpu/mcf52x2/serial.c
+++ b/cpu/mcf52x2/serial.c
@@ -26,6 +26,10 @@
#include <asm/mcfuart.h>
+#ifdef CONFIG_M5271
+#include <asm/m5271.h>
+#endif
+
#ifdef CONFIG_M5272
#include <asm/m5272.h>
#endif
@@ -46,7 +50,7 @@
void rs_serial_setbaudrate(int port,int baudrate)
{
-#if defined(CONFIG_M5272) || defined(CONFIG_M5249)
+#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5271)
volatile unsigned char *uartp;
double clock, fraction;
@@ -61,8 +65,10 @@
uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */
uartp[MCFUART_UBG2] = ((int)clock & 0xff); /* set lsb baud */
+#ifndef CONFIG_M5271
uartp[MCFUART_UFPD] = ((int)fraction & 0xf); /* set baud fraction adjust */
#endif
+#endif
};
void rs_serial_init(int port,int baudrate)
diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S
index b4926e2..8ae9591 100644
--- a/cpu/mcf52x2/start.S
+++ b/cpu/mcf52x2/start.S
@@ -55,7 +55,11 @@
*/
_vectors:
+#ifndef CONFIG_M5271
.long 0x00000000, _START
+#else
+.long 0x00000000, 0x400 /* Flash offset is 0 until we setup CS0 */
+#endif
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
@@ -124,26 +128,42 @@
movec %d0, %RAMBAR0
#endif /* #if defined(CONFIG_M5272) || defined(CONFIG_M5249) */
-#ifdef CONFIG_M5282
+#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
/* Initialize IPSBAR */
move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
move.l %d0, 0x40000000
+#ifdef CONFIG_M5282
/* Initialize FLASHBAR: locate internal Flash and validate it */
move.l #(CFG_INT_FLASH_BASE + 0x21), %d0
movec %d0, %RAMBAR0
+#endif
/* Initialize RAMBAR1: locate SRAM and validate it */
move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
movec %d0, %RAMBAR1
+#ifdef CONFIG_M5271
+ move.l #(_flash_setup-CFG_FLASH_BASE), %a0
+ move.l #(_flash_setup_end-CFG_FLASH_BASE), %a1
+ move.l #(CFG_INIT_RAM_ADDR), %a2
+_copy_flash:
+ move.l (%a0)+, (%a2)+
+ cmp.l %a0, %a1
+ bgt.s _copy_flash
#endif
+ jmp CFG_INIT_RAM_ADDR
+_after_flash_copy:
+#endif
+
+#if 0
/* invalidate and disable cache */
move.l #0x01000000, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
move.l #0, %d0
movec %d0, %ACR0
movec %d0, %ACR1
+#endif
/* set stackpointer to end of internal ram to get some stackspace for the first c-code */
move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
@@ -158,6 +178,18 @@
/*------------------------------------------------------------------------------*/
+#ifdef CONFIG_M5271
+_flash_setup:
+ move.l #0x1000, %d0
+ move.w %d0, 0x40000080
+ move.l #0x2180, %d0
+ move.w %d0, 0x4000008A
+ move.l #0x3f0001, %d0
+ move.l %d0, 0x40000084
+ jmp _after_flash_copy.L
+_flash_setup_end:
+#endif
+
/*
* void relocate_code (addr_sp, gd, addr_moni)
*