Set SDelay register in the DDR controller for the MPC5200B chip.
diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c
index 44831c6..4197a7c 100644
--- a/board/icecube/icecube.c
+++ b/board/icecube/icecube.c
@@ -27,6 +27,7 @@
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
+#include <asm/processor.h>
#if defined(CONFIG_LITE5200B)
#include "mt46v32m16.h"
@@ -89,6 +90,8 @@
{
ulong dramsize = 0;
ulong dramsize2 = 0;
+ uint svr, pvr;
+
#ifndef CFG_RAMBOOT
ulong test1, test2;
@@ -183,6 +186,24 @@
#endif /* CFG_RAMBOOT */
+ /*
+ * On MPC5200B we need to set the special configuration delay in the
+ * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+ * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+ *
+ * "The SDelay should be written to a value of 0x00000004. It is
+ * required to account for changes caused by normal wafer processing
+ * parameters."
+ */
+ svr = get_svr();
+ pvr = get_pvr();
+ if ((SVR_MJREV(svr) >= 2) &&
+ (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+ *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+ __asm__ volatile ("sync");
+ }
+
return dramsize + dramsize2;
}
diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c
index 2d695d1..8d1e7c6 100644
--- a/cpu/mpc5xxx/cpu.c
+++ b/cpu/mpc5xxx/cpu.c
@@ -38,7 +38,7 @@
ulong clock = gd->cpu_clk;
char buf[32];
#ifndef CONFIG_MGT5100
- uint svr;
+ uint svr, pvr;
#endif
puts ("CPU: ");
@@ -47,7 +47,8 @@
puts (CPU_ID_STR);
printf (" (JTAG ID %08lx)", *(vu_long *)MPC5XXX_CDM_JTAGID);
#else
- svr = get_svr ();
+ svr = get_svr();
+ pvr = get_pvr();
switch (SVR_VER (svr)) {
case SVR_MPC5200:
printf ("MPC5200");
@@ -57,11 +58,10 @@
break;
}
- printf (" v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr));
+ printf (" v%d.%d, Core v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr),
+ PVR_MAJ(pvr), PVR_MIN(pvr));
#endif
-
printf (" at %s MHz\n", strmhz (buf, clock));
-
return 0;
}
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
index 596e52c..1152f83 100644
--- a/include/configs/IceCube.h
+++ b/include/configs/IceCube.h
@@ -56,7 +56,9 @@
* 0x40000000 - 0x4fffffff - PCI Memory
* 0x50000000 - 0x50ffffff - PCI IO Space
*/
-#define CONFIG_PCI 1
+#define CONFIG_PCI
+
+#if defined(CONFIG_PCI)
#define CONFIG_PCI_PNP 1
#define CONFIG_PCI_SCAN_SHOW 1
@@ -67,6 +69,8 @@
#define CONFIG_PCI_IO_BUS 0x50000000
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x01000000
+#define ADD_PCI_CMD CFG_CMD_PCI
+#endif
#define CFG_XLB_PIPELINING 1
@@ -76,8 +80,6 @@
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
-#define ADD_PCI_CMD CFG_CMD_PCI
-
#else /* MPC5100 */
#define CONFIG_MII 1
diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h
index f33d858..50a6ac1 100644
--- a/include/mpc5xxx.h
+++ b/include/mpc5xxx.h
@@ -131,6 +131,7 @@
#if defined(CONFIG_MGT5100)
#define MPC5XXX_SDRAM_XLBSEL (MPC5XXX_SDRAM + 0x0010)
#endif
+#define MPC5XXX_SDRAM_SDELAY (MPC5XXX_SDRAM + 0x0090)
/* Clock Distribution Module */
#define MPC5XXX_CDM_JTAGID (MPC5XXX_CDM + 0x0000)