diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index d3e7b4d..5d96454 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -1,7 +1,7 @@
 variables:
   windows_vm: vs2017-win2016
   ubuntu_vm: ubuntu-18.04
-  ci_runner_image: trini/u-boot-gitlab-ci-runner:bionic-20200311-10Apr2020
+  ci_runner_image: trini/u-boot-gitlab-ci-runner:bionic-20200403-27Apr2020
   # Add '-u 0' options for Azure pipelines, otherwise we get "permission
   # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
   # since our $(ci_runner_image) user is not root.
@@ -161,7 +161,7 @@
           TEST_PY_BD: "sandbox"
         sandbox_clang:
           TEST_PY_BD: "sandbox"
-          OVERRIDE: "-O clang-7"
+          OVERRIDE: "-O clang-10"
         sandbox_spl:
           TEST_PY_BD: "sandbox_spl"
           TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff"
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 08bdf81..beaf9b9 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -2,7 +2,7 @@
 
 # Grab our configured image.  The source for this is found at:
 # https://gitlab.denx.de/u-boot/gitlab-ci-runner
-image: trini/u-boot-gitlab-ci-runner:bionic-20200311-10Apr2020
+image: trini/u-boot-gitlab-ci-runner:bionic-20200403-27Apr2020
 
 # We run some tests in different order, to catch some failures quicker.
 stages:
@@ -181,7 +181,7 @@
   tags: [ 'all' ]
   variables:
     TEST_PY_BD: "sandbox"
-    OVERRIDE: "-O clang-7"
+    OVERRIDE: "-O clang-10"
   <<: *buildman_and_testpy_dfn
 
 sandbox_spl test.py:
diff --git a/.readthedocs.yml b/.readthedocs.yml
new file mode 100644
index 0000000..44949ea
--- /dev/null
+++ b/.readthedocs.yml
@@ -0,0 +1,19 @@
+# .readthedocs.yml
+# Read the Docs configuration file
+# See https://docs.readthedocs.io/en/stable/config-file/v2.html for details
+
+# Required
+version: 2
+
+# Build documentation in the docs/ directory with Sphinx
+sphinx:
+  configuration: doc/conf.py
+
+# Optionally build your docs in additional formats such as PDF and ePub
+formats: []
+
+# Optionally set the version of Python and requirements required to build your docs
+# python:
+#   version: 3.7
+#   install:
+#     - requirements: docs/requirements.txt
diff --git a/.travis.yml b/.travis.yml
index 82e3b91..fbfaaaf 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -10,9 +10,10 @@
 
 addons:
   apt:
+    update: true
     sources:
-    - ubuntu-toolchain-r-test
-    - llvm-toolchain-bionic-7
+    - sourceline: 'deb http://apt.llvm.org/bionic/ llvm-toolchain-bionic-10 main'
+      key_url: 'https://apt.llvm.org/llvm-snapshot.gpg.key'
     packages:
     - autopoint
     - cppcheck
@@ -38,7 +39,7 @@
     - liblz4-tool
     - lzma-alone
     - libisl15
-    - clang-7
+    - clang-10
     - srecord
     - graphviz
     - coreutils
@@ -57,7 +58,7 @@
  - ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
  # prepare buildman environment
  - echo -e "[toolchain]\nroot = /usr" > ~/.buildman
- - echo -e "arc = /tmp/arc_gnu_2018.09_prebuilt_uclibc_le_archs_linux_install" >> ~/.buildman
+ - echo -e "arc = /tmp/arc_gnu_2019.09_prebuilt_uclibc_le_archs_linux_install" >> ~/.buildman
  - echo -e "\n[toolchain-alias]\nsh = sh2" >> ~/.buildman
  - echo -e "x86 = i386" >> ~/.buildman;
  - echo -e "riscv = riscv64" >> ~/.buildman;
@@ -86,8 +87,8 @@
       ./tools/buildman/buildman --fetch-arch i386;
     fi
   - if [[ "${TOOLCHAIN}" == arc ]]; then
-       wget https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/download/arc-2018.09-release/arc_gnu_2018.09_prebuilt_uclibc_le_archs_linux_install.tar.gz &&
-       tar -C /tmp -xf arc_gnu_2018.09_prebuilt_uclibc_le_archs_linux_install.tar.gz;
+       wget https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/download/arc-2019.09-release/arc_gnu_2019.09_prebuilt_uclibc_le_archs_linux_install.tar.gz &&
+       tar -C /tmp -xf arc_gnu_2019.09_prebuilt_uclibc_le_archs_linux_install.tar.gz;
     fi
   - if [[ "${TOOLCHAIN}" == "nds32" ]]; then
        wget https://github.com/vincentzwc/prebuilt-nds32-toolchain/releases/download/20180521/nds32le-linux-glibc-v3-upstream.tar.gz &&
@@ -499,7 +500,7 @@
     - name: "test/py sandbox with clang"
       env:
         - TEST_PY_BD="sandbox"
-          OVERRIDE="-O clang-7"
+          OVERRIDE="-O clang-10"
     - name: "test/py sandbox_spl"
       env:
         - TEST_PY_BD="sandbox_spl"
diff --git a/Kbuild b/Kbuild
index 6014f7c..1eac091 100644
--- a/Kbuild
+++ b/Kbuild
@@ -10,7 +10,7 @@
 always  := $(generic-offsets-file)
 targets := lib/asm-offsets.s
 
-$(obj)/$(generic-offsets-file): lib/asm-offsets.s FORCE
+$(obj)/$(generic-offsets-file): $(obj)/lib/asm-offsets.s FORCE
 	$(call filechk,offsets,__GENERIC_ASM_OFFSETS_H__)
 
 #####
@@ -25,5 +25,5 @@
 
 CFLAGS_asm-offsets.o := -DDO_DEPS_ONLY
 
-$(obj)/$(offsets-file): arch/$(ARCH)/lib/asm-offsets.s FORCE
+$(obj)/$(offsets-file): $(obj)/arch/$(ARCH)/lib/asm-offsets.s FORCE
 	$(call filechk,offsets,__ASM_OFFSETS_H__)
diff --git a/Kconfig b/Kconfig
index 9a5e600..15f1a75 100644
--- a/Kconfig
+++ b/Kconfig
@@ -209,6 +209,20 @@
 	  When disabling this, please check if malloc calls, maybe
 	  should be replaced by calloc - if one expects zeroed memory.
 
+config SYS_MALLOC_DEFAULT_TO_INIT
+	bool "Default malloc to init while reserving the memory for it"
+	default n
+	help
+	  It may happen that one needs to move the dynamic allocation
+	  from one to another memory range, eg. when moving the malloc
+	  from the limited static to a potentially large dynamic (DDR)
+	  memory.
+
+	  If so then on top of setting the updated memory aside one
+	  needs to bring the malloc init.
+
+	  If such a scenario is sought choose yes.
+
 config TOOLS_DEBUG
 	bool "Enable debug information for tools"
 	help
diff --git a/MAINTAINERS b/MAINTAINERS
index dd92af5..66f0b07 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -625,6 +625,7 @@
 F:	lib/charset.c
 F:	lib/efi*/
 F:	test/py/tests/test_efi*
+F:	test/py/tests/test_efi*/
 F:	test/unicode_ut.c
 F:	cmd/bootefi.c
 F:	cmd/efidebug.c
diff --git a/Makefile b/Makefile
index b8a4b50..6bb9cf5 100644
--- a/Makefile
+++ b/Makefile
@@ -1,9 +1,9 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 VERSION = 2020
-PATCHLEVEL = 04
+PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
 NAME =
 
 # *DOCUMENTATION*
@@ -512,7 +512,7 @@
 
 no-dot-config-targets := clean clobber mrproper distclean \
 			 help %docs check% coccicheck \
-			 ubootversion backup tests check qcheck
+			 ubootversion backup tests check qcheck tcheck
 
 config-targets := 0
 mixed-targets  := 0
@@ -1002,6 +1002,9 @@
 quiet_cmd_pad_cat = CAT     $@
 cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@
 
+quiet_cmd_lzma = LZMA    $@
+cmd_lzma = lzma -c -z -k -9 $< > $@
+
 cfg: u-boot.cfg
 
 quiet_cmd_cfgcheck = CFGCHK  $2
@@ -1322,7 +1325,9 @@
 # Boards with more complex image requirements can provide an .its source file
 # or a generator script
 ifneq ($(CONFIG_SPL_FIT_SOURCE),"")
-U_BOOT_ITS = $(subst ",,$(CONFIG_SPL_FIT_SOURCE))
+U_BOOT_ITS := u-boot.its
+$(U_BOOT_ITS): $(subst ",,$(CONFIG_SPL_FIT_SOURCE))
+	$(call if_changed,copy)
 else
 ifneq ($(CONFIG_SPL_FIT_GENERATOR),"")
 U_BOOT_ITS := u-boot.its
@@ -1384,6 +1389,16 @@
 UBOOT_BIN := u-boot.bin
 endif
 
+MKIMAGEFLAGS_u-boot-lzma.img = -A $(ARCH) -T standalone -C lzma -O u-boot \
+	-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
+
+u-boot.bin.lzma: u-boot.bin FORCE
+	$(call if_changed,lzma)
+
+u-boot-lzma.img: u-boot.bin.lzma FORCE
+	$(call if_changed,mkimage)
+
 u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \
 		$(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin \
 			$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE),dts/dt.dtb) \
@@ -2098,6 +2113,7 @@
 	@echo  ''
 	@echo  '  check           - Run all automated tests that use sandbox'
 	@echo  '  qcheck          - Run quick automated tests that use sandbox'
+	@echo  '  tcheck          - Run quick automated tests on tools'
 	@echo  ''
 	@echo  'Other generic targets:'
 	@echo  '  all		  - Build all necessary images depending on configuration'
@@ -2143,6 +2159,9 @@
 qcheck:
 	$(srctree)/test/run quick
 
+tcheck:
+	$(srctree)/test/run tools
+
 # Documentation targets
 # ---------------------------------------------------------------------------
 DOC_TARGETS := xmldocs latexdocs pdfdocs htmldocs epubdocs cleandocs \
diff --git a/README b/README
index 0834850..2e8ad3b 100644
--- a/README
+++ b/README
@@ -896,8 +896,6 @@
 
 		CONFIG_TULIP
 		Support for Digital 2114x chips.
-		Optional CONFIG_TULIP_SELECT_MEDIA for board specific
-		modem chip initialisation (KS8761/QS6611).
 
 		CONFIG_NATSEMI
 		Support for National dp83815 chips.
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 545fc3e..6ff201f 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -164,18 +164,16 @@
 
 config TARGET_AXS101
 	bool "Support Synopsys Designware SDP board AXS101"
-	select BOUNCE_BUFFER if CMD_NAND
 
 config TARGET_AXS103
 	bool "Support Synopsys Designware SDP board AXS103"
-	select BOUNCE_BUFFER if CMD_NAND
 
 config TARGET_EMSDP
 	bool "Synopsys EM Software Development Platform"
 	select CPU_ARCEM6
 
 config TARGET_HSDK
-	bool "Support Synpsys HS DevelopmentKit board"
+	bool "Support Synopsys HSDK or HSDK-4xD board"
 
 config TARGET_IOT_DEVKIT
 	bool "Synopsys Brite IoT Development kit"
diff --git a/arch/arc/dts/Makefile b/arch/arc/dts/Makefile
index 4f1e463..515fe1f 100644
--- a/arch/arc/dts/Makefile
+++ b/arch/arc/dts/Makefile
@@ -5,7 +5,7 @@
 dtb-$(CONFIG_TARGET_NSIM) +=  nsim.dtb
 dtb-$(CONFIG_TARGET_TB100) +=  abilis_tb100.dtb
 dtb-$(CONFIG_TARGET_EMSDP) +=  emsdp.dtb
-dtb-$(CONFIG_TARGET_HSDK) +=  hsdk.dtb
+dtb-$(CONFIG_TARGET_HSDK) +=  hsdk.dtb hsdk-4xd.dtb
 dtb-$(CONFIG_TARGET_IOT_DEVKIT) +=  iot_devkit.dtb
 
 targets += $(dtb-y)
diff --git a/arch/arc/dts/hsdk-4xd.dts b/arch/arc/dts/hsdk-4xd.dts
new file mode 100644
index 0000000..b245eea
--- /dev/null
+++ b/arch/arc/dts/hsdk-4xd.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ */
+/dts-v1/;
+
+#include "hsdk-common.dtsi"
+
+/ {
+	model = "snps,hsdk-4xd";
+};
diff --git a/arch/arc/dts/hsdk-common.dtsi b/arch/arc/dts/hsdk-common.dtsi
new file mode 100644
index 0000000..fd4245e
--- /dev/null
+++ b/arch/arc/dts/hsdk-common.dtsi
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017-2020 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ */
+/dts-v1/;
+
+#include "skeleton.dtsi"
+#include "dt-bindings/clock/snps,hsdk-cgu.h"
+#include "dt-bindings/reset/snps,hsdk-reset.h"
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		console = &uart0;
+		spi0 = &spi0;
+	};
+
+	cpu_card {
+		core_clk: core_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <500000000>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	clk-fmeas {
+		clocks = <&cgu_clk CLK_ARC_PLL>, <&cgu_clk CLK_SYS_PLL>,
+			 <&cgu_clk CLK_TUN_PLL>, <&cgu_clk CLK_DDR_PLL>,
+			 <&cgu_clk CLK_ARC>, <&cgu_clk CLK_HDMI_PLL>,
+			 <&cgu_clk CLK_TUN_TUN>, <&cgu_clk CLK_HDMI>,
+			 <&cgu_clk CLK_SYS_APB>, <&cgu_clk CLK_SYS_AXI>,
+			 <&cgu_clk CLK_SYS_ETH>, <&cgu_clk CLK_SYS_USB>,
+			 <&cgu_clk CLK_SYS_SDIO>, <&cgu_clk CLK_SYS_HDMI>,
+			 <&cgu_clk CLK_SYS_GFX_CORE>, <&cgu_clk CLK_SYS_GFX_DMA>,
+			 <&cgu_clk CLK_SYS_GFX_CFG>, <&cgu_clk CLK_SYS_DMAC_CORE>,
+			 <&cgu_clk CLK_SYS_DMAC_CFG>, <&cgu_clk CLK_SYS_SDIO_REF>,
+			 <&cgu_clk CLK_SYS_SPI_REF>, <&cgu_clk CLK_SYS_I2C_REF>,
+			 <&cgu_clk CLK_SYS_UART_REF>, <&cgu_clk CLK_SYS_EBI_REF>,
+			 <&cgu_clk CLK_TUN_ROM>, <&cgu_clk CLK_TUN_PWM>,
+			 <&cgu_clk CLK_TUN_TIMER>;
+		clock-names = "cpu-pll", "sys-pll",
+			      "tun-pll", "ddr-clk",
+			      "cpu-clk", "hdmi-pll",
+			      "tun-clk", "hdmi-clk",
+			      "apb-clk", "axi-clk",
+			      "eth-clk", "usb-clk",
+			      "sdio-clk", "hdmi-sys-clk",
+			      "gfx-core-clk", "gfx-dma-clk",
+			      "gfx-cfg-clk", "dmac-core-clk",
+			      "dmac-cfg-clk", "sdio-ref-clk",
+			      "spi-clk", "i2c-clk",
+			      "uart-clk", "ebi-clk",
+			      "rom-clk", "pwm-clk",
+			      "timer-clk";
+	};
+
+	cgu_clk: cgu-clk@f0000000 {
+		compatible = "snps,hsdk-cgu-clock";
+		reg = <0xf0000000 0x10>, <0xf00014B8 0x4>;
+		#clock-cells = <1>;
+	};
+
+	cgu_rst: reset-controller@f00008a0 {
+		compatible = "snps,hsdk-reset";
+		#reset-cells = <1>;
+		reg = <0xf00008a0 0x4>, <0xf0000ff0 0x4>;
+	};
+
+	uart0: serial0@f0005000 {
+		compatible = "snps,dw-apb-uart";
+		reg = <0xf0005000 0x1000>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+	};
+
+	ethernet@f0008000 {
+		#interrupt-cells = <1>;
+		compatible = "snps,arc-dwmac-3.70a";
+		reg = <0xf0008000 0x2000>;
+		phy-mode = "gmii";
+	};
+
+	ehci@0xf0040000 {
+		compatible = "generic-ehci";
+		reg = <0xf0040000 0x100>;
+	};
+
+	ohci@0xf0060000 {
+		compatible = "generic-ohci";
+		reg = <0xf0060000 0x100>;
+	};
+
+	mmcclk_ciu: mmcclk-ciu {
+		compatible = "fixed-clock";
+		/*
+		 * DW sdio controller has external ciu clock divider
+		 * controlled via register in SDIO IP. Due to its
+		 * unexpected default value (it should divide by 1
+		 * but it divides by 8) SDIO IP uses wrong clock and
+		 * works unstable (see STAR 9001204800)
+		 * We switched to the minimum possible value of the
+		 * divisor (div-by-2) in HSDK platform code.
+		 * So default mmcclk ciu clock is 50000000 Hz.
+		 */
+		clock-frequency = <50000000>;
+		#clock-cells = <0>;
+	};
+
+	mmc: mmc0@f000a000 {
+		compatible = "snps,dw-mshc";
+		reg = <0xf000a000 0x400>;
+		bus-width = <4>;
+		fifo-depth = <256>;
+		clocks = <&cgu_clk CLK_SYS_SDIO>, <&mmcclk_ciu>;
+		clock-names = "biu", "ciu";
+		max-frequency = <25000000>;
+	};
+
+	spi0: spi@f0020000 {
+		compatible = "snps,dw-apb-ssi";
+		reg = <0xf0020000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		spi-max-frequency = <4000000>;
+		clocks = <&cgu_clk CLK_SYS_SPI_REF>;
+		clock-names = "spi_clk";
+		cs-gpio = <&cs_gpio 0>;
+		spi_flash@0 {
+			compatible = "jedec,spi-nor";
+			reg = <0>;
+			spi-max-frequency = <4000000>;
+		};
+	};
+
+	cs_gpio: gpio@f00014b0 {
+		compatible = "snps,creg-gpio";
+		reg = <0xf00014b0 0x4>;
+		gpio-controller;
+		#gpio-cells = <1>;
+		gpio-bank-name = "hsdk-spi-cs";
+		gpio-count = <1>;
+		gpio-first-shift = <0>;
+		gpio-bit-per-line = <2>;
+		gpio-activate-val = <2>;
+		gpio-deactivate-val = <3>;
+		gpio-default-val = <1>;
+	};
+};
diff --git a/arch/arc/dts/hsdk.dts b/arch/arc/dts/hsdk.dts
index cf2ce8a..1a2e3d4 100644
--- a/arch/arc/dts/hsdk.dts
+++ b/arch/arc/dts/hsdk.dts
@@ -1,151 +1,12 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ * Copyright (C) 2017-2020 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
  */
 /dts-v1/;
 
-#include "skeleton.dtsi"
-#include "dt-bindings/clock/snps,hsdk-cgu.h"
-#include "dt-bindings/reset/snps,hsdk-reset.h"
+#include "hsdk-common.dtsi"
 
 / {
 	model = "snps,hsdk";
-
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	aliases {
-		console = &uart0;
-		spi0 = &spi0;
-	};
-
-	cpu_card {
-		core_clk: core_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <500000000>;
-			u-boot,dm-pre-reloc;
-		};
-	};
-
-	clk-fmeas {
-		clocks = <&cgu_clk CLK_ARC_PLL>, <&cgu_clk CLK_SYS_PLL>,
-			 <&cgu_clk CLK_TUN_PLL>, <&cgu_clk CLK_DDR_PLL>,
-			 <&cgu_clk CLK_ARC>, <&cgu_clk CLK_HDMI_PLL>,
-			 <&cgu_clk CLK_TUN_TUN>, <&cgu_clk CLK_HDMI>,
-			 <&cgu_clk CLK_SYS_APB>, <&cgu_clk CLK_SYS_AXI>,
-			 <&cgu_clk CLK_SYS_ETH>, <&cgu_clk CLK_SYS_USB>,
-			 <&cgu_clk CLK_SYS_SDIO>, <&cgu_clk CLK_SYS_HDMI>,
-			 <&cgu_clk CLK_SYS_GFX_CORE>, <&cgu_clk CLK_SYS_GFX_DMA>,
-			 <&cgu_clk CLK_SYS_GFX_CFG>, <&cgu_clk CLK_SYS_DMAC_CORE>,
-			 <&cgu_clk CLK_SYS_DMAC_CFG>, <&cgu_clk CLK_SYS_SDIO_REF>,
-			 <&cgu_clk CLK_SYS_SPI_REF>, <&cgu_clk CLK_SYS_I2C_REF>,
-			 <&cgu_clk CLK_SYS_UART_REF>, <&cgu_clk CLK_SYS_EBI_REF>,
-			 <&cgu_clk CLK_TUN_ROM>, <&cgu_clk CLK_TUN_PWM>;
-		clock-names = "cpu-pll", "sys-pll",
-			      "tun-pll", "ddr-clk",
-			      "cpu-clk", "hdmi-pll",
-			      "tun-clk", "hdmi-clk",
-			      "apb-clk", "axi-clk",
-			      "eth-clk", "usb-clk",
-			      "sdio-clk", "hdmi-sys-clk",
-			      "gfx-core-clk", "gfx-dma-clk",
-			      "gfx-cfg-clk", "dmac-core-clk",
-			      "dmac-cfg-clk", "sdio-ref-clk",
-			      "spi-clk", "i2c-clk",
-			      "uart-clk", "ebi-clk",
-			      "rom-clk", "pwm-clk";
-	};
-
-	cgu_clk: cgu-clk@f0000000 {
-		compatible = "snps,hsdk-cgu-clock";
-		reg = <0xf0000000 0x10>, <0xf00014B8 0x4>;
-		#clock-cells = <1>;
-	};
-
-	cgu_rst: reset-controller@f00008a0 {
-		compatible = "snps,hsdk-reset";
-		#reset-cells = <1>;
-		reg = <0xf00008a0 0x4>, <0xf0000ff0 0x4>;
-	};
-
-	uart0: serial0@f0005000 {
-		compatible = "snps,dw-apb-uart";
-		reg = <0xf0005000 0x1000>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-	};
-
-	ethernet@f0008000 {
-		#interrupt-cells = <1>;
-		compatible = "snps,arc-dwmac-3.70a";
-		reg = <0xf0008000 0x2000>;
-		phy-mode = "gmii";
-	};
-
-	ehci@0xf0040000 {
-		compatible = "generic-ehci";
-		reg = <0xf0040000 0x100>;
-	};
-
-	ohci@0xf0060000 {
-		compatible = "generic-ohci";
-		reg = <0xf0060000 0x100>;
-	};
-
-	mmcclk_ciu: mmcclk-ciu {
-		compatible = "fixed-clock";
-		/*
-		 * DW sdio controller has external ciu clock divider
-		 * controlled via register in SDIO IP. Due to its
-		 * unexpected default value (it should divide by 1
-		 * but it divides by 8) SDIO IP uses wrong clock and
-		 * works unstable (see STAR 9001204800)
-		 * We switched to the minimum possible value of the
-		 * divisor (div-by-2) in HSDK platform code.
-		 * So default mmcclk ciu clock is 50000000 Hz.
-		 */
-		clock-frequency = <50000000>;
-		#clock-cells = <0>;
-	};
-
-	mmc: mmc0@f000a000 {
-		compatible = "snps,dw-mshc";
-		reg = <0xf000a000 0x400>;
-		bus-width = <4>;
-		fifo-depth = <256>;
-		clocks = <&cgu_clk CLK_SYS_SDIO>, <&mmcclk_ciu>;
-		clock-names = "biu", "ciu";
-		max-frequency = <25000000>;
-	};
-
-	spi0: spi@f0020000 {
-		compatible = "snps,dw-apb-ssi";
-		reg = <0xf0020000 0x1000>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		spi-max-frequency = <4000000>;
-		clocks = <&cgu_clk CLK_SYS_SPI_REF>;
-		clock-names = "spi_clk";
-		cs-gpio = <&cs_gpio 0>;
-		spi_flash@0 {
-			compatible = "jedec,spi-nor";
-			reg = <0>;
-			spi-max-frequency = <4000000>;
-		};
-	};
-
-	cs_gpio: gpio@f00014b0 {
-		compatible = "snps,creg-gpio";
-		reg = <0xf00014b0 0x4>;
-		gpio-controller;
-		#gpio-cells = <1>;
-		gpio-bank-name = "hsdk-spi-cs";
-		gpio-count = <1>;
-		gpio-first-shift = <0>;
-		gpio-bit-per-line = <2>;
-		gpio-activate-val = <2>;
-		gpio-deactivate-val = <3>;
-		gpio-default-val = <1>;
-	};
 };
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index fff6591..516c14e 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -51,6 +51,9 @@
 #define ARC_AUX_DCCM_BASE	0x18	/* DCCM Base Addr ARCv2 */
 #define ARC_AUX_ICCM_BASE	0x208	/* ICCM Base Addr ARCv2 */
 
+/* CSM auxiliary registers */
+#define ARC_AUX_CSM_ENABLE	0x9A0
+
 /* Timer related auxiliary registers */
 #define ARC_AUX_TIMER0_CNT	0x21	/* Timer 0 count */
 #define ARC_AUX_TIMER0_CTRL	0x22	/* Timer 0 control */
@@ -100,6 +103,7 @@
 
 /* DSP-extensions related auxiliary registers */
 #define ARC_AUX_DSP_BUILD	0x7A
+#define ARC_AUX_DSP_CTRL	0x59F
 
 /* ARC Subsystems related auxiliary registers */
 #define ARC_AUX_SUBSYS_BUILD	0xF0
diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S
index 8c744f5..016ae85 100644
--- a/arch/arc/lib/start.S
+++ b/arch/arc/lib/start.S
@@ -61,6 +61,21 @@
 1:
 #endif
 
+#ifdef CONFIG_ISA_ARCV2
+	; In case of DSP extension presence in HW some instructions
+	; (related to integer multiply, multiply-accumulate, and divide
+	; operation) executes on this DSP execution unit. So their
+	; execution will depend on dsp configuration register (DSP_CTRL)
+	; As we want these instructions to execute the same way regardless
+	; of DSP presence we need to set DSP_CTRL properly.
+	lr	r5, [ARC_AUX_DSP_BUILD]
+	bmsk	r5, r5, 7
+	breq    r5, 0, 1f
+	mov	r5, 0
+	sr	r5, [ARC_AUX_DSP_CTRL]
+1:
+#endif
+
 #ifdef __ARC_UNALIGNED__
 	/*
 	 * Enable handling of unaligned access in the CPU as by default
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1bcf345..b494bca 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -340,6 +340,34 @@
 	default 64 if SYS_CACHE_SHIFT_6
 	default 32 if SYS_CACHE_SHIFT_5
 
+choice
+	prompt "Select the ARM data write cache policy"
+	default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
+					      TARGET_BCMNSP || CPU_PXA || RZA1
+	default SYS_ARM_CACHE_WRITEBACK
+
+config SYS_ARM_CACHE_WRITEBACK
+	bool "Write-back (WB)"
+	help
+	  A write updates the cache only and marks the cache line as dirty.
+	  External memory is updated only when the line is evicted or explicitly
+	  cleaned.
+
+config SYS_ARM_CACHE_WRITETHROUGH
+	bool "Write-through (WT)"
+	help
+	  A write updates both the cache and the external memory system.
+	  This does not mark the cache line as dirty.
+
+config SYS_ARM_CACHE_WRITEALLOC
+	bool "Write allocation (WA)"
+	help
+	  A cache line is allocated on a write miss. This means that executing a
+	  store instruction on the processor might cause a burst read to occur.
+	  There is a linefill to obtain the data for the cache line, before the
+	  write is performed.
+endchoice
+
 config ARCH_CPU_INIT
 	bool "Enable ARCH_CPU_INIT"
 	help
@@ -475,7 +503,7 @@
 
 config SET_STACK_SIZE
 	bool "Enable an option to set max stack size that can be used"
-	default y if ARCH_VERSAL || ARCH_ZYNQMP
+	default y if ARCH_VERSAL || ARCH_ZYNQMP || ARCH_ZYNQ
 	help
 	  This will enable an option to set max stack size that can be
 	  used by U-Boot.
@@ -484,6 +512,7 @@
 	hex "Define max stack size that can be used by U-Boot"
 	depends on SET_STACK_SIZE
 	default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP
+	default 0x1000000 if ARCH_ZYNQ
 	help
 	  Define Max stack size that can be used by U-Boot so that the
 	  initrd_high will be calculated as base stack pointer minus this
@@ -880,7 +909,7 @@
 	select CLK
 	select CLK_OWL
 	select OF_CONTROL
-	select CONFIG_SYS_RELOC_GD_ENV_ADDR
+	select SYS_RELOC_GD_ENV_ADDR
 	imply CMD_DM
 
 config ARCH_QEMU
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index b256391..2f75b2c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -46,6 +46,7 @@
 	select SYS_FSL_ERRATUM_A009663 if !TFABOOT
 	select SYS_FSL_ERRATUM_A009942 if !TFABOOT
 	select SYS_FSL_ERRATUM_A050382
+	select RESV_RAM if GIC_V3_ITS
 	imply PANIC_HANG
 
 config ARCH_LS1043A
@@ -152,6 +153,7 @@
 	select SYS_I2C_MXC_I2C2 if !TFABOOT
 	select SYS_I2C_MXC_I2C3 if !TFABOOT
 	select SYS_I2C_MXC_I2C4 if !TFABOOT
+	select RESV_RAM if GIC_V3_ITS
 	imply SCSI
 	imply PANIC_HANG
 
@@ -202,6 +204,7 @@
 	select SYS_I2C_MXC_I2C2 if !TFABOOT
 	select SYS_I2C_MXC_I2C3 if !TFABOOT
 	select SYS_I2C_MXC_I2C4 if !TFABOOT
+	select RESV_RAM if GIC_V3_ITS
 	imply DISTRO_DEFAULTS
 	imply PANIC_HANG
 
@@ -229,6 +232,7 @@
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 	select SYS_I2C_MXC
+	select RESV_RAM if GIC_V3_ITS
 	imply DISTRO_DEFAULTS
 	imply PANIC_HANG
 	imply SCSI
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index b443894..b3f5c2f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1156,8 +1156,10 @@
 	fsl_rgmii_init();
 #endif
 #ifdef CONFIG_FMAN_ENET
+#ifndef CONFIG_DM_ETH
 	fman_enet_init();
 #endif
+#endif
 #ifdef CONFIG_SYS_DPAA_QBMAN
 	setup_qbman_portals();
 #endif
@@ -1379,7 +1381,7 @@
 	if (i > 0)
 		ret = 0;
 
-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
 	/* Assign memory for MC */
 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
 	if (gd->bd->bi_dram[2].size >=
@@ -1402,7 +1404,7 @@
 				board_reserve_ram_top(gd->bd->bi_dram[0].size);
 		}
 	}
-#endif	/* CONFIG_FSL_MC_ENET */
+#endif	/* CONFIG_RESV_RAM */
 
 	return ret;
 }
@@ -1465,7 +1467,7 @@
 	}
 #endif	/* CONFIG_SYS_MEM_RESERVE_SECURE */
 
-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
 	/* Assign memory for MC */
 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
 	if (gd->bd->bi_dram[2].size >=
@@ -1488,7 +1490,7 @@
 				board_reserve_ram_top(gd->bd->bi_dram[0].size);
 		}
 	}
-#endif	/* CONFIG_FSL_MC_ENET */
+#endif	/* CONFIG_RESV_RAM */
 
 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 0774387..3bbad82 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -471,6 +471,10 @@
 	do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency",
 			     CONFIG_SYS_CLK_FREQ, 1);
 
+#ifdef CONFIG_GIC_V3_ITS
+	ls_gic_rd_tables_init(blob);
+#endif
+
 #if defined(CONFIG_PCIE_LAYERSCAPE) || defined(CONFIG_PCIE_LAYERSCAPE_GEN4)
 	ft_pci_setup(blob, bd);
 #endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index d0e10cb..28bb1d7 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -6,10 +6,12 @@
 
 #include <common.h>
 #include <clock_legacy.h>
+#include <cpu_func.h>
 #include <env.h>
 #include <fsl_immap.h>
 #include <fsl_ifc.h>
 #include <init.h>
+#include <linux/sizes.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/soc.h>
 #include <asm/io.h>
@@ -17,6 +19,7 @@
 #include <asm/arch-fsl-layerscape/config.h>
 #include <asm/arch-fsl-layerscape/ns_access.h>
 #include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <asm/gic-v3.h>
 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 #include <fsl_csu.h>
 #endif
@@ -30,9 +33,50 @@
 #include <fsl_immap.h>
 #ifdef CONFIG_TFABOOT
 #include <env_internal.h>
+#endif
+#if defined(CONFIG_TFABOOT) || defined(CONFIG_GIC_V3_ITS)
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
+#ifdef CONFIG_GIC_V3_ITS
+#define PENDTABLE_MAX_SZ	ALIGN(BIT(ITS_MAX_LPI_NRBITS), SZ_64K)
+#define PROPTABLE_MAX_SZ	ALIGN(BIT(ITS_MAX_LPI_NRBITS) / 8, SZ_64K)
+#define GIC_LPI_SIZE		ALIGN(cpu_numcores() * PENDTABLE_MAX_SZ + \
+				PROPTABLE_MAX_SZ, SZ_1M)
+static int fdt_add_resv_mem_gic_rd_tables(void *blob, u64 base, size_t size)
+{
+	u32 phandle;
+	int err;
+	struct fdt_memory gic_rd_tables;
+
+	gic_rd_tables.start = base;
+	gic_rd_tables.end = base + size - 1;
+	err = fdtdec_add_reserved_memory(blob, "gic-rd-tables", &gic_rd_tables,
+					 &phandle);
+	if (err < 0)
+		debug("%s: failed to add reserved memory: %d\n", __func__, err);
+
+	return err;
+}
+
+int ls_gic_rd_tables_init(void *blob)
+{
+	u64 gic_lpi_base;
+	int ret;
+
+	gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
+	ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE);
+	if (ret)
+		return ret;
+
+	ret = gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
+	if (ret)
+		debug("%s: failed to init gic-lpi-tables\n", __func__);
+
+	return ret;
+}
+#endif
+
 bool soc_has_dp_ddr(void)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 23aa125..c57a646 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -380,7 +380,8 @@
 	fsl-ls1088a-rdb.dtb \
 	fsl-ls1088a-qds.dtb \
 	fsl-ls1028a-rdb.dtb \
-	fsl-ls1028a-qds.dtb \
+	fsl-ls1028a-qds-duart.dtb \
+	fsl-ls1028a-qds-lpuart.dtb \
 	fsl-lx2160a-rdb.dtb \
 	fsl-lx2160a-qds.dtb
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
@@ -751,11 +752,11 @@
 	r8a7794-silk-u-boot.dtb
 
 dtb-$(CONFIG_RCAR_GEN3) += \
-	r8a7795-h3ulcb-u-boot.dtb \
-	r8a7795-salvator-x-u-boot.dtb \
-	r8a7796-m3ulcb-u-boot.dtb \
-	r8a7796-salvator-x-u-boot.dtb \
-	r8a77965-m3nulcb-u-boot.dtb \
+	r8a77950-ulcb-u-boot.dtb \
+	r8a77950-salvator-x-u-boot.dtb \
+	r8a77960-ulcb-u-boot.dtb \
+	r8a77960-salvator-x-u-boot.dtb \
+	r8a77965-ulcb-u-boot.dtb \
 	r8a77965-salvator-x-u-boot.dtb \
 	r8a77970-eagle-u-boot.dtb \
 	r8a77980-condor-u-boot.dtb \
diff --git a/arch/arm/dts/fsl-ls1028a-qds-duart.dts b/arch/arm/dts/fsl-ls1028a-qds-duart.dts
new file mode 100644
index 0000000..83264e0
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-qds-duart.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Device Tree file for Freescale Layerscape-1028AQDS family SoC.
+ *
+ * Copyright 2020 NXP
+ */
+
+/dts-v1/;
+#include "fsl-ls1028a-qds.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &serial0;
+	};
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-lpuart.dts b/arch/arm/dts/fsl-ls1028a-qds-lpuart.dts
new file mode 100644
index 0000000..063857b
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-qds-lpuart.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Device Tree file for Freescale Layerscape-1028AQDS family SoC.
+ *
+ * Copyright 2020 NXP
+ */
+
+/dts-v1/;
+#include "fsl-ls1028a-qds.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &lpuart0;
+	};
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds.dts b/arch/arm/dts/fsl-ls1028a-qds.dtsi
similarity index 98%
rename from arch/arm/dts/fsl-ls1028a-qds.dts
rename to arch/arm/dts/fsl-ls1028a-qds.dtsi
index 029a8e3..4f56f40 100644
--- a/arch/arm/dts/fsl-ls1028a-qds.dts
+++ b/arch/arm/dts/fsl-ls1028a-qds.dtsi
@@ -151,6 +151,10 @@
 	status = "okay";
 };
 
+&lpuart0 {
+	status = "okay";
+};
+
 &sata {
 	status = "okay";
 };
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 5365bfb..9911690 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -240,6 +240,66 @@
 		status = "disabled";
 	};
 
+	lpuart0: serial@2260000 {
+		compatible = "fsl,ls1021a-lpuart";
+		reg = <0x0 0x2260000 0x0 0x1000>;
+		interrupts = <0 232 0x4>;
+		clocks = <&sysclk>;
+		clock-names = "ipg";
+		little-endian;
+		status = "disabled";
+	};
+
+	lpuart1: serial@2270000 {
+		compatible = "fsl,ls1021a-lpuart";
+		reg = <0x0 0x2270000 0x0 0x1000>;
+		interrupts = <0 233 0x4>;
+		clocks = <&sysclk>;
+		clock-names = "ipg";
+		little-endian;
+		status = "disabled";
+	};
+
+	lpuart2: serial@2280000 {
+		compatible = "fsl,ls1021a-lpuart";
+		reg = <0x0 0x2280000 0x0 0x1000>;
+		interrupts = <0 234 0x4>;
+		clocks = <&sysclk>;
+		clock-names = "ipg";
+		little-endian;
+		status = "disabled";
+	};
+
+	lpuart3: serial@2290000 {
+		compatible = "fsl,ls1021a-lpuart";
+		reg = <0x0 0x2290000 0x0 0x1000>;
+		interrupts = <0 235 0x4>;
+		clocks = <&sysclk>;
+		clock-names = "ipg";
+		little-endian;
+		status = "disabled";
+	};
+
+	lpuart4: serial@22a0000 {
+		compatible = "fsl,ls1021a-lpuart";
+		reg = <0x0 0x22a0000 0x0 0x1000>;
+		interrupts = <0 236 0x4>;
+		clocks = <&sysclk>;
+		clock-names = "ipg";
+		little-endian;
+		status = "disabled";
+	};
+
+	lpuart5: serial@22b0000 {
+		compatible = "fsl,ls1021a-lpuart";
+		reg = <0x0 0x22b0000 0x0 0x1000>;
+		interrupts = <0 237 0x4>;
+		clocks = <&sysclk>;
+		clock-names = "ipg";
+		little-endian;
+		status = "disabled";
+	};
+
 	usb1: usb3@3100000 {
 		compatible = "fsl,layerscape-dwc3";
 		reg = <0x0 0x3100000 0x0 0x10000>;
diff --git a/arch/arm/dts/fsl-ls1043-post.dtsi b/arch/arm/dts/fsl-ls1043-post.dtsi
new file mode 100644
index 0000000..e4eab9e
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1043-post.dtsi
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 device tree nodes for ls1043
+ *
+ * Copyright 2015-2016 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+&soc {
+
+/* include used FMan blocks */
+#include "qoriq-fman3-0.dtsi"
+#include "qoriq-fman3-0-1g-0.dtsi"
+#include "qoriq-fman3-0-1g-1.dtsi"
+#include "qoriq-fman3-0-1g-2.dtsi"
+#include "qoriq-fman3-0-1g-3.dtsi"
+#include "qoriq-fman3-0-1g-4.dtsi"
+#include "qoriq-fman3-0-1g-5.dtsi"
+#include "qoriq-fman3-0-10g-0.dtsi"
+
+};
+
+&fman0 {
+	fsl,erratum-a050385;
+
+	/* these aliases provide the FMan ports mapping */
+	enet0: ethernet@e0000 {
+	};
+
+	enet1: ethernet@e2000 {
+	};
+
+	enet2: ethernet@e4000 {
+	};
+
+	enet3: ethernet@e6000 {
+	};
+
+	enet4: ethernet@e8000 {
+	};
+
+	enet5: ethernet@ea000 {
+	};
+
+	enet6: ethernet@f0000 {
+	};
+};
diff --git a/arch/arm/dts/fsl-ls1043a-rdb.dts b/arch/arm/dts/fsl-ls1043a-rdb.dts
index 721b158..6e4ea5b 100644
--- a/arch/arm/dts/fsl-ls1043a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1043a-rdb.dts
@@ -3,6 +3,7 @@
  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
  *
  * Copyright (C) 2015, Freescale Semiconductor
+ * Copyright 2020 NXP
  *
  * Mingkai Hu <Mingkai.hu@freescale.com>
  */
@@ -98,3 +99,83 @@
 &duart1 {
 	status = "okay";
 };
+
+#include "fsl-ls1043-post.dtsi"
+
+&fman0 {
+	ethernet@e0000 {
+		phy-handle = <&qsgmii_phy1>;
+		phy-connection-type = "qsgmii";
+		status = "okay";
+	};
+
+	ethernet@e2000 {
+		phy-handle = <&qsgmii_phy2>;
+		phy-connection-type = "qsgmii";
+		status = "okay";
+	};
+
+	ethernet@e4000 {
+		phy-handle = <&rgmii_phy1>;
+		phy-connection-type = "rgmii-txid";
+		status = "okay";
+	};
+
+	ethernet@e6000 {
+		phy-handle = <&rgmii_phy2>;
+		phy-connection-type = "rgmii-txid";
+		status = "okay";
+	};
+
+	ethernet@e8000 {
+		phy-handle = <&qsgmii_phy3>;
+		phy-connection-type = "qsgmii";
+		status = "okay";
+	};
+
+	ethernet@ea000 {
+		phy-handle = <&qsgmii_phy4>;
+		phy-connection-type = "qsgmii";
+		status = "okay";
+	};
+
+	ethernet@f0000 { /* 10GEC1 */
+		phy-handle = <&aqr105_phy>;
+		phy-connection-type = "xgmii";
+		status = "okay";
+	};
+
+	mdio@fc000 {
+		rgmii_phy1: ethernet-phy@1 {
+			reg = <0x1>;
+		};
+
+		rgmii_phy2: ethernet-phy@2 {
+			reg = <0x2>;
+		};
+
+		qsgmii_phy1: ethernet-phy@4 {
+			reg = <0x4>;
+		};
+
+		qsgmii_phy2: ethernet-phy@5 {
+			reg = <0x5>;
+		};
+
+		qsgmii_phy3: ethernet-phy@6 {
+			reg = <0x6>;
+		};
+
+		qsgmii_phy4: ethernet-phy@7 {
+			reg = <0x7>;
+		};
+	};
+
+	mdio@fd000 {
+		aqr105_phy: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c45";
+			interrupts = <0 132 4>;
+			reg = <0x1>;
+		};
+	};
+};
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index b159c3c..0a959f0 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -31,7 +31,7 @@
 		interrupts = <1 9 0xf08>;
 	};
 
-	soc {
+	soc: soc {
 		compatible = "simple-bus";
 		#address-cells = <2>;
 		#size-cells = <2>;
diff --git a/arch/arm/dts/fsl-ls1046-post.dtsi b/arch/arm/dts/fsl-ls1046-post.dtsi
new file mode 100644
index 0000000..2dac6a0
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046-post.dtsi
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 device tree nodes for ls1046
+ *
+ * Copyright 2015-2016 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+&soc {
+
+/* include used FMan blocks */
+#include "qoriq-fman3-0.dtsi"
+#include "qoriq-fman3-0-1g-0.dtsi"
+#include "qoriq-fman3-0-1g-1.dtsi"
+#include "qoriq-fman3-0-1g-2.dtsi"
+#include "qoriq-fman3-0-1g-3.dtsi"
+#include "qoriq-fman3-0-1g-4.dtsi"
+#include "qoriq-fman3-0-1g-5.dtsi"
+#include "qoriq-fman3-0-10g-0.dtsi"
+#include "qoriq-fman3-0-10g-1.dtsi"
+};
+
+&fman0 {
+	/* these aliases provide the FMan ports mapping */
+	enet0: ethernet@e0000 {
+	};
+
+	enet1: ethernet@e2000 {
+	};
+
+	enet2: ethernet@e4000 {
+	};
+
+	enet3: ethernet@e6000 {
+	};
+
+	enet4: ethernet@e8000 {
+	};
+
+	enet5: ethernet@ea000 {
+	};
+
+	enet6: ethernet@f0000 {
+	};
+
+	enet7: ethernet@f2000 {
+	};
+};
diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts
index 83e34ab..cac65a7 100644
--- a/arch/arm/dts/fsl-ls1046a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1046a-rdb.dts
@@ -3,6 +3,7 @@
  * Device Tree Include file for Freescale Layerscape-1046A family SoC.
  *
  * Copyright 2016, Freescale Semiconductor
+ * Copyright 2020 NXP
  *
  * Mingkai Hu <Mingkai.hu@freescale.com>
  */
@@ -51,3 +52,69 @@
 &i2c3 {
 	status = "okay";
 };
+
+#include "fsl-ls1046-post.dtsi"
+
+&fman0 {
+	ethernet@e4000 {
+		phy-handle = <&rgmii_phy1>;
+		phy-connection-type = "rgmii-id";
+		status = "okay";
+	};
+
+	ethernet@e6000 {
+		phy-handle = <&rgmii_phy2>;
+		phy-connection-type = "rgmii-id";
+		status = "okay";
+	};
+
+	ethernet@e8000 {
+		phy-handle = <&sgmii_phy1>;
+		phy-connection-type = "sgmii";
+		status = "okay";
+	};
+
+	ethernet@ea000 {
+		phy-handle = <&sgmii_phy2>;
+		phy-connection-type = "sgmii";
+		status = "okay";
+	};
+
+	ethernet@f0000 { /* 10GEC1 */
+		phy-handle = <&aqr106_phy>;
+		phy-connection-type = "xgmii";
+		status = "okay";
+	};
+
+	ethernet@f2000 { /* 10GEC2 */
+		fixed-link = <0 1 1000 0 0>;
+		phy-connection-type = "xgmii";
+		status = "okay";
+	};
+
+	mdio@fc000 {
+		rgmii_phy1: ethernet-phy@1 {
+			reg = <0x1>;
+		};
+
+		rgmii_phy2: ethernet-phy@2 {
+			reg = <0x2>;
+		};
+
+		sgmii_phy1: ethernet-phy@3 {
+			reg = <0x3>;
+		};
+
+		sgmii_phy2: ethernet-phy@4 {
+			reg = <0x4>;
+		};
+	};
+
+	mdio@fd000 {
+		aqr106_phy: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c45";
+			interrupts = <0 131 4>;
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index fdf93fd..4e91d5c 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -31,7 +31,7 @@
 		interrupts = <1 9 0xf08>;
 	};
 
-	soc {
+	soc: soc {
 		compatible = "simple-bus";
 		#address-cells = <2>;
 		#size-cells = <2>;
diff --git a/arch/arm/dts/fsl-ls1088a-rdb.dts b/arch/arm/dts/fsl-ls1088a-rdb.dts
index 0fe3519..46a5780 100644
--- a/arch/arm/dts/fsl-ls1088a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1088a-rdb.dts
@@ -17,6 +17,108 @@
 	};
 };
 
+&dpmac1 {
+	status = "okay";
+	phy-connection-type = "xgmii";
+};
+
+&dpmac2 {
+	status = "okay";
+	phy-handle = <&mdio2_phy1>;
+	phy-connection-type = "xgmii";
+};
+
+&dpmac3 {
+	status = "okay";
+	phy-handle = <&mdio1_phy5>;
+	phy-connection-type = "qsgmii";
+};
+
+&dpmac4 {
+	status = "okay";
+	phy-handle = <&mdio1_phy6>;
+	phy-connection-type = "qsgmii";
+};
+
+&dpmac5 {
+	status = "okay";
+	phy-handle = <&mdio1_phy7>;
+	phy-connection-type = "qsgmii";
+};
+
+&dpmac6 {
+	status = "okay";
+	phy-handle = <&mdio1_phy8>;
+	phy-connection-type = "qsgmii";
+};
+
+&dpmac7 {
+	status = "okay";
+	phy-handle = <&mdio1_phy1>;
+	phy-connection-type = "qsgmii";
+};
+
+&dpmac8 {
+	status = "okay";
+	phy-handle = <&mdio1_phy2>;
+	phy-connection-type = "qsgmii";
+};
+
+&dpmac9 {
+	status = "okay";
+	phy-handle = <&mdio1_phy3>;
+	phy-connection-type = "qsgmii";
+};
+
+&dpmac10 {
+	status = "okay";
+	phy-handle = <&mdio1_phy4>;
+	phy-connection-type = "qsgmii";
+};
+
+&emdio1 {
+	status = "okay";
+
+	/* Freescale F104 PHY1 */
+	mdio1_phy1: emdio1_phy@1 {
+		reg = <0x1c>;
+		};
+	mdio1_phy2: emdio1_phy@2 {
+		reg = <0x1d>;
+		};
+	mdio1_phy3: emdio1_phy@3 {
+		reg = <0x1e>;
+		};
+	mdio1_phy4: emdio1_phy@4 {
+		reg = <0x1f>;
+	};
+
+	/* F104 PHY2 */
+	mdio1_phy5: emdio1_phy@5 {
+		reg = <0x0c>;
+	};
+	mdio1_phy6: emdio1_phy@6 {
+		reg = <0x0d>;
+	};
+	mdio1_phy7: emdio1_phy@7 {
+		reg = <0x0e>;
+	};
+	mdio1_phy8: emdio1_phy@8 {
+		reg = <0x0f>;
+	};
+};
+
+&emdio2 {
+	status = "okay";
+
+	/* Aquantia AQR105 10G PHY */
+	mdio2_phy1: emdio2_phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		interrupts = <0 2 0x4>;
+		reg = <0x0>;
+	};
+};
+
 &i2c0 {
 	status = "okay";
 	u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index abc8b21..133cacb 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -82,12 +82,6 @@
 		interrupts = <0 32 0x1>; /* edge triggered */
 	};
 
-	fsl_mc: fsl-mc@80c000000 {
-		compatible = "fsl,qoriq-mc";
-		reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */
-		      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
-	};
-
 	dspi: dspi@2100000 {
 		compatible = "fsl,vf610-dspi";
 		#address-cells = <1>;
@@ -197,4 +191,100 @@
 		method = "smc";
 	};
 
+	fsl_mc: fsl-mc@80c000000 {
+		compatible = "fsl,qoriq-mc", "simple-mfd";
+		reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
+		      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
+		#address-cells = <3>;
+		#size-cells = <1>;
+
+		/*
+		 * Region type 0x0 - MC portals
+		 * Region type 0x1 - QBMAN portals
+		 */
+		ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
+			  0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
+
+		dpmacs {
+			compatible = "simple-mfd";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			dpmac1: dpmac@1 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x1>;
+				status = "disabled";
+			};
+
+			dpmac2: dpmac@2 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x2>;
+				status = "disabled";
+			};
+
+			dpmac3: dpmac@3 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x3>;
+				status = "disabled";
+			};
+
+			dpmac4: dpmac@4 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x4>;
+				status = "disabled";
+			};
+
+			dpmac5: dpmac@5 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x5>;
+				status = "disabled";
+			};
+
+			dpmac6: dpmac@6 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x6>;
+				status = "disabled";
+			};
+
+			dpmac7: dpmac@7 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x7>;
+				status = "disabled";
+			};
+
+			dpmac8: dpmac@8 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x8>;
+				status = "disabled";
+			};
+
+			dpmac9: dpmac@9 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x9>;
+				status = "disabled";
+			};
+
+			dpmac10: dpmac@a {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0xa>;
+				status = "disabled";
+			};
+		};
+	};
+
+	emdio1: mdio@8B96000 {
+		compatible = "fsl,ls-mdio";
+		reg = <0x0 0x8B96000 0x0 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	emdio2: mdio@8B97000 {
+		compatible = "fsl,ls-mdio";
+		reg = <0x0 0x8B97000 0x0 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
 };
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index 99ed33a..fb5777e 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -50,12 +50,6 @@
 		interrupts = <0 32 0x1>; /* edge triggered */
 	};
 
-	fsl_mc: fsl-mc@80c000000 {
-		compatible = "fsl,qoriq-mc";
-		reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */
-		      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
-	};
-
 	i2c0: i2c@2000000 {
 		status = "disabled";
 		compatible = "fsl,vf610-i2c";
@@ -200,4 +194,88 @@
 			status = "disabled";
 	};
 
+	fsl_mc: fsl-mc@80c000000 {
+		compatible = "fsl,qoriq-mc", "simple-mfd";
+		reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
+		      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
+		#address-cells = <3>;
+		#size-cells = <1>;
+
+		/*
+		 * Region type 0x0 - MC portals
+		 * Region type 0x1 - QBMAN portals
+		 */
+		ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
+			0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
+
+		dpmacs {
+			compatible = "simple-mfd";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			dpmac1: dpmac@1 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x1>;
+				status = "disabled";
+			};
+
+			dpmac2: dpmac@2 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x2>;
+				status = "disabled";
+			};
+
+			dpmac3: dpmac@3 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x3>;
+				status = "disabled";
+			};
+
+			dpmac4: dpmac@4 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x4>;
+				status = "disabled";
+			};
+
+			dpmac5: dpmac@5 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x5>;
+				status = "disabled";
+			};
+
+			dpmac6: dpmac@6 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x6>;
+				status = "disabled";
+			};
+
+			dpmac7: dpmac@7 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x7>;
+				status = "disabled";
+			};
+
+			dpmac8: dpmac@8 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x8>;
+				status = "disabled";
+			};
+		};
+	};
+
+	emdio1: mdio@8B96000 {
+		compatible = "fsl,ls-mdio";
+		reg = <0x0 0x8B96000 0x0 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	emdio2: mdio@8B97000 {
+		compatible = "fsl,ls-mdio";
+		reg = <0x0 0x8B97000 0x0 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
 };
diff --git a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
index 72b2177..16b9aee 100644
--- a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
+++ b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
@@ -21,6 +21,94 @@
 	};
 };
 
+&dpmac1 {
+	status = "okay";
+	phy-handle = <&mdio1_phy1>;
+	phy-connection-type = "xfi";
+};
+
+&dpmac2 {
+	status = "okay";
+	phy-handle = <&mdio1_phy2>;
+	phy-connection-type = "xfi";
+};
+
+&dpmac3 {
+	status = "okay";
+	phy-handle = <&mdio1_phy3>;
+	phy-connection-type = "xfi";
+};
+
+&dpmac4 {
+	status = "okay";
+	phy-handle = <&mdio1_phy4>;
+	phy-connection-type = "xfi";
+};
+
+&dpmac5 {
+	status = "okay";
+	phy-handle = <&mdio2_phy1>;
+	phy-connection-type = "xfi";
+};
+
+&dpmac6 {
+	status = "okay";
+	phy-handle = <&mdio2_phy2>;
+	phy-connection-type = "xfi";
+};
+
+&dpmac7 {
+	status = "okay";
+	phy-handle = <&mdio2_phy3>;
+	phy-connection-type = "xfi";
+};
+
+&dpmac8 {
+	status = "okay";
+	phy-handle = <&mdio2_phy4>;
+	phy-connection-type = "xfi";
+};
+
+&emdio1 {
+	status = "okay";
+
+	/* CS4340 PHYs */
+	mdio1_phy1: emdio1_phy@1 {
+		reg = <0x10>;
+	};
+	mdio1_phy2: emdio1_phy@2 {
+		reg = <0x11>;
+	};
+	mdio1_phy3: emdio1_phy@3 {
+		reg = <0x12>;
+	};
+	mdio1_phy4: emdio1_phy@4 {
+		reg = <0x13>;
+	};
+};
+
+&emdio2 {
+	status = "okay";
+
+	/* AQR405 PHYs */
+	mdio2_phy1: emdio2_phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <0x0>;
+	};
+	mdio2_phy2: emdio2_phy@2 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <0x1>;
+	};
+	mdio2_phy3: emdio2_phy@3 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <0x2>;
+	};
+	mdio2_phy4: emdio2_phy@4 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <0x3>;
+	};
+};
+
 &dspi {
 	bus-num = <0>;
 	status = "okay";
diff --git a/arch/arm/dts/fsl-lx2160a-rdb.dts b/arch/arm/dts/fsl-lx2160a-rdb.dts
index 87617ca..d787778 100644
--- a/arch/arm/dts/fsl-lx2160a-rdb.dts
+++ b/arch/arm/dts/fsl-lx2160a-rdb.dts
@@ -21,6 +21,58 @@
 	};
 };
 
+&dpmac3 {
+	status = "okay";
+	phy-handle = <&aquantia_phy1>;
+	phy-connection-type = "usxgmii";
+};
+
+&dpmac4 {
+	status = "okay";
+	phy-handle = <&aquantia_phy2>;
+	phy-connection-type = "usxgmii";
+};
+
+&dpmac17 {
+	status = "okay";
+	phy-handle = <&rgmii_phy1>;
+	phy-connection-type = "rgmii-id";
+};
+
+&dpmac18 {
+	status = "okay";
+	phy-handle = <&rgmii_phy2>;
+	phy-connection-type = "rgmii-id";
+};
+
+&emdio1 {
+	status = "okay";
+	rgmii_phy1: ethernet-phy@1 {
+		/* AR8035 PHY - "compatible" property not strictly needed */
+		compatible = "ethernet-phy-id004d.d072";
+		reg = <0x1>;
+		/* Poll mode - no "interrupts" property defined */
+	};
+	rgmii_phy2: ethernet-phy@2 {
+		/* AR8035 PHY - "compatible" property not strictly needed */
+		compatible = "ethernet-phy-id004d.d072";
+		reg = <0x2>;
+		/* Poll mode - no "interrupts" property defined */
+	};
+	aquantia_phy1: ethernet-phy@4 {
+		/* AQR107 PHY - "compatible" property not strictly needed */
+		compatible = "ethernet-phy-ieee802.3-c45";
+		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+		reg = <0x4>;
+	};
+	aquantia_phy2: ethernet-phy@5 {
+		/* AQR107 PHY - "compatible" property not strictly needed */
+		compatible = "ethernet-phy-ieee802.3-c45";
+		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+		reg = <0x5>;
+	};
+};
+
 &esdhc0 {
 	status = "okay";
 };
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index 42ce437..17ecdc5 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -363,4 +363,69 @@
 		bus-range = <0x0 0xff>;
 		ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>;
 	};
+
+	fsl_mc: fsl-mc@80c000000 {
+		compatible = "fsl,qoriq-mc", "simple-mfd";
+		reg = <0x00000008 0x0c000000 0 0x40>,
+		      <0x00000000 0x08340000 0 0x40000>;
+		#address-cells = <3>;
+		#size-cells = <1>;
+
+		/*
+		 * Region type 0x0 - MC portals
+		 * Region type 0x1 - QBMAN portals
+		 */
+		ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
+			  0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
+
+		dpmacs {
+			compatible = "simple-mfd";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			dpmac3: dpmac@3 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x3>;
+				status = "disabled";
+			};
+
+			dpmac4: dpmac@4 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x4>;
+				status = "disabled";
+			};
+
+			dpmac17: dpmac@11 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x11>;
+				status = "disabled";
+			};
+
+			dpmac18: dpmac@12 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x12>;
+				status = "disabled";
+			};
+		};
+	};
+
+	/* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
+	emdio1: mdio@8b96000 {
+		compatible = "fsl,ls-mdio";
+		reg = <0x0 0x8b96000 0x0 0x1000>;
+		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	/* WRIOP0: 0x8b8_0000, E-MDIO2: 0x1_7000 */
+	emdio2: mdio@8b97000 {
+		compatible = "fsl,ls-mdio";
+		reg = <0x0 0x8b97000 0x0 0x1000>;
+		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
 };
diff --git a/arch/arm/dts/meson-axg-s400.dts b/arch/arm/dts/meson-axg-s400.dts
index 4cd2d59..cb1360a 100644
--- a/arch/arm/dts/meson-axg-s400.dts
+++ b/arch/arm/dts/meson-axg-s400.dts
@@ -313,15 +313,15 @@
 			dai-tdm-slot-rx-mask-1 = <1 1>;
 			mclk-fs = <256>;
 
-			codec@0 {
+			codec-0 {
 				sound-dai = <&lineout>;
 			};
 
-			codec@1 {
+			codec-1 {
 				sound-dai = <&speaker_amp1>;
 			};
 
-			codec@2 {
+			codec-2 {
 				sound-dai = <&linein>;
 			};
 
diff --git a/arch/arm/dts/meson-g12-common.dtsi b/arch/arm/dts/meson-g12-common.dtsi
index abe04f4..0882ea2 100644
--- a/arch/arm/dts/meson-g12-common.dtsi
+++ b/arch/arm/dts/meson-g12-common.dtsi
@@ -295,17 +295,9 @@
 						};
 					};
 
-					emmc_pins: emmc {
+					emmc_ctrl_pins: emmc-ctrl {
 						mux-0 {
-							groups = "emmc_nand_d0",
-								 "emmc_nand_d1",
-								 "emmc_nand_d2",
-								 "emmc_nand_d3",
-								 "emmc_nand_d4",
-								 "emmc_nand_d5",
-								 "emmc_nand_d6",
-								 "emmc_nand_d7",
-								 "emmc_cmd";
+							groups = "emmc_cmd";
 							function = "emmc";
 							bias-pull-up;
 							drive-strength-microamp = <4000>;
@@ -319,6 +311,34 @@
 						};
 					};
 
+					emmc_data_4b_pins: emmc-data-4b {
+						mux-0 {
+							groups = "emmc_nand_d0",
+								 "emmc_nand_d1",
+								 "emmc_nand_d2",
+								 "emmc_nand_d3";
+							function = "emmc";
+							bias-pull-up;
+							drive-strength-microamp = <4000>;
+						};
+					};
+
+					emmc_data_8b_pins: emmc-data-8b {
+						mux-0 {
+							groups = "emmc_nand_d0",
+								 "emmc_nand_d1",
+								 "emmc_nand_d2",
+								 "emmc_nand_d3",
+								 "emmc_nand_d4",
+								 "emmc_nand_d5",
+								 "emmc_nand_d6",
+								 "emmc_nand_d7";
+							function = "emmc";
+							bias-pull-up;
+							drive-strength-microamp = <4000>;
+						};
+					};
+
 					emmc_ds_pins: emmc-ds {
 						mux {
 							groups = "emmc_nand_ds";
@@ -573,6 +593,17 @@
 						};
 					};
 
+					nor_pins: nor {
+						mux {
+							groups = "nor_d",
+							       "nor_q",
+							       "nor_c",
+							       "nor_cs";
+							function = "nor";
+							bias-disable;
+						};
+					};
+
 					pdm_din0_a_pins: pdm-din0-a {
 						mux {
 							groups = "pdm_din0_a";
@@ -957,6 +988,57 @@
 						};
 					};
 
+					spicc0_x_pins: spicc0-x {
+						mux {
+							groups = "spi0_mosi_x",
+							       "spi0_miso_x",
+							       "spi0_clk_x";
+							function = "spi0";
+							drive-strength-microamp = <4000>;
+							bias-disable;
+						};
+					};
+
+					spicc0_ss0_x_pins: spicc0-ss0-x {
+						mux {
+							groups = "spi0_ss0_x";
+							function = "spi0";
+							drive-strength-microamp = <4000>;
+							bias-disable;
+						};
+					};
+
+					spicc0_c_pins: spicc0-c {
+						mux {
+							groups = "spi0_mosi_c",
+							       "spi0_miso_c",
+							       "spi0_ss0_c",
+							       "spi0_clk_c";
+							function = "spi0";
+							drive-strength-microamp = <4000>;
+							bias-disable;
+						};
+					};
+
+					spicc1_pins: spicc1 {
+						mux {
+							groups = "spi1_mosi",
+							       "spi1_miso",
+							       "spi1_clk";
+							function = "spi1";
+							drive-strength-microamp = <4000>;
+						};
+					};
+
+					spicc1_ss0_pins: spicc1-ss0 {
+						mux {
+							groups = "spi1_ss0";
+							function = "spi1";
+							drive-strength-microamp = <4000>;
+							bias-disable;
+						};
+					};
+
 					tdm_a_din0_pins: tdm-a-din0 {
 						mux {
 							groups = "tdm_a_din0";
@@ -2051,6 +2133,39 @@
 				amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
 			};
 
+			spicc0: spi@13000 {
+				compatible = "amlogic,meson-g12a-spicc";
+				reg = <0x0 0x13000 0x0 0x44>;
+				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clkc CLKID_SPICC0>,
+					 <&clkc CLKID_SPICC0_SCLK>;
+				clock-names = "core", "pclk";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			spicc1: spi@15000 {
+				compatible = "amlogic,meson-g12a-spicc";
+				reg = <0x0 0x15000 0x0 0x44>;
+				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clkc CLKID_SPICC1>,
+					 <&clkc CLKID_SPICC1_SCLK>;
+				clock-names = "core", "pclk";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			spifc: spi@14000 {
+				compatible = "amlogic,meson-gxbb-spifc";
+				status = "disabled";
+				reg = <0x0 0x14000 0x0 0x80>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks = <&clkc CLKID_CLK81>;
+			};
+
 			pwm_ef: pwm@19000 {
 				compatible = "amlogic,meson-g12a-ee-pwm";
 				reg = <0x0 0x19000 0x0 0x20>;
@@ -2220,6 +2335,7 @@
 				dr_mode = "host";
 				snps,dis_u2_susphy_quirk;
 				snps,quirk-frame-length-adjustment;
+				snps,parkmode-disable-ss-quirk;
 			};
 		};
 
diff --git a/arch/arm/dts/meson-g12.dtsi b/arch/arm/dts/meson-g12.dtsi
index 03054c4..55d3902 100644
--- a/arch/arm/dts/meson-g12.dtsi
+++ b/arch/arm/dts/meson-g12.dtsi
@@ -56,6 +56,7 @@
 			 <&clkc_audio AUD_CLKID_PDM_DCLK>,
 			 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
 		clock-names = "pclk", "dclk", "sysclk";
+		resets = <&clkc_audio AUD_RESET_PDM>;
 		status = "disabled";
 	};
 
diff --git a/arch/arm/dts/meson-g12a-sei510.dts b/arch/arm/dts/meson-g12a-sei510.dts
index 2ac9e3a..b00d046 100644
--- a/arch/arm/dts/meson-g12a-sei510.dts
+++ b/arch/arm/dts/meson-g12a-sei510.dts
@@ -269,7 +269,7 @@
 			dai-tdm-slot-tx-mask-3 = <1 1>;
 			mclk-fs = <256>;
 
-			codec@0 {
+			codec {
 				sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
 			};
 		};
@@ -472,7 +472,7 @@
 /* eMMC */
 &sd_emmc_c {
 	status = "okay";
-	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+	pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
 	pinctrl-1 = <&emmc_clk_gate_pins>;
 	pinctrl-names = "default", "clk-gate";
 
diff --git a/arch/arm/dts/meson-g12a-u200.dts b/arch/arm/dts/meson-g12a-u200.dts
index 2a324f0..a26bfe7 100644
--- a/arch/arm/dts/meson-g12a-u200.dts
+++ b/arch/arm/dts/meson-g12a-u200.dts
@@ -271,7 +271,7 @@
 /* eMMC */
 &sd_emmc_c {
 	status = "okay";
-	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+	pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
 	pinctrl-1 = <&emmc_clk_gate_pins>;
 	pinctrl-names = "default", "clk-gate";
 
diff --git a/arch/arm/dts/meson-g12b-a311d-khadas-vim3-u-boot.dtsi b/arch/arm/dts/meson-g12b-a311d-khadas-vim3-u-boot.dtsi
new file mode 100644
index 0000000..f66eca1
--- /dev/null
+++ b/arch/arm/dts/meson-g12b-a311d-khadas-vim3-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-khadas-vim3-u-boot.dtsi"
diff --git a/arch/arm/dts/meson-g12b-khadas-vim3.dtsi b/arch/arm/dts/meson-g12b-khadas-vim3.dtsi
index 5548634..c33e85f 100644
--- a/arch/arm/dts/meson-g12b-khadas-vim3.dtsi
+++ b/arch/arm/dts/meson-g12b-khadas-vim3.dtsi
@@ -8,6 +8,8 @@
 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
 
 / {
+	model = "Khadas VIM3";
+
 	vddcpu_a: regulator-vddcpu-a {
 		/*
 		 * MP8756GD Regulator.
@@ -48,7 +50,7 @@
 
 	sound {
 		compatible = "amlogic,axg-sound-card";
-		model = "G12A-KHADAS-VIM3";
+		model = "G12B-KHADAS-VIM3";
 		audio-aux-devs = <&tdmout_b>;
 		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
 				"TDMOUT_B IN 1", "FRDDR_B OUT 1",
diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dts b/arch/arm/dts/meson-g12b-odroid-n2.dts
index 0e54c1d..169ea28 100644
--- a/arch/arm/dts/meson-g12b-odroid-n2.dts
+++ b/arch/arm/dts/meson-g12b-odroid-n2.dts
@@ -208,7 +208,7 @@
 
 	sound {
 		compatible = "amlogic,axg-sound-card";
-		model = "G12A-ODROIDN2";
+		model = "G12B-ODROID-N2";
 		audio-aux-devs = <&tdmout_b>;
 		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
 				"TDMOUT_B IN 1", "FRDDR_B OUT 1",
@@ -435,7 +435,7 @@
 /* eMMC */
 &sd_emmc_c {
 	status = "okay";
-	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+	pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
 	pinctrl-1 = <&emmc_clk_gate_pins>;
 	pinctrl-names = "default", "clk-gate";
 
@@ -451,6 +451,27 @@
 	vqmmc-supply = <&flash_1v8>;
 };
 
+/*
+ * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR pins
+ * and eMMC Data 4 to 7 pins.
+ * Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0,
+ * and change bus-width to 4 then spifc can be enabled.
+ * The SW1 slide should also be set to the correct position.
+ */
+&spifc {
+	status = "disabled";
+	pinctrl-0 = <&nor_pins>;
+	pinctrl-names = "default";
+
+	mx25u64: spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "mxicy,mx25u6435f", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <104000000>;
+	};
+};
+
 &tdmif_b {
 	status = "okay";
 };
diff --git a/arch/arm/dts/meson-gx.dtsi b/arch/arm/dts/meson-gx.dtsi
index 40db06e..03f79fe 100644
--- a/arch/arm/dts/meson-gx.dtsi
+++ b/arch/arm/dts/meson-gx.dtsi
@@ -12,6 +12,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
 
 / {
 	interrupt-parent = <&gic>;
@@ -83,6 +84,7 @@
 			enable-method = "psci";
 			next-level-cache = <&l2>;
 			clocks = <&scpi_dvfs 0>;
+			#cooling-cells = <2>;
 		};
 
 		cpu1: cpu@1 {
@@ -92,6 +94,7 @@
 			enable-method = "psci";
 			next-level-cache = <&l2>;
 			clocks = <&scpi_dvfs 0>;
+			#cooling-cells = <2>;
 		};
 
 		cpu2: cpu@2 {
@@ -101,6 +104,7 @@
 			enable-method = "psci";
 			next-level-cache = <&l2>;
 			clocks = <&scpi_dvfs 0>;
+			#cooling-cells = <2>;
 		};
 
 		cpu3: cpu@3 {
@@ -110,6 +114,7 @@
 			enable-method = "psci";
 			next-level-cache = <&l2>;
 			clocks = <&scpi_dvfs 0>;
+			#cooling-cells = <2>;
 		};
 
 		l2: l2-cache0 {
@@ -117,6 +122,53 @@
 		};
 	};
 
+	thermal-zones {
+		cpu-thermal {
+			polling-delay-passive = <250>; /* milliseconds */
+			polling-delay = <1000>; /* milliseconds */
+
+			thermal-sensors = <&scpi_sensors 0>;
+
+			trips {
+				cpu_passive: cpu-passive {
+					temperature = <80000>; /* millicelsius */
+					hysteresis = <2000>; /* millicelsius */
+					type = "passive";
+				};
+
+				cpu_hot: cpu-hot {
+					temperature = <90000>; /* millicelsius */
+					hysteresis = <2000>; /* millicelsius */
+					type = "hot";
+				};
+
+				cpu_critical: cpu-critical {
+					temperature = <110000>; /* millicelsius */
+					hysteresis = <2000>; /* millicelsius */
+					type = "critical";
+				};
+			};
+
+			cpu_cooling_maps: cooling-maps {
+				map0 {
+					trip = <&cpu_passive>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map1 {
+					trip = <&cpu_hot>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+	};
+
 	arm-pmu {
 		compatible = "arm,cortex-a53-pmu";
 		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts b/arch/arm/dts/meson-gxbb-odroidc2.dts
index 6ded279..b46ef98 100644
--- a/arch/arm/dts/meson-gxbb-odroidc2.dts
+++ b/arch/arm/dts/meson-gxbb-odroidc2.dts
@@ -248,6 +248,7 @@
 	status = "okay";
 	pinctrl-0 = <&remote_input_ao_pins>;
 	pinctrl-names = "default";
+	linux,rc-map-name = "rc-odroid";
 };
 
 &gpio_ao {
diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dtsi b/arch/arm/dts/meson-gxl-s905x-p212.dtsi
index 43eb7d1..6ac678f 100644
--- a/arch/arm/dts/meson-gxl-s905x-p212.dtsi
+++ b/arch/arm/dts/meson-gxl-s905x-p212.dtsi
@@ -15,7 +15,6 @@
 / {
 	aliases {
 		serial0 = &uart_AO;
-		serial1 = &uart_A;
 		ethernet0 = &ethmac;
 	};
 
@@ -180,6 +179,14 @@
 	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
 	pinctrl-names = "default";
 	uart-has-rtscts;
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+		max-speed = <2000000>;
+		clocks = <&wifi32k>;
+		clock-names = "lpo";
+	};
 };
 
 &uart_AO {
diff --git a/arch/arm/dts/meson-gxm-khadas-vim2-u-boot.dtsi b/arch/arm/dts/meson-gxm-khadas-vim2-u-boot.dtsi
index c35158d..bec9e05 100644
--- a/arch/arm/dts/meson-gxm-khadas-vim2-u-boot.dtsi
+++ b/arch/arm/dts/meson-gxm-khadas-vim2-u-boot.dtsi
@@ -5,3 +5,18 @@
  */
 
 #include "meson-gx-u-boot.dtsi"
+
+/ {
+	aliases {
+		spi0 = &spifc;
+	};
+};
+
+&sd_emmc_c {
+	status = "okay";
+	pinctrl-0 = <&emmc_pins>;
+};
+
+&spifc {
+	status = "okay";
+};
diff --git a/arch/arm/dts/meson-gxm-khadas-vim2.dts b/arch/arm/dts/meson-gxm-khadas-vim2.dts
index f82f25c..27eeab7 100644
--- a/arch/arm/dts/meson-gxm-khadas-vim2.dts
+++ b/arch/arm/dts/meson-gxm-khadas-vim2.dts
@@ -8,7 +8,6 @@
 /dts-v1/;
 
 #include <dt-bindings/input/input.h>
-#include <dt-bindings/thermal/thermal.h>
 
 #include "meson-gxm.dtsi"
 
@@ -100,49 +99,6 @@
 		clock-names = "ext_clock";
 	};
 
-	thermal-zones {
-		cpu-thermal {
-			polling-delay-passive = <250>; /* milliseconds */
-			polling-delay = <1000>; /* milliseconds */
-
-			thermal-sensors = <&scpi_sensors 0>;
-
-			trips {
-				cpu_alert0: cpu-alert0 {
-					temperature = <70000>; /* millicelsius */
-					hysteresis = <2000>; /* millicelsius */
-					type = "active";
-				};
-
-				cpu_alert1: cpu-alert1 {
-					temperature = <80000>; /* millicelsius */
-					hysteresis = <2000>; /* millicelsius */
-					type = "passive";
-				};
-			};
-
-			cooling-maps {
-				map0 {
-					trip = <&cpu_alert0>;
-					cooling-device = <&gpio_fan THERMAL_NO_LIMIT 1>;
-				};
-
-				map1 {
-					trip = <&cpu_alert1>;
-					cooling-device = <&gpio_fan 2 THERMAL_NO_LIMIT>,
-							 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-							 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-							 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-							 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-							 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-				};
-			};
-		};
-	};
-
 	hdmi_5v: regulator-hdmi-5v {
 		compatible = "regulator-fixed";
 
@@ -198,36 +154,23 @@
 	hdmi-phandle = <&hdmi_tx>;
 };
 
-&cpu0 {
-	#cooling-cells = <2>;
-};
-
-&cpu1 {
-	#cooling-cells = <2>;
-};
-
-&cpu2 {
-	#cooling-cells = <2>;
-};
-
-&cpu3 {
-	#cooling-cells = <2>;
-};
-
-&cpu4 {
-	#cooling-cells = <2>;
-};
-
-&cpu5 {
-	#cooling-cells = <2>;
-};
 
-&cpu6 {
-	#cooling-cells = <2>;
-};
+&cpu_cooling_maps {
+	map0 {
+		cooling-device = <&gpio_fan THERMAL_NO_LIMIT 1>;
+	};
 
-&cpu7 {
-	#cooling-cells = <2>;
+	map1 {
+		cooling-device = <&gpio_fan 2 THERMAL_NO_LIMIT>,
+				 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+				 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+				 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+				 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+				 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+				 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+				 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+				 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+	};
 };
 
 &ethmac {
@@ -327,7 +270,7 @@
 	#size-cells = <0>;
 
 	bus-width = <4>;
-	max-frequency = <50000000>;
+	max-frequency = <60000000>;
 
 	non-removable;
 	disable-wp;
diff --git a/arch/arm/dts/meson-gxm.dtsi b/arch/arm/dts/meson-gxm.dtsi
index 5ff64a0..b6f89f1 100644
--- a/arch/arm/dts/meson-gxm.dtsi
+++ b/arch/arm/dts/meson-gxm.dtsi
@@ -49,6 +49,7 @@
 			enable-method = "psci";
 			next-level-cache = <&l2>;
 			clocks = <&scpi_dvfs 1>;
+			#cooling-cells = <2>;
 		};
 
 		cpu5: cpu@101 {
@@ -58,6 +59,7 @@
 			enable-method = "psci";
 			next-level-cache = <&l2>;
 			clocks = <&scpi_dvfs 1>;
+			#cooling-cells = <2>;
 		};
 
 		cpu6: cpu@102 {
@@ -67,6 +69,7 @@
 			enable-method = "psci";
 			next-level-cache = <&l2>;
 			clocks = <&scpi_dvfs 1>;
+			#cooling-cells = <2>;
 		};
 
 		cpu7: cpu@103 {
@@ -76,6 +79,7 @@
 			enable-method = "psci";
 			next-level-cache = <&l2>;
 			clocks = <&scpi_dvfs 1>;
+			#cooling-cells = <2>;
 		};
 	};
 };
@@ -124,6 +128,30 @@
 	compatible = "amlogic,meson-gxm-aoclkc", "amlogic,meson-gx-aoclkc";
 };
 
+&cpu_cooling_maps {
+	map0 {
+		cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+				 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+				 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+				 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+				 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+				 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+				 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+				 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+	};
+
+	map1 {
+		cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+				 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+				 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+				 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+				 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+				 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+				 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+				 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+	};
+};
+
 &saradc {
 	compatible = "amlogic,meson-gxm-saradc", "amlogic,meson-saradc";
 };
diff --git a/arch/arm/dts/meson-khadas-vim3-u-boot.dtsi b/arch/arm/dts/meson-khadas-vim3-u-boot.dtsi
new file mode 100644
index 0000000..81fd5be
--- /dev/null
+++ b/arch/arm/dts/meson-khadas-vim3-u-boot.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/ {
+	aliases {
+		spi0 = &spifc;
+	};
+};
+
+&sd_emmc_c {
+	status = "okay";
+	pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_4b_pins>, <&emmc_ds_pins>;
+	bus-width = <4>;
+};
+
+&spifc {
+	status = "okay";
+};
diff --git a/arch/arm/dts/meson-khadas-vim3.dtsi b/arch/arm/dts/meson-khadas-vim3.dtsi
index 90815fa..094ecf2 100644
--- a/arch/arm/dts/meson-khadas-vim3.dtsi
+++ b/arch/arm/dts/meson-khadas-vim3.dtsi
@@ -9,8 +9,6 @@
 #include <dt-bindings/gpio/meson-g12a-gpio.h>
 
 / {
-	model = "Khadas VIM3";
-
 	aliases {
 		serial0 = &uart_AO;
 		ethernet0 = &ethmac;
@@ -312,7 +310,7 @@
 /* eMMC */
 &sd_emmc_c {
 	status = "okay";
-	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+	pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
 	pinctrl-1 = <&emmc_clk_gate_pins>;
 	pinctrl-names = "default", "clk-gate";
 
@@ -328,6 +326,26 @@
 	vqmmc-supply = <&emmc_1v8>;
 };
 
+/*
+ * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR CS
+ * and eMMC Data 4 to 7 pins.
+ * Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0,
+ * and change bus-width to 4 then spifc can be enabled.
+ */
+&spifc {
+	status = "disabled";
+	pinctrl-0 = <&nor_pins>;
+	pinctrl-names = "default";
+
+	w25q32: spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "winbond,w25q128fw", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <104000000>;
+	};
+};
+
 &uart_A {
 	status = "okay";
 	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
diff --git a/arch/arm/dts/meson-sm1-khadas-vim3l-u-boot.dtsi b/arch/arm/dts/meson-sm1-khadas-vim3l-u-boot.dtsi
new file mode 100644
index 0000000..f66eca1
--- /dev/null
+++ b/arch/arm/dts/meson-sm1-khadas-vim3l-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-khadas-vim3-u-boot.dtsi"
diff --git a/arch/arm/dts/meson-sm1-khadas-vim3l.dts b/arch/arm/dts/meson-sm1-khadas-vim3l.dts
index 1001b37..dbbf29a 100644
--- a/arch/arm/dts/meson-sm1-khadas-vim3l.dts
+++ b/arch/arm/dts/meson-sm1-khadas-vim3l.dts
@@ -72,9 +72,10 @@
 /*
  * The VIM3 on-board  MCU can mux the PCIe/USB3.0 shared differential
  * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
- * an USB3.0 Type A connector and a M.2 Key M slot. The PHY driving
- * these differential lines is shared between the USB3.0 controller
- * and the PCIe Controller, thus only a single controller can use it.
+ * an USB3.0 Type A connector and a M.2 Key M slot.
+ * The PHY driving these differential lines is shared between
+ * the USB3.0 controller and the PCIe Controller, thus only
+ * a single controller can use it.
  * If the MCU is configured to mux the PCIe/USB3.0 differential lines
  * to the M.2 Key M slot, uncomment the following block to disable
  * USB3.0 from the USB Complex and enable the PCIe controller.
@@ -82,7 +83,6 @@
  * testing purposes, but instead rely on the firmware/bootloader to
  * update these nodes accordingly if PCIe mode is selected by the MCU.
  */
-
 /*
 &pcie {
 	status = "okay";
diff --git a/arch/arm/dts/meson-sm1-sei610.dts b/arch/arm/dts/meson-sm1-sei610.dts
index a8bb3fa..dfb2438 100644
--- a/arch/arm/dts/meson-sm1-sei610.dts
+++ b/arch/arm/dts/meson-sm1-sei610.dts
@@ -518,7 +518,7 @@
 /* eMMC */
 &sd_emmc_c {
 	status = "okay";
-	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+	pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
 	pinctrl-1 = <&emmc_clk_gate_pins>;
 	pinctrl-names = "default", "clk-gate";
 
@@ -593,6 +593,7 @@
 		compatible = "brcm,bcm43438-bt";
 		interrupt-parent = <&gpio_intc>;
 		interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "host-wakeup";
 		shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
 		max-speed = <2000000>;
 		clocks = <&wifi32k>;
diff --git a/arch/arm/dts/meson-sm1.dtsi b/arch/arm/dts/meson-sm1.dtsi
index d847a3f..d4ec735 100644
--- a/arch/arm/dts/meson-sm1.dtsi
+++ b/arch/arm/dts/meson-sm1.dtsi
@@ -448,6 +448,7 @@
 			 <&clkc_audio AUD_CLKID_PDM_DCLK>,
 			 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
 		clock-names = "pclk", "dclk", "sysclk";
+		resets = <&clkc_audio AUD_RESET_PDM>;
 		status = "disabled";
 	};
 };
diff --git a/arch/arm/dts/qoriq-fman3-0-10g-0.dtsi b/arch/arm/dts/qoriq-fman3-0-10g-0.dtsi
new file mode 100644
index 0000000..8f4776e
--- /dev/null
+++ b/arch/arm/dts/qoriq-fman3-0-10g-0.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 10g port #0 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@1a00000 {
+	fman0_rx_0x10: port@90000 {
+		cell-index = <0x10>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x90000 0x1000>;
+		fsl,fman-10g-port;
+	};
+
+	fman0_tx_0x30: port@b0000 {
+		cell-index = <0x30>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xb0000 0x1000>;
+		fsl,fman-10g-port;
+	};
+
+	ethernet@f0000 {
+		cell-index = <0x8>;
+		compatible = "fsl,fman-memac";
+		reg = <0xf0000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>;
+		pcsphy-handle = <&pcsphy6>;
+		status = "disabled";
+	};
+
+	mdio@f1000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xf1000 0x1000>;
+
+		pcsphy6: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/arch/arm/dts/qoriq-fman3-0-10g-1.dtsi b/arch/arm/dts/qoriq-fman3-0-10g-1.dtsi
new file mode 100644
index 0000000..b5eb22f
--- /dev/null
+++ b/arch/arm/dts/qoriq-fman3-0-10g-1.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 10g port #1 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@1a00000 {
+	fman0_rx_0x11: port@91000 {
+		cell-index = <0x11>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x91000 0x1000>;
+		fsl,fman-10g-port;
+	};
+
+	fman0_tx_0x31: port@b1000 {
+		cell-index = <0x31>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xb1000 0x1000>;
+		fsl,fman-10g-port;
+	};
+
+	ethernet@f2000 {
+		cell-index = <0x9>;
+		compatible = "fsl,fman-memac";
+		reg = <0xf2000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>;
+		pcsphy-handle = <&pcsphy7>;
+		status = "disabled";
+	};
+
+	mdio@f3000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xf3000 0x1000>;
+
+		pcsphy7: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/arch/arm/dts/qoriq-fman3-0-1g-0.dtsi b/arch/arm/dts/qoriq-fman3-0-1g-0.dtsi
new file mode 100644
index 0000000..4264d47
--- /dev/null
+++ b/arch/arm/dts/qoriq-fman3-0-1g-0.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 1g port #0 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@1a00000 {
+	fman0_rx_0x08: port@88000 {
+		cell-index = <0x8>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x88000 0x1000>;
+	};
+
+	fman0_tx_0x28: port@a8000 {
+		cell-index = <0x28>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xa8000 0x1000>;
+	};
+
+	ethernet@e0000 {
+		cell-index = <0>;
+		compatible = "fsl,fman-memac";
+		reg = <0xe0000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
+		ptp-timer = <&ptp_timer0>;
+		pcsphy-handle = <&pcsphy0>;
+		status = "disabled";
+	};
+
+	mdio@e1000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xe1000 0x1000>;
+
+		pcsphy0: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/arch/arm/dts/qoriq-fman3-0-1g-1.dtsi b/arch/arm/dts/qoriq-fman3-0-1g-1.dtsi
new file mode 100644
index 0000000..d60f8c7
--- /dev/null
+++ b/arch/arm/dts/qoriq-fman3-0-1g-1.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 1g port #1 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@1a00000 {
+	fman0_rx_0x09: port@89000 {
+		cell-index = <0x9>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x89000 0x1000>;
+	};
+
+	fman0_tx_0x29: port@a9000 {
+		cell-index = <0x29>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xa9000 0x1000>;
+	};
+
+	ethernet@e2000 {
+		cell-index = <1>;
+		compatible = "fsl,fman-memac";
+		reg = <0xe2000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
+		ptp-timer = <&ptp_timer0>;
+		pcsphy-handle = <&pcsphy1>;
+		status = "disabled";
+	};
+
+	mdio@e3000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xe3000 0x1000>;
+
+		pcsphy1: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/arch/arm/dts/qoriq-fman3-0-1g-2.dtsi b/arch/arm/dts/qoriq-fman3-0-1g-2.dtsi
new file mode 100644
index 0000000..7c5edc0
--- /dev/null
+++ b/arch/arm/dts/qoriq-fman3-0-1g-2.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 1g port #2 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@1a00000 {
+	fman0_rx_0x0a: port@8a000 {
+		cell-index = <0xa>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x8a000 0x1000>;
+	};
+
+	fman0_tx_0x2a: port@aa000 {
+		cell-index = <0x2a>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xaa000 0x1000>;
+	};
+
+	ethernet@e4000 {
+		cell-index = <2>;
+		compatible = "fsl,fman-memac";
+		reg = <0xe4000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>;
+		ptp-timer = <&ptp_timer0>;
+		pcsphy-handle = <&pcsphy2>;
+		status = "disabled";
+	};
+
+	mdio@e5000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xe5000 0x1000>;
+
+		pcsphy2: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/arch/arm/dts/qoriq-fman3-0-1g-3.dtsi b/arch/arm/dts/qoriq-fman3-0-1g-3.dtsi
new file mode 100644
index 0000000..2d2de58
--- /dev/null
+++ b/arch/arm/dts/qoriq-fman3-0-1g-3.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 1g port #3 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@1a00000 {
+	fman0_rx_0x0b: port@8b000 {
+		cell-index = <0xb>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x8b000 0x1000>;
+	};
+
+	fman0_tx_0x2b: port@ab000 {
+		cell-index = <0x2b>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xab000 0x1000>;
+	};
+
+	ethernet@e6000 {
+		cell-index = <3>;
+		compatible = "fsl,fman-memac";
+		reg = <0xe6000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>;
+		ptp-timer = <&ptp_timer0>;
+		pcsphy-handle = <&pcsphy3>;
+		status = "disabled";
+	};
+
+	mdio@e7000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xe7000 0x1000>;
+
+		pcsphy3: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/arch/arm/dts/qoriq-fman3-0-1g-4.dtsi b/arch/arm/dts/qoriq-fman3-0-1g-4.dtsi
new file mode 100644
index 0000000..f5a73dc
--- /dev/null
+++ b/arch/arm/dts/qoriq-fman3-0-1g-4.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 1g port #4 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@1a00000 {
+	fman0_rx_0x0c: port@8c000 {
+		cell-index = <0xc>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x8c000 0x1000>;
+	};
+
+	fman0_tx_0x2c: port@ac000 {
+		cell-index = <0x2c>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xac000 0x1000>;
+	};
+
+	ethernet@e8000 {
+		cell-index = <4>;
+		compatible = "fsl,fman-memac";
+		reg = <0xe8000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>;
+		ptp-timer = <&ptp_timer0>;
+		pcsphy-handle = <&pcsphy4>;
+		status = "disabled";
+	};
+
+	mdio@e9000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xe9000 0x1000>;
+
+		pcsphy4: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/arch/arm/dts/qoriq-fman3-0-1g-5.dtsi b/arch/arm/dts/qoriq-fman3-0-1g-5.dtsi
new file mode 100644
index 0000000..baa5751
--- /dev/null
+++ b/arch/arm/dts/qoriq-fman3-0-1g-5.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 1g port #5 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@1a00000 {
+	fman0_rx_0x0d: port@8d000 {
+		cell-index = <0xd>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x8d000 0x1000>;
+	};
+
+	fman0_tx_0x2d: port@ad000 {
+		cell-index = <0x2d>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xad000 0x1000>;
+	};
+
+	ethernet@ea000 {
+		cell-index = <5>;
+		compatible = "fsl,fman-memac";
+		reg = <0xea000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>;
+		ptp-timer = <&ptp_timer0>;
+		pcsphy-handle = <&pcsphy5>;
+		status = "disabled";
+	};
+
+	mdio@eb000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xeb000 0x1000>;
+
+		pcsphy5: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/arch/arm/dts/qoriq-fman3-0.dtsi b/arch/arm/dts/qoriq-fman3-0.dtsi
new file mode 100644
index 0000000..82fe796
--- /dev/null
+++ b/arch/arm/dts/qoriq-fman3-0.dtsi
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman0: fman@1a00000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	cell-index = <0>;
+	compatible = "fsl,fman";
+	ranges = <0x0 0x0 0x1a00000 0xfe000>;
+	reg = <0x0 0x1a00000 0x0 0xfe000>;
+	clocks = <&clockgen 3 0>;
+	clock-names = "fmanclk";
+	fsl,qman-channel-range = <0x800 0x10>;
+	ptimer-handle = <&ptp_timer0>;
+
+	muram@0 {
+		compatible = "fsl,fman-muram";
+		reg = <0x0 0x60000>;
+	};
+
+	fman0_oh_0x2: port@82000 {
+		cell-index = <0x2>;
+		compatible = "fsl,fman-v3-port-oh";
+		reg = <0x82000 0x1000>;
+	};
+
+	fman0_oh_0x3: port@83000 {
+		cell-index = <0x3>;
+		compatible = "fsl,fman-v3-port-oh";
+		reg = <0x83000 0x1000>;
+	};
+
+	fman0_oh_0x4: port@84000 {
+		cell-index = <0x4>;
+		compatible = "fsl,fman-v3-port-oh";
+		reg = <0x84000 0x1000>;
+	};
+
+	fman0_oh_0x5: port@85000 {
+		cell-index = <0x5>;
+		compatible = "fsl,fman-v3-port-oh";
+		reg = <0x85000 0x1000>;
+	};
+
+	fman0_oh_0x6: port@86000 {
+		cell-index = <0x6>;
+		compatible = "fsl,fman-v3-port-oh";
+		reg = <0x86000 0x1000>;
+	};
+
+	fman0_oh_0x7: port@87000 {
+		cell-index = <0x7>;
+		compatible = "fsl,fman-v3-port-oh";
+		reg = <0x87000 0x1000>;
+	};
+
+	mdio0: mdio@fc000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xfc000 0x1000>;
+	};
+
+	xmdio0: mdio@fd000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xfd000 0x1000>;
+	};
+};
+
+ptp_timer0: ptp-timer@1afe000 {
+	compatible = "fsl,fman-ptp-timer";
+	reg = <0x0 0x1afe000 0x0 0x1000>;
+	clocks = <&clockgen 3 0>;
+};
diff --git a/arch/arm/dts/r8a7790-lager.dts b/arch/arm/dts/r8a7790-lager.dts
index 7b9508e..097fd93 100644
--- a/arch/arm/dts/r8a7790-lager.dts
+++ b/arch/arm/dts/r8a7790-lager.dts
@@ -56,7 +56,7 @@
 	};
 
 	chosen {
-		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
 		stdout-path = "serial0:115200n8";
 	};
 
@@ -150,8 +150,7 @@
 
 		gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
 		gpios-states = <1>;
-		states = <3300000 1
-			  1800000 0>;
+		states = <3300000 1>, <1800000 0>;
 	};
 
 	vcc_sdhi2: regulator-vcc-sdhi2 {
@@ -174,8 +173,7 @@
 
 		gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>;
 		gpios-states = <1>;
-		states = <3300000 1
-			  1800000 0>;
+		states = <3300000 1>, <1800000 0>;
 	};
 
 	audio_clock: audio_clock {
@@ -325,10 +323,10 @@
 		#size-cells = <0>;
 	};
 
-        /*
-         * IIC2 and I2C2 may be switched using pinmux.
-         * A fallback to GPIO is also provided.
-         */
+	/*
+	 * IIC2 and I2C2 may be switched using pinmux.
+	 * A fallback to GPIO is also provided.
+	 */
 	i2chdmi: i2c-12 {
 		compatible = "i2c-demux-pinctrl";
 		i2c-parent = <&iic2>, <&i2c2>, <&gpioi2c2>;
@@ -423,6 +421,8 @@
 	 */
 	i2cpwr: i2c-13 {
 		compatible = "i2c-demux-pinctrl";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_irq_pins>;
 		i2c-parent = <&iic3>, <&i2c3>;
 		i2c-bus-name = "i2c-pwr";
 		#address-cells = <1>;
@@ -615,6 +615,11 @@
 		function = "iic3";
 	};
 
+	pmic_irq_pins: pmicirq {
+		groups = "intc_irq2";
+		function = "intc";
+	};
+
 	hsusb_pins: hsusb {
 		groups = "usb0_ovc_vbus";
 		function = "usb0";
diff --git a/arch/arm/dts/r8a7790-stout.dts b/arch/arm/dts/r8a7790-stout.dts
index 7a7d3b8..a315ba7 100644
--- a/arch/arm/dts/r8a7790-stout.dts
+++ b/arch/arm/dts/r8a7790-stout.dts
@@ -19,7 +19,7 @@
 	};
 
 	chosen {
-		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
 		stdout-path = "serial0:115200n8";
 	};
 
@@ -179,6 +179,11 @@
 		function = "iic3";
 	};
 
+	pmic_irq_pins: pmicirq {
+		groups = "intc_irq2";
+		function = "intc";
+	};
+
 	usb0_pins: usb0 {
 		groups = "usb0";
 		function = "usb0";
@@ -317,7 +322,7 @@
 
 &iic3 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&iic3_pins>;
+	pinctrl-0 = <&iic3_pins &pmic_irq_pins>;
 	status = "okay";
 
 	pmic@58 {
diff --git a/arch/arm/dts/r8a7790.dtsi b/arch/arm/dts/r8a7790.dtsi
index 5a27477..334ba19 100644
--- a/arch/arm/dts/r8a7790.dtsi
+++ b/arch/arm/dts/r8a7790.dtsi
@@ -487,6 +487,9 @@
 		icram0:	sram@e63a0000 {
 			compatible = "mmio-sram";
 			reg = <0 0xe63a0000 0 0x12000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0 0xe63a0000 0x12000>;
 		};
 
 		icram1:	sram@e63c0000 {
@@ -669,8 +672,8 @@
 			compatible = "renesas,r8a7790-usb-dmac",
 				     "renesas,usb-dmac";
 			reg = <0 0xe65a0000 0 0x100>;
-			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "ch0", "ch1";
 			clocks = <&cpg CPG_MOD 330>;
 			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
@@ -683,8 +686,8 @@
 			compatible = "renesas,r8a7790-usb-dmac",
 				     "renesas,usb-dmac";
 			reg = <0 0xe65b0000 0 0x100>;
-			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "ch0", "ch1";
 			clocks = <&cpg CPG_MOD 331>;
 			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
@@ -697,22 +700,22 @@
 			compatible = "renesas,dmac-r8a7790",
 				     "renesas,rcar-dmac";
 			reg = <0 0xe6700000 0 0x20000>;
-			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					  "ch0", "ch1", "ch2", "ch3",
 					  "ch4", "ch5", "ch6", "ch7",
@@ -730,22 +733,22 @@
 			compatible = "renesas,dmac-r8a7790",
 				     "renesas,rcar-dmac";
 			reg = <0 0xe6720000 0 0x20000>;
-			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					  "ch0", "ch1", "ch2", "ch3",
 					  "ch4", "ch5", "ch6", "ch7",
@@ -1300,20 +1303,20 @@
 			compatible = "renesas,dmac-r8a7790",
 				     "renesas,rcar-dmac";
 			reg = <0 0xec700000 0 0x10000>;
-			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					  "ch0", "ch1", "ch2", "ch3",
 					  "ch4", "ch5", "ch6", "ch7",
@@ -1331,20 +1334,20 @@
 			compatible = "renesas,dmac-r8a7790",
 				     "renesas,rcar-dmac";
 			reg = <0 0xec720000 0 0x10000>;
-			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					  "ch0", "ch1", "ch2", "ch3",
 					  "ch4", "ch5", "ch6", "ch7",
@@ -1388,10 +1391,10 @@
 			#size-cells = <2>;
 			#interrupt-cells = <1>;
 			ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
-			interrupt-map-mask = <0xff00 0 0 0x7>;
-			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
-					 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
-					 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-map-mask = <0xf800 0 0 0x7>;
+			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+					<0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+					<0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 
 			usb@1,0 {
 				reg = <0x800 0 0 0 0>;
@@ -1423,10 +1426,10 @@
 			#size-cells = <2>;
 			#interrupt-cells = <1>;
 			ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
-			interrupt-map-mask = <0xff00 0 0 0x7>;
-			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
-					 0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
-					 0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-map-mask = <0xf800 0 0 0x7>;
+			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+					<0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+					<0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
 		pci2: pci@ee0d0000 {
@@ -1446,10 +1449,10 @@
 			#size-cells = <2>;
 			#interrupt-cells = <1>;
 			ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
-			interrupt-map-mask = <0xff00 0 0 0x7>;
-			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
-					 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
-					 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-map-mask = <0xf800 0 0 0x7>;
+			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+					<0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+					<0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 
 			usb@1,0 {
 				reg = <0x20800 0 0 0 0>;
@@ -1614,13 +1617,13 @@
 			#size-cells = <2>;
 			bus-range = <0x00 0xff>;
 			device_type = "pci";
-			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
-				  0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
-				  0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
-				  0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
+				 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
+				 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
+				 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
 			/* Map all possible DDR as inbound ranges */
-			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
-				      0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
+			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>,
+				     <0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
 			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/dts/r8a7791-koelsch.dts b/arch/arm/dts/r8a7791-koelsch.dts
index e6580aa..2b096d5 100644
--- a/arch/arm/dts/r8a7791-koelsch.dts
+++ b/arch/arm/dts/r8a7791-koelsch.dts
@@ -56,7 +56,7 @@
 	};
 
 	chosen {
-		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
 		stdout-path = "serial0:115200n8";
 	};
 
@@ -193,8 +193,7 @@
 
 		gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
 		gpios-states = <1>;
-		states = <3300000 1
-			  1800000 0>;
+		states = <3300000 1>, <1800000 0>;
 	};
 
 	vcc_sdhi1: regulator-vcc-sdhi1 {
@@ -217,8 +216,7 @@
 
 		gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
 		gpios-states = <1>;
-		states = <3300000 1
-			  1800000 0>;
+		states = <3300000 1>, <1800000 0>;
 	};
 
 	vcc_sdhi2: regulator-vcc-sdhi2 {
@@ -241,8 +239,7 @@
 
 		gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
 		gpios-states = <1>;
-		states = <3300000 1
-			  1800000 0>;
+		states = <3300000 1>, <1800000 0>;
 	};
 
 	audio_clock: audio_clock {
@@ -540,6 +537,11 @@
 		function = "intc";
 	};
 
+	pmic_irq_pins: pmicirq {
+		groups = "intc_irq2";
+		function = "intc";
+	};
+
 	sdhi0_pins: sd0 {
 		groups = "sdhi0_data4", "sdhi0_ctrl";
 		function = "sdhi0";
@@ -776,6 +778,8 @@
 };
 
 &i2c6 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pmic_irq_pins>;
 	status = "okay";
 	clock-frequency = <100000>;
 
diff --git a/arch/arm/dts/r8a7791-porter.dts b/arch/arm/dts/r8a7791-porter.dts
index fefdf82..f9ece7a 100644
--- a/arch/arm/dts/r8a7791-porter.dts
+++ b/arch/arm/dts/r8a7791-porter.dts
@@ -31,7 +31,7 @@
 	};
 
 	chosen {
-		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
 		stdout-path = "serial0:115200n8";
 	};
 
@@ -63,8 +63,7 @@
 
 		gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
 		gpios-states = <1>;
-		states = <3300000 1
-			  1800000 0>;
+		states = <3300000 1>, <1800000 0>;
 	};
 
 	vcc_sdhi2: regulator-vcc-sdhi2 {
@@ -85,8 +84,7 @@
 
 		gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
 		gpios-states = <1>;
-		states = <3300000 1
-			  1800000 0>;
+		states = <3300000 1>, <1800000 0>;
 	};
 
 	hdmi-out {
@@ -228,6 +226,11 @@
 		function = "intc";
 	};
 
+	pmic_irq_pins: pmicirq {
+		groups = "intc_irq2";
+		function = "intc";
+	};
+
 	sdhi0_pins: sd0 {
 		groups = "sdhi0_data4", "sdhi0_ctrl";
 		function = "sdhi0";
@@ -373,6 +376,8 @@
 };
 
 &i2c6 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pmic_irq_pins>;
 	status = "okay";
 	clock-frequency = <100000>;
 
diff --git a/arch/arm/dts/r8a7791.dtsi b/arch/arm/dts/r8a7791.dtsi
index 6f87550..59a55e8 100644
--- a/arch/arm/dts/r8a7791.dtsi
+++ b/arch/arm/dts/r8a7791.dtsi
@@ -420,6 +420,9 @@
 		icram0:	sram@e63a0000 {
 			compatible = "mmio-sram";
 			reg = <0 0xe63a0000 0 0x12000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0 0xe63a0000 0x12000>;
 		};
 
 		icram1:	sram@e63c0000 {
@@ -618,8 +621,8 @@
 			compatible = "renesas,r8a7791-usb-dmac",
 				     "renesas,usb-dmac";
 			reg = <0 0xe65a0000 0 0x100>;
-			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "ch0", "ch1";
 			clocks = <&cpg CPG_MOD 330>;
 			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
@@ -632,8 +635,8 @@
 			compatible = "renesas,r8a7791-usb-dmac",
 				     "renesas,usb-dmac";
 			reg = <0 0xe65b0000 0 0x100>;
-			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "ch0", "ch1";
 			clocks = <&cpg CPG_MOD 331>;
 			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
@@ -646,22 +649,22 @@
 			compatible = "renesas,dmac-r8a7791",
 				     "renesas,rcar-dmac";
 			reg = <0 0xe6700000 0 0x20000>;
-			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					  "ch0", "ch1", "ch2", "ch3",
 					  "ch4", "ch5", "ch6", "ch7",
@@ -679,22 +682,22 @@
 			compatible = "renesas,dmac-r8a7791",
 				     "renesas,rcar-dmac";
 			reg = <0 0xe6720000 0 0x20000>;
-			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					  "ch0", "ch1", "ch2", "ch3",
 					  "ch4", "ch5", "ch6", "ch7",
@@ -1338,20 +1341,20 @@
 			compatible = "renesas,dmac-r8a7791",
 				     "renesas,rcar-dmac";
 			reg = <0 0xec700000 0 0x10000>;
-			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					  "ch0", "ch1", "ch2", "ch3",
 					  "ch4", "ch5", "ch6", "ch7",
@@ -1369,20 +1372,20 @@
 			compatible = "renesas,dmac-r8a7791",
 				     "renesas,rcar-dmac";
 			reg = <0 0xec720000 0 0x10000>;
-			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					  "ch0", "ch1", "ch2", "ch3",
 					  "ch4", "ch5", "ch6", "ch7",
@@ -1426,10 +1429,10 @@
 			#size-cells = <2>;
 			#interrupt-cells = <1>;
 			ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
-			interrupt-map-mask = <0xff00 0 0 0x7>;
-			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
-					 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
-					 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-map-mask = <0xf800 0 0 0x7>;
+			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+					<0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+					<0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 
 			usb@1,0 {
 				reg = <0x800 0 0 0 0>;
@@ -1461,10 +1464,10 @@
 			#size-cells = <2>;
 			#interrupt-cells = <1>;
 			ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
-			interrupt-map-mask = <0xff00 0 0 0x7>;
-			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
-					 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
-					 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-map-mask = <0xf800 0 0 0x7>;
+			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+					<0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+					<0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 
 			usb@1,0 {
 				reg = <0x10800 0 0 0 0>;
@@ -1598,13 +1601,13 @@
 			#size-cells = <2>;
 			bus-range = <0x00 0xff>;
 			device_type = "pci";
-			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
-				  0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
-				  0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
-				  0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
+				 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
+				 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
+				 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
 			/* Map all possible DDR as inbound ranges */
-			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
-				      0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
+			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>,
+				     <0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
 			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/dts/r8a7792-blanche.dts b/arch/arm/dts/r8a7792-blanche.dts
index f923012..248eb71 100644
--- a/arch/arm/dts/r8a7792-blanche.dts
+++ b/arch/arm/dts/r8a7792-blanche.dts
@@ -21,7 +21,7 @@
 	};
 
 	chosen {
-		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
 		stdout-path = "serial0:115200n8";
 	};
 
@@ -234,6 +234,11 @@
 		groups = "du1_rgb666", "du1_sync", "du1_disp";
 		function = "du1";
 	};
+
+	pmic_irq_pins: pmicirq {
+		groups = "intc_irq2";
+		function = "intc";
+	};
 };
 
 &rwdt {
@@ -308,6 +313,28 @@
 	};
 };
 
+&iic3 {
+	status = "okay";
+
+	pmic@58 {
+		compatible = "dlg,da9063";
+		reg = <0x58>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_irq_pins>;
+		interrupt-parent = <&irqc>;
+		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-controller;
+
+		rtc {
+			compatible = "dlg,da9063-rtc";
+		};
+
+		wdt {
+			compatible = "dlg,da9063-watchdog";
+		};
+	};
+};
+
 &du {
 	pinctrl-0 = <&du0_pins &du1_pins>;
 	pinctrl-names = "default";
diff --git a/arch/arm/dts/r8a7792.dtsi b/arch/arm/dts/r8a7792.dtsi
index 6fd80e3..39af16c 100644
--- a/arch/arm/dts/r8a7792.dtsi
+++ b/arch/arm/dts/r8a7792.dtsi
@@ -22,6 +22,7 @@
 		i2c3 = &i2c3;
 		i2c4 = &i2c4;
 		i2c5 = &i2c5;
+		i2c6 = &iic3;
 		spi0 = &qspi;
 		spi1 = &msiof0;
 		spi2 = &msiof1;
@@ -344,6 +345,9 @@
 		icram0:	sram@e63a0000 {
 			compatible = "mmio-sram";
 			reg = <0 0xe63a0000 0 0x12000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0 0xe63a0000 0x12000>;
 		};
 
 		icram1:	sram@e63c0000 {
@@ -465,22 +469,22 @@
 			compatible = "renesas,dmac-r8a7792",
 				     "renesas,rcar-dmac";
 			reg = <0 0xe6700000 0 0x20000>;
-			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					  "ch0", "ch1", "ch2", "ch3",
 					  "ch4", "ch5", "ch6", "ch7",
@@ -498,22 +502,22 @@
 			compatible = "renesas,dmac-r8a7792",
 				     "renesas,rcar-dmac";
 			reg = <0 0xe6720000 0 0x20000>;
-			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					  "ch0", "ch1", "ch2", "ch3",
 					  "ch4", "ch5", "ch6", "ch7",
@@ -874,6 +878,40 @@
 			compatible = "renesas,prr";
 			reg = <0 0xff000044 0 4>;
 		};
+
+		cmt0: timer@ffca0000 {
+			compatible = "renesas,r8a7792-cmt0",
+				     "renesas,rcar-gen2-cmt0";
+			reg = <0 0xffca0000 0 0x1004>;
+			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 124>;
+			clock-names = "fck";
+			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+			resets = <&cpg 124>;
+
+			status = "disabled";
+		};
+
+		cmt1: timer@e6130000 {
+			compatible = "renesas,r8a7792-cmt1",
+				     "renesas,rcar-gen2-cmt1";
+			reg = <0 0xe6130000 0 0x1004>;
+			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 329>;
+			clock-names = "fck";
+			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+			resets = <&cpg 329>;
+
+			status = "disabled";
+		};
 	};
 
 	timer {
diff --git a/arch/arm/dts/r8a7793-gose.dts b/arch/arm/dts/r8a7793-gose.dts
index f51601a..22ca7cd 100644
--- a/arch/arm/dts/r8a7793-gose.dts
+++ b/arch/arm/dts/r8a7793-gose.dts
@@ -52,7 +52,7 @@
 	};
 
 	chosen {
-		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
 		stdout-path = "serial0:115200n8";
 	};
 
@@ -65,81 +65,81 @@
 		compatible = "gpio-keys";
 
 		key-1 {
-		        gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
-		        linux,code = <KEY_1>;
-		        label = "SW2-1";
-		        wakeup-source;
-		        debounce-interval = <20>;
+			gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_1>;
+			label = "SW2-1";
+			wakeup-source;
+			debounce-interval = <20>;
 		};
 		key-2 {
-		        gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
-		        linux,code = <KEY_2>;
-		        label = "SW2-2";
-		        wakeup-source;
-		        debounce-interval = <20>;
+			gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_2>;
+			label = "SW2-2";
+			wakeup-source;
+			debounce-interval = <20>;
 		};
 		key-3 {
-		        gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
-		        linux,code = <KEY_3>;
-		        label = "SW2-3";
-		        wakeup-source;
-		        debounce-interval = <20>;
+			gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_3>;
+			label = "SW2-3";
+			wakeup-source;
+			debounce-interval = <20>;
 		};
 		key-4 {
-		        gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
-		        linux,code = <KEY_4>;
-		        label = "SW2-4";
-		        wakeup-source;
-		        debounce-interval = <20>;
+			gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_4>;
+			label = "SW2-4";
+			wakeup-source;
+			debounce-interval = <20>;
 		};
 		key-a {
-		        gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
-		        linux,code = <KEY_A>;
-		        label = "SW30";
-		        wakeup-source;
-		        debounce-interval = <20>;
+			gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_A>;
+			label = "SW30";
+			wakeup-source;
+			debounce-interval = <20>;
 		};
 		key-b {
-		        gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
-		        linux,code = <KEY_B>;
-		        label = "SW31";
-		        wakeup-source;
-		        debounce-interval = <20>;
+			gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_B>;
+			label = "SW31";
+			wakeup-source;
+			debounce-interval = <20>;
 		};
 		key-c {
-		        gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
-		        linux,code = <KEY_C>;
-		        label = "SW32";
-		        wakeup-source;
-		        debounce-interval = <20>;
+			gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_C>;
+			label = "SW32";
+			wakeup-source;
+			debounce-interval = <20>;
 		};
 		key-d {
-		        gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
-		        linux,code = <KEY_D>;
-		        label = "SW33";
-		        wakeup-source;
-		        debounce-interval = <20>;
+			gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_D>;
+			label = "SW33";
+			wakeup-source;
+			debounce-interval = <20>;
 		};
 		key-e {
-		        gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
-		        linux,code = <KEY_E>;
-		        label = "SW34";
-		        wakeup-source;
-		        debounce-interval = <20>;
+			gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_E>;
+			label = "SW34";
+			wakeup-source;
+			debounce-interval = <20>;
 		};
 		key-f {
-		        gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
-		        linux,code = <KEY_F>;
-		        label = "SW35";
-		        wakeup-source;
-		        debounce-interval = <20>;
+			gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_F>;
+			label = "SW35";
+			wakeup-source;
+			debounce-interval = <20>;
 		};
 		key-g {
-		        gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
-		        linux,code = <KEY_G>;
-		        label = "SW36";
-		        wakeup-source;
-		        debounce-interval = <20>;
+			gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_G>;
+			label = "SW36";
+			wakeup-source;
+			debounce-interval = <20>;
 		};
 	};
 
@@ -179,8 +179,7 @@
 
 		gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
 		gpios-states = <1>;
-		states = <3300000 1
-			  1800000 0>;
+		states = <3300000 1>, <1800000 0>;
 	};
 
 	vcc_sdhi1: regulator-vcc-sdhi1 {
@@ -203,8 +202,7 @@
 
 		gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
 		gpios-states = <1>;
-		states = <3300000 1
-			  1800000 0>;
+		states = <3300000 1>, <1800000 0>;
 	};
 
 	vcc_sdhi2: regulator-vcc-sdhi2 {
@@ -227,8 +225,7 @@
 
 		gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
 		gpios-states = <1>;
-		states = <3300000 1
-			  1800000 0>;
+		states = <3300000 1>, <1800000 0>;
 	};
 
 	audio_clock: audio_clock {
@@ -514,6 +511,11 @@
 		function = "intc";
 	};
 
+	pmic_irq_pins: pmicirq {
+		groups = "intc_irq2";
+		function = "intc";
+	};
+
 	sdhi0_pins: sd0 {
 		groups = "sdhi0_data4", "sdhi0_ctrl";
 		function = "sdhi0";
@@ -711,6 +713,8 @@
 };
 
 &i2c6 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pmic_irq_pins>;
 	status = "okay";
 	clock-frequency = <100000>;
 
diff --git a/arch/arm/dts/r8a7793.dtsi b/arch/arm/dts/r8a7793.dtsi
index bf05110..eef035c 100644
--- a/arch/arm/dts/r8a7793.dtsi
+++ b/arch/arm/dts/r8a7793.dtsi
@@ -406,6 +406,9 @@
 		icram0:	sram@e63a0000 {
 			compatible = "mmio-sram";
 			reg = <0 0xe63a0000 0 0x12000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0 0xe63a0000 0x12000>;
 		};
 
 		icram1:	sram@e63c0000 {
@@ -565,22 +568,22 @@
 			compatible = "renesas,dmac-r8a7793",
 				     "renesas,rcar-dmac";
 			reg = <0 0xe6700000 0 0x20000>;
-			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					  "ch0", "ch1", "ch2", "ch3",
 					  "ch4", "ch5", "ch6", "ch7",
@@ -598,22 +601,22 @@
 			compatible = "renesas,dmac-r8a7793",
 				     "renesas,rcar-dmac";
 			reg = <0 0xe6720000 0 0x20000>;
-			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					  "ch0", "ch1", "ch2", "ch3",
 					  "ch4", "ch5", "ch6", "ch7",
@@ -1166,20 +1169,20 @@
 			compatible = "renesas,dmac-r8a7793",
 				     "renesas,rcar-dmac";
 			reg = <0 0xec700000 0 0x10000>;
-			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					  "ch0", "ch1", "ch2", "ch3",
 					  "ch4", "ch5", "ch6", "ch7",
@@ -1197,20 +1200,20 @@
 			compatible = "renesas,dmac-r8a7793",
 				     "renesas,rcar-dmac";
 			reg = <0 0xec720000 0 0x10000>;
-			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					  "ch0", "ch1", "ch2", "ch3",
 					  "ch4", "ch5", "ch6", "ch7",
diff --git a/arch/arm/dts/r8a7794-alt.dts b/arch/arm/dts/r8a7794-alt.dts
index ef7e2a8..f79fce7 100644
--- a/arch/arm/dts/r8a7794-alt.dts
+++ b/arch/arm/dts/r8a7794-alt.dts
@@ -22,7 +22,7 @@
 	};
 
 	chosen {
-		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
 		stdout-path = "serial0:115200n8";
 	};
 
@@ -60,8 +60,7 @@
 
 		gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
 		gpios-states = <1>;
-		states = <3300000 1
-			  1800000 0>;
+		states = <3300000 1>, <1800000 0>;
 	};
 
 	vcc_sdhi1: regulator-vcc-sdhi1 {
@@ -84,8 +83,7 @@
 
 		gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
 		gpios-states = <1>;
-		states = <3300000 1
-			  1800000 0>;
+		states = <3300000 1>, <1800000 0>;
 	};
 
 	lbsc {
@@ -199,6 +197,22 @@
 	};
 };
 
+&pci0 {
+	status = "okay";
+	pinctrl-0 = <&usb0_pins>;
+	pinctrl-names = "default";
+};
+
+&pci1 {
+	status = "okay";
+	pinctrl-0 = <&usb1_pins>;
+	pinctrl-names = "default";
+};
+
+&usbphy {
+	status = "okay";
+};
+
 &du {
 	pinctrl-0 = <&du_pins>;
 	pinctrl-names = "default";
@@ -293,6 +307,16 @@
 		function = "sdhi1";
 		power-source = <1800>;
 	};
+
+	usb0_pins: usb0 {
+		groups = "usb0";
+		function = "usb0";
+	};
+
+	usb1_pins: usb1 {
+		groups = "usb1";
+		function = "usb1";
+	};
 };
 
 &cmt0 {
@@ -377,6 +401,27 @@
 	pinctrl-names = "i2c-exio4";
 };
 
+&i2c7 {
+	status = "okay";
+	clock-frequency = <100000>;
+
+	pmic@58 {
+		compatible = "dlg,da9063";
+		reg = <0x58>;
+		interrupt-parent = <&gpio3>;
+		interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-controller;
+
+		rtc {
+			compatible = "dlg,da9063-rtc";
+		};
+
+		wdt {
+			compatible = "dlg,da9063-watchdog";
+		};
+	};
+};
+
 &vin0 {
 	status = "okay";
 	pinctrl-0 = <&vin0_pins>;
diff --git a/arch/arm/dts/r8a7794-silk.dts b/arch/arm/dts/r8a7794-silk.dts
index 60e91eb..2c16ad8 100644
--- a/arch/arm/dts/r8a7794-silk.dts
+++ b/arch/arm/dts/r8a7794-silk.dts
@@ -34,7 +34,7 @@
 	};
 
 	chosen {
-		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
 		stdout-path = "serial0:115200n8";
 	};
 
@@ -126,8 +126,7 @@
 
 		gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
 		gpios-states = <1>;
-		states = <3300000 1
-			  1800000 0>;
+		states = <3300000 1>, <1800000 0>;
 	};
 
 	vga-encoder {
diff --git a/arch/arm/dts/r8a7794.dtsi b/arch/arm/dts/r8a7794.dtsi
index 8d797d3..05ef79c 100644
--- a/arch/arm/dts/r8a7794.dtsi
+++ b/arch/arm/dts/r8a7794.dtsi
@@ -351,6 +351,9 @@
 		icram0:	sram@e63a0000 {
 			compatible = "mmio-sram";
 			reg = <0 0xe63a0000 0 0x12000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0 0xe63a0000 0x12000>;
 		};
 
 		icram1:	sram@e63c0000 {
@@ -527,22 +530,22 @@
 			compatible = "renesas,dmac-r8a7794",
 				     "renesas,rcar-dmac";
 			reg = <0 0xe6700000 0 0x20000>;
-			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					  "ch0", "ch1", "ch2", "ch3",
 					  "ch4", "ch5", "ch6", "ch7",
@@ -560,22 +563,22 @@
 			compatible = "renesas,dmac-r8a7794",
 				     "renesas,rcar-dmac";
 			reg = <0 0xe6720000 0 0x20000>;
-			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					  "ch0", "ch1", "ch2", "ch3",
 					  "ch4", "ch5", "ch6", "ch7",
@@ -1132,20 +1135,20 @@
 			compatible = "renesas,dmac-r8a7794",
 				     "renesas,rcar-dmac";
 			reg = <0 0xec700000 0 0x10000>;
-			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					  "ch0", "ch1", "ch2", "ch3", "ch4",
 					  "ch5", "ch6", "ch7", "ch8", "ch9",
@@ -1176,10 +1179,10 @@
 			#size-cells = <2>;
 			#interrupt-cells = <1>;
 			ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
-			interrupt-map-mask = <0xff00 0 0 0x7>;
-			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
-					 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
-					 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-map-mask = <0xf800 0 0 0x7>;
+			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+					<0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+					<0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 
 			usb@1,0 {
 				reg = <0x800 0 0 0 0>;
@@ -1211,10 +1214,10 @@
 			#size-cells = <2>;
 			#interrupt-cells = <1>;
 			ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
-			interrupt-map-mask = <0xff00 0 0 0x7>;
-			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
-					 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
-					 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-map-mask = <0xf800 0 0 0x7>;
+			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+					<0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+					<0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 
 			usb@1,0 {
 				reg = <0x10800 0 0 0 0>;
diff --git a/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts b/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts
deleted file mode 100644
index ef1c57f..0000000
--- a/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts
+++ /dev/null
@@ -1,36 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source extras for U-Boot for the ULCB board
- *
- * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
- */
-
-#include "r8a7795-h3ulcb.dts"
-#include "r8a7795-u-boot.dtsi"
-
-/ {
-	cpld {
-		compatible = "renesas,ulcb-cpld";
-		status = "okay";
-		gpio-sck = <&gpio6 8 0>;
-		gpio-mosi = <&gpio6 7 0>;
-		gpio-miso = <&gpio6 10 0>;
-		gpio-sstbz = <&gpio2 3 0>;
-	};
-};
-
-&sdhi0 {
-	sd-uhs-sdr12;
-	sd-uhs-sdr25;
-	sd-uhs-sdr104;
-	max-frequency = <208000000>;
-};
-
-&sdhi2 {
-	mmc-hs400-1_8v;
-	max-frequency = <200000000>;
-};
-
-&vcc_sdhi0 {
-	u-boot,off-on-delay-us = <20000>;
-};
diff --git a/arch/arm/dts/r8a7795-u-boot.dtsi b/arch/arm/dts/r8a7795-u-boot.dtsi
deleted file mode 100644
index 3f4b1f5..0000000
--- a/arch/arm/dts/r8a7795-u-boot.dtsi
+++ /dev/null
@@ -1,24 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source extras for U-Boot on RCar R8A7795 SoC
- *
- * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
- */
-
-#include "r8a779x-u-boot.dtsi"
-
-&extalr_clk {
-	u-boot,dm-pre-reloc;
-};
-
-/ {
-	soc {
-		rpc: rpc@0xee200000 {
-			compatible = "renesas,rpc-r8a7795", "renesas,rpc";
-			reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
-			clocks = <&cpg CPG_MOD 917>;
-			bank-width = <2>;
-			status = "disabled";
-		};
-	};
-};
diff --git a/arch/arm/dts/r8a7795-salvator-x-u-boot.dts b/arch/arm/dts/r8a77950-salvator-x-u-boot.dts
similarity index 88%
copy from arch/arm/dts/r8a7795-salvator-x-u-boot.dts
copy to arch/arm/dts/r8a77950-salvator-x-u-boot.dts
index e93afe3..6e5c271 100644
--- a/arch/arm/dts/r8a7795-salvator-x-u-boot.dts
+++ b/arch/arm/dts/r8a77950-salvator-x-u-boot.dts
@@ -5,8 +5,8 @@
  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  */
 
-#include "r8a7795-salvator-x.dts"
-#include "r8a7795-u-boot.dtsi"
+#include "r8a77950-salvator-x.dts"
+#include "r8a77950-u-boot.dtsi"
 
 &sdhi0 {
 	sd-uhs-sdr12;
diff --git a/arch/arm/dts/r8a7795-salvator-x.dts b/arch/arm/dts/r8a77950-salvator-x.dts
similarity index 94%
rename from arch/arm/dts/r8a7795-salvator-x.dts
rename to arch/arm/dts/r8a77950-salvator-x.dts
index d2d48b3..2438825 100644
--- a/arch/arm/dts/r8a7795-salvator-x.dts
+++ b/arch/arm/dts/r8a77950-salvator-x.dts
@@ -1,16 +1,16 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the Salvator-X board with R-Car H3 ES2.0
+ * Device Tree Source for the Salvator-X board with R-Car H3 ES1.x
  *
  * Copyright (C) 2015 Renesas Electronics Corp.
  */
 
 /dts-v1/;
-#include "r8a7795.dtsi"
+#include "r8a77950.dtsi"
 #include "salvator-x.dtsi"
 
 / {
-	model = "Renesas Salvator-X board based on r8a7795 ES2.0+";
+	model = "Renesas Salvator-X board based on r8a77950";
 	compatible = "renesas,salvator-x", "renesas,r8a7795";
 
 	memory@48000000 {
@@ -52,12 +52,6 @@
 	status = "okay";
 };
 
-&sound_card {
-	dais = <&rsnd_port0	/* ak4613 */
-		&rsnd_port1	/* HDMI0  */
-		&rsnd_port2>;	/* HDMI1  */
-};
-
 &hdmi0 {
 	status = "okay";
 
@@ -108,6 +102,13 @@
 	status = "okay";
 };
 
+&pfc {
+	usb2_pins: usb2 {
+		groups = "usb2";
+		function = "usb2";
+	};
+};
+
 &rcar_sound {
 	ports {
 		/* rsnd_port0 is on salvator-common */
@@ -138,17 +139,16 @@
 	};
 };
 
-&pfc {
-	usb2_pins: usb2 {
-		groups = "usb2";
-		function = "usb2";
-	};
-};
-
 &sata {
 	status = "okay";
 };
 
+&sound_card {
+	dais = <&rsnd_port0	/* ak4613 */
+		&rsnd_port1	/* HDMI0  */
+		&rsnd_port2>;	/* HDMI1  */
+};
+
 &usb2_phy2 {
 	pinctrl-0 = <&usb2_pins>;
 	pinctrl-names = "default";
diff --git a/arch/arm/dts/r8a77950-u-boot.dtsi b/arch/arm/dts/r8a77950-u-boot.dtsi
new file mode 100644
index 0000000..0317f47
--- /dev/null
+++ b/arch/arm/dts/r8a77950-u-boot.dtsi
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot on RCar R8A7795 SoC
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+&extalr_clk {
+	u-boot,dm-pre-reloc;
+};
+
+/ {
+	soc {
+		rpc: rpc@0xee200000 {
+			compatible = "renesas,rpc-r8a7795", "renesas,rpc";
+			reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
+			clocks = <&cpg CPG_MOD 917>;
+			bank-width = <2>;
+			status = "disabled";
+		};
+	};
+};
+
+/delete-node/ &ak4613;
+/delete-node/ &audma0;
+/delete-node/ &audma1;
+/delete-node/ &can0;
+/delete-node/ &can1;
+/delete-node/ &canfd;
+/delete-node/ &csi20;
+/delete-node/ &csi21;
+/delete-node/ &csi40;
+/delete-node/ &csi41;
+/delete-node/ &drif00;
+/delete-node/ &drif01;
+/delete-node/ &drif10;
+/delete-node/ &drif11;
+/delete-node/ &drif20;
+/delete-node/ &drif21;
+/delete-node/ &drif30;
+/delete-node/ &drif31;
+/delete-node/ &du;
+/delete-node/ &fcpf0;
+/delete-node/ &fcpf1;
+/delete-node/ &fcpf2;
+/delete-node/ &fcpvb0;
+/delete-node/ &fcpvb1;
+/delete-node/ &fcpvd0;
+/delete-node/ &fcpvd1;
+/delete-node/ &fcpvd2;
+/delete-node/ &fcpvd3;
+/delete-node/ &fcpvi0;
+/delete-node/ &fcpvi1;
+/delete-node/ &fcpvi2;
+/delete-node/ &hdmi0;
+/delete-node/ &hdmi1;
+/delete-node/ &lvds0;
+/delete-node/ &rcar_sound;
+/delete-node/ &sound_card;
+/delete-node/ &vin0;
+/delete-node/ &vin1;
+/delete-node/ &vin2;
+/delete-node/ &vin3;
+/delete-node/ &vin4;
+/delete-node/ &vin5;
+/delete-node/ &vin6;
+/delete-node/ &vin7;
+/delete-node/ &vspbc;
+/delete-node/ &vspbd;
+/delete-node/ &vspd0;
+/delete-node/ &vspd1;
+/delete-node/ &vspd2;
+/delete-node/ &vspd3;
+/delete-node/ &vspi0;
+/delete-node/ &vspi1;
+/delete-node/ &vspi2;
+
+/ {
+	/delete-node/ cvbs-in;
+	/delete-node/ hdmi-in;
+	/delete-node/ hdmi0-out;
+	/delete-node/ hdmi1-out;
+	/delete-node/ vga-encoder;
+	/delete-node/ vga;
+};
+
+&i2c4 {
+	/delete-node/ video-receiver@70;
+};
+
+&soc {
+	/delete-node/ fdp1@fe940000;
+	/delete-node/ fdp1@fe944000;
+	/delete-node/ fdp1@fe948000;
+	/delete-node/ imr-lx4@fe860000;
+	/delete-node/ imr-lx4@fe870000;
+	/delete-node/ imr-lx4@fe880000;
+	/delete-node/ imr-lx4@fe890000;
+};
diff --git a/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts b/arch/arm/dts/r8a77950-ulcb-u-boot.dts
similarity index 89%
rename from arch/arm/dts/r8a7796-m3ulcb-u-boot.dts
rename to arch/arm/dts/r8a77950-ulcb-u-boot.dts
index 314eacc..fb9bbe1 100644
--- a/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts
+++ b/arch/arm/dts/r8a77950-ulcb-u-boot.dts
@@ -5,8 +5,8 @@
  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  */
 
-#include "r8a7796-m3ulcb.dts"
-#include "r8a7796-u-boot.dtsi"
+#include "r8a77950-ulcb.dts"
+#include "r8a77950-u-boot.dtsi"
 
 / {
 	cpld {
diff --git a/arch/arm/dts/r8a7795-h3ulcb.dts b/arch/arm/dts/r8a77950-ulcb.dts
similarity index 65%
rename from arch/arm/dts/r8a7795-h3ulcb.dts
rename to arch/arm/dts/r8a77950-ulcb.dts
index 54515ea..38a6d6a 100644
--- a/arch/arm/dts/r8a7795-h3ulcb.dts
+++ b/arch/arm/dts/r8a77950-ulcb.dts
@@ -7,11 +7,11 @@
  */
 
 /dts-v1/;
-#include "r8a7795.dtsi"
+#include "r8a77950.dtsi"
 #include "ulcb.dtsi"
 
 / {
-	model = "Renesas H3ULCB board based on r8a7795 ES2.0+";
+	model = "Renesas H3ULCB board based on r8a77950";
 	compatible = "renesas,h3ulcb", "renesas,r8a7795";
 
 	memory@48000000 {
@@ -35,16 +35,3 @@
 		reg = <0x7 0x00000000 0x0 0x40000000>;
 	};
 };
-
-&du {
-	clocks = <&cpg CPG_MOD 724>,
-		 <&cpg CPG_MOD 723>,
-		 <&cpg CPG_MOD 722>,
-		 <&cpg CPG_MOD 721>,
-		 <&versaclock5 1>,
-		 <&versaclock5 3>,
-		 <&versaclock5 4>,
-		 <&versaclock5 2>;
-	clock-names = "du.0", "du.1", "du.2", "du.3",
-		      "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
-};
diff --git a/arch/arm/dts/r8a77950.dtsi b/arch/arm/dts/r8a77950.dtsi
new file mode 100644
index 0000000..1521649
--- /dev/null
+++ b/arch/arm/dts/r8a77950.dtsi
@@ -0,0 +1,319 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the R-Car H3 (R8A77950) SoC
+ *
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ */
+
+#include "r8a77951.dtsi"
+
+&audma0 {
+	iommus = <&ipmmu_mp1 0>, <&ipmmu_mp1 1>,
+	       <&ipmmu_mp1 2>, <&ipmmu_mp1 3>,
+	       <&ipmmu_mp1 4>, <&ipmmu_mp1 5>,
+	       <&ipmmu_mp1 6>, <&ipmmu_mp1 7>,
+	       <&ipmmu_mp1 8>, <&ipmmu_mp1 9>,
+	       <&ipmmu_mp1 10>, <&ipmmu_mp1 11>,
+	       <&ipmmu_mp1 12>, <&ipmmu_mp1 13>,
+	       <&ipmmu_mp1 14>, <&ipmmu_mp1 15>;
+};
+
+&audma1 {
+	iommus = <&ipmmu_mp1 16>, <&ipmmu_mp1 17>,
+	       <&ipmmu_mp1 18>, <&ipmmu_mp1 19>,
+	       <&ipmmu_mp1 20>, <&ipmmu_mp1 21>,
+	       <&ipmmu_mp1 22>, <&ipmmu_mp1 23>,
+	       <&ipmmu_mp1 24>, <&ipmmu_mp1 25>,
+	       <&ipmmu_mp1 26>, <&ipmmu_mp1 27>,
+	       <&ipmmu_mp1 28>, <&ipmmu_mp1 29>,
+	       <&ipmmu_mp1 30>, <&ipmmu_mp1 31>;
+};
+
+&du {
+	vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd3 0>;
+};
+
+&fcpvb1 {
+	iommus = <&ipmmu_vp0 7>;
+};
+
+&fcpf1 {
+	iommus = <&ipmmu_vp0 1>;
+};
+
+&fcpvi1 {
+	iommus = <&ipmmu_vp0 9>;
+};
+
+&fcpvd2 {
+	iommus = <&ipmmu_vi0 10>;
+};
+
+&gpio1 {
+	gpio-ranges = <&pfc 0 32 28>;
+};
+
+&ipmmu_vi0 {
+	renesas,ipmmu-main = <&ipmmu_mm 11>;
+};
+
+&ipmmu_vp0 {
+	renesas,ipmmu-main = <&ipmmu_mm 12>;
+};
+
+&ipmmu_vc0 {
+	renesas,ipmmu-main = <&ipmmu_mm 9>;
+};
+
+&ipmmu_vc1 {
+	renesas,ipmmu-main = <&ipmmu_mm 10>;
+};
+
+&ipmmu_rt {
+	renesas,ipmmu-main = <&ipmmu_mm 7>;
+};
+
+&soc {
+	/delete-node/ dma-controller@e6460000;
+	/delete-node/ dma-controller@e6470000;
+
+	ipmmu_mp1: mmu@ec680000 {
+		compatible = "renesas,ipmmu-r8a7795";
+		reg = <0 0xec680000 0 0x1000>;
+		renesas,ipmmu-main = <&ipmmu_mm 5>;
+		power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+		#iommu-cells = <1>;
+	};
+
+	ipmmu_sy: mmu@e7730000 {
+		compatible = "renesas,ipmmu-r8a7795";
+		reg = <0 0xe7730000 0 0x1000>;
+		renesas,ipmmu-main = <&ipmmu_mm 8>;
+		power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+		#iommu-cells = <1>;
+	};
+
+	/delete-node/ mmu@fd950000;
+	/delete-node/ mmu@fd960000;
+	/delete-node/ mmu@fd970000;
+	/delete-node/ mmu@febe0000;
+	/delete-node/ mmu@fe980000;
+
+	xhci1: usb@ee040000 {
+		compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";
+		reg = <0 0xee040000 0 0xc00>;
+		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cpg CPG_MOD 327>;
+		power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+		resets = <&cpg 327>;
+		status = "disabled";
+	};
+
+	/delete-node/ usb@e659c000;
+	/delete-node/ usb@ee0e0000;
+	/delete-node/ usb@ee0e0100;
+
+	/delete-node/ usb-phy@ee0e0200;
+
+	fdp1@fe948000 {
+		compatible = "renesas,fdp1";
+		reg = <0 0xfe948000 0 0x2400>;
+		interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cpg CPG_MOD 117>;
+		power-domains = <&sysc R8A7795_PD_A3VP>;
+		resets = <&cpg 117>;
+		renesas,fcp = <&fcpf2>;
+	};
+
+	fcpf2: fcp@fe952000 {
+		compatible = "renesas,fcpf";
+		reg = <0 0xfe952000 0 0x200>;
+		clocks = <&cpg CPG_MOD 613>;
+		power-domains = <&sysc R8A7795_PD_A3VP>;
+		resets = <&cpg 613>;
+		iommus = <&ipmmu_vp0 2>;
+	};
+
+	fcpvd3: fcp@fea3f000 {
+		compatible = "renesas,fcpv";
+		reg = <0 0xfea3f000 0 0x200>;
+		clocks = <&cpg CPG_MOD 600>;
+		power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+		resets = <&cpg 600>;
+		iommus = <&ipmmu_vi0 11>;
+	};
+
+	fcpvi2: fcp@fe9cf000 {
+		compatible = "renesas,fcpv";
+		reg = <0 0xfe9cf000 0 0x200>;
+		clocks = <&cpg CPG_MOD 609>;
+		power-domains = <&sysc R8A7795_PD_A3VP>;
+		resets = <&cpg 609>;
+		iommus = <&ipmmu_vp0 10>;
+	};
+
+	vspd3: vsp@fea38000 {
+		compatible = "renesas,vsp2";
+		reg = <0 0xfea38000 0 0x5000>;
+		interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cpg CPG_MOD 620>;
+		power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+		resets = <&cpg 620>;
+
+		renesas,fcp = <&fcpvd3>;
+	};
+
+	vspi2: vsp@fe9c0000 {
+		compatible = "renesas,vsp2";
+		reg = <0 0xfe9c0000 0 0x8000>;
+		interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cpg CPG_MOD 629>;
+		power-domains = <&sysc R8A7795_PD_A3VP>;
+		resets = <&cpg 629>;
+
+		renesas,fcp = <&fcpvi2>;
+	};
+
+	csi21: csi2@fea90000 {
+		compatible = "renesas,r8a7795-csi2";
+		reg = <0 0xfea90000 0 0x10000>;
+		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cpg CPG_MOD 713>;
+		power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+		resets = <&cpg 713>;
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reg = <1>;
+
+				csi21vin0: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&vin0csi21>;
+				};
+				csi21vin1: endpoint@1 {
+					reg = <1>;
+					remote-endpoint = <&vin1csi21>;
+				};
+				csi21vin2: endpoint@2 {
+					reg = <2>;
+					remote-endpoint = <&vin2csi21>;
+				};
+				csi21vin3: endpoint@3 {
+					reg = <3>;
+					remote-endpoint = <&vin3csi21>;
+				};
+				csi21vin4: endpoint@4 {
+					reg = <4>;
+					remote-endpoint = <&vin4csi21>;
+				};
+				csi21vin5: endpoint@5 {
+					reg = <5>;
+					remote-endpoint = <&vin5csi21>;
+				};
+				csi21vin6: endpoint@6 {
+					reg = <6>;
+					remote-endpoint = <&vin6csi21>;
+				};
+				csi21vin7: endpoint@7 {
+					reg = <7>;
+					remote-endpoint = <&vin7csi21>;
+				};
+			};
+		};
+	};
+};
+
+&vin0 {
+	ports {
+		port@1 {
+			vin0csi21: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&csi21vin0>;
+			};
+		};
+	};
+};
+
+&vin1 {
+	ports {
+		port@1 {
+			vin1csi21: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&csi21vin1>;
+			};
+		};
+	};
+};
+
+&vin2 {
+	ports {
+		port@1 {
+			vin2csi21: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&csi21vin2>;
+			};
+		};
+	};
+};
+
+&vin3 {
+	ports {
+		port@1 {
+			vin3csi21: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&csi21vin3>;
+			};
+		};
+	};
+};
+
+&vin4 {
+	ports {
+		port@1 {
+			vin4csi21: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&csi21vin4>;
+			};
+		};
+	};
+};
+
+&vin5 {
+	ports {
+		port@1 {
+			vin5csi21: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&csi21vin5>;
+			};
+		};
+	};
+};
+
+&vin6 {
+	ports {
+		port@1 {
+			vin6csi21: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&csi21vin6>;
+			};
+		};
+	};
+};
+
+&vin7 {
+	ports {
+		port@1 {
+			vin7csi21: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&csi21vin7>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/dts/r8a7795.dtsi b/arch/arm/dts/r8a77951.dtsi
similarity index 91%
rename from arch/arm/dts/r8a7795.dtsi
rename to arch/arm/dts/r8a77951.dtsi
index 097538c..a8729eb 100644
--- a/arch/arm/dts/r8a7795.dtsi
+++ b/arch/arm/dts/r8a77951.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the R-Car H3 (R8A77950) SoC
+ * Device Tree Source for the R-Car H3 (R8A77951) SoC
  *
  * Copyright (C) 2015 Renesas Electronics Corp.
  */
@@ -155,6 +155,8 @@
 			power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
 			next-level-cache = <&L2_CA57>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
+			dynamic-power-coefficient = <854>;
 			clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
 			operating-points-v2 = <&cluster0_opp>;
 			capacity-dmips-mhz = <1024>;
@@ -168,6 +170,7 @@
 			power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
 			next-level-cache = <&L2_CA57>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
 			clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
 			operating-points-v2 = <&cluster0_opp>;
 			capacity-dmips-mhz = <1024>;
@@ -181,6 +184,7 @@
 			power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
 			next-level-cache = <&L2_CA57>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
 			clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
 			operating-points-v2 = <&cluster0_opp>;
 			capacity-dmips-mhz = <1024>;
@@ -194,6 +198,7 @@
 			power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
 			next-level-cache = <&L2_CA57>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
 			clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
 			operating-points-v2 = <&cluster0_opp>;
 			capacity-dmips-mhz = <1024>;
@@ -207,6 +212,9 @@
 			power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_1>;
+			#cooling-cells = <2>;
+			dynamic-power-coefficient = <277>;
 			clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
 			operating-points-v2 = <&cluster1_opp>;
 			capacity-dmips-mhz = <535>;
@@ -219,6 +227,7 @@
 			power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_1>;
 			clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
 			operating-points-v2 = <&cluster1_opp>;
 			capacity-dmips-mhz = <535>;
@@ -231,6 +240,7 @@
 			power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_1>;
 			clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
 			operating-points-v2 = <&cluster1_opp>;
 			capacity-dmips-mhz = <535>;
@@ -243,6 +253,7 @@
 			power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_1>;
 			clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
 			operating-points-v2 = <&cluster1_opp>;
 			capacity-dmips-mhz = <535>;
@@ -261,6 +272,28 @@
 			cache-unified;
 			cache-level = <2>;
 		};
+
+		idle-states {
+			entry-method = "psci";
+
+			CPU_SLEEP_0: cpu-sleep-0 {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x0010000>;
+				local-timer-stop;
+				entry-latency-us = <400>;
+				exit-latency-us = <500>;
+				min-residency-us = <4000>;
+			};
+
+			CPU_SLEEP_1: cpu-sleep-1 {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x0010000>;
+				local-timer-stop;
+				entry-latency-us = <700>;
+				exit-latency-us = <700>;
+				min-residency-us = <5000>;
+			};
+		};
 	};
 
 	extal_clk: extal {
@@ -572,12 +605,12 @@
 			#interrupt-cells = <2>;
 			interrupt-controller;
 			reg = <0 0xe61c0000 0 0x200>;
-			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 407>;
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 			resets = <&cpg 407>;
@@ -812,7 +845,7 @@
 			       <&usb_dmac1 0>, <&usb_dmac1 1>;
 			dma-names = "ch0", "ch1", "ch2", "ch3";
 			renesas,buswait = <11>;
-			phys = <&usb2_phy0>;
+			phys = <&usb2_phy0 3>;
 			phy-names = "usb";
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 			resets = <&cpg 704>, <&cpg 703>;
@@ -829,7 +862,7 @@
 			       <&usb_dmac3 0>, <&usb_dmac3 1>;
 			dma-names = "ch0", "ch1", "ch2", "ch3";
 			renesas,buswait = <11>;
-			phys = <&usb2_phy3>;
+			phys = <&usb2_phy3 3>;
 			phy-names = "usb";
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 			resets = <&cpg 705>, <&cpg 700>;
@@ -840,8 +873,8 @@
 			compatible = "renesas,r8a7795-usb-dmac",
 				     "renesas,usb-dmac";
 			reg = <0 0xe65a0000 0 0x100>;
-			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "ch0", "ch1";
 			clocks = <&cpg CPG_MOD 330>;
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -854,8 +887,8 @@
 			compatible = "renesas,r8a7795-usb-dmac",
 				     "renesas,usb-dmac";
 			reg = <0 0xe65b0000 0 0x100>;
-			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "ch0", "ch1";
 			clocks = <&cpg CPG_MOD 331>;
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -868,8 +901,8 @@
 			compatible = "renesas,r8a7795-usb-dmac",
 				     "renesas,usb-dmac";
 			reg = <0 0xe6460000 0 0x100>;
-			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "ch0", "ch1";
 			clocks = <&cpg CPG_MOD 326>;
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -882,8 +915,8 @@
 			compatible = "renesas,r8a7795-usb-dmac",
 				     "renesas,usb-dmac";
 			reg = <0 0xe6470000 0 0x100>;
-			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "ch0", "ch1";
 			clocks = <&cpg CPG_MOD 329>;
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -918,23 +951,23 @@
 			compatible = "renesas,dmac-r8a7795",
 				     "renesas,rcar-dmac";
 			reg = <0 0xe6700000 0 0x10000>;
-			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					"ch0", "ch1", "ch2", "ch3",
 					"ch4", "ch5", "ch6", "ch7",
@@ -960,23 +993,23 @@
 			compatible = "renesas,dmac-r8a7795",
 				     "renesas,rcar-dmac";
 			reg = <0 0xe7300000 0 0x10000>;
-			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					"ch0", "ch1", "ch2", "ch3",
 					"ch4", "ch5", "ch6", "ch7",
@@ -1002,23 +1035,23 @@
 			compatible = "renesas,dmac-r8a7795",
 				     "renesas,rcar-dmac";
 			reg = <0 0xe7310000 0 0x10000>;
-			interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					"ch0", "ch1", "ch2", "ch3",
 					"ch4", "ch5", "ch6", "ch7",
@@ -1450,6 +1483,17 @@
 			status = "disabled";
 		};
 
+		tpu: pwm@e6e80000 {
+			compatible = "renesas,tpu-r8a7795", "renesas,tpu";
+			reg = <0 0xe6e80000 0 0x148>;
+			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 304>;
+			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+			resets = <&cpg 304>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
 		msiof0: spi@e6e90000 {
 			compatible = "renesas,msiof-r8a7795",
 				     "renesas,rcar-gen3-msiof";
@@ -2299,23 +2343,23 @@
 			compatible = "renesas,dmac-r8a7795",
 				     "renesas,rcar-dmac";
 			reg = <0 0xec700000 0 0x10000>;
-			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					"ch0", "ch1", "ch2", "ch3",
 					"ch4", "ch5", "ch6", "ch7",
@@ -2341,23 +2385,23 @@
 			compatible = "renesas,dmac-r8a7795",
 				     "renesas,rcar-dmac";
 			reg = <0 0xec720000 0 0x10000>;
-			interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					"ch0", "ch1", "ch2", "ch3",
 					"ch4", "ch5", "ch6", "ch7",
@@ -2405,7 +2449,7 @@
 			reg = <0 0xee080000 0 0x100>;
 			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
-			phys = <&usb2_phy0>;
+			phys = <&usb2_phy0 1>;
 			phy-names = "usb";
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 			resets = <&cpg 703>, <&cpg 704>;
@@ -2417,7 +2461,7 @@
 			reg = <0 0xee0a0000 0 0x100>;
 			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 702>;
-			phys = <&usb2_phy1>;
+			phys = <&usb2_phy1 1>;
 			phy-names = "usb";
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 			resets = <&cpg 702>;
@@ -2429,7 +2473,7 @@
 			reg = <0 0xee0c0000 0 0x100>;
 			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 701>;
-			phys = <&usb2_phy2>;
+			phys = <&usb2_phy2 1>;
 			phy-names = "usb";
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 			resets = <&cpg 701>;
@@ -2441,7 +2485,7 @@
 			reg = <0 0xee0e0000 0 0x100>;
 			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>;
-			phys = <&usb2_phy3>;
+			phys = <&usb2_phy3 1>;
 			phy-names = "usb";
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 			resets = <&cpg 700>, <&cpg 705>;
@@ -2453,7 +2497,7 @@
 			reg = <0 0xee080100 0 0x100>;
 			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
-			phys = <&usb2_phy0>;
+			phys = <&usb2_phy0 2>;
 			phy-names = "usb";
 			companion = <&ohci0>;
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -2466,7 +2510,7 @@
 			reg = <0 0xee0a0100 0 0x100>;
 			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 702>;
-			phys = <&usb2_phy1>;
+			phys = <&usb2_phy1 2>;
 			phy-names = "usb";
 			companion = <&ohci1>;
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -2479,7 +2523,7 @@
 			reg = <0 0xee0c0100 0 0x100>;
 			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 701>;
-			phys = <&usb2_phy2>;
+			phys = <&usb2_phy2 2>;
 			phy-names = "usb";
 			companion = <&ohci2>;
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -2492,7 +2536,7 @@
 			reg = <0 0xee0e0100 0 0x100>;
 			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>;
-			phys = <&usb2_phy3>;
+			phys = <&usb2_phy3 2>;
 			phy-names = "usb";
 			companion = <&ohci3>;
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -2508,7 +2552,7 @@
 			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 			resets = <&cpg 703>, <&cpg 704>;
-			#phy-cells = <0>;
+			#phy-cells = <1>;
 			status = "disabled";
 		};
 
@@ -2519,7 +2563,7 @@
 			clocks = <&cpg CPG_MOD 702>;
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 			resets = <&cpg 702>;
-			#phy-cells = <0>;
+			#phy-cells = <1>;
 			status = "disabled";
 		};
 
@@ -2530,7 +2574,7 @@
 			clocks = <&cpg CPG_MOD 701>;
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 			resets = <&cpg 701>;
-			#phy-cells = <0>;
+			#phy-cells = <1>;
 			status = "disabled";
 		};
 
@@ -2542,7 +2586,7 @@
 			clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>;
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 			resets = <&cpg 700>, <&cpg 705>;
-			#phy-cells = <0>;
+			#phy-cells = <1>;
 			status = "disabled";
 		};
 
@@ -2555,6 +2599,7 @@
 			max-frequency = <200000000>;
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 			resets = <&cpg 314>;
+			iommus = <&ipmmu_ds1 32>;
 			status = "disabled";
 		};
 
@@ -2567,6 +2612,7 @@
 			max-frequency = <200000000>;
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 			resets = <&cpg 313>;
+			iommus = <&ipmmu_ds1 33>;
 			status = "disabled";
 		};
 
@@ -2579,6 +2625,7 @@
 			max-frequency = <200000000>;
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 			resets = <&cpg 312>;
+			iommus = <&ipmmu_ds1 34>;
 			status = "disabled";
 		};
 
@@ -2591,6 +2638,7 @@
 			max-frequency = <200000000>;
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 			resets = <&cpg 311>;
+			iommus = <&ipmmu_ds1 35>;
 			status = "disabled";
 		};
 
@@ -2631,10 +2679,10 @@
 			#size-cells = <2>;
 			bus-range = <0x00 0xff>;
 			device_type = "pci";
-			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
-				0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
-				0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
-				0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
+				 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
+				 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
+				 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
 			/* Map all possible DDR as inbound ranges */
 			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
 			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
@@ -2658,10 +2706,10 @@
 			#size-cells = <2>;
 			bus-range = <0x00 0xff>;
 			device_type = "pci";
-			ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000
-				0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000
-				0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000
-				0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
+			ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
+				 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
+				 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
+				 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
 			/* Map all possible DDR as inbound ranges */
 			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
 			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
@@ -2717,6 +2765,83 @@
 			resets = <&cpg 820>;
 		};
 
+		vspbc: vsp@fe920000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfe920000 0 0x8000>;
+			interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 624>;
+			power-domains = <&sysc R8A7795_PD_A3VP>;
+			resets = <&cpg 624>;
+
+			renesas,fcp = <&fcpvb1>;
+		};
+
+		vspbd: vsp@fe960000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfe960000 0 0x8000>;
+			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 626>;
+			power-domains = <&sysc R8A7795_PD_A3VP>;
+			resets = <&cpg 626>;
+
+			renesas,fcp = <&fcpvb0>;
+		};
+
+		vspd0: vsp@fea20000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfea20000 0 0x5000>;
+			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 623>;
+			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+			resets = <&cpg 623>;
+
+			renesas,fcp = <&fcpvd0>;
+		};
+
+		vspd1: vsp@fea28000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfea28000 0 0x5000>;
+			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 622>;
+			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+			resets = <&cpg 622>;
+
+			renesas,fcp = <&fcpvd1>;
+		};
+
+		vspd2: vsp@fea30000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfea30000 0 0x5000>;
+			interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 621>;
+			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+			resets = <&cpg 621>;
+
+			renesas,fcp = <&fcpvd2>;
+		};
+
+		vspi0: vsp@fe9a0000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfe9a0000 0 0x8000>;
+			interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 631>;
+			power-domains = <&sysc R8A7795_PD_A3VP>;
+			resets = <&cpg 631>;
+
+			renesas,fcp = <&fcpvi0>;
+		};
+
+		vspi1: vsp@fe9b0000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfe9b0000 0 0x8000>;
+			interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 630>;
+			power-domains = <&sysc R8A7795_PD_A3VP>;
+			resets = <&cpg 630>;
+
+			renesas,fcp = <&fcpvi1>;
+		};
+
 		fdp1@fe940000 {
 			compatible = "renesas,fdp1";
 			reg = <0 0xfe940000 0 0x2400>;
@@ -2818,81 +2943,40 @@
 			iommus = <&ipmmu_vi1 10>;
 		};
 
-		vspbd: vsp@fe960000 {
-			compatible = "renesas,vsp2";
-			reg = <0 0xfe960000 0 0x8000>;
-			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 626>;
-			power-domains = <&sysc R8A7795_PD_A3VP>;
-			resets = <&cpg 626>;
-
-			renesas,fcp = <&fcpvb0>;
-		};
-
-		vspbc: vsp@fe920000 {
-			compatible = "renesas,vsp2";
-			reg = <0 0xfe920000 0 0x8000>;
-			interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 624>;
-			power-domains = <&sysc R8A7795_PD_A3VP>;
-			resets = <&cpg 624>;
-
-			renesas,fcp = <&fcpvb1>;
-		};
-
-		vspd0: vsp@fea20000 {
-			compatible = "renesas,vsp2";
-			reg = <0 0xfea20000 0 0x5000>;
-			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 623>;
+		cmm0: cmm@fea40000 {
+			compatible = "renesas,r8a7795-cmm",
+				     "renesas,rcar-gen3-cmm";
+			reg = <0 0xfea40000 0 0x1000>;
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
-			resets = <&cpg 623>;
-
-			renesas,fcp = <&fcpvd0>;
+			clocks = <&cpg CPG_MOD 711>;
+			resets = <&cpg 711>;
 		};
 
-		vspd1: vsp@fea28000 {
-			compatible = "renesas,vsp2";
-			reg = <0 0xfea28000 0 0x5000>;
-			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 622>;
+		cmm1: cmm@fea50000 {
+			compatible = "renesas,r8a7795-cmm",
+				     "renesas,rcar-gen3-cmm";
+			reg = <0 0xfea50000 0 0x1000>;
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
-			resets = <&cpg 622>;
-
-			renesas,fcp = <&fcpvd1>;
+			clocks = <&cpg CPG_MOD 710>;
+			resets = <&cpg 710>;
 		};
 
-		vspd2: vsp@fea30000 {
-			compatible = "renesas,vsp2";
-			reg = <0 0xfea30000 0 0x5000>;
-			interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 621>;
+		cmm2: cmm@fea60000 {
+			compatible = "renesas,r8a7795-cmm",
+				     "renesas,rcar-gen3-cmm";
+			reg = <0 0xfea60000 0 0x1000>;
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
-			resets = <&cpg 621>;
-
-			renesas,fcp = <&fcpvd2>;
+			clocks = <&cpg CPG_MOD 709>;
+			resets = <&cpg 709>;
 		};
 
-		vspi0: vsp@fe9a0000 {
-			compatible = "renesas,vsp2";
-			reg = <0 0xfe9a0000 0 0x8000>;
-			interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 631>;
-			power-domains = <&sysc R8A7795_PD_A3VP>;
-			resets = <&cpg 631>;
-
-			renesas,fcp = <&fcpvi0>;
-		};
-
-		vspi1: vsp@fe9b0000 {
-			compatible = "renesas,vsp2";
-			reg = <0 0xfe9b0000 0 0x8000>;
-			interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 630>;
-			power-domains = <&sysc R8A7795_PD_A3VP>;
-			resets = <&cpg 630>;
-
-			renesas,fcp = <&fcpvi1>;
+		cmm3: cmm@fea70000 {
+			compatible = "renesas,r8a7795-cmm",
+				     "renesas,rcar-gen3-cmm";
+			reg = <0 0xfea70000 0 0x1000>;
+			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+			clocks = <&cpg CPG_MOD 708>;
+			resets = <&cpg 708>;
 		};
 
 		csi20: csi2@fea80000 {
@@ -3098,7 +3182,10 @@
 				 <&cpg CPG_MOD 722>,
 				 <&cpg CPG_MOD 721>;
 			clock-names = "du.0", "du.1", "du.2", "du.3";
-			vsps = <&vspd0 0 &vspd1 0 &vspd2 0 &vspd0 1>;
+
+			renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>;
+			vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
+
 			status = "disabled";
 
 			ports {
@@ -3168,58 +3255,30 @@
 			polling-delay-passive = <250>;
 			polling-delay = <1000>;
 			thermal-sensors = <&tsc 0>;
+			sustainable-power = <6313>;
 
 			trips {
-				sensor1_passive: sensor1-passive {
-					temperature = <95000>;
-					hysteresis = <1000>;
-					type = "passive";
-				};
 				sensor1_crit: sensor1-crit {
 					temperature = <120000>;
 					hysteresis = <1000>;
 					type = "critical";
 				};
 			};
-
-			cooling-maps {
-				map0 {
-					trip = <&sensor1_passive>;
-					cooling-device = <&a57_0 4 4>,
-							 <&a57_1 4 4>,
-							 <&a57_2 4 4>,
-							 <&a57_3 4 4>;
-				};
-			};
 		};
 
 		sensor_thermal2: sensor-thermal2 {
 			polling-delay-passive = <250>;
 			polling-delay = <1000>;
 			thermal-sensors = <&tsc 1>;
+			sustainable-power = <6313>;
 
 			trips {
-				sensor2_passive: sensor2-passive {
-					temperature = <95000>;
-					hysteresis = <1000>;
-					type = "passive";
-				};
 				sensor2_crit: sensor2-crit {
 					temperature = <120000>;
 					hysteresis = <1000>;
 					type = "critical";
 				};
 			};
-
-			cooling-maps {
-				map0 {
-					trip = <&sensor2_passive>;
-					cooling-device = <&a57_0 4 4>,
-							 <&a57_1 4 4>,
-							 <&a57_2 4 4>,
-							 <&a57_3 4 4>;
-				};
-			};
 		};
 
 		sensor_thermal3: sensor-thermal3 {
@@ -3228,11 +3287,12 @@
 			thermal-sensors = <&tsc 2>;
 
 			trips {
-				sensor3_passive: sensor3-passive {
-					temperature = <95000>;
+				target: trip-point1 {
+					temperature = <100000>;
 					hysteresis = <1000>;
 					type = "passive";
 				};
+
 				sensor3_crit: sensor3-crit {
 					temperature = <120000>;
 					hysteresis = <1000>;
@@ -3242,11 +3302,15 @@
 
 			cooling-maps {
 				map0 {
-					trip = <&sensor3_passive>;
-					cooling-device = <&a57_0 4 4>,
-							 <&a57_1 4 4>,
-							 <&a57_2 4 4>,
-							 <&a57_3 4 4>;
+					trip = <&target>;
+					cooling-device = <&a57_0 2 4>;
+					contribution = <1024>;
+				};
+
+				map1 {
+					trip = <&target>;
+					cooling-device = <&a53_0 0 2>;
+					contribution = <1024>;
 				};
 			};
 		};
diff --git a/arch/arm/dts/r8a7796-salvator-x-u-boot.dts b/arch/arm/dts/r8a7796-salvator-x-u-boot.dts
deleted file mode 100644
index 2a7b149..0000000
--- a/arch/arm/dts/r8a7796-salvator-x-u-boot.dts
+++ /dev/null
@@ -1,36 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source extras for U-Boot for the Salvator-X board
- *
- * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
- */
-
-#include "r8a7796-salvator-x.dts"
-#include "r8a7796-u-boot.dtsi"
-
-&sdhi0 {
-	sd-uhs-sdr12;
-	sd-uhs-sdr25;
-	sd-uhs-sdr104;
-	max-frequency = <208000000>;
-};
-
-&sdhi2 {
-	mmc-hs400-1_8v;
-	max-frequency = <200000000>;
-};
-
-&sdhi3 {
-	sd-uhs-sdr12;
-	sd-uhs-sdr25;
-	sd-uhs-sdr104;
-	max-frequency = <208000000>;
-};
-
-&vcc_sdhi0 {
-	u-boot,off-on-delay-us = <20000>;
-};
-
-&vcc_sdhi3 {
-	u-boot,off-on-delay-us = <20000>;
-};
diff --git a/arch/arm/dts/r8a7796-u-boot.dtsi b/arch/arm/dts/r8a7796-u-boot.dtsi
deleted file mode 100644
index 6221054..0000000
--- a/arch/arm/dts/r8a7796-u-boot.dtsi
+++ /dev/null
@@ -1,24 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source extras for U-Boot on RCar R8A7796 SoC
- *
- * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
- */
-
-#include "r8a779x-u-boot.dtsi"
-
-&extalr_clk {
-	u-boot,dm-pre-reloc;
-};
-
-/ {
-	soc {
-		rpc: rpc@0xee200000 {
-			compatible = "renesas,rpc-r8a7796", "renesas,rpc";
-			reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
-			clocks = <&cpg CPG_MOD 917>;
-			bank-width = <2>;
-			status = "disabled";
-		};
-	};
-};
diff --git a/arch/arm/dts/r8a7795-salvator-x-u-boot.dts b/arch/arm/dts/r8a77960-salvator-x-u-boot.dts
similarity index 88%
rename from arch/arm/dts/r8a7795-salvator-x-u-boot.dts
rename to arch/arm/dts/r8a77960-salvator-x-u-boot.dts
index e93afe3..a3f2d74 100644
--- a/arch/arm/dts/r8a7795-salvator-x-u-boot.dts
+++ b/arch/arm/dts/r8a77960-salvator-x-u-boot.dts
@@ -5,8 +5,8 @@
  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  */
 
-#include "r8a7795-salvator-x.dts"
-#include "r8a7795-u-boot.dtsi"
+#include "r8a77960-salvator-x.dts"
+#include "r8a77960-u-boot.dtsi"
 
 &sdhi0 {
 	sd-uhs-sdr12;
diff --git a/arch/arm/dts/r8a7796-salvator-x.dts b/arch/arm/dts/r8a77960-salvator-x.dts
similarity index 94%
rename from arch/arm/dts/r8a7796-salvator-x.dts
rename to arch/arm/dts/r8a77960-salvator-x.dts
index 2aefa53..ecfbeaf 100644
--- a/arch/arm/dts/r8a7796-salvator-x.dts
+++ b/arch/arm/dts/r8a77960-salvator-x.dts
@@ -6,11 +6,11 @@
  */
 
 /dts-v1/;
-#include "r8a7796.dtsi"
+#include "r8a77960.dtsi"
 #include "salvator-x.dtsi"
 
 / {
-	model = "Renesas Salvator-X board based on r8a7796";
+	model = "Renesas Salvator-X board based on r8a77960";
 	compatible = "renesas,salvator-x", "renesas,r8a7796";
 
 	memory@48000000 {
@@ -36,11 +36,6 @@
 		      "dclkin.0", "dclkin.1", "dclkin.2";
 };
 
-&sound_card {
-	dais = <&rsnd_port0	/* ak4613 */
-		&rsnd_port1>;	/* HDMI0  */
-};
-
 &hdmi0 {
 	status = "okay";
 
@@ -81,3 +76,8 @@
 		};
 	};
 };
+
+&sound_card {
+	dais = <&rsnd_port0	/* ak4613 */
+		&rsnd_port1>;	/* HDMI0  */
+};
diff --git a/arch/arm/dts/r8a77960-u-boot.dtsi b/arch/arm/dts/r8a77960-u-boot.dtsi
new file mode 100644
index 0000000..826c238
--- /dev/null
+++ b/arch/arm/dts/r8a77960-u-boot.dtsi
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot on RCar R8A7796 SoC
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+&extalr_clk {
+	u-boot,dm-pre-reloc;
+};
+
+/ {
+	soc {
+		rpc: rpc@0xee200000 {
+			compatible = "renesas,rpc-r8a7796", "renesas,rpc";
+			reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
+			clocks = <&cpg CPG_MOD 917>;
+			bank-width = <2>;
+			status = "disabled";
+		};
+	};
+};
+
+/delete-node/ &ak4613;
+/delete-node/ &audma0;
+/delete-node/ &audma1;
+/delete-node/ &can0;
+/delete-node/ &can1;
+/delete-node/ &canfd;
+/delete-node/ &csi20;
+/delete-node/ &csi40;
+/delete-node/ &drif00;
+/delete-node/ &drif01;
+/delete-node/ &drif10;
+/delete-node/ &drif11;
+/delete-node/ &drif20;
+/delete-node/ &drif21;
+/delete-node/ &drif30;
+/delete-node/ &drif31;
+/delete-node/ &du;
+/delete-node/ &fcpf0;
+/delete-node/ &fcpvb0;
+/delete-node/ &fcpvd0;
+/delete-node/ &fcpvd1;
+/delete-node/ &fcpvd2;
+/delete-node/ &fcpvi0;
+/delete-node/ &hdmi0;
+/delete-node/ &lvds0;
+/delete-node/ &rcar_sound;
+/delete-node/ &sound_card;
+/delete-node/ &vin0;
+/delete-node/ &vin1;
+/delete-node/ &vin2;
+/delete-node/ &vin3;
+/delete-node/ &vin4;
+/delete-node/ &vin5;
+/delete-node/ &vin6;
+/delete-node/ &vin7;
+/delete-node/ &vspb;
+/delete-node/ &vspd0;
+/delete-node/ &vspd1;
+/delete-node/ &vspd2;
+/delete-node/ &vspi0;
+
+/ {
+	/delete-node/ cvbs-in;
+	/delete-node/ hdmi-in;
+	/delete-node/ hdmi0-out;
+	/delete-node/ hdmi1-out;
+	/delete-node/ vga-encoder;
+	/delete-node/ vga;
+};
+
+&i2c4 {
+	/delete-node/ video-receiver@70;
+};
+
+/ {
+	soc {
+		/delete-node/ fdp1@fe940000;
+		/delete-node/ fdp1@fe944000;
+		/delete-node/ fdp1@fe948000;
+		/delete-node/ imr-lx4@fe860000;
+		/delete-node/ imr-lx4@fe870000;
+		/delete-node/ imr-lx4@fe880000;
+		/delete-node/ imr-lx4@fe890000;
+	};
+};
diff --git a/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts b/arch/arm/dts/r8a77960-ulcb-u-boot.dts
similarity index 89%
copy from arch/arm/dts/r8a7796-m3ulcb-u-boot.dts
copy to arch/arm/dts/r8a77960-ulcb-u-boot.dts
index 314eacc..04023d9 100644
--- a/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts
+++ b/arch/arm/dts/r8a77960-ulcb-u-boot.dts
@@ -5,8 +5,8 @@
  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  */
 
-#include "r8a7796-m3ulcb.dts"
-#include "r8a7796-u-boot.dtsi"
+#include "r8a77960-ulcb.dts"
+#include "r8a77960-u-boot.dtsi"
 
 / {
 	cpld {
diff --git a/arch/arm/dts/r8a7796-m3ulcb.dts b/arch/arm/dts/r8a77960-ulcb.dts
similarity index 90%
rename from arch/arm/dts/r8a7796-m3ulcb.dts
rename to arch/arm/dts/r8a77960-ulcb.dts
index 9e4594c..d041042 100644
--- a/arch/arm/dts/r8a7796-m3ulcb.dts
+++ b/arch/arm/dts/r8a77960-ulcb.dts
@@ -7,11 +7,11 @@
  */
 
 /dts-v1/;
-#include "r8a7796.dtsi"
+#include "r8a77960.dtsi"
 #include "ulcb.dtsi"
 
 / {
-	model = "Renesas M3ULCB board based on r8a7796";
+	model = "Renesas M3ULCB board based on r8a77960";
 	compatible = "renesas,m3ulcb", "renesas,r8a7796";
 
 	memory@48000000 {
diff --git a/arch/arm/dts/r8a7796.dtsi b/arch/arm/dts/r8a77960.dtsi
similarity index 90%
rename from arch/arm/dts/r8a7796.dtsi
rename to arch/arm/dts/r8a77960.dtsi
index d5e2f4a..60f156c 100644
--- a/arch/arm/dts/r8a7796.dtsi
+++ b/arch/arm/dts/r8a77960.dtsi
@@ -160,6 +160,8 @@
 			power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
 			next-level-cache = <&L2_CA57>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
+			dynamic-power-coefficient = <854>;
 			clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
 			operating-points-v2 = <&cluster0_opp>;
 			capacity-dmips-mhz = <1024>;
@@ -173,6 +175,7 @@
 			power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
 			next-level-cache = <&L2_CA57>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
 			clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
 			operating-points-v2 = <&cluster0_opp>;
 			capacity-dmips-mhz = <1024>;
@@ -186,6 +189,9 @@
 			power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_1>;
+			#cooling-cells = <2>;
+			dynamic-power-coefficient = <277>;
 			clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
 			operating-points-v2 = <&cluster1_opp>;
 			capacity-dmips-mhz = <535>;
@@ -198,6 +204,7 @@
 			power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_1>;
 			clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
 			operating-points-v2 = <&cluster1_opp>;
 			capacity-dmips-mhz = <535>;
@@ -210,6 +217,7 @@
 			power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_1>;
 			clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
 			operating-points-v2 = <&cluster1_opp>;
 			capacity-dmips-mhz = <535>;
@@ -222,6 +230,7 @@
 			power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_1>;
 			clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
 			operating-points-v2 = <&cluster1_opp>;
 			capacity-dmips-mhz = <535>;
@@ -240,6 +249,28 @@
 			cache-unified;
 			cache-level = <2>;
 		};
+
+		idle-states {
+			entry-method = "psci";
+
+			CPU_SLEEP_0: cpu-sleep-0 {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x0010000>;
+				local-timer-stop;
+				entry-latency-us = <400>;
+				exit-latency-us = <500>;
+				min-residency-us = <4000>;
+			};
+
+			CPU_SLEEP_1: cpu-sleep-1 {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x0010000>;
+				local-timer-stop;
+				entry-latency-us = <700>;
+				exit-latency-us = <700>;
+				min-residency-us = <5000>;
+			};
+		};
 	};
 
 	extal_clk: extal {
@@ -543,12 +574,12 @@
 			#interrupt-cells = <2>;
 			interrupt-controller;
 			reg = <0 0xe61c0000 0 0x200>;
-			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 407>;
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 			resets = <&cpg 407>;
@@ -783,7 +814,7 @@
 			       <&usb_dmac1 0>, <&usb_dmac1 1>;
 			dma-names = "ch0", "ch1", "ch2", "ch3";
 			renesas,buswait = <11>;
-			phys = <&usb2_phy0>;
+			phys = <&usb2_phy0 3>;
 			phy-names = "usb";
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 			resets = <&cpg 704>, <&cpg 703>;
@@ -794,8 +825,8 @@
 			compatible = "renesas,r8a7796-usb-dmac",
 				     "renesas,usb-dmac";
 			reg = <0 0xe65a0000 0 0x100>;
-			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "ch0", "ch1";
 			clocks = <&cpg CPG_MOD 330>;
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -808,8 +839,8 @@
 			compatible = "renesas,r8a7796-usb-dmac",
 				     "renesas,usb-dmac";
 			reg = <0 0xe65b0000 0 0x100>;
-			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "ch0", "ch1";
 			clocks = <&cpg CPG_MOD 331>;
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -835,23 +866,23 @@
 			compatible = "renesas,dmac-r8a7796",
 				     "renesas,rcar-dmac";
 			reg = <0 0xe6700000 0 0x10000>;
-			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					"ch0", "ch1", "ch2", "ch3",
 					"ch4", "ch5", "ch6", "ch7",
@@ -877,23 +908,23 @@
 			compatible = "renesas,dmac-r8a7796",
 				     "renesas,rcar-dmac";
 			reg = <0 0xe7300000 0 0x10000>;
-			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					"ch0", "ch1", "ch2", "ch3",
 					"ch4", "ch5", "ch6", "ch7",
@@ -919,23 +950,23 @@
 			compatible = "renesas,dmac-r8a7796",
 				     "renesas,rcar-dmac";
 			reg = <0 0xe7310000 0 0x10000>;
-			interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					"ch0", "ch1", "ch2", "ch3",
 					"ch4", "ch5", "ch6", "ch7",
@@ -1319,6 +1350,17 @@
 			status = "disabled";
 		};
 
+		tpu: pwm@e6e80000 {
+			compatible = "renesas,tpu-r8a7796", "renesas,tpu";
+			reg = <0 0xe6e80000 0 0x148>;
+			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 304>;
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			resets = <&cpg 304>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
 		msiof0: spi@e6e90000 {
 			compatible = "renesas,msiof-r8a7796",
 				     "renesas,rcar-gen3-msiof";
@@ -1819,6 +1861,17 @@
 				      "ssi.1", "ssi.0";
 			status = "disabled";
 
+			rcar_sound,ctu {
+				ctu00: ctu-0 { };
+				ctu01: ctu-1 { };
+				ctu02: ctu-2 { };
+				ctu03: ctu-3 { };
+				ctu10: ctu-4 { };
+				ctu11: ctu-5 { };
+				ctu12: ctu-6 { };
+				ctu13: ctu-7 { };
+			};
+
 			rcar_sound,dvc {
 				dvc0: dvc-0 {
 					dmas = <&audma1 0xbc>;
@@ -1835,17 +1888,6 @@
 				mix1: mix-1 { };
 			};
 
-			rcar_sound,ctu {
-				ctu00: ctu-0 { };
-				ctu01: ctu-1 { };
-				ctu02: ctu-2 { };
-				ctu03: ctu-3 { };
-				ctu10: ctu-4 { };
-				ctu11: ctu-5 { };
-				ctu12: ctu-6 { };
-				ctu13: ctu-7 { };
-			};
-
 			rcar_sound,src {
 				src0: src-0 {
 					interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
@@ -1897,6 +1939,59 @@
 					dmas = <&audma0 0x97>, <&audma1 0xba>;
 					dma-names = "rx", "tx";
 				};
+			};
+
+			rcar_sound,ssi {
+				ssi0: ssi-0 {
+					interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x01>, <&audma1 0x02>;
+					dma-names = "rx", "tx";
+				};
+				ssi1: ssi-1 {
+					interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x03>, <&audma1 0x04>;
+					dma-names = "rx", "tx";
+				};
+				ssi2: ssi-2 {
+					interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x05>, <&audma1 0x06>;
+					dma-names = "rx", "tx";
+				};
+				ssi3: ssi-3 {
+					interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x07>, <&audma1 0x08>;
+					dma-names = "rx", "tx";
+				};
+				ssi4: ssi-4 {
+					interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x09>, <&audma1 0x0a>;
+					dma-names = "rx", "tx";
+				};
+				ssi5: ssi-5 {
+					interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x0b>, <&audma1 0x0c>;
+					dma-names = "rx", "tx";
+				};
+				ssi6: ssi-6 {
+					interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x0d>, <&audma1 0x0e>;
+					dma-names = "rx", "tx";
+				};
+				ssi7: ssi-7 {
+					interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x0f>, <&audma1 0x10>;
+					dma-names = "rx", "tx";
+				};
+				ssi8: ssi-8 {
+					interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x11>, <&audma1 0x12>;
+					dma-names = "rx", "tx";
+				};
+				ssi9: ssi-9 {
+					interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x13>, <&audma1 0x14>;
+					dma-names = "rx", "tx";
+				};
 			};
 
 			rcar_sound,ssiu {
@@ -2109,82 +2204,29 @@
 					dma-names = "rx", "tx";
 				};
 			};
-
-			rcar_sound,ssi {
-				ssi0: ssi-0 {
-					interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
-					dmas = <&audma0 0x01>, <&audma1 0x02>;
-					dma-names = "rx", "tx";
-				};
-				ssi1: ssi-1 {
-					interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
-					dmas = <&audma0 0x03>, <&audma1 0x04>;
-					dma-names = "rx", "tx";
-				};
-				ssi2: ssi-2 {
-					interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
-					dmas = <&audma0 0x05>, <&audma1 0x06>;
-					dma-names = "rx", "tx";
-				};
-				ssi3: ssi-3 {
-					interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
-					dmas = <&audma0 0x07>, <&audma1 0x08>;
-					dma-names = "rx", "tx";
-				};
-				ssi4: ssi-4 {
-					interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
-					dmas = <&audma0 0x09>, <&audma1 0x0a>;
-					dma-names = "rx", "tx";
-				};
-				ssi5: ssi-5 {
-					interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
-					dmas = <&audma0 0x0b>, <&audma1 0x0c>;
-					dma-names = "rx", "tx";
-				};
-				ssi6: ssi-6 {
-					interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
-					dmas = <&audma0 0x0d>, <&audma1 0x0e>;
-					dma-names = "rx", "tx";
-				};
-				ssi7: ssi-7 {
-					interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
-					dmas = <&audma0 0x0f>, <&audma1 0x10>;
-					dma-names = "rx", "tx";
-				};
-				ssi8: ssi-8 {
-					interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
-					dmas = <&audma0 0x11>, <&audma1 0x12>;
-					dma-names = "rx", "tx";
-				};
-				ssi9: ssi-9 {
-					interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
-					dmas = <&audma0 0x13>, <&audma1 0x14>;
-					dma-names = "rx", "tx";
-				};
-			};
 		};
 
 		audma0: dma-controller@ec700000 {
 			compatible = "renesas,dmac-r8a7796",
 				     "renesas,rcar-dmac";
 			reg = <0 0xec700000 0 0x10000>;
-			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					"ch0", "ch1", "ch2", "ch3",
 					"ch4", "ch5", "ch6", "ch7",
@@ -2210,23 +2252,23 @@
 			compatible = "renesas,dmac-r8a7796",
 				     "renesas,rcar-dmac";
 			reg = <0 0xec720000 0 0x10000>;
-			interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					"ch0", "ch1", "ch2", "ch3",
 					"ch4", "ch5", "ch6", "ch7",
@@ -2275,7 +2317,7 @@
 			reg = <0 0xee080000 0 0x100>;
 			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
-			phys = <&usb2_phy0>;
+			phys = <&usb2_phy0 1>;
 			phy-names = "usb";
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 			resets = <&cpg 703>, <&cpg 704>;
@@ -2287,7 +2329,7 @@
 			reg = <0 0xee0a0000 0 0x100>;
 			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 702>;
-			phys = <&usb2_phy1>;
+			phys = <&usb2_phy1 1>;
 			phy-names = "usb";
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 			resets = <&cpg 702>;
@@ -2299,7 +2341,7 @@
 			reg = <0 0xee080100 0 0x100>;
 			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
-			phys = <&usb2_phy0>;
+			phys = <&usb2_phy0 2>;
 			phy-names = "usb";
 			companion = <&ohci0>;
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -2312,7 +2354,7 @@
 			reg = <0 0xee0a0100 0 0x100>;
 			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 702>;
-			phys = <&usb2_phy1>;
+			phys = <&usb2_phy1 2>;
 			phy-names = "usb";
 			companion = <&ohci1>;
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -2328,7 +2370,7 @@
 			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 			resets = <&cpg 703>, <&cpg 704>;
-			#phy-cells = <0>;
+			#phy-cells = <1>;
 			status = "disabled";
 		};
 
@@ -2339,7 +2381,7 @@
 			clocks = <&cpg CPG_MOD 702>;
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 			resets = <&cpg 702>;
-			#phy-cells = <0>;
+			#phy-cells = <1>;
 			status = "disabled";
 		};
 
@@ -2352,6 +2394,7 @@
 			max-frequency = <200000000>;
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 			resets = <&cpg 314>;
+			iommus = <&ipmmu_ds1 32>;
 			status = "disabled";
 		};
 
@@ -2364,6 +2407,7 @@
 			max-frequency = <200000000>;
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 			resets = <&cpg 313>;
+			iommus = <&ipmmu_ds1 33>;
 			status = "disabled";
 		};
 
@@ -2376,6 +2420,7 @@
 			max-frequency = <200000000>;
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 			resets = <&cpg 312>;
+			iommus = <&ipmmu_ds1 34>;
 			status = "disabled";
 		};
 
@@ -2388,6 +2433,7 @@
 			max-frequency = <200000000>;
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 			resets = <&cpg 311>;
+			iommus = <&ipmmu_ds1 35>;
 			status = "disabled";
 		};
 
@@ -2416,10 +2462,10 @@
 			#size-cells = <2>;
 			bus-range = <0x00 0xff>;
 			device_type = "pci";
-			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
-				0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
-				0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
-				0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
+				 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
+				 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
+				 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
 			/* Map all possible DDR as inbound ranges */
 			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
 			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
@@ -2443,10 +2489,10 @@
 			#size-cells = <2>;
 			bus-range = <0x00 0xff>;
 			device_type = "pci";
-			ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000
-				0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000
-				0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000
-				0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
+			ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
+				 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
+				 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
+				 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
 			/* Map all possible DDR as inbound ranges */
 			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
 			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
@@ -2599,6 +2645,33 @@
 			renesas,fcp = <&fcpvi0>;
 		};
 
+		cmm0: cmm@fea40000 {
+			compatible = "renesas,r8a7796-cmm",
+				     "renesas,rcar-gen3-cmm";
+			reg = <0 0xfea40000 0 0x1000>;
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			clocks = <&cpg CPG_MOD 711>;
+			resets = <&cpg 711>;
+		};
+
+		cmm1: cmm@fea50000 {
+			compatible = "renesas,r8a7796-cmm",
+				     "renesas,rcar-gen3-cmm";
+			reg = <0 0xfea50000 0 0x1000>;
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			clocks = <&cpg CPG_MOD 710>;
+			resets = <&cpg 710>;
+		};
+
+		cmm2: cmm@fea60000 {
+			compatible = "renesas,r8a7796-cmm",
+				     "renesas,rcar-gen3-cmm";
+			reg = <0 0xfea60000 0 0x1000>;
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			clocks = <&cpg CPG_MOD 709>;
+			resets = <&cpg 709>;
+		};
+
 		csi20: csi2@fea80000 {
 			compatible = "renesas,r8a7796-csi2";
 			reg = <0 0xfea80000 0 0x10000>;
@@ -2749,9 +2822,11 @@
 				 <&cpg CPG_MOD 723>,
 				 <&cpg CPG_MOD 722>;
 			clock-names = "du.0", "du.1", "du.2";
-			status = "disabled";
 
-			vsps = <&vspd0 &vspd1 &vspd2>;
+			renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>;
+			vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
+
+			status = "disabled";
 
 			ports {
 				#address-cells = <1>;
@@ -2814,78 +2889,63 @@
 			polling-delay-passive = <250>;
 			polling-delay = <1000>;
 			thermal-sensors = <&tsc 0>;
+			sustainable-power = <3874>;
 
 			trips {
-				sensor1_passive: sensor1-passive {
-					temperature = <95000>;
-					hysteresis = <1000>;
-					type = "passive";
-				};
 				sensor1_crit: sensor1-crit {
 					temperature = <120000>;
 					hysteresis = <1000>;
 					type = "critical";
 				};
 			};
-
-			cooling-maps {
-				map0 {
-					trip = <&sensor1_passive>;
-					cooling-device = <&a57_0 5 5>, <&a57_1 5 5>;
-				};
-			};
 		};
 
 		sensor_thermal2: sensor-thermal2 {
 			polling-delay-passive = <250>;
 			polling-delay = <1000>;
 			thermal-sensors = <&tsc 1>;
+			sustainable-power = <3874>;
 
 			trips {
-				sensor2_passive: sensor2-passive {
-					temperature = <95000>;
-					hysteresis = <1000>;
-					type = "passive";
-				};
 				sensor2_crit: sensor2-crit {
 					temperature = <120000>;
 					hysteresis = <1000>;
 					type = "critical";
 				};
 			};
-
-			cooling-maps {
-				map0 {
-					trip = <&sensor2_passive>;
-					cooling-device = <&a57_0 5 5>, <&a57_1 5 5>;
-				};
-			};
 		};
 
 		sensor_thermal3: sensor-thermal3 {
 			polling-delay-passive = <250>;
 			polling-delay = <1000>;
 			thermal-sensors = <&tsc 2>;
+			sustainable-power = <3874>;
 
+			cooling-maps {
+				map0 {
+					trip = <&target>;
+					cooling-device = <&a57_0 2 4>;
+					contribution = <1024>;
+				};
+				map1 {
+					trip = <&target>;
+					cooling-device = <&a53_0 0 2>;
+					contribution = <1024>;
+				};
+			};
 			trips {
-				sensor3_passive: sensor3-passive {
-					temperature = <95000>;
+				target: trip-point1 {
+					temperature = <100000>;
 					hysteresis = <1000>;
 					type = "passive";
 				};
+
 				sensor3_crit: sensor3-crit {
 					temperature = <120000>;
 					hysteresis = <1000>;
 					type = "critical";
 				};
 			};
-
-			cooling-maps {
-				map0 {
-					trip = <&sensor3_passive>;
-					cooling-device = <&a57_0 5 5>, <&a57_1 5 5>;
-				};
-			};
 		};
 	};
 
diff --git a/arch/arm/dts/r8a77965-salvator-x.dts b/arch/arm/dts/r8a77965-salvator-x.dts
index 340a3c7..660a024 100644
--- a/arch/arm/dts/r8a77965-salvator-x.dts
+++ b/arch/arm/dts/r8a77965-salvator-x.dts
@@ -41,9 +41,37 @@
 				remote-endpoint = <&hdmi0_con>;
 			};
 		};
+		port@2 {
+			reg = <2>;
+			dw_hdmi0_snd_in: endpoint {
+				remote-endpoint = <&rsnd_endpoint1>;
+			};
+		};
 	};
 };
 
 &hdmi0_con {
 	remote-endpoint = <&rcar_dw_hdmi0_out>;
 };
+
+&rcar_sound {
+	ports {
+		rsnd_port1: port@1 {
+			reg = <1>;
+			rsnd_endpoint1: endpoint {
+				remote-endpoint = <&dw_hdmi0_snd_in>;
+
+				dai-format = "i2s";
+				bitclock-master = <&rsnd_endpoint1>;
+				frame-master = <&rsnd_endpoint1>;
+
+				playback = <&ssi2>;
+			};
+		};
+	};
+};
+
+&sound_card {
+	dais = <&rsnd_port0	/* ak4613 */
+		&rsnd_port1>;	/* HDMI0  */
+};
diff --git a/arch/arm/dts/r8a77965-u-boot.dtsi b/arch/arm/dts/r8a77965-u-boot.dtsi
index 81ee096..33ff5b1 100644
--- a/arch/arm/dts/r8a77965-u-boot.dtsi
+++ b/arch/arm/dts/r8a77965-u-boot.dtsi
@@ -22,3 +22,59 @@
 		};
 	};
 };
+
+/delete-node/ &ak4613;
+/delete-node/ &audma0;
+/delete-node/ &audma1;
+/delete-node/ &can0;
+/delete-node/ &can1;
+/delete-node/ &canfd;
+/delete-node/ &csi20;
+/delete-node/ &csi40;
+/delete-node/ &du;
+/delete-node/ &fcpf0;
+/delete-node/ &fcpvb0;
+/delete-node/ &fcpvd0;
+/delete-node/ &fcpvd1;
+/delete-node/ &fcpvi0;
+/delete-node/ &hdmi0;
+/delete-node/ &lvds0;
+/delete-node/ &rcar_sound;
+/delete-node/ &sound_card;
+/delete-node/ &vin0;
+/delete-node/ &vin1;
+/delete-node/ &vin2;
+/delete-node/ &vin3;
+/delete-node/ &vin4;
+/delete-node/ &vin5;
+/delete-node/ &vin6;
+/delete-node/ &vin7;
+/delete-node/ &vspb;
+/delete-node/ &vspd0;
+/delete-node/ &vspd1;
+/delete-node/ &vspi0;
+
+/ {
+	/delete-node/ cvbs-in;
+	/delete-node/ hdmi-in;
+	/delete-node/ hdmi0-out;
+	/delete-node/ hdmi1-out;
+	/delete-node/ vga-encoder;
+	/delete-node/ vga;
+};
+
+&i2c4 {
+	/delete-node/ video-receiver@70;
+};
+
+/ {
+	soc {
+		/delete-node/ fdp1@fe940000;
+		/delete-node/ fdp1@fe944000;
+		/delete-node/ fdp1@fe948000;
+		/delete-node/ imr-lx4@fe860000;
+		/delete-node/ imr-lx4@fe870000;
+		/delete-node/ imr-lx4@fe880000;
+		/delete-node/ imr-lx4@fe890000;
+	};
+};
diff --git a/arch/arm/dts/r8a77965-m3nulcb-u-boot.dts b/arch/arm/dts/r8a77965-ulcb-u-boot.dts
similarity index 94%
rename from arch/arm/dts/r8a77965-m3nulcb-u-boot.dts
rename to arch/arm/dts/r8a77965-ulcb-u-boot.dts
index cf10431..28fb30e 100644
--- a/arch/arm/dts/r8a77965-m3nulcb-u-boot.dts
+++ b/arch/arm/dts/r8a77965-ulcb-u-boot.dts
@@ -5,7 +5,7 @@
  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  */
 
-#include "r8a77965-m3nulcb.dts"
+#include "r8a77965-ulcb.dts"
 #include "r8a77965-u-boot.dtsi"
 
 / {
diff --git a/arch/arm/dts/r8a77965-m3nulcb.dts b/arch/arm/dts/r8a77965-ulcb.dts
similarity index 100%
rename from arch/arm/dts/r8a77965-m3nulcb.dts
rename to arch/arm/dts/r8a77965-ulcb.dts
diff --git a/arch/arm/dts/r8a77965.dtsi b/arch/arm/dts/r8a77965.dtsi
index 2554b17..c17d90b 100644
--- a/arch/arm/dts/r8a77965.dtsi
+++ b/arch/arm/dts/r8a77965.dtsi
@@ -111,6 +111,8 @@
 			power-domains = <&sysc R8A77965_PD_CA57_CPU0>;
 			next-level-cache = <&L2_CA57>;
 			enable-method = "psci";
+			#cooling-cells = <2>;
+			dynamic-power-coefficient = <854>;
 			clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
 			operating-points-v2 = <&cluster0_opp>;
 		};
@@ -427,12 +429,12 @@
 			#interrupt-cells = <2>;
 			interrupt-controller;
 			reg = <0 0xe61c0000 0 0x200>;
-			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 407>;
 			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
 			resets = <&cpg 407>;
@@ -667,7 +669,7 @@
 			       <&usb_dmac1 0>, <&usb_dmac1 1>;
 			dma-names = "ch0", "ch1", "ch2", "ch3";
 			renesas,buswait = <11>;
-			phys = <&usb2_phy0>;
+			phys = <&usb2_phy0 3>;
 			phy-names = "usb";
 			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
 			resets = <&cpg 704>, <&cpg 703>;
@@ -678,8 +680,8 @@
 			compatible = "renesas,r8a77965-usb-dmac",
 				     "renesas,usb-dmac";
 			reg = <0 0xe65a0000 0 0x100>;
-			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "ch0", "ch1";
 			clocks = <&cpg CPG_MOD 330>;
 			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
@@ -692,8 +694,8 @@
 			compatible = "renesas,r8a77965-usb-dmac",
 				     "renesas,usb-dmac";
 			reg = <0 0xe65b0000 0 0x100>;
-			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "ch0", "ch1";
 			clocks = <&cpg CPG_MOD 331>;
 			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
@@ -719,23 +721,23 @@
 			compatible = "renesas,dmac-r8a77965",
 				     "renesas,rcar-dmac";
 			reg = <0 0xe6700000 0 0x10000>;
-			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					"ch0", "ch1", "ch2", "ch3",
 					"ch4", "ch5", "ch6", "ch7",
@@ -761,23 +763,23 @@
 			compatible = "renesas,dmac-r8a77965",
 				     "renesas,rcar-dmac";
 			reg = <0 0xe7300000 0 0x10000>;
-			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					"ch0", "ch1", "ch2", "ch3",
 					"ch4", "ch5", "ch6", "ch7",
@@ -803,23 +805,23 @@
 			compatible = "renesas,dmac-r8a77965",
 				     "renesas,rcar-dmac";
 			reg = <0 0xe7310000 0 0x10000>;
-			interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					"ch0", "ch1", "ch2", "ch3",
 					"ch4", "ch5", "ch6", "ch7",
@@ -1195,6 +1197,17 @@
 			status = "disabled";
 		};
 
+		tpu: pwm@e6e80000 {
+			compatible = "renesas,tpu-r8a77965", "renesas,tpu";
+			reg = <0 0xe6e80000 0 0x148>;
+			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 304>;
+			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+			resets = <&cpg 304>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
 		msiof0: spi@e6e90000 {
 			compatible = "renesas,msiof-r8a77965",
 				     "renesas,rcar-gen3-msiof";
@@ -1924,23 +1937,23 @@
 			compatible = "renesas,dmac-r8a77965",
 				     "renesas,rcar-dmac";
 			reg = <0 0xec700000 0 0x10000>;
-			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					"ch0", "ch1", "ch2", "ch3",
 					"ch4", "ch5", "ch6", "ch7",
@@ -1958,23 +1971,23 @@
 			compatible = "renesas,dmac-r8a77965",
 				     "renesas,rcar-dmac";
 			reg = <0 0xec720000 0 0x10000>;
-			interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					"ch0", "ch1", "ch2", "ch3",
 					"ch4", "ch5", "ch6", "ch7",
@@ -2015,7 +2028,7 @@
 			reg = <0 0xee080000 0 0x100>;
 			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
-			phys = <&usb2_phy0>;
+			phys = <&usb2_phy0 1>;
 			phy-names = "usb";
 			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
 			resets = <&cpg 703>, <&cpg 704>;
@@ -2027,7 +2040,7 @@
 			reg = <0 0xee0a0000 0 0x100>;
 			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 702>;
-			phys = <&usb2_phy1>;
+			phys = <&usb2_phy1 1>;
 			phy-names = "usb";
 			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
 			resets = <&cpg 702>;
@@ -2039,7 +2052,7 @@
 			reg = <0 0xee080100 0 0x100>;
 			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
-			phys = <&usb2_phy0>;
+			phys = <&usb2_phy0 2>;
 			phy-names = "usb";
 			companion = <&ohci0>;
 			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
@@ -2052,7 +2065,7 @@
 			reg = <0 0xee0a0100 0 0x100>;
 			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 702>;
-			phys = <&usb2_phy1>;
+			phys = <&usb2_phy1 2>;
 			phy-names = "usb";
 			companion = <&ohci1>;
 			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
@@ -2068,7 +2081,7 @@
 			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
 			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
 			resets = <&cpg 703>, <&cpg 704>;
-			#phy-cells = <0>;
+			#phy-cells = <1>;
 			status = "disabled";
 		};
 
@@ -2079,7 +2092,7 @@
 			clocks = <&cpg CPG_MOD 702>;
 			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
 			resets = <&cpg 702>;
-			#phy-cells = <0>;
+			#phy-cells = <1>;
 			status = "disabled";
 		};
 
@@ -2092,6 +2105,7 @@
 			max-frequency = <200000000>;
 			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
 			resets = <&cpg 314>;
+			iommus = <&ipmmu_ds1 32>;
 			status = "disabled";
 		};
 
@@ -2104,6 +2118,7 @@
 			max-frequency = <200000000>;
 			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
 			resets = <&cpg 313>;
+			iommus = <&ipmmu_ds1 33>;
 			status = "disabled";
 		};
 
@@ -2116,6 +2131,7 @@
 			max-frequency = <200000000>;
 			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
 			resets = <&cpg 312>;
+			iommus = <&ipmmu_ds1 34>;
 			status = "disabled";
 		};
 
@@ -2128,6 +2144,7 @@
 			max-frequency = <200000000>;
 			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
 			resets = <&cpg 311>;
+			iommus = <&ipmmu_ds1 35>;
 			status = "disabled";
 		};
 
@@ -2167,10 +2184,10 @@
 			#size-cells = <2>;
 			bus-range = <0x00 0xff>;
 			device_type = "pci";
-			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
-				0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
-				0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
-				0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
+				 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
+				 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
+				 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
 			/* Map all possible DDR as inbound ranges */
 			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
 			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
@@ -2194,10 +2211,10 @@
 			#size-cells = <2>;
 			bus-range = <0x00 0xff>;
 			device_type = "pci";
-			ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000
-				0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000
-				0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000
-				0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
+			ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
+				 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
+				 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
+				 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
 			/* Map all possible DDR as inbound ranges */
 			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
 			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
@@ -2242,14 +2259,6 @@
 			renesas,fcp = <&fcpvb0>;
 		};
 
-		fcpvb0: fcp@fe96f000 {
-			compatible = "renesas,fcpv";
-			reg = <0 0xfe96f000 0 0x200>;
-			clocks = <&cpg CPG_MOD 607>;
-			power-domains = <&sysc R8A77965_PD_A3VP>;
-			resets = <&cpg 607>;
-		};
-
 		vspi0: vsp@fe9a0000 {
 			compatible = "renesas,vsp2";
 			reg = <0 0xfe9a0000 0 0x8000>;
@@ -2261,14 +2270,6 @@
 			renesas,fcp = <&fcpvi0>;
 		};
 
-		fcpvi0: fcp@fe9af000 {
-			compatible = "renesas,fcpv";
-			reg = <0 0xfe9af000 0 0x200>;
-			clocks = <&cpg CPG_MOD 611>;
-			power-domains = <&sysc R8A77965_PD_A3VP>;
-			resets = <&cpg 611>;
-		};
-
 		vspd0: vsp@fea20000 {
 			compatible = "renesas,vsp2";
 			reg = <0 0xfea20000 0 0x5000>;
@@ -2280,14 +2281,6 @@
 			renesas,fcp = <&fcpvd0>;
 		};
 
-		fcpvd0: fcp@fea27000 {
-			compatible = "renesas,fcpv";
-			reg = <0 0xfea27000 0 0x200>;
-			clocks = <&cpg CPG_MOD 603>;
-			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
-			resets = <&cpg 603>;
-		};
-
 		vspd1: vsp@fea28000 {
 			compatible = "renesas,vsp2";
 			reg = <0 0xfea28000 0 0x5000>;
@@ -2299,6 +2292,22 @@
 			renesas,fcp = <&fcpvd1>;
 		};
 
+		fcpvb0: fcp@fe96f000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfe96f000 0 0x200>;
+			clocks = <&cpg CPG_MOD 607>;
+			power-domains = <&sysc R8A77965_PD_A3VP>;
+			resets = <&cpg 607>;
+		};
+
+		fcpvd0: fcp@fea27000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfea27000 0 0x200>;
+			clocks = <&cpg CPG_MOD 603>;
+			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+			resets = <&cpg 603>;
+		};
+
 		fcpvd1: fcp@fea2f000 {
 			compatible = "renesas,fcpv";
 			reg = <0 0xfea2f000 0 0x200>;
@@ -2307,6 +2316,41 @@
 			resets = <&cpg 602>;
 		};
 
+		fcpvi0: fcp@fe9af000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfe9af000 0 0x200>;
+			clocks = <&cpg CPG_MOD 611>;
+			power-domains = <&sysc R8A77965_PD_A3VP>;
+			resets = <&cpg 611>;
+		};
+
+		cmm0: cmm@fea40000 {
+			compatible = "renesas,r8a77965-cmm",
+				     "renesas,rcar-gen3-cmm";
+			reg = <0 0xfea40000 0 0x1000>;
+			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+			clocks = <&cpg CPG_MOD 711>;
+			resets = <&cpg 711>;
+		};
+
+		cmm1: cmm@fea50000 {
+			compatible = "renesas,r8a77965-cmm",
+				     "renesas,rcar-gen3-cmm";
+			reg = <0 0xfea50000 0 0x1000>;
+			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+			clocks = <&cpg CPG_MOD 710>;
+			resets = <&cpg 710>;
+		};
+
+		cmm3: cmm@fea70000 {
+			compatible = "renesas,r8a77965-cmm",
+				     "renesas,rcar-gen3-cmm";
+			reg = <0 0xfea70000 0 0x1000>;
+			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+			clocks = <&cpg CPG_MOD 708>;
+			resets = <&cpg 708>;
+		};
+
 		csi20: csi2@fea80000 {
 			compatible = "renesas,r8a77965-csi2";
 			reg = <0 0xfea80000 0 0x10000>;
@@ -2454,9 +2498,11 @@
 				 <&cpg CPG_MOD 723>,
 				 <&cpg CPG_MOD 721>;
 			clock-names = "du.0", "du.1", "du.3";
-			status = "disabled";
 
-			vsps = <&vspd0 0 &vspd1 0 &vspd0 1>;
+			renesas,cmms = <&cmm0>, <&cmm1>, <&cmm3>;
+			vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
+
+			status = "disabled";
 
 			ports {
 				#address-cells = <1>;
@@ -2519,6 +2565,7 @@
 			polling-delay-passive = <250>;
 			polling-delay = <1000>;
 			thermal-sensors = <&tsc 0>;
+			sustainable-power = <2439>;
 
 			trips {
 				sensor1_crit: sensor1-crit {
@@ -2533,6 +2580,7 @@
 			polling-delay-passive = <250>;
 			polling-delay = <1000>;
 			thermal-sensors = <&tsc 1>;
+			sustainable-power = <2439>;
 
 			trips {
 				sensor2_crit: sensor2-crit {
@@ -2547,14 +2595,30 @@
 			polling-delay-passive = <250>;
 			polling-delay = <1000>;
 			thermal-sensors = <&tsc 2>;
+			sustainable-power = <2439>;
 
 			trips {
+				target: trip-point1 {
+					/* miliCelsius  */
+					temperature = <100000>;
+					hysteresis = <1000>;
+					type = "passive";
+				};
+
 				sensor3_crit: sensor3-crit {
 					temperature = <120000>;
 					hysteresis = <1000>;
 					type = "critical";
 				};
 			};
+
+			cooling-maps {
+				map0 {
+					trip = <&target>;
+					cooling-device = <&a57_0 2 4>;
+					contribution = <1024>;
+				};
+			};
 		};
 	};
 
diff --git a/arch/arm/dts/r8a77970-eagle.dts b/arch/arm/dts/r8a77970-eagle.dts
index b6d5332..2afb91e 100644
--- a/arch/arm/dts/r8a77970-eagle.dts
+++ b/arch/arm/dts/r8a77970-eagle.dts
@@ -19,14 +19,17 @@
 	};
 
 	chosen {
-		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
 		stdout-path = "serial0:115200n8";
 	};
 
-	memory@48000000 {
-		device_type = "memory";
-		/* first 128MB is reserved for secure area. */
-		reg = <0x0 0x48000000 0x0 0x38000000>;
+	d3p3: regulator-fixed {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
 	};
 
 	hdmi-out {
@@ -40,15 +43,6 @@
 		};
 	};
 
-	d3p3: regulator-fixed {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
 	lvds-decoder {
 		compatible = "thine,thc63lvd1024";
 
@@ -73,6 +67,12 @@
 			};
 		};
 	};
+
+	memory@48000000 {
+		device_type = "memory";
+		/* first 128MB is reserved for secure area. */
+		reg = <0x0 0x48000000 0x0 0x38000000>;
+	};
 };
 
 &avb {
@@ -102,6 +102,10 @@
 	};
 };
 
+&du {
+	status = "okay";
+};
+
 &extal_clk {
 	clock-frequency = <16666666>;
 };
@@ -157,6 +161,18 @@
 	};
 };
 
+&lvds0 {
+	status = "okay";
+
+	ports {
+		port@1 {
+			lvds0_out: endpoint {
+				remote-endpoint = <&thc63lvd1024_in>;
+			};
+		};
+	};
+};
+
 &pfc {
 	avb_pins: avb0 {
 		groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
@@ -190,19 +206,3 @@
 
 	status = "okay";
 };
-
-&du {
-	status = "okay";
-};
-
-&lvds0 {
-	status = "okay";
-
-	ports {
-		port@1 {
-			lvds0_out: endpoint {
-				remote-endpoint = <&thc63lvd1024_in>;
-			};
-		};
-	};
-};
diff --git a/arch/arm/dts/r8a77970.dtsi b/arch/arm/dts/r8a77970.dtsi
index 5b6164d..664a73a 100644
--- a/arch/arm/dts/r8a77970.dtsi
+++ b/arch/arm/dts/r8a77970.dtsi
@@ -302,8 +302,8 @@
 
 		thermal: thermal@e6190000 {
 			compatible = "renesas,thermal-r8a77970";
-			reg =  <0 0xe6190000 0 0x10
-				0 0xe6190100 0 0x120>;
+			reg = <0 0xe6190000 0 0x10>,
+			      <0 0xe6190100 0 0x120>;
 			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
@@ -318,12 +318,12 @@
 			#interrupt-cells = <2>;
 			interrupt-controller;
 			reg = <0 0xe61c0000 0 0x200>;
-			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 407>;
 			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 			resets = <&cpg 407>;
@@ -652,7 +652,7 @@
 		};
 
 		pwm3: pwm@e6e33000 {
-			compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+			compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar";
 			reg = <0 0xe6e33000 0 8>;
 			#pwm-cells = <2>;
 			clocks = <&cpg CPG_MOD 523>;
@@ -933,15 +933,15 @@
 			compatible = "renesas,dmac-r8a77970",
 				     "renesas,rcar-dmac";
 			reg = <0 0xe7300000 0 0x10000>;
-			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					  "ch0", "ch1", "ch2", "ch3",
 					  "ch4", "ch5", "ch6", "ch7";
@@ -961,15 +961,15 @@
 			compatible = "renesas,dmac-r8a77970",
 				     "renesas,rcar-dmac";
 			reg = <0 0xe7310000 0 0x10000>;
-			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					  "ch0", "ch1", "ch2", "ch3",
 					  "ch4", "ch5", "ch6", "ch7";
@@ -1035,6 +1035,7 @@
 			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 			resets = <&cpg 314>;
 			max-frequency = <200000000>;
+			iommus = <&ipmmu_ds1 32>;
 			status = "disabled";
 		};
 
@@ -1120,7 +1121,7 @@
 			clock-names = "du.0";
 			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 			resets = <&cpg 724>;
-			vsps = <&vspd0>;
+			vsps = <&vspd0 0>;
 			status = "disabled";
 
 			ports {
@@ -1181,6 +1182,9 @@
 			polling-delay = <1000>;
 			thermal-sensors = <&thermal>;
 
+			cooling-maps {
+			};
+
 			trips {
 				cpu-crit {
 					temperature = <120000>;
@@ -1188,9 +1192,6 @@
 					type = "critical";
 				};
 			};
-
-			cooling-maps {
-			};
 		};
 	};
 
diff --git a/arch/arm/dts/r8a77980-condor.dts b/arch/arm/dts/r8a77980-condor.dts
index 5a7012b..3dde028 100644
--- a/arch/arm/dts/r8a77980-condor.dts
+++ b/arch/arm/dts/r8a77980-condor.dts
@@ -22,35 +22,20 @@
 		stdout-path = "serial0:115200n8";
 	};
 
-	memory@48000000 {
-		device_type = "memory";
-		/* first 128MB is reserved for secure area. */
-		reg = <0 0x48000000 0 0x78000000>;
-	};
-
-	d3_3v: regulator-0 {
-		compatible = "regulator-fixed";
-		regulator-name = "D3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	vddq_vin01: regulator-1 {
+	d1_8v: regulator-2 {
 		compatible = "regulator-fixed";
-		regulator-name = "VDDQ_VIN01";
+		regulator-name = "D1.8V";
 		regulator-min-microvolt = <1800000>;
 		regulator-max-microvolt = <1800000>;
 		regulator-boot-on;
 		regulator-always-on;
 	};
 
-	d1_8v: regulator-2 {
+	d3_3v: regulator-0 {
 		compatible = "regulator-fixed";
-		regulator-name = "D1.8V";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
+		regulator-name = "D3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
 		regulator-boot-on;
 		regulator-always-on;
 	};
@@ -90,6 +75,21 @@
 		};
 	};
 
+	memory@48000000 {
+		device_type = "memory";
+		/* first 128MB is reserved for secure area. */
+		reg = <0 0x48000000 0 0x78000000>;
+	};
+
+	vddq_vin01: regulator-1 {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDQ_VIN01";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
 	x1_clk: x1-clock {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
diff --git a/arch/arm/dts/r8a77980.dtsi b/arch/arm/dts/r8a77980.dtsi
index a901a34..b340fb4 100644
--- a/arch/arm/dts/r8a77980.dtsi
+++ b/arch/arm/dts/r8a77980.dtsi
@@ -348,12 +348,12 @@
 			#interrupt-cells = <2>;
 			interrupt-controller;
 			reg = <0 0xe61c0000 0 0x200>;
-			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 407>;
 			power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 			resets = <&cpg 407>;
@@ -1174,23 +1174,23 @@
 			compatible = "renesas,dmac-r8a77980",
 				     "renesas,rcar-dmac";
 			reg = <0 0xe7300000 0 0x10000>;
-			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					  "ch0", "ch1", "ch2", "ch3",
 					  "ch4", "ch5", "ch6", "ch7",
@@ -1216,23 +1216,23 @@
 			compatible = "renesas,dmac-r8a77980",
 				     "renesas,rcar-dmac";
 			reg = <0 0xe7310000 0 0x10000>;
-			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					  "ch0", "ch1", "ch2", "ch3",
 					  "ch4", "ch5", "ch6", "ch7",
@@ -1299,9 +1299,9 @@
 			#iommu-cells = <1>;
 		};
 
-		ipmmu_vc0: mmu@fe6b0000 {
+		ipmmu_vc0: mmu@fe990000 {
 			compatible = "renesas,ipmmu-r8a77980";
-			reg = <0 0xfe6b0000 0 0x1000>;
+			reg = <0 0xfe990000 0 0x1000>;
 			renesas,ipmmu-main = <&ipmmu_mm 12>;
 			power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 			#iommu-cells = <1>;
@@ -1338,6 +1338,7 @@
 			power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 			resets = <&cpg 314>;
 			max-frequency = <200000000>;
+			iommus = <&ipmmu_ds1 32>;
 			status = "disabled";
 		};
 
@@ -1366,21 +1367,17 @@
 			#size-cells = <2>;
 			bus-range = <0x00 0xff>;
 			device_type = "pci";
-			ranges = <
-				0x01000000 0 0x00000000 0 0xfe100000 0 0x0100000
-				0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000
-				0x02000000 0 0x30000000 0 0x30000000 0 0x8000000
-				0x42000000 0 0x38000000 0 0x38000000 0 0x8000000
-			>;
-			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000
-				      0 0x80000000>;
+			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x0100000>,
+				 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000>,
+				 <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>,
+				 <0x42000000 0 0x38000000 0 0x38000000 0 0x8000000>;
+			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
 			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 0>;
-			interrupt-map = <0 0 0 0 &gic GIC_SPI 148
-					 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
 			clock-names = "pcie", "pcie_bus";
 			power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
@@ -1495,7 +1492,7 @@
 			clock-names = "du.0";
 			power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 			resets = <&cpg 724>;
-			vsps = <&vspd0>;
+			vsps = <&vspd0 0>;
 			status = "disabled";
 
 			ports {
diff --git a/arch/arm/dts/r8a77990-ebisu.dts b/arch/arm/dts/r8a77990-ebisu.dts
index c727725..4fd2b14 100644
--- a/arch/arm/dts/r8a77990-ebisu.dts
+++ b/arch/arm/dts/r8a77990-ebisu.dts
@@ -19,16 +19,10 @@
 	};
 
 	chosen {
-		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
 		stdout-path = "serial0:115200n8";
 	};
 
-	memory@48000000 {
-		device_type = "memory";
-		/* first 128MB is reserved for secure area. */
-		reg = <0x0 0x48000000 0x0 0x38000000>;
-	};
-
 	audio_clkout: audio-clkout {
 		/*
 		 * This is same as <&rcar_sound 0>
@@ -107,36 +101,10 @@
 		};
 	};
 
-	vga {
-		compatible = "vga-connector";
-
-		port {
-			vga_in: endpoint {
-				remote-endpoint = <&adv7123_out>;
-			};
-		};
-	};
-
-	vga-encoder {
-		compatible = "adi,adv7123";
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				adv7123_in: endpoint {
-					remote-endpoint = <&du_out_rgb>;
-				};
-			};
-			port@1 {
-				reg = <1>;
-				adv7123_out: endpoint {
-					remote-endpoint = <&vga_in>;
-				};
-			};
-		};
+	memory@48000000 {
+		device_type = "memory";
+		/* first 128MB is reserved for secure area. */
+		reg = <0x0 0x48000000 0x0 0x38000000>;
 	};
 
 	reg_1p8v: regulator0 {
@@ -157,15 +125,13 @@
 		regulator-always-on;
 	};
 
-	vbus0_usb2: regulator-vbus0-usb2 {
+	reg_12p0v: regulator2 {
 		compatible = "regulator-fixed";
-
-		regulator-name = "USB20_VBUS_CN";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-
-		gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
+		regulator-name = "D12.0V";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		regulator-boot-on;
+		regulator-always-on;
 	};
 
 	rsnd_ak4613: sound {
@@ -176,34 +142,24 @@
 		simple-audio-card,bitclock-master = <&sndcpu>;
 		simple-audio-card,frame-master = <&sndcpu>;
 
-		sndcpu: simple-audio-card,cpu {
-			sound-dai = <&rcar_sound>;
-		};
-
 		sndcodec: simple-audio-card,codec {
 			sound-dai = <&ak4613>;
 		};
-	};
 
-	x12_clk: x12 {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <24576000>;
+		sndcpu: simple-audio-card,cpu {
+			sound-dai = <&rcar_sound>;
+		};
 	};
 
-	reg_12p0v: regulator2 {
+	vbus0_usb2: regulator-vbus0-usb2 {
 		compatible = "regulator-fixed";
-		regulator-name = "D12.0V";
-		regulator-min-microvolt = <12000000>;
-		regulator-max-microvolt = <12000000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
 
-	x13_clk: x13 {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <74250000>;
+		regulator-name = "USB20_VBUS_CN";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+
+		gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
 	};
 
 	vcc_sdhi0: regulator-vcc-sdhi0 {
@@ -226,8 +182,7 @@
 
 		gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
 		gpios-states = <1>;
-		states = <3300000 1
-			  1800000 0>;
+		states = <3300000 1>, <1800000 0>;
 	};
 
 	vcc_sdhi1: regulator-vcc-sdhi1 {
@@ -250,8 +205,51 @@
 
 		gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
 		gpios-states = <1>;
-		states = <3300000 1
-			  1800000 0>;
+		states = <3300000 1>, <1800000 0>;
+	};
+
+	vga {
+		compatible = "vga-connector";
+
+		port {
+			vga_in: endpoint {
+				remote-endpoint = <&adv7123_out>;
+			};
+		};
+	};
+
+	vga-encoder {
+		compatible = "adi,adv7123";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				adv7123_in: endpoint {
+					remote-endpoint = <&du_out_rgb>;
+				};
+			};
+			port@1 {
+				reg = <1>;
+				adv7123_out: endpoint {
+					remote-endpoint = <&vga_in>;
+				};
+			};
+		};
+	};
+
+	x12_clk: x12 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24576000>;
+	};
+
+	x13_clk: x13 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <74250000>;
 	};
 };
 
@@ -262,7 +260,6 @@
 &avb {
 	pinctrl-0 = <&avb_pins>;
 	pinctrl-names = "default";
-	renesas,no-ether-link;
 	phy-handle = <&phy0>;
 	status = "okay";
 
@@ -272,6 +269,14 @@
 		interrupt-parent = <&gpio2>;
 		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
 		reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
+		/*
+		 * TX clock internal delay mode is required for reliable
+		 * 1Gbps communication using the KSZ9031RNX phy present on
+		 * the Ebisu board, however, TX clock internal delay mode
+		 * isn't supported on r8a77990.  Thus, limit speed to
+		 * 100Mbps for reliable communication.
+		 */
+		max-speed = <100>;
 	};
 };
 
@@ -548,6 +553,11 @@
 		function = "pwm5";
 	};
 
+	scif2_pins: scif2 {
+		groups = "scif2_data_a";
+		function = "scif2";
+	};
+
 	sdhi0_pins: sd0 {
 		groups = "sdhi0_data4", "sdhi0_ctrl";
 		function = "sdhi0";
@@ -578,20 +588,15 @@
 		power-source = <1800>;
 	};
 
-	sound_pins: sound {
-		groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data";
-		function = "ssi";
-	};
-
 	sound_clk_pins: sound_clk {
 		groups = "audio_clk_a", "audio_clk_b_a", "audio_clk_c_a",
 			 "audio_clkout_a", "audio_clkout1_a";
 		function = "audio_clk";
 	};
 
-	scif2_pins: scif2 {
-		groups = "scif2_data_a";
-		function = "scif2";
+	sound_pins: sound {
+		groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data";
+		function = "ssi";
 	};
 
 	usb0_pins: usb {
@@ -629,7 +634,6 @@
 	/* audio_clkout0/1/2/3 */
 	#clock-cells = <1>;
 	clock-frequency = <12288000 11289600>;
-	clkout-lr-synchronous;
 
 	status = "okay";
 
@@ -669,41 +673,9 @@
 	pinctrl-0 = <&scif2_pins>;
 	pinctrl-names = "default";
 
-	status = "okay";
-};
-
-&ssi1 {
-	shared-pin;
-};
-
-&usb2_phy0 {
-	pinctrl-0 = <&usb0_pins>;
-	pinctrl-names = "default";
-
-	vbus-supply = <&vbus0_usb2>;
 	status = "okay";
 };
 
-&usb3_peri0 {
-	companion = <&xhci0>;
-	status = "okay";
-};
-
-&vin4 {
-	status = "okay";
-};
-
-&vin5 {
-	status = "okay";
-};
-
-&xhci0 {
-	pinctrl-0 = <&usb30_pins>;
-	pinctrl-names = "default";
-
-	status = "okay";
-};
-
 &sdhi0 {
 	pinctrl-0 = <&sdhi0_pins>;
 	pinctrl-1 = <&sdhi0_pins_uhs>;
@@ -747,3 +719,35 @@
 	non-removable;
 	status = "okay";
 };
+
+&ssi1 {
+	shared-pin;
+};
+
+&usb2_phy0 {
+	pinctrl-0 = <&usb0_pins>;
+	pinctrl-names = "default";
+
+	vbus-supply = <&vbus0_usb2>;
+	status = "okay";
+};
+
+&usb3_peri0 {
+	companion = <&xhci0>;
+	status = "okay";
+};
+
+&vin4 {
+	status = "okay";
+};
+
+&vin5 {
+	status = "okay";
+};
+
+&xhci0 {
+	pinctrl-0 = <&usb30_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
diff --git a/arch/arm/dts/r8a77990.dtsi b/arch/arm/dts/r8a77990.dtsi
index 56cb566..32d91f2 100644
--- a/arch/arm/dts/r8a77990.dtsi
+++ b/arch/arm/dts/r8a77990.dtsi
@@ -84,9 +84,11 @@
 			compatible = "arm,cortex-a53";
 			reg = <0>;
 			device_type = "cpu";
+			#cooling-cells = <2>;
 			power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			dynamic-power-coefficient = <277>;
 			clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
 			operating-points-v2 = <&cluster1_opp>;
 		};
@@ -392,12 +394,12 @@
 			#interrupt-cells = <2>;
 			interrupt-controller;
 			reg = <0 0xe61c0000 0 0x200>;
-			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 407>;
 			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 			resets = <&cpg 407>;
@@ -630,7 +632,7 @@
 			       <&usb_dmac1 0>, <&usb_dmac1 1>;
 			dma-names = "ch0", "ch1", "ch2", "ch3";
 			renesas,buswait = <11>;
-			phys = <&usb2_phy0>;
+			phys = <&usb2_phy0 3>;
 			phy-names = "usb";
 			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 			resets = <&cpg 704>, <&cpg 703>;
@@ -641,8 +643,8 @@
 			compatible = "renesas,r8a77990-usb-dmac",
 				     "renesas,usb-dmac";
 			reg = <0 0xe65a0000 0 0x100>;
-			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "ch0", "ch1";
 			clocks = <&cpg CPG_MOD 330>;
 			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
@@ -655,8 +657,8 @@
 			compatible = "renesas,r8a77990-usb-dmac",
 				     "renesas,usb-dmac";
 			reg = <0 0xe65b0000 0 0x100>;
-			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "ch0", "ch1";
 			clocks = <&cpg CPG_MOD 331>;
 			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
@@ -669,23 +671,23 @@
 			compatible = "renesas,dmac-r8a77990",
 				     "renesas,rcar-dmac";
 			reg = <0 0xe6700000 0 0x10000>;
-			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					"ch0", "ch1", "ch2", "ch3",
 					"ch4", "ch5", "ch6", "ch7",
@@ -711,23 +713,23 @@
 			compatible = "renesas,dmac-r8a77990",
 				     "renesas,rcar-dmac";
 			reg = <0 0xe7300000 0 0x10000>;
-			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					"ch0", "ch1", "ch2", "ch3",
 					"ch4", "ch5", "ch6", "ch7",
@@ -753,23 +755,23 @@
 			compatible = "renesas,dmac-r8a77990",
 				     "renesas,rcar-dmac";
 			reg = <0 0xe7310000 0 0x10000>;
-			interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					"ch0", "ch1", "ch2", "ch3",
 					"ch4", "ch5", "ch6", "ch7",
@@ -1324,6 +1326,17 @@
 				      "ssi.1", "ssi.0";
 			status = "disabled";
 
+			rcar_sound,ctu {
+				ctu00: ctu-0 { };
+				ctu01: ctu-1 { };
+				ctu02: ctu-2 { };
+				ctu03: ctu-3 { };
+				ctu10: ctu-4 { };
+				ctu11: ctu-5 { };
+				ctu12: ctu-6 { };
+				ctu13: ctu-7 { };
+			};
+
 			rcar_sound,dvc {
 				dvc0: dvc-0 {
 					dmas = <&audma0 0xbc>;
@@ -1340,17 +1353,6 @@
 				mix1: mix-1 { };
 			};
 
-			rcar_sound,ctu {
-				ctu00: ctu-0 { };
-				ctu01: ctu-1 { };
-				ctu02: ctu-2 { };
-				ctu03: ctu-3 { };
-				ctu10: ctu-4 { };
-				ctu11: ctu-5 { };
-				ctu12: ctu-6 { };
-				ctu13: ctu-7 { };
-			};
-
 			rcar_sound,src {
 				src0: src-0 {
 					interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
@@ -1472,23 +1474,23 @@
 			compatible = "renesas,dmac-r8a77990",
 				     "renesas,rcar-dmac";
 			reg = <0 0xec700000 0 0x10000>;
-			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					"ch0", "ch1", "ch2", "ch3",
 					"ch4", "ch5", "ch6", "ch7",
@@ -1537,7 +1539,7 @@
 			reg = <0 0xee080000 0 0x100>;
 			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
-			phys = <&usb2_phy0>;
+			phys = <&usb2_phy0 1>;
 			phy-names = "usb";
 			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 			resets = <&cpg 703>, <&cpg 704>;
@@ -1549,7 +1551,7 @@
 			reg = <0 0xee080100 0 0x100>;
 			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
-			phys = <&usb2_phy0>;
+			phys = <&usb2_phy0 2>;
 			phy-names = "usb";
 			companion = <&ohci0>;
 			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
@@ -1565,7 +1567,7 @@
 			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
 			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 			resets = <&cpg 703>, <&cpg 704>;
-			#phy-cells = <0>;
+			#phy-cells = <1>;
 			status = "disabled";
 		};
 
@@ -1578,6 +1580,7 @@
 			max-frequency = <200000000>;
 			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 			resets = <&cpg 314>;
+			iommus = <&ipmmu_ds1 32>;
 			status = "disabled";
 		};
 
@@ -1590,6 +1593,7 @@
 			max-frequency = <200000000>;
 			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 			resets = <&cpg 313>;
+			iommus = <&ipmmu_ds1 33>;
 			status = "disabled";
 		};
 
@@ -1602,6 +1606,7 @@
 			max-frequency = <200000000>;
 			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 			resets = <&cpg 311>;
+			iommus = <&ipmmu_ds1 35>;
 			status = "disabled";
 		};
 
@@ -1630,10 +1635,10 @@
 			#size-cells = <2>;
 			bus-range = <0x00 0xff>;
 			device_type = "pci";
-			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
-				  0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
-				  0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
-				  0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
+				 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
+				 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
+				 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
 			/* Map all possible DDR as inbound ranges */
 			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
 			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
@@ -1725,6 +1730,24 @@
 			iommus = <&ipmmu_vi0 9>;
 		};
 
+		cmm0: cmm@fea40000 {
+			compatible = "renesas,r8a77990-cmm",
+				     "renesas,rcar-gen3-cmm";
+			reg = <0 0xfea40000 0 0x1000>;
+			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+			clocks = <&cpg CPG_MOD 711>;
+			resets = <&cpg 711>;
+		};
+
+		cmm1: cmm@fea50000 {
+			compatible = "renesas,r8a77990-cmm",
+				     "renesas,rcar-gen3-cmm";
+			reg = <0 0xfea50000 0 0x1000>;
+			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+			clocks = <&cpg CPG_MOD 710>;
+			resets = <&cpg 710>;
+		};
+
 		csi40: csi2@feaa0000 {
 			compatible = "renesas,r8a77990-csi2";
 			reg = <0 0xfeaa0000 0 0x10000>;
@@ -1758,13 +1781,18 @@
 
 		du: display@feb00000 {
 			compatible = "renesas,du-r8a77990";
-			reg = <0 0xfeb00000 0 0x80000>;
+			reg = <0 0xfeb00000 0 0x40000>;
 			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 724>,
 				 <&cpg CPG_MOD 723>;
 			clock-names = "du.0", "du.1";
-			vsps = <&vspd0 0 &vspd1 0>;
+			resets = <&cpg 724>;
+			reset-names = "du.0";
+
+			renesas,cmms = <&cmm0>, <&cmm1>;
+			vsps = <&vspd0 0>, <&vspd1 0>;
+
 			status = "disabled";
 
 			ports {
@@ -1801,6 +1829,8 @@
 			resets = <&cpg 727>;
 			status = "disabled";
 
+			renesas,companion = <&lvds1>;
+
 			ports {
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -1856,18 +1886,30 @@
 	thermal-zones {
 		cpu-thermal {
 			polling-delay-passive = <250>;
-			polling-delay = <1000>;
-			thermal-sensors = <&thermal>;
+			polling-delay = <0>;
+			thermal-sensors = <&thermal 0>;
+			sustainable-power = <717>;
+
+			cooling-maps {
+				map0 {
+					trip = <&target>;
+					cooling-device = <&a53_0 0 2>;
+					contribution = <1024>;
+				};
+			};
 
 			trips {
-				cpu-crit {
+				sensor1_crit: sensor1-crit {
 					temperature = <120000>;
 					hysteresis = <2000>;
 					type = "critical";
 				};
-			};
 
-			cooling-maps {
+				target: trip-point1 {
+					temperature = <100000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
 			};
 		};
 	};
diff --git a/arch/arm/dts/r8a77995-draak.dts b/arch/arm/dts/r8a77995-draak.dts
index a7dc11e..67634cb 100644
--- a/arch/arm/dts/r8a77995-draak.dts
+++ b/arch/arm/dts/r8a77995-draak.dts
@@ -19,11 +19,6 @@
 		ethernet0 = &avb;
 	};
 
-	chosen {
-		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
-		stdout-path = "serial0:115200n8";
-	};
-
 	backlight: backlight {
 		compatible = "pwm-backlight";
 		pwms = <&pwm1 0 50000>;
@@ -35,6 +30,11 @@
 		enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
 	};
 
+	chosen {
+		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
+		stdout-path = "serial0:115200n8";
+	};
+
 	composite-in {
 		compatible = "composite-video-connector";
 
@@ -97,7 +97,7 @@
 		reg = <0x0 0x48000000 0x0 0x18000000>;
 	};
 
-	reg_1p8v: regulator0 {
+	reg_1p8v: regulator-1p8v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-1.8V";
 		regulator-min-microvolt = <1800000>;
@@ -106,7 +106,7 @@
 		regulator-always-on;
 	};
 
-	reg_3p3v: regulator1 {
+	reg_3p3v: regulator-3p3v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-3.3V";
 		regulator-min-microvolt = <3300000>;
@@ -115,7 +115,7 @@
 		regulator-always-on;
 	};
 
-	reg_12p0v: regulator1 {
+	reg_12p0v: regulator-12p0v {
 		compatible = "regulator-fixed";
 		regulator-name = "D12.0V";
 		regulator-min-microvolt = <12000000>;
@@ -175,6 +175,14 @@
 		reg = <0>;
 		interrupt-parent = <&gpio5>;
 		interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+		/*
+		 * TX clock internal delay mode is required for reliable
+		 * 1Gbps communication using the KSZ9031RNX phy present on
+		 * the Draak board, however, TX clock internal delay mode
+		 * isn't supported on r8a77995.  Thus, limit speed to
+		 * 100Mbps for reliable communication.
+		 */
+		max-speed = <100>;
 	};
 };
 
@@ -511,12 +519,7 @@
 	status = "okay";
 
 	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		port@0 {
-			reg = <0>;
-
+		port {
 			vin4_in: endpoint {
 				remote-endpoint = <&adv7180_out>;
 			};
diff --git a/arch/arm/dts/r8a77995.dtsi b/arch/arm/dts/r8a77995.dtsi
index 5bf3af2..9503007 100644
--- a/arch/arm/dts/r8a77995.dtsi
+++ b/arch/arm/dts/r8a77995.dtsi
@@ -231,52 +231,17 @@
 			#interrupt-cells = <2>;
 			interrupt-controller;
 			reg = <0 0xe61c0000 0 0x200>;
-			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 407>;
 			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 			resets = <&cpg 407>;
 		};
 
-		hscif0: serial@e6540000 {
-			compatible = "renesas,hscif-r8a77995",
-				     "renesas,rcar-gen3-hscif",
-				     "renesas,hscif";
-			reg = <0 0xe6540000 0 0x60>;
-			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 520>,
-				 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
-				 <&scif_clk>;
-			clock-names = "fck", "brg_int", "scif_clk";
-			dmas = <&dmac1 0x31>, <&dmac1 0x30>,
-			       <&dmac2 0x31>, <&dmac2 0x30>;
-			dma-names = "tx", "rx", "tx", "rx";
-			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
-			resets = <&cpg 520>;
-			status = "disabled";
-		};
-
-		hscif3: serial@e66a0000 {
-			compatible = "renesas,hscif-r8a77995",
-				     "renesas,rcar-gen3-hscif",
-				     "renesas,hscif";
-			reg = <0 0xe66a0000 0 0x60>;
-			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 517>,
-				 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
-				 <&scif_clk>;
-			clock-names = "fck", "brg_int", "scif_clk";
-			dmas = <&dmac0 0x37>, <&dmac0 0x36>;
-			dma-names = "tx", "rx";
-			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
-			resets = <&cpg 517>;
-			status = "disabled";
-		};
-
 		i2c0: i2c@e6500000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -344,6 +309,41 @@
 			status = "disabled";
 		};
 
+		hscif0: serial@e6540000 {
+			compatible = "renesas,hscif-r8a77995",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe6540000 0 0x60>;
+			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 520>,
+				 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+			       <&dmac2 0x31>, <&dmac2 0x30>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 520>;
+			status = "disabled";
+		};
+
+		hscif3: serial@e66a0000 {
+			compatible = "renesas,hscif-r8a77995",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe66a0000 0 0x60>;
+			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 517>,
+				 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac0 0x37>, <&dmac0 0x36>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 517>;
+			status = "disabled";
+		};
+
 		hsusb: usb@e6590000 {
 			compatible = "renesas,usbhs-r8a77995",
 				     "renesas,rcar-gen3-usbhs";
@@ -354,7 +354,7 @@
 			       <&usb_dmac1 0>, <&usb_dmac1 1>;
 			dma-names = "ch0", "ch1", "ch2", "ch3";
 			renesas,buswait = <11>;
-			phys = <&usb2_phy0>;
+			phys = <&usb2_phy0 3>;
 			phy-names = "usb";
 			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 			resets = <&cpg 704>, <&cpg 703>;
@@ -365,8 +365,8 @@
 			compatible = "renesas,r8a77995-usb-dmac",
 				     "renesas,usb-dmac";
 			reg = <0 0xe65a0000 0 0x100>;
-			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "ch0", "ch1";
 			clocks = <&cpg CPG_MOD 330>;
 			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
@@ -379,8 +379,8 @@
 			compatible = "renesas,r8a77995-usb-dmac",
 				     "renesas,usb-dmac";
 			reg = <0 0xe65b0000 0 0x100>;
-			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "ch0", "ch1";
 			clocks = <&cpg CPG_MOD 331>;
 			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
@@ -418,15 +418,15 @@
 			compatible = "renesas,dmac-r8a77995",
 				     "renesas,rcar-dmac";
 			reg = <0 0xe6700000 0 0x10000>;
-			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					"ch0", "ch1", "ch2", "ch3",
 					"ch4", "ch5", "ch6", "ch7";
@@ -446,15 +446,15 @@
 			compatible = "renesas,dmac-r8a77995",
 				     "renesas,rcar-dmac";
 			reg = <0 0xe7300000 0 0x10000>;
-			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					"ch0", "ch1", "ch2", "ch3",
 					"ch4", "ch5", "ch6", "ch7";
@@ -474,15 +474,15 @@
 			compatible = "renesas,dmac-r8a77995",
 				     "renesas,rcar-dmac";
 			reg = <0 0xe7310000 0 0x10000>;
-			interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
-				      GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					"ch0", "ch1", "ch2", "ch3",
 					"ch4", "ch5", "ch6", "ch7";
@@ -875,7 +875,7 @@
 			reg = <0 0xee080000 0 0x100>;
 			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
-			phys = <&usb2_phy0>;
+			phys = <&usb2_phy0 1>;
 			phy-names = "usb";
 			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 			resets = <&cpg 703>, <&cpg 704>;
@@ -887,7 +887,7 @@
 			reg = <0 0xee080100 0 0x100>;
 			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
-			phys = <&usb2_phy0>;
+			phys = <&usb2_phy0 2>;
 			phy-names = "usb";
 			companion = <&ohci0>;
 			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
@@ -903,7 +903,7 @@
 			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
 			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 			resets = <&cpg 703>, <&cpg 704>;
-			#phy-cells = <0>;
+			#phy-cells = <1>;
 			status = "disabled";
 		};
 
@@ -916,6 +916,7 @@
 			max-frequency = <200000000>;
 			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 			resets = <&cpg 312>;
+			iommus = <&ipmmu_ds1 34>;
 			status = "disabled";
 		};
 
@@ -993,15 +994,38 @@
 			iommus = <&ipmmu_vi0 9>;
 		};
 
+		cmm0: cmm@fea40000 {
+			compatible = "renesas,r8a77995-cmm",
+				     "renesas,rcar-gen3-cmm";
+			reg = <0 0xfea40000 0 0x1000>;
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			clocks = <&cpg CPG_MOD 711>;
+			resets = <&cpg 711>;
+		};
+
+		cmm1: cmm@fea50000 {
+			compatible = "renesas,r8a77995-cmm",
+				     "renesas,rcar-gen3-cmm";
+			reg = <0 0xfea50000 0 0x1000>;
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			clocks = <&cpg CPG_MOD 710>;
+			resets = <&cpg 710>;
+		};
+
 		du: display@feb00000 {
 			compatible = "renesas,du-r8a77995";
-			reg = <0 0xfeb00000 0 0x80000>;
+			reg = <0 0xfeb00000 0 0x40000>;
 			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 724>,
 				 <&cpg CPG_MOD 723>;
 			clock-names = "du.0", "du.1";
-			vsps = <&vspd0 0 &vspd1 0>;
+			resets = <&cpg 724>;
+			reset-names = "du.0";
+
+			renesas,cmms = <&cmm0>, <&cmm1>;
+			vsps = <&vspd0 0>, <&vspd1 0>;
+
 			status = "disabled";
 
 			ports {
@@ -1038,6 +1062,8 @@
 			resets = <&cpg 727>;
 			status = "disabled";
 
+			renesas,companion = <&lvds1>;
+
 			ports {
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -1096,6 +1122,9 @@
 			polling-delay = <1000>;
 			thermal-sensors = <&thermal>;
 
+			cooling-maps {
+			};
+
 			trips {
 				cpu-crit {
 					temperature = <120000>;
@@ -1103,9 +1132,6 @@
 					type = "critical";
 				};
 			};
-
-			cooling-maps {
-			};
 		};
 	};
 
diff --git a/arch/arm/dts/salvator-common.dtsi b/arch/arm/dts/salvator-common.dtsi
index 2dba132..98bbcaf 100644
--- a/arch/arm/dts/salvator-common.dtsi
+++ b/arch/arm/dts/salvator-common.dtsi
@@ -39,7 +39,7 @@
 	};
 
 	chosen {
-		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
 		stdout-path = "serial0:115200n8";
 	};
 
@@ -87,6 +87,28 @@
 		};
 	};
 
+	hdmi0-out {
+		compatible = "hdmi-connector";
+		label = "HDMI0 OUT";
+		type = "a";
+
+		port {
+			hdmi0_con: endpoint {
+			};
+		};
+	};
+
+	hdmi1-out {
+		compatible = "hdmi-connector";
+		label = "HDMI1 OUT";
+		type = "a";
+
+		port {
+			hdmi1_con: endpoint {
+			};
+		};
+	};
+
 	keys {
 		compatible = "gpio-keys";
 
@@ -210,8 +232,7 @@
 
 		gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
 		gpios-states = <1>;
-		states = <3300000 1
-			  1800000 0>;
+		states = <3300000 1>, <1800000 0>;
 	};
 
 	vcc_sdhi3: regulator-vcc-sdhi3 {
@@ -234,30 +255,7 @@
 
 		gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
 		gpios-states = <1>;
-		states = <3300000 1
-			  1800000 0>;
-	};
-
-	hdmi0-out {
-		compatible = "hdmi-connector";
-		label = "HDMI0 OUT";
-		type = "a";
-
-		port {
-			hdmi0_con: endpoint {
-			};
-		};
-	};
-
-	hdmi1-out {
-		compatible = "hdmi-connector";
-		label = "HDMI1 OUT";
-		type = "a";
-
-		port {
-			hdmi1_con: endpoint {
-			};
-		};
+		states = <3300000 1>, <1800000 0>;
 	};
 
 	vga {
@@ -462,20 +460,6 @@
 		#gpio-cells = <2>;
 	};
 
-	csa_vdd: adc@7c {
-		compatible = "maxim,max9611";
-		reg = <0x7c>;
-
-		shunt-resistor-micro-ohms = <5000>;
-	};
-
-	csa_dvfs: adc@7f {
-		compatible = "maxim,max9611";
-		reg = <0x7f>;
-
-		shunt-resistor-micro-ohms = <5000>;
-	};
-
 	video-receiver@70 {
 		compatible = "adi,adv7482";
 		reg = <0x70 0x71 0x72 0x73 0x74 0x75
@@ -527,6 +511,20 @@
 			};
 		};
 	};
+
+	csa_vdd: adc@7c {
+		compatible = "maxim,max9611";
+		reg = <0x7c>;
+
+		shunt-resistor-micro-ohms = <5000>;
+	};
+
+	csa_dvfs: adc@7f {
+		compatible = "maxim,max9611";
+		reg = <0x7f>;
+
+		shunt-resistor-micro-ohms = <5000>;
+	};
 };
 
 &i2c_dvfs {
diff --git a/arch/arm/dts/salvator-xs.dtsi b/arch/arm/dts/salvator-xs.dtsi
new file mode 100644
index 0000000..717d427
--- /dev/null
+++ b/arch/arm/dts/salvator-xs.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Salvator-X 2nd version board
+ *
+ * Copyright (C) 2015-2017 Renesas Electronics Corp.
+ */
+
+#include "salvator-common.dtsi"
+
+/ {
+	model = "Renesas Salvator-X 2nd version board";
+	compatible = "renesas,salvator-xs";
+};
+
+&extal_clk {
+	clock-frequency = <16640000>;
+};
+
+&i2c4 {
+	clock-frequency = <400000>;
+
+	versaclock6: clock-generator@6a {
+		compatible = "idt,5p49v6901";
+		reg = <0x6a>;
+		#clock-cells = <1>;
+		clocks = <&x23_clk>;
+		clock-names = "xin";
+	};
+};
diff --git a/arch/arm/dts/ulcb.dtsi b/arch/arm/dts/ulcb.dtsi
index e70e1ba..ff88af8 100644
--- a/arch/arm/dts/ulcb.dtsi
+++ b/arch/arm/dts/ulcb.dtsi
@@ -26,7 +26,7 @@
 	};
 
 	chosen {
-		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
 		stdout-path = "serial0:115200n8";
 	};
 
@@ -120,8 +120,7 @@
 
 		gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
 		gpios-states = <1>;
-		states = <3300000 1
-			  1800000 0>;
+		states = <3300000 1>, <1800000 0>;
 	};
 
 	x12_clk: x12 {
@@ -428,6 +427,11 @@
 	};
 };
 
+&rwdt {
+	timeout-sec = <60>;
+	status = "okay";
+};
+
 &scif2 {
 	pinctrl-0 = <&scif2_pins>;
 	pinctrl-names = "default";
@@ -478,8 +482,3 @@
 
 	status = "okay";
 };
-
-&rwdt {
-	timeout-sec = <60>;
-	status = "okay";
-};
diff --git a/arch/arm/dts/zynq-cse-nand.dts b/arch/arm/dts/zynq-cse-nand.dts
index 1e16d7f..32cb3bf 100644
--- a/arch/arm/dts/zynq-cse-nand.dts
+++ b/arch/arm/dts/zynq-cse-nand.dts
@@ -38,6 +38,21 @@
 		#size-cells = <1>;
 		ranges;
 
+		smcc: memory-controller@e000e000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clock-names = "memclk", "apb_pclk";
+			clocks = <&clkc 11>, <&clkc 44>;
+			compatible = "arm,pl353-smc-r2p1", "arm,primecell";
+			ranges;
+			reg = <0xe000e000 0x1000>;
+
+			nand0: flash@e1000000 {
+				compatible = "arm,pl353-nand-r2p1";
+				reg = <0xe1000000 0x1000000>;
+			};
+		};
+
 		slcr: slcr@f8000000 {
 			u-boot,dm-pre-reloc;
 			#address-cells = <1>;
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
index 39b5d7f..bf982e2 100644
--- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
@@ -162,9 +162,9 @@
 		  "", "", "", "", "", /* 65 - 69 */
 		  "", "", "", "", "", /* 70 - 74 */
 		  "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
-		  "", "", /* 78 - 79 */
-		  "", "", "", "", "", /* 80 - 84 */
-		  "", "", "", "", "", /* 85 -89 */
+		  "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
+		  "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */
+		  "", "", "", "", "", /* 85 - 89 */
 		  "", "", "", "", "", /* 90 - 94 */
 		  "", "", "", "", "", /* 95 - 99 */
 		  "", "", "", "", "", /* 100 - 104 */
@@ -198,9 +198,6 @@
 			#size-cells = <0>;
 			reg = <0>;
 			/* u152 IR35215 0x16/0x46 vcc_soc */
-			/* u160 IRPS5401 0x17/0x47 */
-			/* u167 IRPS5401 0x1c/0x4c */
-			/* u175 IRPS5401 0x1d/0x4d */
 			/* u179 ir38164 0x19/0x49 vcco_500 */
 			/* u181 ir38164 0x1a/0x4a vcco_501 */
 			/* u183 ir38164 0x1b/0x4b vcco_502 */
@@ -209,6 +206,19 @@
 			/* u189 ir38164 0x20/0x50 mgtyavtt */
 			/* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */
 			/* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */
+
+			irps5401_47: irps5401@47 { /* IRPS5401 - u160 */
+				compatible = "infineon,irps5401";
+				reg = <0x47>; /* pmbus / i2c 0x17 */
+			};
+			irps5401_4c: irps5401@4c { /* IRPS5401 - u167 */
+				compatible = "infineon,irps5401";
+				reg = <0x4c>; /* pmbus / i2c 0x1c */
+			};
+			irps5401_4d: irps5401@4d { /* IRPS5401 - u175 */
+				compatible = "infineon,irps5401";
+				reg = <0x4d>; /* pmbus / i2c 0x1d */
+			};
 		};
 		i2c@1 { /* PMBUS1_INA226 */
 			#address-cells = <1>;
diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts
index 3ceb39d..a4bd6b8 100644
--- a/arch/arm/dts/zynqmp-zcu104-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revA.dts
@@ -147,15 +147,13 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <2>;
-			irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
-				#clock-cells = <0>;
+			irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
 				compatible = "infineon,irps5401";
-				reg = <0x43>;
+				reg = <0x43>; /* pmbus / i2c 0x13 */
 			};
-			irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
-				#clock-cells = <0>;
+			irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
 				compatible = "infineon,irps5401";
-				reg = <0x4d>;
+				reg = <0x44>; /* pmbus / i2c 0x14 */
 			};
 		};
 
diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts
index 7dad452..d4b3769 100644
--- a/arch/arm/dts/zynqmp-zcu104-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revC.dts
@@ -172,15 +172,13 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <2>;
-			irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
-				#clock-cells = <0>;
+			irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
 				compatible = "infineon,irps5401";
-				reg = <0x43>;
+				reg = <0x43>; /* pmbus / i2c 0x13 */
 			};
-			irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
-				#clock-cells = <0>;
+			irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
 				compatible = "infineon,irps5401";
-				reg = <0x4d>;
+				reg = <0x44>; /* pmbus / i2c 0x14 */
 			};
 		};
 
diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts
index d16bf8a..63e285f 100644
--- a/arch/arm/dts/zynqmp-zcu111-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu111-revA.dts
@@ -327,18 +327,15 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <2>;
-			irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */
-				#clock-cells = <0>;
+			irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */
 				compatible = "infineon,irps5401";
 				reg = <0x43>;
 			};
-			irps5401_44: irps54012@44 { /* IRPS5401 - u55 */
-				#clock-cells = <0>;
+			irps5401_44: irps5401@44 { /* IRPS5401 - u55 */
 				compatible = "infineon,irps5401";
 				reg = <0x44>;
 			};
-			irps5401_45: irps54012@45 { /* IRPS5401 - u57 */
-				#clock-cells = <0>;
+			irps5401_45: irps5401@45 { /* IRPS5401 - u57 */
 				compatible = "infineon,irps5401";
 				reg = <0x45>;
 			};
diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts
index 75ecd7a..118a2de 100644
--- a/arch/arm/dts/zynqmp-zcu208-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu208-revA.dts
@@ -351,13 +351,11 @@
 			/* u112 - ir38164 0x13/0x43 */
 			/* u123 - ir38164 0x1c/0x4c */
 
-			irps5401_44: irps54012@44 { /* IRPS5401 - u53 */
-				#clock-cells = <0>;
+			irps5401_44: irps5401@44 { /* IRPS5401 - u53 */
 				compatible = "infineon,irps5401";
 				reg = <0x44>; /* i2c addr 0x14 */
 			};
-			irps5401_45: irps54012@45 { /* IRPS5401 - u55 */
-				#clock-cells = <0>;
+			irps5401_45: irps5401@45 { /* IRPS5401 - u55 */
 				compatible = "infineon,irps5401";
 				reg = <0x45>; /* i2c addr 0x15 */
 			};
diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts
index f3b5edf..e454bfc 100644
--- a/arch/arm/dts/zynqmp-zcu216-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu216-revA.dts
@@ -355,13 +355,11 @@
 			/* u112 - ir38164 0x13/0x43 */
 			/* u123 - ir38164 0x1c/0x4c */
 
-			irps5401_44: irps54012@44 { /* IRPS5401 - u53 */
-				#clock-cells = <0>;
+			irps5401_44: irps5401@44 { /* IRPS5401 - u53 */
 				compatible = "infineon,irps5401";
 				reg = <0x44>; /* i2c addr 0x14 */
 			};
-			irps5401_45: irps54012@45 { /* IRPS5401 - u55 */
-				#clock-cells = <0>;
+			irps5401_45: irps5401@45 { /* IRPS5401 - u55 */
 				compatible = "infineon,irps5401";
 				reg = <0x45>; /* i2c addr 0x15 */
 			};
diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h
index 9eafe43..bf05cb3 100644
--- a/arch/arm/include/asm/arch-bcmcygnus/configs.h
+++ b/arch/arm/include/asm/arch-bcmcygnus/configs.h
@@ -21,7 +21,6 @@
 #define CONFIG_SYS_NS16550_COM3		0x18023000
 
 /* Ethernet */
-#define CONFIG_PHY_BROADCOM
 #define CONFIG_PHY_RESET_DELAY 10000 /* PHY reset delay in us*/
 
 #endif /* __ARCH_CONFIGS_H */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index c62d414..020548a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -158,6 +158,10 @@
 
 bool soc_has_dp_ddr(void);
 bool soc_has_aiop(void);
+
+#ifdef CONFIG_GIC_V3_ITS
+int ls_gic_rd_tables_init(void *blob);
+#endif
 #endif
 
 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
diff --git a/arch/arm/include/asm/iproc-common/configs.h b/arch/arm/include/asm/iproc-common/configs.h
index 96c4f54..4733c07 100644
--- a/arch/arm/include/asm/iproc-common/configs.h
+++ b/arch/arm/include/asm/iproc-common/configs.h
@@ -10,7 +10,6 @@
 
 /* Architecture, CPU, chip, etc */
 #define CONFIG_IPROC
-#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
 
 /* Memory Info */
 #define CONFIG_SYS_SDRAM_BASE		0x61000000
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 81ccead..a3147fd 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -485,6 +485,14 @@
 };
 #endif
 
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+#define DCACHE_DEFAULT_OPTION	DCACHE_WRITETHROUGH
+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
+#define DCACHE_DEFAULT_OPTION	DCACHE_WRITEALLOC
+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK)
+#define DCACHE_DEFAULT_OPTION	DCACHE_WRITEBACK
+#endif
+
 /* Size of an MMU section */
 enum {
 #ifdef CONFIG_ARMV7_LPAE
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index f8d2096..f803d6f 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -61,8 +61,11 @@
 	unsigned long startpt, stoppt;
 	unsigned long upto, end;
 
-	end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
+	/* div by 2 before start + size to avoid phys_addr_t overflow */
+	end = ALIGN((start / 2) + (size / 2), MMU_SECTION_SIZE / 2)
+	      >> (MMU_SECTION_SHIFT - 1);
 	start = start >> MMU_SECTION_SHIFT;
+
 #ifdef CONFIG_ARMV7_LPAE
 	debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size,
 	      option);
@@ -91,19 +94,16 @@
 	bd_t *bd = gd->bd;
 	int	i;
 
+	/* bd->bi_dram is available only after relocation */
+	if ((gd->flags & GD_FLG_RELOC) == 0)
+		return;
+
 	debug("%s: bank: %d\n", __func__, bank);
 	for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
 	     i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
 		 (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
-	     i++) {
-#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
-		set_section_dcache(i, DCACHE_WRITETHROUGH);
-#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
-		set_section_dcache(i, DCACHE_WRITEALLOC);
-#else
-		set_section_dcache(i, DCACHE_WRITEBACK);
-#endif
-	}
+	     i++)
+		set_section_dcache(i, DCACHE_DEFAULT_OPTION);
 }
 
 /* to activate the MMU we need to set up virtual memory: use 1M areas */
diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c
index 6dbf03b..36299d6 100644
--- a/arch/arm/lib/interrupts.c
+++ b/arch/arm/lib/interrupts.c
@@ -34,6 +34,8 @@
 	 */
 	IRQ_STACK_START_IN = gd->irq_sp + 8;
 
+	enable_interrupts();
+
 	return 0;
 }
 
diff --git a/arch/arm/lib/interrupts_64.c b/arch/arm/lib/interrupts_64.c
index dffdf57..a2df7cf 100644
--- a/arch/arm/lib/interrupts_64.c
+++ b/arch/arm/lib/interrupts_64.c
@@ -13,6 +13,8 @@
 
 int interrupt_init(void)
 {
+	enable_interrupts();
+
 	return 0;
 }
 
diff --git a/arch/arm/lib/interrupts_m.c b/arch/arm/lib/interrupts_m.c
index 1f6fdf2..2ae1c5b 100644
--- a/arch/arm/lib/interrupts_m.c
+++ b/arch/arm/lib/interrupts_m.c
@@ -31,6 +31,8 @@
 
 int interrupt_init(void)
 {
+	enable_interrupts();
+
 	return 0;
 }
 
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
index e710aa2..9d2b3ba 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
@@ -85,7 +85,7 @@
 #define CLKMGR_S10_MAINPLL_VCOCALIB			0x8c
 /* Periphpll group */
 #define CLKMGR_S10_PERPLL_EN				0xa4
-#define CLKMGR_S10_PERPLL_BYPASS			0xac
+#define CLKMGR_S10_PERPLL_BYPASS			0xb0
 #define CLKMGR_S10_PERPLL_CNTR2CLK			0xbc
 #define CLKMGR_S10_PERPLL_CNTR3CLK			0xc0
 #define CLKMGR_S10_PERPLL_CNTR4CLK			0xc4
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index a3ae603..48e754c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -98,6 +98,7 @@
 	select SUPPORTS_CPU_MIPS32_R2
 	select SUPPORTS_LITTLE_ENDIAN
 	select SYSRESET
+	select SUPPORT_SPL
 
 config ARCH_JZ47XX
 	bool "Support Ingenic JZ47xx"
@@ -287,6 +288,60 @@
 
 	  If unsure, leave at the default value.
 
+config RESTORE_EXCEPTION_VECTOR_BASE
+	bool "Restore exception vector base before booting linux kernel"
+	default n
+	help
+	  In U-Boot the exception vector base will be moved to top of memory,
+	  to be used to display register dump when exception occurs.
+	  But some old linux kernel does not honor the base set in CP0_EBASE.
+	  A modified exception vector base will cause kernel crash.
+
+	  This option will restore the exception vector base to its previous
+	  value.
+
+	  If unsure, say N.
+
+config OVERRIDE_EXCEPTION_VECTOR_BASE
+	bool "Override the exception vector base to be restored"
+	depends on RESTORE_EXCEPTION_VECTOR_BASE
+	default n
+	help
+	  Enable this option if you want to use a different exception vector
+	  base rather than the previously saved one.
+
+config NEW_EXCEPTION_VECTOR_BASE
+	hex "New exception vector base"
+	depends on OVERRIDE_EXCEPTION_VECTOR_BASE
+	range 0x80000000 0xbffff000
+	default 0x80000000
+	help
+	  The exception vector base to be restored before booting linux kernel
+
+config INIT_STACK_WITHOUT_MALLOC_F
+	bool "Do not reserve malloc space on initial stack"
+	default n
+	help
+	  Enable this option if you don't want to reserve malloc space on
+	  initial stack. This is useful if the initial stack can't hold large
+	  malloc space. Platform should set the malloc_base later when DRAM is
+	  ready to use.
+
+config SPL_INIT_STACK_WITHOUT_MALLOC_F
+	bool "Do not reserve malloc space on initial stack in SPL"
+	default n
+	help
+	  Enable this option if you don't want to reserve malloc space on
+	  initial stack. This is useful if the initial stack can't hold large
+	  malloc space. Platform should set the malloc_base later when DRAM is
+	  ready to use.
+
+config SPL_LOADER_SUPPORT
+	bool
+	default n
+	help
+	  Enable this option if you want to use SPL loaders without DM enabled.
+
 endmenu
 
 menu "OS boot interface"
@@ -389,6 +444,15 @@
 	  lowlevel_init. Thus lowlevel_init does not need to be implemented
 	  in assembler.
 
+config MIPS_SRAM_INIT
+	bool
+	default n
+	depends on MIPS_INIT_STACK_IN_SRAM
+	help
+	  Select this if the SRAM for initial stack needs to be initialized
+	  before it can be used. If enabled, a function mips_sram_init() will
+	  be called just before setup_stack_gd.
+
 config SYS_DCACHE_SIZE
 	int
 	default 0
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index 1d21b23..6de9a2f 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -59,7 +59,8 @@
 		sp, sp, GD_SIZE		# reserve space for gd
 	and	sp, sp, t0		# force 16 byte alignment
 	move	k0, sp			# save gd pointer
-#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+#if CONFIG_VAL(SYS_MALLOC_F_LEN) && \
+    !CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F)
 	li	t2, CONFIG_VAL(SYS_MALLOC_F_LEN)
 	PTR_SUBU \
 		sp, sp, t2		# reserve space for early malloc
@@ -71,10 +72,12 @@
 	move	t0, k0
 1:
 	PTR_S	zero, 0(t0)
+	PTR_ADDIU t0, PTRSIZE
 	blt	t0, t1, 1b
-	 PTR_ADDIU t0, PTRSIZE
+	 nop
 
-#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+#if CONFIG_VAL(SYS_MALLOC_F_LEN) && \
+    !CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F)
 	PTR_S	sp, GD_MALLOC_BASE(k0)	# gd->malloc_base offset
 #endif
 	.endm
@@ -216,6 +219,13 @@
 #endif
 
 #ifdef CONFIG_MIPS_INIT_STACK_IN_SRAM
+#ifdef CONFIG_MIPS_SRAM_INIT
+	/* Initialize the SRAM first */
+	PTR_LA	t9, mips_sram_init
+	jalr	t9
+	 nop
+#endif
+
 	/* Set up initial stack and global data */
 	setup_stack_gd
 
diff --git a/arch/mips/cpu/u-boot-spl.lds b/arch/mips/cpu/u-boot-spl.lds
index d08d622..28ea4f2 100644
--- a/arch/mips/cpu/u-boot-spl.lds
+++ b/arch/mips/cpu/u-boot-spl.lds
@@ -27,7 +27,7 @@
 		*(SORT_BY_ALIGNMENT(.sdata*))
 	} > .spl_mem
 
-#ifdef CONFIG_SPL_DM
+#if defined(CONFIG_SPL_DM) || defined(CONFIG_SPL_LOADER_SUPPORT)
 	. = ALIGN(4);
 	.u_boot_list : {
 		KEEP(*(SORT(.u_boot_list*)));
@@ -37,6 +37,8 @@
 	. = ALIGN(4);
 	__image_copy_end = .;
 
+	_image_binary_end = .;
+
 	.bss (NOLOAD) : {
 		__bss_start = .;
 		*(.bss*)
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index c9d7559..f711e9f 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -17,11 +17,13 @@
 dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb
 dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb
 dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
+dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb
 dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
 dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
 dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb
 dtb-$(CONFIG_BOARD_SFR_NB4_SER) += sfr,nb4-ser.dtb
 dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
+dtb-$(CONFIG_BOARD_VOCORE2) += vocore_vocore2.dtb
 dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
 dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb
 dtb-$(CONFIG_SOC_OCELOT) += ocelot_pcb120.dtb ocelot_pcb123.dtb
diff --git a/arch/mips/dts/mediatek,mt7628-rfb.dts b/arch/mips/dts/mediatek,mt7628-rfb.dts
new file mode 100644
index 0000000..6ff36da
--- /dev/null
+++ b/arch/mips/dts/mediatek,mt7628-rfb.dts
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+/dts-v1/;
+
+#include "mt7628a.dtsi"
+
+/ {
+	compatible = "mediatek,mt7628-rfb", "ralink,mt7628a-soc";
+	model = "MediaTek MT7628 RFB";
+
+	aliases {
+		serial0 = &uart0;
+		spi0 = &spi0;
+	};
+
+	chosen {
+		stdout-path = &uart0;
+	};
+};
+
+&pinctrl {
+	state_default: pin_state {
+		pleds {
+			groups = "p0led", "p1led", "p2led", "p3led", "p4led";
+			function = "led";
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+	num-cs = <2>;
+
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <25000000>;
+		reg = <0>;
+	};
+};
+
+&eth {
+	mediatek,wan-port = <0>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&ephy_router_mode>;
+};
+
+&mmc {
+	bus-width = <4>;
+	cap-sd-highspeed;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&sd_router_mode>;
+
+	status = "okay";
+};
diff --git a/arch/mips/dts/mt7628-u-boot.dtsi b/arch/mips/dts/mt7628-u-boot.dtsi
new file mode 100644
index 0000000..eea5dc6
--- /dev/null
+++ b/arch/mips/dts/mt7628-u-boot.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+&palmbus {
+	u-boot,dm-pre-reloc;
+};
+
+&reboot {
+	u-boot,dm-pre-reloc;
+};
+
+&clkctrl {
+	u-boot,dm-pre-reloc;
+};
+
+&rstctrl {
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+	u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+};
+
+&uart1 {
+	u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi
index 76a80c8..6baa63a 100644
--- a/arch/mips/dts/mt7628a.dtsi
+++ b/arch/mips/dts/mt7628a.dtsi
@@ -33,7 +33,7 @@
 		#clock-cells = <0>;
 	};
 
-	palmbus@10000000 {
+	palmbus: palmbus@10000000 {
 		compatible = "palmbus", "simple-bus";
 		reg = <0x10000000 0x200000>;
 		ranges = <0x0 0x10000000 0x1FFFFF>;
@@ -46,11 +46,11 @@
 			reg = <0x0 0x100>;
 		};
 
-		syscon-reboot {
-			compatible = "syscon-reboot";
-			regmap = <&sysc>;
-			offset = <0x34>;
-			mask = <0x1>;
+		reboot: resetctl-reboot {
+			compatible = "resetctl-reboot";
+
+			resets = <&rstctrl MT7628_SYS_RST>;
+			reset-names = "sysreset";
 		};
 
 		clkctrl: clkctrl@0x2c {
@@ -110,6 +110,11 @@
 				function = "uart2";
 			};
 
+			uart2_pwm_pins: uart2_pwm_pins {
+				groups = "spis";
+				function = "pwm_uart2";
+			};
+
 			i2c_pins: i2c_pins {
 				groups = "i2c";
 				function = "i2c";
diff --git a/arch/mips/dts/vocore_vocore2.dts b/arch/mips/dts/vocore_vocore2.dts
new file mode 100644
index 0000000..3502e4b
--- /dev/null
+++ b/arch/mips/dts/vocore_vocore2.dts
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Mauro Condarelli <mc5686@mclink.it>
+ */
+
+/dts-v1/;
+
+#include "mt7628a.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	compatible = "vocore,vocore2", "ralink,mt7628a-soc";
+	model = "VoCore2";
+
+	aliases {
+		serial0 = &uart2;
+		spi0 = &spi0;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x08000000>;
+	};
+	leds {
+		compatible = "gpio-leds";
+
+		power {
+			label = "vocore:power";
+			gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
+
+	chosen {
+		bootargs = "console=ttyS2,115200";
+		stdout-path = &uart2;
+	};
+};
+
+&pinctrl {
+	state_default: pin_state {
+		p0led {
+			groups = "p0led_a";
+			function = "led";
+		};
+	};
+};
+
+&uart2 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2_pwm_pins>;
+};
+
+&spi0 {
+	status = "okay";
+	nor0: spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <25000000>;
+		reg = <0>;
+	};
+};
+
+&eth {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&ephy_iot_mode>;
+	mediatek,poll-link-phy = <0>;
+};
+
+&mmc {
+	status = "okay";
+
+	bus-width = <4>;
+	max-frequency = <48000000>;
+	cap-sd-highspeed;
+	cap-mmc-highspeed;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&sd_iot_mode>;
+};
diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h
index 7b4ad08..4c30fab 100644
--- a/arch/mips/include/asm/global_data.h
+++ b/arch/mips/include/asm/global_data.h
@@ -27,6 +27,9 @@
 #ifdef CONFIG_MIPS_L2_CACHE
 	unsigned short l2_line_size;
 #endif
+#ifdef CONFIG_ARCH_MTMIPS
+	unsigned long timer_freq;
+#endif
 };
 
 #include <asm-generic/global_data.h>
diff --git a/arch/mips/include/asm/u-boot-mips.h b/arch/mips/include/asm/u-boot-mips.h
index 88438b9..8b37cc4 100644
--- a/arch/mips/include/asm/u-boot-mips.h
+++ b/arch/mips/include/asm/u-boot-mips.h
@@ -9,4 +9,6 @@
 
 int arch_misc_init(void);
 
+void trap_restore(void);
+
 #endif /* _U_BOOT_MIPS_H_ */
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index 24a72d9..9ee1fcb 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -12,5 +12,6 @@
 
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-$(CONFIG_CMD_GO) += boot.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
 
 lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index 8c0d767..f1db6d2 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -294,6 +294,9 @@
 	bootstage_report();
 #endif
 
+	if (CONFIG_IS_ENABLED(RESTORE_EXCEPTION_VECTOR_BASE))
+		trap_restore();
+
 	if (images->ft_len)
 		kernel(-2, (ulong)images->ft_addr, 0, 0);
 	else
diff --git a/arch/mips/lib/spl.c b/arch/mips/lib/spl.c
new file mode 100644
index 0000000..7ba3e53
--- /dev/null
+++ b/arch/mips/lib/spl.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <spl.h>
+
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+	typedef void __noreturn (*image_entry_noargs_t)(void);
+	image_entry_noargs_t image_entry =
+		(image_entry_noargs_t)spl_image->entry_point;
+
+	/* Flush cache before jumping to application */
+	flush_cache((unsigned long)spl_image->load_addr, spl_image->size);
+
+	debug("image entry point: 0x%lx\n", spl_image->entry_point);
+	image_entry();
+}
diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c
index b8568c0..8fff754 100644
--- a/arch/mips/lib/traps.c
+++ b/arch/mips/lib/traps.c
@@ -20,6 +20,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static unsigned long saved_ebase;
+
 static void show_regs(const struct pt_regs *regs)
 {
 	const int field = 2 * sizeof(unsigned long);
@@ -102,7 +104,24 @@
 	set_handler(0x180, &except_vec3_generic, 0x80);
 	set_handler(0x280, &except_vec_ejtag_debug, 0x80);
 
+	saved_ebase = read_c0_ebase() & 0xfffff000;
+
 	write_c0_ebase(ebase);
 	clear_c0_status(ST0_BEV);
 	execution_hazard_barrier();
 }
+
+void trap_restore(void)
+{
+	set_c0_status(ST0_BEV);
+	execution_hazard_barrier();
+
+#ifdef CONFIG_OVERRIDE_EXCEPTION_VECTOR_BASE
+	write_c0_ebase(CONFIG_NEW_EXCEPTION_VECTOR_BASE & 0xfffff000);
+#else
+	write_c0_ebase(saved_ebase);
+#endif
+
+	clear_c0_status(ST0_BEV);
+	execution_hazard_barrier();
+}
diff --git a/arch/mips/mach-mtmips/Kconfig b/arch/mips/mach-mtmips/Kconfig
index c8dcf19..737de2c 100644
--- a/arch/mips/mach-mtmips/Kconfig
+++ b/arch/mips/mach-mtmips/Kconfig
@@ -7,14 +7,52 @@
 config SYS_SOC
 	default "mt7628" if SOC_MT7628
 
+config SYS_DCACHE_SIZE
+	default 32768
+
+config SYS_DCACHE_LINE_SIZE
+	default 32
+
+config SYS_ICACHE_SIZE
+	default 65536
+
+config SYS_ICACHE_LINE_SIZE
+	default 32
+
+config SYS_TEXT_BASE
+	default 0x9c000000 if !SPL
+	default 0x80200000 if SPL
+
+config SPL_TEXT_BASE
+	default 0x9c000000
+
+config SPL_PAYLOAD
+	default "u-boot-lzma.img" if SPL_LZMA
+
+config BUILD_TARGET
+	default "u-boot-with-spl.bin" if SPL
+
 choice
 	prompt "MediaTek MIPS SoC select"
 
 config SOC_MT7628
 	bool "MT7628"
 	select MIPS_L1_CACHE_SHIFT_5
+	select MIPS_INIT_STACK_IN_SRAM
+	select MIPS_SRAM_INIT
+	select SYS_MIPS_CACHE_INIT_RAM_LOAD
 	select PINCTRL_MT7628
 	select MTK_SERIAL
+	select SYSRESET_RESETCTL
+	select SPL_SEPARATE_BSS if SPL
+	select SPL_INIT_STACK_WITHOUT_MALLOC_F if SPL
+	select SPL_LOADER_SUPPORT if SPL
+	select SPL_OF_CONTROL if SPL_DM
+	select SPL_SIMPLE_BUS if SPL_DM
+	select SPL_DM_SERIAL if SPL_DM
+	select SPL_CLK if SPL_DM && SPL_SERIAL_SUPPORT
+	select SPL_SYSRESET if SPL_DM
+	select SPL_OF_LIBFDT if SPL_OF_CONTROL
 	help
 	  This supports MediaTek MT7628/MT7688.
 
@@ -27,7 +65,6 @@
 	bool "GARDENA smart Gateway"
 	depends on SOC_MT7628
 	select BOARD_LATE_INIT
-	select SUPPORTS_BOOT_RAM
 	help
 	  GARDENA smart Gateway boards have a MT7688 SoC with 128 MiB of RAM
 	  and 8 MiB of flash (SPI NOR) and additional SPI NAND storage.
@@ -35,7 +72,6 @@
 config BOARD_LINKIT_SMART_7688
 	bool "LinkIt Smart 7688"
 	depends on SOC_MT7628
-	select SUPPORTS_BOOT_RAM
 	help
 	  Seeed LinkIt Smart 7688 boards have a MT7688 SoC with 128 MiB of RAM
 	  and 32 MiB of flash (SPI).
@@ -43,96 +79,36 @@
 	  ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and
 	  a MT7688 (PCIe).
 
-endchoice
-
-choice
-	prompt "Boot mode"
-
-config BOOT_RAM
-	bool "RAM boot"
-	depends on SUPPORTS_BOOT_RAM
-	help
-	  This builds an image that is linked to a RAM address. It can be used
-	  for booting from CFE via TFTP using an ELF image, but it can also be
-	  booted from RAM by other bootloaders using a BIN image.
-
-config BOOT_ROM
-	bool "ROM boot"
-	depends on SUPPORTS_BOOT_RAM
-	help
-	  This builds an image that is linked to a ROM address. It can be
-	  used as main bootloader image which is programmed onto the onboard
-	  flash storage (SPI NOR).
-
-endchoice
-
-choice
-	prompt "DDR2 size"
-
-config ONBOARD_DDR2_SIZE_256MBIT
-	bool "256MBit (32MByte) total size"
-	depends on BOOT_ROM
-	help
-	  Use 256MBit (32MByte) of DDR total size
-
-config ONBOARD_DDR2_SIZE_512MBIT
-	bool "512MBit (64MByte) total size"
-	depends on BOOT_ROM
-	help
-	  Use 512MBit (64MByte) of DDR total size
-
-config ONBOARD_DDR2_SIZE_1024MBIT
-	bool "1024MBit (128MByte) total size"
-	depends on BOOT_ROM
-	help
-	  Use 1024MBit (128MByte) of DDR total size
-
-config ONBOARD_DDR2_SIZE_2048MBIT
-	bool "2048MBit (256MByte) total size"
-	depends on BOOT_ROM
-	help
-	  Use 2048MBit (256MByte) of DDR total size
-
-endchoice
-
-choice
-	prompt "DDR2 chip width"
-
-config ONBOARD_DDR2_CHIP_WIDTH_8BIT
-	bool "8bit DDR chip width"
-	depends on BOOT_ROM
+config BOARD_MT7628_RFB
+	bool "MediaTek MT7628 RFB"
+	depends on SOC_MT7628
 	help
-	  Use DDR chips with 8bit width
+	  The reference design of MT7628. The board has 128 MiB DDR2, 8 MiB
+	  SPI-NOR flash, 1 built-in switch with 5 ports, 1 UART, 1 USB host,
+	  1 SDXC, 1 PCIe socket and JTAG pins.
 
-config ONBOARD_DDR2_CHIP_WIDTH_16BIT
-	bool "16bit DDR chip width"
-	depends on BOOT_ROM
+config BOARD_VOCORE2
+	bool "VoCore2"
+	depends on SOC_MT7628
+	select SPL_SERIAL_SUPPORT
+	select SPL_UART2_SPIS_PINMUX
 	help
-	  Use DDR chips with 16bit width
+	  VoCore VoCore2 board has a MT7628 SoC with 128 MiB of RAM
+	  and 16 MiB of flash (SPI).
 
 endchoice
 
-choice
-	prompt "DDR2 bus width"
-
-config ONBOARD_DDR2_BUS_WIDTH_16BIT
-	bool "16bit DDR bus width"
-	depends on BOOT_ROM
+config SPL_UART2_SPIS_PINMUX
+	bool "Use alternative pinmux for UART2 in SPL stage"
+	depends on SPL_SERIAL_SUPPORT
+	default n
 	help
-	  Use 16bit DDR bus width
-
-config ONBOARD_DDR2_BUS_WIDTH_32BIT
-	bool "32bit DDR bus width"
-	depends on BOOT_ROM
-	help
-	  Use 32bit DDR bus width
-
-endchoice
-
-config SUPPORTS_BOOT_RAM
-	bool
+	  Select this if the UART2 of your board is connected to GPIO 16/17
+	  (shared with SPIS) rather than the usual GPIO 20/21.
 
 source "board/gardena/smart-gateway-mt7688/Kconfig"
+source "board/mediatek/mt7628/Kconfig"
 source "board/seeed/linkit-smart-7688/Kconfig"
+source "board/vocore/vocore2/Kconfig"
 
 endmenu
diff --git a/arch/mips/mach-mtmips/Makefile b/arch/mips/mach-mtmips/Makefile
index 1f3e65e..a7e6a66 100644
--- a/arch/mips/mach-mtmips/Makefile
+++ b/arch/mips/mach-mtmips/Makefile
@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 obj-y += cpu.o
+obj-y += ddr_init.o
+obj-y += ddr_cal.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
 
-ifndef CONFIG_SKIP_LOWLEVEL_INIT
-obj-y += ddr_calibrate.o
-obj-y += lowlevel_init.o
-endif
+obj-$(CONFIG_SOC_MT7628) += mt7628/
diff --git a/arch/mips/mach-mtmips/cpu.c b/arch/mips/mach-mtmips/cpu.c
index 8976ef5..459a967 100644
--- a/arch/mips/mach-mtmips/cpu.c
+++ b/arch/mips/mach-mtmips/cpu.c
@@ -4,69 +4,17 @@
  */
 
 #include <common.h>
-#include <dm.h>
-#include <init.h>
 #include <malloc.h>
-#include <ram.h>
-#include <wdt.h>
-#include <asm/io.h>
 #include <linux/io.h>
 #include <linux/sizes.h>
-#include "mt76xx.h"
 
-#define STR_LEN			6
-
-#ifdef CONFIG_BOOT_ROM
-int mach_cpu_init(void)
-{
-	ddr_calibrate();
-
-	return 0;
-}
-#endif
+DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
 {
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
 	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_256M);
-
-	return 0;
-}
-
-int print_cpuinfo(void)
-{
-	static const char * const boot_str[] = { "PLL (3-Byte SPI Addr)",
-						 "PLL (4-Byte SPI Addr)",
-						 "XTAL (3-Byte SPI Addr)",
-						 "XTAL (4-Byte SPI Addr)" };
-	const void *blob = gd->fdt_blob;
-	void __iomem *sysc_base;
-	char buf[STR_LEN + 1];
-	fdt_addr_t base;
-	fdt_size_t size;
-	char *str;
-	int node;
-	u32 val;
-
-	/* Get system controller base address */
-	node = fdt_node_offset_by_compatible(blob, -1, "ralink,mt7620a-sysc");
-	if (node < 0)
-		return -FDT_ERR_NOTFOUND;
-
-	base = fdtdec_get_addr_size_auto_noparent(blob, node, "reg",
-						  0, &size, true);
-	if (base == FDT_ADDR_T_NONE)
-		return -EINVAL;
-
-	sysc_base = ioremap_nocache(base, size);
-
-	str = (char *)sysc_base + MT76XX_CHIPID_OFFS;
-	snprintf(buf, STR_LEN + 1, "%s", str);
-	val = readl(sysc_base + MT76XX_CHIP_REV_ID_OFFS);
-	printf("CPU:   %-*s Rev %ld.%ld - ", STR_LEN, buf,
-	       (val & GENMASK(11, 8)) >> 8, val & GENMASK(3, 0));
-
-	val = (readl(sysc_base + MT76XX_SYSCFG0_OFFS) & GENMASK(3, 1)) >> 1;
-	printf("Boot from %s\n", boot_str[val]);
+#endif
 
 	return 0;
 }
diff --git a/arch/mips/mach-mtmips/ddr_cal.c b/arch/mips/mach-mtmips/ddr_cal.c
new file mode 100644
index 0000000..71a53c3
--- /dev/null
+++ b/arch/mips/mach-mtmips/ddr_cal.c
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ *
+ * Author:  Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <common.h>
+#include <asm/addrspace.h>
+#include <asm/cacheops.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <mach/mc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define COARSE_MIN_START	6
+#define FINE_MIN_START		15
+#define COARSE_MAX_START	7
+#define FINE_MAX_START		0
+
+#define NUM_OF_CACHELINE	128
+#define TEST_PAT_SIZE		(NUM_OF_CACHELINE * CONFIG_SYS_CACHELINE_SIZE)
+
+#define INIT_DQS_VAL		((7 << DQS1_DELAY_COARSE_TUNING_S) | \
+				(4 << DQS1_DELAY_FINE_TUNING_S) | \
+				(7 << DQS0_DELAY_COARSE_TUNING_S) | \
+				(4 << DQS0_DELAY_FINE_TUNING_S))
+
+static inline void pref_op(int op, const volatile void *addr)
+{
+	__asm__ __volatile__("pref %0, 0(%1)" : : "i" (op), "r" (addr));
+}
+
+static inline bool dqs_test_error(void __iomem *memc, u32 memsize, u32 dqsval,
+				  u32 bias)
+{
+	u32 *nca, *ca;
+	u32 off;
+	int i;
+
+	for (off = 0; off < memsize - TEST_PAT_SIZE; off += (memsize >> 6)) {
+		nca = (u32 *)KSEG1ADDR(off);
+		ca = (u32 *)KSEG0ADDR(off);
+
+		writel(INIT_DQS_VAL, memc + MEMCTL_DDR_DQS_DLY_REG);
+		wmb();
+
+		for (i = 0; i < TEST_PAT_SIZE / sizeof(u32); i++)
+			ca[i] = 0x1f1f1f1f;
+
+		for (i = 0; i < TEST_PAT_SIZE / sizeof(u32); i++)
+			nca[i] = (u32)nca + i + bias;
+
+		writel(dqsval, memc + MEMCTL_DDR_DQS_DLY_REG);
+		wmb();
+
+		for (i = 0; i < TEST_PAT_SIZE; i += CONFIG_SYS_CACHELINE_SIZE)
+			mips_cache(HIT_INVALIDATE_D, (u8 *)ca + i);
+		wmb();
+
+		for (i = 0; i < TEST_PAT_SIZE; i += CONFIG_SYS_CACHELINE_SIZE)
+			pref_op(0, (u8 *)ca + i);
+
+		for (i = 0; i < TEST_PAT_SIZE / sizeof(u32); i++) {
+			if (ca[i] != (u32)nca + i + bias)
+				return true;
+		}
+	}
+
+	return false;
+}
+
+static inline int dqs_find_max(void __iomem *memc, u32 memsize, int initval,
+			       int maxval, int shift, u32 regval)
+{
+	int fieldval;
+	u32 dqsval;
+
+	for (fieldval = initval; fieldval <= maxval; fieldval++) {
+		dqsval = regval | (fieldval << shift);
+		if (dqs_test_error(memc, memsize, dqsval, 3))
+			return max(fieldval - 1, initval);
+	}
+
+	return maxval;
+}
+
+static inline int dqs_find_min(void __iomem *memc, u32 memsize, int initval,
+			       int minval, int shift, u32 regval)
+{
+	int fieldval;
+	u32 dqsval;
+
+	for (fieldval = initval; fieldval >= minval; fieldval--) {
+		dqsval = regval | (fieldval << shift);
+		if (dqs_test_error(memc, memsize, dqsval, 1))
+			return min(fieldval + 1, initval);
+	}
+
+	return minval;
+}
+
+void ddr_calibrate(void __iomem *memc, u32 memsize, u32 bw)
+{
+	u32 dqs_coarse_min, dqs_coarse_max, dqs_coarse_val;
+	u32 dqs_fine_min, dqs_fine_max, dqs_fine_val;
+	u32 dqs_coarse_min_limit, dqs_fine_min_limit;
+	u32 dlls, dqs_dll, ddr_cfg2_reg;
+	u32 dqs_dly_tmp, dqs_dly, test_dqs, shift;
+	u32 rem, mask;
+	int i;
+
+	/* Disable Self-refresh */
+	clrbits_32(memc + MEMCTL_DDR_SELF_REFRESH_REG, SR_AUTO_EN);
+
+	/* Save DDR_CFG2 and modify its DQS gating window */
+	ddr_cfg2_reg = readl(memc + MEMCTL_DDR_CFG2_REG);
+	mask = DQS0_GATING_WINDOW_M;
+	if (bw == IND_SDRAM_WIDTH_16BIT)
+		mask |= DQS1_GATING_WINDOW_M;
+	clrbits_32(memc + MEMCTL_DDR_CFG2_REG, mask);
+
+	/* Get minimum available DQS value */
+	dlls = readl(memc + MEMCTL_DLL_DBG_REG);
+	dlls = (dlls & MST_DLY_SEL_M) >> MST_DLY_SEL_S;
+
+	dqs_dll = dlls >> 4;
+	if (dqs_dll <= 8)
+		dqs_coarse_min_limit = 8 - dqs_dll;
+	else
+		dqs_coarse_min_limit = 0;
+
+	dqs_dll = dlls & 0xf;
+	if (dqs_dll <= 8)
+		dqs_fine_min_limit = 8 - dqs_dll;
+	else
+		dqs_fine_min_limit = 0;
+
+	/* Initial DQS register value */
+	dqs_dly = INIT_DQS_VAL;
+
+	/* Calibrate DQS0 and/or DQS1 */
+	for (i = 0; i < bw; i++) {
+		shift = i * 8;
+		dqs_dly &= ~(0xff << shift);
+
+		/* Find maximum DQS coarse-grain */
+		dqs_dly_tmp = dqs_dly | (0xf << shift);
+		dqs_coarse_max = dqs_find_max(memc, memsize, COARSE_MAX_START,
+					      0xf, 4 + shift, dqs_dly_tmp);
+
+		/* Find maximum DQS fine-grain */
+		dqs_dly_tmp = dqs_dly | (dqs_coarse_max << (4 + shift));
+		test_dqs = dqs_find_max(memc, memsize, FINE_MAX_START, 0xf,
+					shift, dqs_dly_tmp);
+
+		if (test_dqs == FINE_MAX_START) {
+			dqs_coarse_max--;
+			dqs_fine_max = 0xf;
+		} else {
+			dqs_fine_max = test_dqs - 1;
+		}
+
+		/* Find minimum DQS coarse-grain */
+		dqs_dly_tmp = dqs_dly;
+		dqs_coarse_min = dqs_find_min(memc, memsize, COARSE_MIN_START,
+					      dqs_coarse_min_limit, 4 + shift,
+					      dqs_dly_tmp);
+
+		/* Find minimum DQS fine-grain */
+		dqs_dly_tmp = dqs_dly | (dqs_coarse_min << (4 + shift));
+		test_dqs = dqs_find_min(memc, memsize, FINE_MIN_START,
+					dqs_fine_min_limit, shift, dqs_dly_tmp);
+
+		if (test_dqs == FINE_MIN_START + 1) {
+			dqs_coarse_min++;
+			dqs_fine_min = 0;
+		} else {
+			dqs_fine_min = test_dqs;
+		}
+
+		/* Calculate central DQS coarse/fine value */
+		dqs_coarse_val = (dqs_coarse_max + dqs_coarse_min) >> 1;
+		rem = (dqs_coarse_max + dqs_coarse_min) % 2;
+
+		dqs_fine_val = (rem * 4) + ((dqs_fine_max + dqs_fine_min) >> 1);
+		if (dqs_fine_val >= 0x10) {
+			dqs_coarse_val++;
+			dqs_fine_val -= 8;
+		}
+
+		/* Save current DQS value */
+		dqs_dly |= ((dqs_coarse_val << 4) | dqs_fine_val) << shift;
+	}
+
+	/* Set final DQS value */
+	writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG);
+
+	/* Restore DDR_CFG2 */
+	writel(ddr_cfg2_reg, memc + MEMCTL_DDR_CFG2_REG);
+
+	/* Enable Self-refresh */
+	setbits_32(memc + MEMCTL_DDR_SELF_REFRESH_REG, SR_AUTO_EN);
+}
diff --git a/arch/mips/mach-mtmips/ddr_calibrate.c b/arch/mips/mach-mtmips/ddr_calibrate.c
deleted file mode 100644
index 3cd4408..0000000
--- a/arch/mips/mach-mtmips/ddr_calibrate.c
+++ /dev/null
@@ -1,309 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Stefan Roese <sr@denx.de>
- *
- * This code is mostly based on the code extracted from this MediaTek
- * github repository:
- *
- * https://github.com/MediaTek-Labs/linkit-smart-uboot.git
- *
- * I was not able to find a specific license or other developers
- * copyrights here, so I can't add them here.
- *
- * Most functions in this file are copied from the MediaTek U-Boot
- * repository. Without any documentation, it was impossible to really
- * implement this differently. So its mostly a cleaned-up version of
- * the original code, with only support for the MT7628 / MT7688 SoC.
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <linux/io.h>
-#include <asm/cacheops.h>
-#include <asm/io.h>
-#include "mt76xx.h"
-
-#define NUM_OF_CACHELINE	128
-#define MIN_START		6
-#define MIN_FINE_START		0xf
-#define MAX_START		7
-#define MAX_FINE_START		0x0
-
-#define CPU_FRAC_DIV		1
-
-#if defined(CONFIG_ONBOARD_DDR2_SIZE_256MBIT)
-#define DRAM_BUTTOM 0x02000000
-#endif
-#if defined(CONFIG_ONBOARD_DDR2_SIZE_512MBIT)
-#define DRAM_BUTTOM 0x04000000
-#endif
-#if defined(CONFIG_ONBOARD_DDR2_SIZE_1024MBIT)
-#define DRAM_BUTTOM 0x08000000
-#endif
-#if defined(CONFIG_ONBOARD_DDR2_SIZE_2048MBIT)
-#define DRAM_BUTTOM 0x10000000
-#endif
-
-static inline void cal_memcpy(void *src, void *dst, u32 size)
-{
-	u8 *psrc = (u8 *)src;
-	u8 *pdst = (u8 *)dst;
-	int i;
-
-	for (i = 0; i < size; i++, psrc++, pdst++)
-		*pdst = *psrc;
-}
-
-static inline void cal_memset(void *src, u8 pat, u32 size)
-{
-	u8 *psrc = (u8 *)src;
-	int i;
-
-	for (i = 0; i < size; i++, psrc++)
-		*psrc = pat;
-}
-
-#define pref_op(hint, addr)						\
-	__asm__ __volatile__(						\
-		".set	push\n"						\
-		".set	noreorder\n"					\
-		"pref	%0, %1\n"					\
-		".set	pop\n"						\
-		:							\
-		: "i" (hint), "R" (*(u8 *)(addr)))
-
-static inline void cal_patgen(u32 start_addr, u32 size, u32 bias)
-{
-	u32 *addr = (u32 *)start_addr;
-	int i;
-
-	for (i = 0; i < size; i++)
-		addr[i] = start_addr + i + bias;
-}
-
-static inline int test_loop(int k, int dqs, u32 test_dqs, u32 *coarse_dqs,
-			    u32 offs, u32 pat, u32 val)
-{
-	u32 nc_addr;
-	u32 *c_addr;
-	int i;
-
-	for (nc_addr = 0xa0000000;
-	     nc_addr < (0xa0000000 + DRAM_BUTTOM - NUM_OF_CACHELINE * 32);
-	     nc_addr += (DRAM_BUTTOM >> 6) + offs) {
-		writel(0x00007474, (void *)MT76XX_MEMCTRL_BASE + 0x64);
-		wmb();		/* Make sure store if finished */
-
-		c_addr = (u32 *)(nc_addr & 0xdfffffff);
-		cal_memset(((u8 *)c_addr), 0x1F, NUM_OF_CACHELINE * 32);
-		cal_patgen(nc_addr, NUM_OF_CACHELINE * 8, pat);
-
-		if (dqs > 0)
-			writel(0x00000074 |
-			       (((k == 1) ? coarse_dqs[dqs] : test_dqs) << 12) |
-			       (((k == 0) ? val : test_dqs) << 8),
-			       (void *)MT76XX_MEMCTRL_BASE + 0x64);
-		else
-			writel(0x00007400 |
-			       (((k == 1) ? coarse_dqs[dqs] : test_dqs) << 4) |
-			       (((k == 0) ? val : test_dqs) << 0),
-			       (void *)MT76XX_MEMCTRL_BASE + 0x64);
-		wmb();		/* Make sure store if finished */
-
-		invalidate_dcache_range((u32)c_addr,
-					(u32)c_addr +
-					NUM_OF_CACHELINE * 32);
-		wmb();		/* Make sure store if finished */
-
-		for (i = 0; i < NUM_OF_CACHELINE * 8; i++) {
-			if (i % 8 == 0)
-				pref_op(0, &c_addr[i]);
-		}
-
-		for (i = 0; i < NUM_OF_CACHELINE * 8; i++) {
-			if (c_addr[i] != nc_addr + i + pat)
-				return -1;
-		}
-	}
-
-	return 0;
-}
-
-void ddr_calibrate(void)
-{
-	u32 min_coarse_dqs[2];
-	u32 max_coarse_dqs[2];
-	u32 min_fine_dqs[2];
-	u32 max_fine_dqs[2];
-	u32 coarse_dqs[2];
-	u32 fine_dqs[2];
-	int reg = 0, ddr_cfg2_reg;
-	int flag;
-	int i, k;
-	int dqs = 0;
-	u32 min_coarse_dqs_bnd, min_fine_dqs_bnd, coarse_dqs_dll, fine_dqs_dll;
-	u32 val;
-	u32 fdiv = 0, frac = 0;
-
-	/* Setup clock to run at full speed */
-	val = readl((void *)MT76XX_DYN_CFG0_REG);
-	fdiv = (u32)((val >> 8) & 0x0F);
-	if (CPU_FRAC_DIV < 1 || CPU_FRAC_DIV > 10)
-		frac = val & 0x0f;
-	else
-		frac = CPU_FRAC_DIV;
-
-	while (frac < fdiv) {
-		val = readl((void *)MT76XX_DYN_CFG0_REG);
-		fdiv = (val >> 8) & 0x0f;
-		fdiv--;
-		val &= ~(0x0f << 8);
-		val |= (fdiv << 8);
-		writel(val, (void *)MT76XX_DYN_CFG0_REG);
-		udelay(500);
-		val = readl((void *)MT76XX_DYN_CFG0_REG);
-		fdiv = (val >> 8) & 0x0f;
-	}
-
-	clrbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x10, BIT(4));
-	ddr_cfg2_reg = readl((void *)MT76XX_MEMCTRL_BASE + 0x48);
-	clrbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x48,
-		     (0x3 << 28) | (0x3 << 26));
-
-	min_coarse_dqs[0] = MIN_START;
-	min_coarse_dqs[1] = MIN_START;
-	min_fine_dqs[0] = MIN_FINE_START;
-	min_fine_dqs[1] = MIN_FINE_START;
-	max_coarse_dqs[0] = MAX_START;
-	max_coarse_dqs[1] = MAX_START;
-	max_fine_dqs[0] = MAX_FINE_START;
-	max_fine_dqs[1] = MAX_FINE_START;
-	dqs = 0;
-
-	/* Add by KP, DQS MIN boundary */
-	reg = readl((void *)MT76XX_MEMCTRL_BASE + 0x20);
-	coarse_dqs_dll = (reg & 0xf00) >> 8;
-	fine_dqs_dll = (reg & 0xf0) >> 4;
-	if (coarse_dqs_dll <= 8)
-		min_coarse_dqs_bnd = 8 - coarse_dqs_dll;
-	else
-		min_coarse_dqs_bnd = 0;
-
-	if (fine_dqs_dll <= 8)
-		min_fine_dqs_bnd = 8 - fine_dqs_dll;
-	else
-		min_fine_dqs_bnd = 0;
-	/* DQS MIN boundary */
-
-DQS_CAL:
-
-	for (k = 0; k < 2; k++) {
-		u32 test_dqs;
-
-		if (k == 0)
-			test_dqs = MAX_START;
-		else
-			test_dqs = MAX_FINE_START;
-
-		do {
-			flag = test_loop(k, dqs, test_dqs, max_coarse_dqs,
-					 0x400, 0x3, 0xf);
-			if (flag == -1)
-				break;
-
-			test_dqs++;
-		} while (test_dqs <= 0xf);
-
-		if (k == 0) {
-			max_coarse_dqs[dqs] = test_dqs;
-		} else {
-			test_dqs--;
-
-			if (test_dqs == MAX_FINE_START - 1) {
-				max_coarse_dqs[dqs]--;
-				max_fine_dqs[dqs] = 0xf;
-			} else {
-				max_fine_dqs[dqs] = test_dqs;
-			}
-		}
-	}
-
-	for (k = 0; k < 2; k++) {
-		u32 test_dqs;
-
-		if (k == 0)
-			test_dqs = MIN_START;
-		else
-			test_dqs = MIN_FINE_START;
-
-		do {
-			flag = test_loop(k, dqs, test_dqs, min_coarse_dqs,
-					 0x480, 0x1, 0x0);
-			if (k == 0) {
-				if (flag == -1 ||
-				    test_dqs == min_coarse_dqs_bnd)
-					break;
-
-				test_dqs--;
-
-				if (test_dqs < min_coarse_dqs_bnd)
-					break;
-			} else {
-				if (flag == -1) {
-					test_dqs++;
-					break;
-				} else if (test_dqs == min_fine_dqs_bnd) {
-					break;
-				}
-
-				test_dqs--;
-
-				if (test_dqs < min_fine_dqs_bnd)
-					break;
-			}
-		} while (test_dqs >= 0);
-
-		if (k == 0) {
-			min_coarse_dqs[dqs] = test_dqs;
-		} else {
-			if (test_dqs == MIN_FINE_START + 1) {
-				min_coarse_dqs[dqs]++;
-				min_fine_dqs[dqs] = 0x0;
-			} else {
-				min_fine_dqs[dqs] = test_dqs;
-			}
-		}
-	}
-
-	if (dqs == 0) {
-		dqs = 1;
-		goto DQS_CAL;
-	}
-
-	for (i = 0; i < 2; i++) {
-		u32 temp;
-
-		coarse_dqs[i] = (max_coarse_dqs[i] + min_coarse_dqs[i]) >> 1;
-		temp =
-		    (((max_coarse_dqs[i] + min_coarse_dqs[i]) % 2) * 4) +
-		    ((max_fine_dqs[i] + min_fine_dqs[i]) >> 1);
-		if (temp >= 0x10) {
-			coarse_dqs[i]++;
-			fine_dqs[i] = (temp - 0x10) + 0x8;
-		} else {
-			fine_dqs[i] = temp;
-		}
-	}
-	reg = (coarse_dqs[1] << 12) | (fine_dqs[1] << 8) |
-		(coarse_dqs[0] << 4) | fine_dqs[0];
-
-	clrbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x10, BIT(4));
-	writel(reg, (void *)MT76XX_MEMCTRL_BASE + 0x64);
-	writel(ddr_cfg2_reg, (void *)MT76XX_MEMCTRL_BASE + 0x48);
-	setbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x10, BIT(4));
-
-	for (i = 0; i < 2; i++)
-		debug("[%02X%02X%02X%02X]", min_coarse_dqs[i],
-		      min_fine_dqs[i], max_coarse_dqs[i], max_fine_dqs[i]);
-	debug("\nDDR Calibration DQS reg = %08X\n", reg);
-}
diff --git a/arch/mips/mach-mtmips/ddr_init.c b/arch/mips/mach-mtmips/ddr_init.c
new file mode 100644
index 0000000..cd355cc
--- /dev/null
+++ b/arch/mips/mach-mtmips/ddr_init.c
@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ *
+ * Author:  Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <common.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <mach/ddr.h>
+#include <mach/mc.h>
+
+#define DDR_BW_TEST_PAT			0xaa5555aa
+
+static const u32 dram_size[] = {
+	[DRAM_8MB] = SZ_8M,
+	[DRAM_16MB] = SZ_16M,
+	[DRAM_32MB] = SZ_32M,
+	[DRAM_64MB] = SZ_64M,
+	[DRAM_128MB] = SZ_128M,
+	[DRAM_256MB] = SZ_256M,
+};
+
+static void dram_test_write(u32 addr, u32 val)
+{
+	volatile ulong *target = (volatile ulong *)(KSEG1 + addr);
+
+	sync();
+	*target = val;
+	sync();
+}
+
+static u32 dram_test_read(u32 addr)
+{
+	volatile ulong *target = (volatile ulong *)(KSEG1 + addr);
+	u32 val;
+
+	sync();
+	val = *target;
+	sync();
+
+	return val;
+}
+
+static int dram_addr_test_bit(u32 bit)
+{
+	u32 val;
+
+	dram_test_write(0, 0);
+	dram_test_write(BIT(bit), DDR_BW_TEST_PAT);
+	val = dram_test_read(0);
+
+	if (val == DDR_BW_TEST_PAT)
+		return 1;
+
+	return 0;
+}
+
+static void mc_ddr_init(void __iomem *memc, const struct mc_ddr_cfg *cfg,
+			u32 dq_dly, u32 dqs_dly, mc_reset_t mc_reset, u32 bw)
+{
+	u32 val;
+
+	mc_reset(1);
+	__udelay(200);
+	mc_reset(0);
+
+	clrbits_32(memc + MEMCTL_SDRAM_CFG1_REG, RBC_MAPPING);
+
+	writel(cfg->cfg2, memc + MEMCTL_DDR_CFG2_REG);
+	writel(cfg->cfg3, memc + MEMCTL_DDR_CFG3_REG);
+	writel(cfg->cfg4, memc + MEMCTL_DDR_CFG4_REG);
+	writel(dq_dly, memc + MEMCTL_DDR_DQ_DLY_REG);
+	writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG);
+
+	writel(cfg->cfg0, memc + MEMCTL_DDR_CFG0_REG);
+
+	val = cfg->cfg1;
+	if (bw) {
+		val &= ~IND_SDRAM_WIDTH_M;
+		val |= (bw << IND_SDRAM_WIDTH_S) & IND_SDRAM_WIDTH_M;
+	}
+
+	writel(val, memc + MEMCTL_DDR_CFG1_REG);
+
+	clrsetbits_32(memc + MEMCTL_PWR_SAVE_CNT_REG, SR_TAR_CNT_M,
+		      1 << SR_TAR_CNT_S);
+
+	setbits_32(memc + MEMCTL_DDR_SELF_REFRESH_REG, SR_AUTO_EN);
+}
+
+void ddr1_init(struct mc_ddr_init_param *param)
+{
+	enum mc_dram_size sz;
+	u32 bw = 0;
+
+	/* First initialization, determine bus width */
+	mc_ddr_init(param->memc, &param->cfgs[DRAM_8MB], param->dq_dly,
+		    param->dqs_dly, param->mc_reset, IND_SDRAM_WIDTH_16BIT);
+
+	/* Test bus width */
+	dram_test_write(0, DDR_BW_TEST_PAT);
+	if (dram_test_read(0) == DDR_BW_TEST_PAT)
+		bw = IND_SDRAM_WIDTH_16BIT;
+	else
+		bw = IND_SDRAM_WIDTH_8BIT;
+
+	/* Second initialization, determine DDR capacity */
+	mc_ddr_init(param->memc, &param->cfgs[DRAM_128MB], param->dq_dly,
+		    param->dqs_dly, param->mc_reset, bw);
+
+	if (dram_addr_test_bit(9)) {
+		sz = DRAM_8MB;
+	} else {
+		if (dram_addr_test_bit(10)) {
+			if (dram_addr_test_bit(23))
+				sz = DRAM_16MB;
+			else
+				sz = DRAM_32MB;
+		} else {
+			if (dram_addr_test_bit(24))
+				sz = DRAM_64MB;
+			else
+				sz = DRAM_128MB;
+		}
+	}
+
+	/* Final initialization, with DDR calibration */
+	mc_ddr_init(param->memc, &param->cfgs[sz], param->dq_dly,
+		    param->dqs_dly, param->mc_reset, bw);
+
+	/* Return actual DDR configuration */
+	param->memsize = dram_size[sz];
+	param->bus_width = bw;
+}
+
+void ddr2_init(struct mc_ddr_init_param *param)
+{
+	enum mc_dram_size sz;
+	u32 bw = 0;
+
+	/* First initialization, determine bus width */
+	mc_ddr_init(param->memc, &param->cfgs[DRAM_32MB], param->dq_dly,
+		    param->dqs_dly, param->mc_reset, IND_SDRAM_WIDTH_16BIT);
+
+	/* Test bus width */
+	dram_test_write(0, DDR_BW_TEST_PAT);
+	if (dram_test_read(0) == DDR_BW_TEST_PAT)
+		bw = IND_SDRAM_WIDTH_16BIT;
+	else
+		bw = IND_SDRAM_WIDTH_8BIT;
+
+	/* Second initialization, determine DDR capacity */
+	mc_ddr_init(param->memc, &param->cfgs[DRAM_256MB], param->dq_dly,
+		    param->dqs_dly, param->mc_reset, bw);
+
+	if (bw == IND_SDRAM_WIDTH_16BIT) {
+		if (dram_addr_test_bit(10)) {
+			sz = DRAM_32MB;
+		} else {
+			if (dram_addr_test_bit(24)) {
+				if (dram_addr_test_bit(27))
+					sz = DRAM_64MB;
+				else
+					sz = DRAM_128MB;
+			} else {
+				sz = DRAM_256MB;
+			}
+		}
+	} else {
+		if (dram_addr_test_bit(23)) {
+			sz = DRAM_32MB;
+		} else {
+			if (dram_addr_test_bit(24)) {
+				if (dram_addr_test_bit(27))
+					sz = DRAM_64MB;
+				else
+					sz = DRAM_128MB;
+			} else {
+				sz = DRAM_256MB;
+			}
+		}
+	}
+
+	/* Final initialization, with DDR calibration */
+	mc_ddr_init(param->memc, &param->cfgs[sz], param->dq_dly,
+		    param->dqs_dly, param->mc_reset, bw);
+
+	/* Return actual DDR configuration */
+	param->memsize = dram_size[sz];
+	param->bus_width = bw;
+}
diff --git a/arch/mips/mach-mtmips/include/mach/ddr.h b/arch/mips/mach-mtmips/include/mach/ddr.h
new file mode 100644
index 0000000..f921981
--- /dev/null
+++ b/arch/mips/mach-mtmips/include/mach/ddr.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ *
+ * Author:  Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#ifndef _MTMIPS_DDR_H_
+#define _MTMIPS_DDR_H_
+
+#include <linux/io.h>
+#include <linux/types.h>
+
+enum mc_dram_size {
+	DRAM_8MB,
+	DRAM_16MB,
+	DRAM_32MB,
+	DRAM_64MB,
+	DRAM_128MB,
+	DRAM_256MB,
+
+	__DRAM_SZ_MAX
+};
+
+struct mc_ddr_cfg {
+	u32 cfg0;
+	u32 cfg1;
+	u32 cfg2;
+	u32 cfg3;
+	u32 cfg4;
+};
+
+typedef void (*mc_reset_t)(int assert);
+
+struct mc_ddr_init_param {
+	void __iomem *memc;
+
+	u32 dq_dly;
+	u32 dqs_dly;
+
+	const struct mc_ddr_cfg *cfgs;
+	mc_reset_t mc_reset;
+
+	u32 memsize;
+	u32 bus_width;
+};
+
+void ddr1_init(struct mc_ddr_init_param *param);
+void ddr2_init(struct mc_ddr_init_param *param);
+void ddr_calibrate(void __iomem *memc, u32 memsize, u32 bw);
+
+#endif /* _MTMIPS_DDR_H_ */
diff --git a/arch/mips/mach-mtmips/include/mach/mc.h b/arch/mips/mach-mtmips/include/mach/mc.h
new file mode 100644
index 0000000..d7d623a
--- /dev/null
+++ b/arch/mips/mach-mtmips/include/mach/mc.h
@@ -0,0 +1,180 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ *
+ * Author:  Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#ifndef _MTMIPS_MC_H_
+#define _MTMIPS_MC_H_
+
+#define MEMCTL_SDRAM_CFG0_REG		0x00
+#define DIS_CLK_GT			0x80000000
+#define CLK_SLEW_S			29
+#define CLK_SLEW_M			0x60000000
+#define TWR				0x10000000
+#define TMRD_S				24
+#define TMRD_M				0xf000000
+#define TRFC_S				20
+#define TRFC_M				0xf00000
+#define TCAS_S				16
+#define TCAS_M				0x30000
+#define TRAS_S				12
+#define TRAS_M				0xf000
+#define TRCD_S				8
+#define TRCD_M				0x300
+#define TRC_S				4
+#define TRC_M				0xf0
+#define TRP_S				0
+#define TRP_M				0x03
+
+#define MEMCTL_SDRAM_CFG1_REG		0x04
+#define SDRAM_INIT_START		0x80000000
+#define SDRAM_INIT_DONE			0x40000000
+#define RBC_MAPPING			0x20000000
+#define PWR_DOWN_EN			0x10000000
+#define PWR_DOWN_MODE			0x8000000
+#define SDRAM_WIDTH			0x1000000
+#define NUMCOLS_S			20
+#define NUMCOLS_M			0x300000
+#define NUMROWS_S			16
+#define NUMROWS_M			0x30000
+#define TREFR_S				0
+#define TREFR_M				0xffff
+
+#define MEMCTL_DDR_SELF_REFRESH_REG	0x10
+#define ODT_SRC_SEL_S			24
+#define ODT_SRC_SEL_M			0xf000000
+#define ODT_OFF_DLY_S			20
+#define ODT_OFF_DLY_M			0xf00000
+#define ODT_ON_DLY_S			16
+#define ODT_ON_DLY_M			0xf0000
+#define SR_AUTO_EN			0x10
+#define SRACK_B				0x02
+#define SRREQ_B				0x01
+
+#define MEMCTL_PWR_SAVE_CNT_REG		0x14
+#define PD_CNT_S			24
+#define PD_CNT_M			0xff000000
+#define SR_TAR_CNT_S			0
+#define SR_TAR_CNT_M			0xffffff
+
+#define MEMCTL_DLL_DBG_REG		0x20
+#define TDC_STABLE_S			12
+#define TDC_STABLE_M			0x3f000
+#define MST_DLY_SEL_S			4
+#define MST_DLY_SEL_M			0xff0
+#define CURR_STATE_S			1
+#define CURR_STATE_M			0x06
+#define ADLL_LOCK_DONE			0x01
+
+#define MEMCTL_DDR_CFG0_REG		0x40
+#define T_RRD_S				28
+#define T_RRD_M				0xf0000000
+#define T_RAS_S				23
+#define T_RAS_M				0xf800000
+#define T_RP_S				19
+#define T_RP_M				0x780000
+#define T_RFC_S				13
+#define T_RFC_M				0x7e000
+#define T_REFI_S			0
+#define T_REFI_M			0x1fff
+
+#define MEMCTL_DDR_CFG1_REG		0x44
+#define T_WTR_S				28
+#define T_WTR_M				0xf0000000
+#define T_RTP_S				24
+#define T_RTP_M				0xf000000
+#define USER_DATA_WIDTH			0x200000
+#define IND_SDRAM_SIZE_S		18
+#define IND_SDRAM_SIZE_M		0x1c0000
+#define IND_SDRAM_SIZE_8MB		1
+#define IND_SDRAM_SIZE_16MB		2
+#define IND_SDRAM_SIZE_32MB		3
+#define IND_SDRAM_SIZE_64MB		4
+#define IND_SDRAM_SIZE_128MB		5
+#define IND_SDRAM_SIZE_256MB		6
+#define IND_SDRAM_WIDTH_S		16
+#define IND_SDRAM_WIDTH_M		0x30000
+#define IND_SDRAM_WIDTH_8BIT		1
+#define IND_SDRAM_WIDTH_16BIT		2
+#define EXT_BANK_S			14
+#define EXT_BANK_M			0xc000
+#define TOTAL_SDRAM_WIDTH_S		12
+#define TOTAL_SDRAM_WIDTH_M		0x3000
+#define T_WR_S				8
+#define T_WR_M				0xf00
+#define T_MRD_S				4
+#define T_MRD_M				0xf0
+#define T_RCD_S				0
+#define T_RCD_M				0x0f
+
+#define MEMCTL_DDR_CFG2_REG		0x48
+#define REGE				0x80000000
+#define DDR2_MODE			0x40000000
+#define DQS0_GATING_WINDOW_S		28
+#define DQS0_GATING_WINDOW_M		0x30000000
+#define DQS1_GATING_WINDOW_S		26
+#define DQS1_GATING_WINDOW_M		0xc000000
+#define PD				0x1000
+#define WR_S				9
+#define WR_M				0xe00
+#define DLLRESET			0x100
+#define TESTMODE			0x80
+#define CAS_LATENCY_S			4
+#define CAS_LATENCY_M			0x70
+#define BURST_TYPE			0x08
+#define BURST_LENGTH_S			0
+#define BURST_LENGTH_M			0x07
+
+#define MEMCTL_DDR_CFG3_REG		0x4c
+#define Q_OFF				0x1000
+#define RDOS				0x800
+#define DIS_DIFF_DQS			0x400
+#define OCD_S				7
+#define OCD_M				0x380
+#define RTT1				0x40
+#define ADDITIVE_LATENCY_S		3
+#define ADDITIVE_LATENCY_M		0x38
+#define RTT0				0x04
+#define DS				0x02
+#define DLL				0x01
+
+#define MEMCTL_DDR_CFG4_REG		0x50
+#define FAW_S				0
+#define FAW_M				0x0f
+
+#define MEMCTL_DDR_DQ_DLY_REG		0x60
+#define DQ1_DELAY_SEL_S			24
+#define DQ1_DELAY_SEL_M			0xff000000
+#define DQ0_DELAY_SEL_S			16
+#define DQ0_DELAY_SEL_M			0xff0000
+#define DQ1_DELAY_COARSE_TUNING_S	12
+#define DQ1_DELAY_COARSE_TUNING_M	0xf000
+#define DQ1_DELAY_FINE_TUNING_S		8
+#define DQ1_DELAY_FINE_TUNING_M		0xf00
+#define DQ0_DELAY_COARSE_TUNING_S	4
+#define DQ0_DELAY_COARSE_TUNING_M	0xf0
+#define DQ0_DELAY_FINE_TUNING_S		0
+#define DQ0_DELAY_FINE_TUNING_M		0x0f
+
+#define MEMCTL_DDR_DQS_DLY_REG		0x64
+#define DQS1_DELAY_SEL_S		24
+#define DQS1_DELAY_SEL_M		0xff000000
+#define DQS0_DELAY_SEL_S		16
+#define DQS0_DELAY_SEL_M		0xff0000
+#define DQS1_DELAY_COARSE_TUNING_S	12
+#define DQS1_DELAY_COARSE_TUNING_M	0xf000
+#define DQS1_DELAY_FINE_TUNING_S	8
+#define DQS1_DELAY_FINE_TUNING_M	0xf00
+#define DQS0_DELAY_COARSE_TUNING_S	4
+#define DQS0_DELAY_COARSE_TUNING_M	0xf0
+#define DQS0_DELAY_FINE_TUNING_S	0
+#define DQS0_DELAY_FINE_TUNING_M	0x0f
+
+#define MEMCTL_DDR_DLL_SLV_REG		0x68
+#define DLL_SLV_UPDATE_MODE		0x100
+#define DQS_DLY_SEL_EN			0x80
+#define DQ_DLY_SEL_EN			0x01
+
+#endif /* _MTMIPS_MC_H_ */
diff --git a/arch/mips/mach-mtmips/include/mach/serial.h b/arch/mips/mach-mtmips/include/mach/serial.h
new file mode 100644
index 0000000..bfa246b
--- /dev/null
+++ b/arch/mips/mach-mtmips/include/mach/serial.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ *
+ * Author:  Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#ifndef _MTMIPS_SERIAL_H_
+#define _MTMIPS_SERIAL_H_
+
+void mtmips_spl_serial_init(void);
+
+#endif /* _MTMIPS_SERIAL_H_ */
diff --git a/arch/mips/mach-mtmips/lowlevel_init.S b/arch/mips/mach-mtmips/lowlevel_init.S
deleted file mode 100644
index aa707e0..0000000
--- a/arch/mips/mach-mtmips/lowlevel_init.S
+++ /dev/null
@@ -1,328 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (c) 2018 Stefan Roese <sr@denx.de>
- *
- * This code is mostly based on the code extracted from this MediaTek
- * github repository:
- *
- * https://github.com/MediaTek-Labs/linkit-smart-uboot.git
- *
- * I was not able to find a specific license or other developers
- * copyrights here, so I can't add them here.
- */
-
-#include <config.h>
-#include <asm/regdef.h>
-#include <asm/mipsregs.h>
-#include <asm/addrspace.h>
-#include <asm/asm.h>
-#include "mt76xx.h"
-
-#ifndef BIT
-#define BIT(nr)			(1 << (nr))
-#endif
-
-#define DELAY_USEC(us)		((us) / 100)
-
-#define DDR_CFG1_CHIP_WIDTH_MASK (0x3 << 16)
-#define DDR_CFG1_BUS_WIDTH_MASK	(0x3 << 12)
-
-#if defined(CONFIG_ONBOARD_DDR2_SIZE_256MBIT)
-#define DDR_CFG1_SIZE_VAL	0x222e2323
-#define DDR_CFG4_SIZE_VAL	7
-#endif
-#if defined(CONFIG_ONBOARD_DDR2_SIZE_512MBIT)
-#define DDR_CFG1_SIZE_VAL	0x22322323
-#define DDR_CFG4_SIZE_VAL	9
-#endif
-#if defined(CONFIG_ONBOARD_DDR2_SIZE_1024MBIT)
-#define DDR_CFG1_SIZE_VAL	0x22362323
-#define DDR_CFG4_SIZE_VAL	9
-#endif
-#if defined(CONFIG_ONBOARD_DDR2_SIZE_2048MBIT)
-#define DDR_CFG1_SIZE_VAL	0x223a2323
-#define DDR_CFG4_SIZE_VAL	9
-#endif
-
-#if defined(CONFIG_ONBOARD_DDR2_CHIP_WIDTH_8BIT)
-#define DDR_CFG1_CHIP_WIDTH_VAL	(0x1 << 16)
-#endif
-#if defined(CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT)
-#define DDR_CFG1_CHIP_WIDTH_VAL	(0x2 << 16)
-#endif
-
-#if defined(CONFIG_ONBOARD_DDR2_BUS_WIDTH_16BIT)
-#define DDR_CFG1_BUS_WIDTH_VAL	(0x2 << 12)
-#endif
-#if defined(CONFIG_ONBOARD_DDR2_BUS_WIDTH_32BIT)
-#define DDR_CFG1_BUS_WIDTH_VAL	(0x3 << 12)
-#endif
-
-	.set noreorder
-
-LEAF(lowlevel_init)
-
-	/* Load base addresses as physical addresses for later usage */
-	li	s0, CKSEG1ADDR(MT76XX_SYSCTL_BASE)
-	li	s1, CKSEG1ADDR(MT76XX_MEMCTRL_BASE)
-	li	s2, CKSEG1ADDR(MT76XX_RGCTRL_BASE)
-
-	/* polling CPLL is ready */
-	li	t1, DELAY_USEC(1000000)
-	la	t5, MT76XX_ROM_STATUS_REG
-1:
-	lw	t2, 0(t5)
-	andi	t2, t2, 0x1
-	bnez	t2, CPLL_READY
-	subu	t1, t1, 1
-	bgtz	t1, 1b
-	nop
-	la      t0, MT76XX_CLKCFG0_REG
-	lw      t3, 0(t0)
-	ori	t3, t3, 0x1
-	sw	t3, 0(t0)
-	b	CPLL_DONE
-	nop
-CPLL_READY:
-	la	t0, MT76XX_CLKCFG0_REG
-	lw	t1, 0(t0)
-	li	t2, ~0x0c
-	and	t1, t1, t2
-	ori	t1, t1, 0xc
-	sw	t1, 0(t0)
-	la	t0, MT76XX_DYN_CFG0_REG
-	lw	t3, 0(t0)
-	li	t5, ~((0x0f << 8) | (0x0f << 0))
-	and	t3, t3, t5
-	li	t5, (10 << 8) | (1 << 0)
-	or	t3, t3, t5
-	sw	t3, 0(t0)
-	la	t0, MT76XX_CLKCFG0_REG
-	lw	t3, 0(t0)
-	li	t4, ~0x0F
-	and     t3, t3, t4
-	ori	t3, t3, 0xc
-	sw	t3, 0(t0)
-	lw	t3, 0(t0)
-	ori	t3, t3, 0x08
-	sw	t3, 0(t0)
-
-CPLL_DONE:
-	/* Reset MC */
-	lw	t2, 0x34(s0)
-	ori	t2, BIT(10)
-	sw	t2, 0x34(s0)
-	nop
-
-	/*
-	 * SDR and DDR initialization: delay 200us
-	 */
-	li	t0, DELAY_USEC(200 + 40)
-	li	t1, 0x1
-1:
-	sub	t0, t0, t1
-	bnez	t0, 1b
-	nop
-
-	/* set DRAM IO PAD for MT7628IC */
-	/* DDR LDO Enable  */
-	lw	t4, 0x100(s2)
-	li	t2, BIT(31)
-	or	t4, t4, t2
-	sw	t4, 0x100(s2)
-	lw	t4, 0x10c(s2)
-	j	LDO_1P8V
-	nop
-LDO_1P8V:
-	li	t2, ~BIT(6)
-	and	t4, t4, t2
-	sw	t4, 0x10c(s2)
-	j	DDRLDO_SOFT_START
-LDO_2P5V:
-	/* suppose external DDR1 LDO 2.5V */
-	li	t2, BIT(6)
-	or	t4, t4, t2
-	sw	t4, 0x10c(s2)
-
-DDRLDO_SOFT_START:
-	lw	t2, 0x10c(s2)
-	li	t3, BIT(16)
-	or	t2, t2, t3
-	sw	t2, 0x10c(s2)
-	li	t3, DELAY_USEC(250*50)
-LDO_DELAY:
-	subu	t3, t3, 1
-	bnez	t3, LDO_DELAY
-	nop
-
-	lw	t2, 0x10c(s2)
-	li	t3, BIT(18)
-	or	t2, t2, t3
-	sw	t2, 0x10c(s2)
-
-SET_RG_BUCK_FPWM:
-	lw	t2, 0x104(s2)
-	ori	t2, t2, BIT(10)
-	sw	t2, 0x104(s2)
-
-DDR_PAD_CFG:
-	/* clean CLK PAD */
-	lw	t2, 0x704(s2)
-	li	t8, 0xfffff0f0
-	and	t2, t2, t8
-	/* clean CMD PAD */
-	lw	t3, 0x70c(s2)
-	li	t8, 0xfffff0f0
-	and	t3, t3, t8
-	/* clean DQ IPAD */
-	lw	t4, 0x710(s2)
-	li	t8, 0xfffff8ff
-	and	t4, t4, t8
-	/* clean DQ OPAD */
-	lw	t5, 0x714(s2)
-	li	t8, 0xfffff0f0
-	and	t5, t5, t8
-	/* clean DQS IPAD */
-	lw	t6, 0x718(s2)
-	li	t8, 0xfffff8ff
-	and	t6, t6, t8
-	/* clean DQS OPAD */
-	lw	t7, 0x71c(s2)
-	li	t8, 0xfffff0f0
-	and	t7, t7, t8
-
-	lw	t9, 0xc(s0)
-	srl	t9, t9, 16
-	andi	t9, t9, 0x1
-	bnez	t9, MT7628_AN_DDR1_PAD
-MT7628_KN_PAD:
-	li	t8, 0x00000303
-	or	t2, t2, t8
-	or	t3, t3, t8
-	or	t5, t5, t8
-	or	t7, t7, t8
-	li	t8, 0x00000000
-	or	t4, t4, t8
-	or	t6, t6, t8
-	j	SET_PAD_CFG
-MT7628_AN_DDR1_PAD:
-	lw	t1, 0x10(s0)
-	andi	t1, t1, 0x1
-	beqz	t1, MT7628_AN_DDR2_PAD
-	li	t8, 0x00000c0c
-	or	t2, t2, t8
-	li	t8, 0x00000202
-	or	t3, t3, t8
-	li	t8, 0x00000707
-	or	t5, t5, t8
-	li	t8, 0x00000c0c
-	or	t7, t7, t8
-	li	t8, 0x00000000
-	or	t4, t4, t8
-	or	t6, t6, t8
-	j	SET_PAD_CFG
-MT7628_AN_DDR2_PAD:
-	li	t8, 0x00000c0c
-	or	t2, t2, t8
-	li	t8, 0x00000202
-	or	t3, t3, t8
-	li	t8, 0x00000404
-	or	t5, t5, t8
-	li	t8, 0x00000c0c
-	or	t7, t7, t8
-	li	t8, 0x00000000		/* ODT off */
-	or	t4, t4, t8
-	or	t6, t6, t8
-
-SET_PAD_CFG:
-	sw	t2, 0x704(s2)
-	sw	t3, 0x70c(s2)
-	sw	t4, 0x710(s2)
-	sw	t5, 0x714(s2)
-	sw	t6, 0x718(s2)
-	sw	t7, 0x71c(s2)
-
-	/*
-	 * DDR initialization: reset pin to 0
-	 */
-	lw	t2, 0x34(s0)
-	and	t2, ~BIT(10)
-	sw	t2, 0x34(s0)
-	nop
-
-	/*
-	 * DDR initialization: wait til reg DDR_CFG1 bit 21 equal to 1 (ready)
-	 */
-DDR_READY:
-	li	t1, DDR_CFG1_REG
-	lw	t0, 0(t1)
-	nop
-	and	t2, t0, BIT(21)
-	beqz	t2, DDR_READY
-	nop
-
-	/*
-	 * DDR initialization
-	 *
-	 * Only DDR2 supported right now. DDR2 support can be added, once
-	 * boards using it will get added to mainline U-Boot.
-	 */
-	li	t1, DDR_CFG2_REG
-	lw	t0, 0(t1)
-	nop
-	and	t0, ~BIT(30)
-	and	t0, ~(7 << 4)
-	or	t0, (4 << 4)
-	or	t0, BIT(30)
-	or	t0, BIT(11)
-	sw	t0, 0(t1)
-	nop
-
-	li	t1, DDR_CFG3_REG
-	lw	t2, 0(t1)
-	/* Disable ODT; reference board ok, ev board fail */
-	and	t2, ~BIT(6)
-	or	t2, BIT(2)
-	li	t0, DDR_CFG4_REG
-	lw	t1, 0(t0)
-	li	t2, ~(0x01f | 0x0f0)
-	and	t1, t1, t2
-	ori	t1, t1, DDR_CFG4_SIZE_VAL
-	sw	t1, 0(t0)
-	nop
-
-	/*
-	 * DDR initialization: config size and width on reg DDR_CFG1
-	 */
-	li	t6, DDR_CFG1_SIZE_VAL
-
-	and	t6, ~DDR_CFG1_CHIP_WIDTH_MASK
-	or	t6, DDR_CFG1_CHIP_WIDTH_VAL
-
-	/* CONFIG DDR_CFG1[13:12] about TOTAL WIDTH */
-	and	t6, ~DDR_CFG1_BUS_WIDTH_MASK
-	or	t6, DDR_CFG1_BUS_WIDTH_VAL
-
-	li	t5, DDR_CFG1_REG
-	sw	t6, 0(t5)
-	nop
-
-	/*
-	 * DDR: enable self auto refresh for power saving
-	 * enable it by default for both RAM and ROM version (for CoC)
-	 */
-	lw	t1, 0x14(s1)
-	nop
-	and	t1, 0xff000000
-	or	t1, 0x01
-	sw	t1, 0x14(s1)
-	nop
-	lw	t1, 0x10(s1)
-	nop
-	or	t1, 0x10
-	sw	t1, 0x10(s1)
-	nop
-
-	jr	ra
-	nop
-	END(lowlevel_init)
diff --git a/arch/mips/mach-mtmips/mt7628/Makefile b/arch/mips/mach-mtmips/mt7628/Makefile
new file mode 100644
index 0000000..7e139d5
--- /dev/null
+++ b/arch/mips/mach-mtmips/mt7628/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += lowlevel_init.o
+obj-y += init.o
+obj-y += ddr.o
+obj-$(CONFIG_SPL_BUILD) += serial.o
diff --git a/arch/mips/mach-mtmips/mt7628/ddr.c b/arch/mips/mach-mtmips/mt7628/ddr.c
new file mode 100644
index 0000000..06c0ca6
--- /dev/null
+++ b/arch/mips/mach-mtmips/mt7628/ddr.c
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ *
+ * Author:  Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <common.h>
+#include <asm/addrspace.h>
+#include <linux/bitops.h>
+#include <linux/sizes.h>
+#include <linux/io.h>
+#include <mach/ddr.h>
+#include <mach/mc.h>
+#include "mt7628.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* DDR2 DQ_DLY */
+#define DDR2_DQ_DLY \
+				((0x8 << DQ1_DELAY_COARSE_TUNING_S) | \
+				(0x2 << DQ1_DELAY_FINE_TUNING_S) | \
+				(0x8 << DQ0_DELAY_COARSE_TUNING_S) | \
+				(0x2 << DQ0_DELAY_FINE_TUNING_S))
+
+/* DDR2 DQS_DLY */
+#define DDR2_DQS_DLY \
+				((0x8 << DQS1_DELAY_COARSE_TUNING_S) | \
+				(0x3 << DQS1_DELAY_FINE_TUNING_S) | \
+				(0x8 << DQS0_DELAY_COARSE_TUNING_S) | \
+				(0x3 << DQS0_DELAY_FINE_TUNING_S))
+
+const struct mc_ddr_cfg ddr1_cfgs_200mhz[] = {
+	[DRAM_8MB]   = { 0x34A1EB94, 0x20262324, 0x28000033, 0x00000002, 0x00000000 },
+	[DRAM_16MB]  = { 0x34A1EB94, 0x202A2324, 0x28000033, 0x00000002, 0x00000000 },
+	[DRAM_32MB]  = { 0x34A1E5CA, 0x202E2324, 0x28000033, 0x00000002, 0x00000000 },
+	[DRAM_64MB]  = { 0x3421E5CA, 0x20322324, 0x28000033, 0x00000002, 0x00000000 },
+	[DRAM_128MB] = { 0x241B05CA, 0x20362334, 0x28000033, 0x00000002, 0x00000000 },
+};
+
+const struct mc_ddr_cfg ddr1_cfgs_160mhz[] = {
+	[DRAM_8MB]   = { 0x239964A1, 0x20262323, 0x00000033, 0x00000002, 0x00000000 },
+	[DRAM_16MB]  = { 0x239964A1, 0x202A2323, 0x00000033, 0x00000002, 0x00000000 },
+	[DRAM_32MB]  = { 0x239964A1, 0x202E2323, 0x00000033, 0x00000002, 0x00000000 },
+	[DRAM_64MB]  = { 0x239984A1, 0x20322323, 0x00000033, 0x00000002, 0x00000000 },
+	[DRAM_128MB] = { 0x239AB4A1, 0x20362333, 0x00000033, 0x00000002, 0x00000000 },
+};
+
+const struct mc_ddr_cfg ddr2_cfgs_200mhz[] = {
+	[DRAM_32MB]  = { 0x2519E2E5, 0x222E2323, 0x68000C43, 0x00000452, 0x0000000A },
+	[DRAM_64MB]  = { 0x249AA2E5, 0x22322323, 0x68000C43, 0x00000452, 0x0000000A },
+	[DRAM_128MB] = { 0x249B42E5, 0x22362323, 0x68000C43, 0x00000452, 0x0000000A },
+	[DRAM_256MB] = { 0x249CE2E5, 0x223A2323, 0x68000C43, 0x00000452, 0x0000000A },
+};
+
+const struct mc_ddr_cfg ddr2_cfgs_160mhz[] = {
+	[DRAM_32MB]  = { 0x23918250, 0x222E2322, 0x40000A43, 0x00000452, 0x00000006 },
+	[DRAM_64MB]  = { 0x239A2250, 0x22322322, 0x40000A43, 0x00000452, 0x00000008 },
+	[DRAM_128MB] = { 0x2392A250, 0x22362322, 0x40000A43, 0x00000452, 0x00000008 },
+	[DRAM_256MB] = { 0x24140250, 0x223A2322, 0x40000A43, 0x00000452, 0x00000008 },
+};
+
+static void mt7628_memc_reset(int assert)
+{
+	void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
+
+	if (assert)
+		setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST);
+	else
+		clrbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST);
+}
+
+static void mt7628_ddr_pad_ldo_config(int ddr_type, int pkg_type)
+{
+	void __iomem *rgc = ioremap_nocache(RGCTL_BASE, RGCTL_SIZE);
+	u32 ck_pad1, cmd_pad1, dq_pad0, dq_pad1, dqs_pad0, dqs_pad1;
+
+	setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN);
+
+	if (ddr_type == DRAM_DDR1)
+		setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL);
+	else
+		clrbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL);
+
+	setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN);
+
+	__udelay(250 * 50);
+
+	setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB);
+	setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM);
+
+	ck_pad1 = readl(rgc + RGCTL_DDR_PAD_CK_G1_REG);
+	cmd_pad1 = readl(rgc + RGCTL_DDR_PAD_CMD_G1_REG);
+	dq_pad0 = readl(rgc + RGCTL_DDR_PAD_DQ_G0_REG);
+	dq_pad1 = readl(rgc + RGCTL_DDR_PAD_DQ_G1_REG);
+	dqs_pad0 = readl(rgc + RGCTL_DDR_PAD_DQS_G0_REG);
+	dqs_pad1 = readl(rgc + RGCTL_DDR_PAD_DQS_G1_REG);
+
+	ck_pad1 &= ~(DRVP_M | DRVN_M);
+	cmd_pad1 &= ~(DRVP_M | DRVN_M);
+	dq_pad0 &= ~RTT_M;
+	dq_pad1 &= ~(DRVP_M | DRVN_M);
+	dqs_pad0 &= ~RTT_M;
+	dqs_pad1 &= ~(DRVP_M | DRVN_M);
+
+	if (pkg_type == PKG_ID_KN) {
+		ck_pad1 |= (3 << DRVP_S) | (3 << DRVN_S);
+		cmd_pad1 |= (3 << DRVP_S) | (3 << DRVN_S);
+		dq_pad1 |= (3 << DRVP_S) | (3 << DRVN_S);
+		dqs_pad1 |= (3 << DRVP_S) | (3 << DRVN_S);
+	} else {
+		ck_pad1 |= (12 << DRVP_S) | (12 << DRVN_S);
+		cmd_pad1 |= (2 << DRVP_S) | (2 << DRVN_S);
+		dqs_pad1 |= (12 << DRVP_S) | (12 << DRVN_S);
+		if (ddr_type == DRAM_DDR1)
+			dq_pad1 |= (7 << DRVP_S) | (7 << DRVN_S);
+		else
+			dq_pad1 |= (4 << DRVP_S) | (4 << DRVN_S);
+	}
+
+	writel(ck_pad1, rgc + RGCTL_DDR_PAD_CK_G1_REG);
+	writel(cmd_pad1, rgc + RGCTL_DDR_PAD_CMD_G1_REG);
+	writel(dq_pad0, rgc + RGCTL_DDR_PAD_DQ_G0_REG);
+	writel(dq_pad1, rgc + RGCTL_DDR_PAD_DQ_G1_REG);
+	writel(dqs_pad0, rgc + RGCTL_DDR_PAD_DQS_G0_REG);
+	writel(dqs_pad1, rgc + RGCTL_DDR_PAD_DQS_G1_REG);
+}
+
+void mt7628_ddr_init(void)
+{
+	void __iomem *sysc;
+	int ddr_type, pkg_type, lspd;
+	struct mc_ddr_init_param param;
+
+	sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
+	ddr_type = readl(sysc + SYSCTL_SYSCFG0_REG) & DRAM_TYPE;
+	pkg_type = !!(readl(sysc + SYSCTL_CHIP_REV_ID_REG) & PKG_ID);
+	lspd = readl(sysc + SYSCTL_CLKCFG0_REG) &
+	       (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL);
+
+	mt7628_memc_reset(1);
+	__udelay(200);
+
+	mt7628_ddr_pad_ldo_config(ddr_type, pkg_type);
+
+	param.memc = ioremap_nocache(MEMCTL_BASE, MEMCTL_SIZE);
+	param.dq_dly = DDR2_DQ_DLY;
+	param.dqs_dly = DDR2_DQS_DLY;
+	param.mc_reset = mt7628_memc_reset;
+	param.memsize = 0;
+	param.bus_width = 0;
+
+	if (pkg_type == PKG_ID_KN)
+		ddr_type = DRAM_DDR1;
+
+	if (ddr_type == DRAM_DDR1) {
+		if (lspd)
+			param.cfgs = ddr1_cfgs_160mhz;
+		else
+			param.cfgs = ddr1_cfgs_200mhz;
+		ddr1_init(&param);
+	} else {
+		if (lspd)
+			param.cfgs = ddr2_cfgs_160mhz;
+		else
+			param.cfgs = ddr2_cfgs_200mhz;
+		ddr2_init(&param);
+	}
+
+	ddr_calibrate(param.memc, param.memsize, param.bus_width);
+
+	gd->ram_size = param.memsize;
+}
diff --git a/arch/mips/mach-mtmips/mt7628/init.c b/arch/mips/mach-mtmips/mt7628/init.c
new file mode 100644
index 0000000..77d1f2e
--- /dev/null
+++ b/arch/mips/mach-mtmips/mt7628/init.c
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ *
+ * Author:  Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/uclass.h>
+#include <dt-bindings/clock/mt7628-clk.h>
+#include <linux/io.h>
+#include "mt7628.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void set_init_timer_freq(void)
+{
+	void __iomem *sysc;
+	u32 bs, val, timer_freq_post;
+
+	sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
+
+	/* We can't use the clk driver as the DM has not been initialized yet */
+	bs = readl(sysc + SYSCTL_SYSCFG0_REG);
+	if ((bs & XTAL_FREQ_SEL) == XTAL_25MHZ) {
+		gd->arch.timer_freq = 25000000;
+		timer_freq_post = 575000000;
+	} else {
+		gd->arch.timer_freq = 40000000;
+		timer_freq_post = 580000000;
+	}
+
+	val = readl(sysc + SYSCTL_CLKCFG0_REG);
+	if (!(val & (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL)))
+		gd->arch.timer_freq = timer_freq_post;
+}
+
+void mt7628_init(void)
+{
+	set_init_timer_freq();
+
+	mt7628_ddr_init();
+}
+
+int print_cpuinfo(void)
+{
+	void __iomem *sysc;
+	struct udevice *clkdev;
+	u32 val, ver, eco, pkg, ddr, chipmode, ee;
+	ulong cpu_clk, bus_clk, xtal_clk, timer_freq;
+	struct clk clk;
+	int ret;
+
+	sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
+
+	val = readl(sysc + SYSCTL_CHIP_REV_ID_REG);
+	ver = (val & VER_M) >> VER_S;
+	eco = (val & ECO_M) >> ECO_S;
+	pkg = !!(val & PKG_ID);
+
+	val = readl(sysc + SYSCTL_SYSCFG0_REG);
+	ddr = val & DRAM_TYPE;
+	chipmode = (val & CHIP_MODE_M) >> CHIP_MODE_S;
+
+	val = readl(sysc + SYSCTL_EFUSE_CFG_REG);
+	ee = val & EFUSE_MT7688;
+
+	printf("CPU:   MediaTek MT%u%c ver:%u eco:%u\n",
+	       ee ? 7688 : 7628, pkg ? 'A' : 'K', ver, eco);
+
+	printf("Boot:  DDR%s, SPI-NOR %u-Byte Addr, CPU clock from %s\n",
+	       ddr ? "" : "2", chipmode & 0x01 ? 4 : 3,
+	       chipmode & 0x02 ? "XTAL" : "CPLL");
+
+	ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(mt7628_clk),
+					  &clkdev);
+	if (ret)
+		return ret;
+
+	clk.dev = clkdev;
+
+	clk.id = CLK_CPU;
+	cpu_clk = clk_get_rate(&clk);
+
+	clk.id = CLK_SYS;
+	bus_clk = clk_get_rate(&clk);
+
+	clk.id = CLK_XTAL;
+	xtal_clk = clk_get_rate(&clk);
+
+	clk.id = CLK_MIPS_CNT;
+	timer_freq = clk_get_rate(&clk);
+
+	/* Set final timer frequency */
+	if (timer_freq)
+		gd->arch.timer_freq = timer_freq;
+
+	printf("Clock: CPU: %luMHz, Bus: %luMHz, XTAL: %luMHz\n",
+	       cpu_clk / 1000000, bus_clk / 1000000, xtal_clk / 1000000);
+
+	return 0;
+}
+
+ulong notrace get_tbclk(void)
+{
+	return gd->arch.timer_freq;
+}
diff --git a/arch/mips/mach-mtmips/mt7628/lowlevel_init.S b/arch/mips/mach-mtmips/mt7628/lowlevel_init.S
new file mode 100644
index 0000000..e4a6c03
--- /dev/null
+++ b/arch/mips/mach-mtmips/mt7628/lowlevel_init.S
@@ -0,0 +1,161 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ *
+ * Author:  Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <config.h>
+#include <asm-offsets.h>
+#include <asm/cacheops.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/asm.h>
+#include "mt7628.h"
+
+/* Set temporary stack address range */
+#ifndef CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + \
+				CONFIG_SYS_INIT_SP_OFFSET)
+#endif
+
+#define CACHE_STACK_SIZE	0x4000
+#define CACHE_STACK_BASE	(CONFIG_SYS_INIT_SP_ADDR - CACHE_STACK_SIZE)
+
+#define DELAY_USEC(us)		((58 * (us)) / 3)
+
+	.set noreorder
+
+LEAF(mips_sram_init)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	/* Setup CPU PLL */
+	li	t0, DELAY_USEC(1000000)
+	li	t1, KSEG1ADDR(SYSCTL_BASE + SYSCTL_ROM_STATUS_REG)
+	li	t2, KSEG1ADDR(SYSCTL_BASE + SYSCTL_CLKCFG0_REG)
+
+_check_rom_status:
+	lw	t3, 0(t1)
+	andi	t3, t3, 1
+	bnez	t3, _rom_normal
+	subu	t0, t0, 1
+	bnez	t0, _check_rom_status
+	 nop
+
+	lw	t3, 0(t2)
+	ori	t3, (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL)
+	xori	t3, CPU_PLL_FROM_BBP
+	b	_cpu_pll_done
+	 nop
+
+_rom_normal:
+	lw	t3, 0(t2)
+	ori	t3, (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL | \
+		    DIS_BBP_SLEEP | EN_BBP_CLK)
+	xori	t3, (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL)
+
+_cpu_pll_done:
+	sw	t3, 0(t2)
+
+	li	t2, KSEG1ADDR(RBUSCTL_BASE + RBUSCTL_DYN_CFG0_REG)
+	lw	t3, 0(t2)
+	ori	t3, t3, (CPU_FDIV_M | CPU_FFRAC_M)
+	xori	t3, t3, (CPU_FDIV_M | CPU_FFRAC_M)
+	ori	t3, t3, ((1 << CPU_FDIV_S) | (1 << CPU_FFRAC_S))
+	sw	t3, 0(t2)
+
+	/* Clear WST & SPR bits in ErrCtl */
+	mfc0	t0, CP0_ECC
+	ins	t0, zero, 30, 2
+	mtc0	t0, CP0_ECC
+	ehb
+
+	/* Simply initialize I-Cache */
+	li	a0, 0
+	li	a1, CONFIG_SYS_ICACHE_SIZE
+
+	mtc0	zero, CP0_TAGLO		/* Zero to DDataLo */
+
+1:	cache	INDEX_STORE_TAG_I, 0(a0)
+	addiu	a0, CONFIG_SYS_ICACHE_LINE_SIZE
+	bne	a0, a1, 1b
+	 nop
+
+	/* Simply initialize D-Cache */
+	li	a0, 0
+	li	a1, CONFIG_SYS_DCACHE_SIZE
+
+	mtc0	zero, CP0_TAGLO, 2
+
+2:	cache	INDEX_STORE_TAG_D, 0(a0)
+	addiu	a0, CONFIG_SYS_DCACHE_LINE_SIZE
+	bne	a0, a1, 2b
+	 nop
+
+	/* Set KSEG0 Cachable */
+	mfc0	t0, CP0_CONFIG
+	and	t0, t0, MIPS_CONF_IMPL
+	or	t0, t0, CONF_CM_CACHABLE_NONCOHERENT
+	mtc0	t0, CP0_CONFIG
+	ehb
+
+	/* Lock D-Cache */
+	PTR_LI	a0, CACHE_STACK_BASE		/* D-Cache lock base */
+	li	a1, CACHE_STACK_SIZE		/* D-Cache lock size */
+	li	a2, 0x1ffff800			/* Mask of DTagLo[PTagLo] */
+
+3:
+	/* Lock one cacheline */
+	and	t0, a0, a2
+	ori	t0, 0xe0			/* Valid & Dirty & Lock bits */
+	mtc0	t0, CP0_TAGLO, 2		/* Write to DTagLo */
+	ehb
+	cache	INDEX_STORE_TAG_D, 0(a0)
+
+	addiu	a0, CONFIG_SYS_DCACHE_LINE_SIZE
+	sub	a1, CONFIG_SYS_DCACHE_LINE_SIZE
+	bnez	a1, 3b
+	 nop
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+	jr	ra
+	 nop
+	END(mips_sram_init)
+
+NESTED(lowlevel_init, 0, ra)
+	/* Save ra and do real lowlevel initialization */
+	move	s0, ra
+
+	PTR_LA	t9, mt7628_init
+	jalr	t9
+	 nop
+
+	move	ra, s0
+
+#if CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F)
+	/* Set malloc base */
+	li	t0, (CONFIG_SYS_INIT_SP_ADDR + 15) & (~15)
+	PTR_S	t0, GD_MALLOC_BASE(k0)	# gd->malloc_base offset
+#endif
+
+	/* Write back data in locked cache to DRAM */
+	PTR_LI	a0, CACHE_STACK_BASE		/* D-Cache unlock base */
+	li	a1, CACHE_STACK_SIZE		/* D-Cache unlock size */
+
+1:
+	cache	HIT_WRITEBACK_INV_D, 0(a0)
+	addiu	a0, CONFIG_SYS_DCACHE_LINE_SIZE
+	sub	a1, CONFIG_SYS_DCACHE_LINE_SIZE
+	bnez	a1, 1b
+	 nop
+
+	/* Set KSEG0 Uncached */
+	mfc0	t0, CP0_CONFIG
+	and	t0, t0, MIPS_CONF_IMPL
+	or	t0, t0, CONF_CM_UNCACHED
+	mtc0	t0, CP0_CONFIG
+	ehb
+
+	jr	ra
+	 nop
+	END(lowlevel_init)
diff --git a/arch/mips/mach-mtmips/mt7628/mt7628.h b/arch/mips/mach-mtmips/mt7628/mt7628.h
new file mode 100644
index 0000000..391880b
--- /dev/null
+++ b/arch/mips/mach-mtmips/mt7628/mt7628.h
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ *
+ * Author:  Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#ifndef _MT7628_H_
+#define _MT7628_H_
+
+#define SYSCTL_BASE			0x10000000
+#define SYSCTL_SIZE			0x100
+#define MEMCTL_BASE			0x10000300
+#define MEMCTL_SIZE			0x100
+#define RBUSCTL_BASE			0x10000400
+#define RBUSCTL_SIZE			0x100
+#define RGCTL_BASE			0x10001000
+#define RGCTL_SIZE			0x800
+
+#define SYSCTL_EFUSE_CFG_REG		0x08
+#define EFUSE_MT7688			0x100000
+
+#define SYSCTL_CHIP_REV_ID_REG		0x0c
+#define PKG_ID				0x10000
+#define PKG_ID_AN			1
+#define PKG_ID_KN			0
+#define VER_S				8
+#define VER_M				0xf00
+#define ECO_S				0
+#define ECO_M				0x0f
+
+#define SYSCTL_SYSCFG0_REG		0x10
+#define XTAL_FREQ_SEL			0x40
+#define XTAL_40MHZ			1
+#define XTAL_25MHZ			0
+#define CHIP_MODE_S			1
+#define CHIP_MODE_M			0x0e
+#define DRAM_TYPE			0x01
+#define DRAM_DDR1			1
+#define DRAM_DDR2			0
+
+#define SYSCTL_ROM_STATUS_REG		0x28
+
+#define SYSCTL_CLKCFG0_REG		0x2c
+#define DIS_BBP_SLEEP			0x08
+#define EN_BBP_CLK			0x04
+#define CPU_PLL_FROM_BBP		0x02
+#define CPU_PLL_FROM_XTAL		0x01
+
+#define SYSCTL_RSTCTL_REG		0x34
+#define MC_RST				0x400
+
+#define SYSCTL_AGPIO_CFG_REG		0x3c
+#define EPHY_GPIO_AIO_EN_S		17
+#define EPHY_GPIO_AIO_EN_M		0x1e0000
+
+#define SYSCTL_GPIO_MODE1_REG		0x60
+#define UART2_MODE_S			26
+#define UART2_MODE_M			0xc000000
+#define UART1_MODE_S			24
+#define UART1_MODE_M			0x3000000
+#define UART0_MODE_S			8
+#define UART0_MODE_M			0x300
+#define SPIS_MODE_S			2
+#define SPIS_MODE_M			0x0c
+
+#define RBUSCTL_DYN_CFG0_REG		0x40
+#define CPU_FDIV_S			8
+#define CPU_FDIV_M			0xf00
+#define CPU_FFRAC_S			0
+#define CPU_FFRAC_M			0x0f
+
+#define RGCTL_PMU_G0_REG		0x100
+#define PMU_CFG_EN			0x80000000
+
+#define RGCTL_PMU_G1_REG		0x104
+#define RG_BUCK_FPWM			0x02
+
+#define RGCTL_PMU_G3_REG		0x10c
+#define NI_DDRLDO_STB			0x40000
+#define NI_DDRLDO_EN			0x10000
+#define RG_DDRLDO_VOSEL			0x40
+
+#define RGCTL_DDR_PAD_CK_G0_REG		0x700
+#define RGCTL_DDR_PAD_CMD_G0_REG	0x708
+#define RGCTL_DDR_PAD_DQ_G0_REG		0x710
+#define RGCTL_DDR_PAD_DQS_G0_REG	0x718
+#define RTT_S				8
+#define RTT_M				0x700
+
+#define RGCTL_DDR_PAD_CK_G1_REG		0x704
+#define RGCTL_DDR_PAD_CMD_G1_REG	0x70c
+#define RGCTL_DDR_PAD_DQ_G1_REG		0x714
+#define RGCTL_DDR_PAD_DQS_G1_REG	0x71c
+#define DRVP_S				0
+#define DRVP_M				0x0f
+#define DRVN_S				8
+#define DRVN_M				0xf00
+
+#ifndef __ASSEMBLY__
+void mt7628_ddr_init(void);
+#endif
+
+#endif /* _MT7628_H_ */
diff --git a/arch/mips/mach-mtmips/mt7628/serial.c b/arch/mips/mach-mtmips/mt7628/serial.c
new file mode 100644
index 0000000..a7d3247
--- /dev/null
+++ b/arch/mips/mach-mtmips/mt7628/serial.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ *
+ * Author:  Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include "mt7628.h"
+
+void mtmips_spl_serial_init(void)
+{
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+	void __iomem *base = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
+
+#if CONFIG_CONS_INDEX == 1
+	clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART0_MODE_M);
+#elif CONFIG_CONS_INDEX == 2
+	clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART1_MODE_M);
+#elif CONFIG_CONS_INDEX == 3
+	setbits_32(base + SYSCTL_AGPIO_CFG_REG, EPHY_GPIO_AIO_EN_M);
+#ifdef CONFIG_SPL_UART2_SPIS_PINMUX
+	setbits_32(base + SYSCTL_GPIO_MODE1_REG, SPIS_MODE_M);
+	clrsetbits_32(base + SYSCTL_GPIO_MODE1_REG, UART2_MODE_M,
+		      1 << UART2_MODE_S);
+#else
+	clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART2_MODE_M);
+	clrsetbits_32(base + SYSCTL_GPIO_MODE1_REG, SPIS_MODE_M,
+		      1 << SPIS_MODE_S);
+#endif /* CONFIG_SPL_UART2_SPIS_PINMUX */
+#endif /* CONFIG_CONS_INDEX */
+#endif /* CONFIG_SPL_SERIAL_SUPPORT */
+}
diff --git a/arch/mips/mach-mtmips/mt76xx.h b/arch/mips/mach-mtmips/mt76xx.h
deleted file mode 100644
index 17473ea..0000000
--- a/arch/mips/mach-mtmips/mt76xx.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2018 Stefan Roese <sr@denx.de>
- */
-
-#ifndef __MT76XX_H
-#define __MT76XX_H
-
-#define MT76XX_SYSCTL_BASE	0x10000000
-
-#define MT76XX_CHIPID_OFFS	0x00
-#define MT76XX_CHIP_REV_ID_OFFS	0x0c
-#define MT76XX_SYSCFG0_OFFS	0x10
-
-#define MT76XX_MEMCTRL_BASE	(MT76XX_SYSCTL_BASE + 0x0300)
-#define MT76XX_RGCTRL_BASE	(MT76XX_SYSCTL_BASE + 0x1000)
-
-#define MT76XX_ROM_STATUS_REG	(MT76XX_SYSCTL_BASE + 0x0028)
-#define MT76XX_CLKCFG0_REG	(MT76XX_SYSCTL_BASE + 0x002c)
-#define MT76XX_DYN_CFG0_REG	(MT76XX_SYSCTL_BASE + 0x0440)
-
-#define DDR_CFG1_REG		(MT76XX_MEMCTRL_BASE + 0x44)
-#define DDR_CFG2_REG		(MT76XX_MEMCTRL_BASE + 0x48)
-#define DDR_CFG3_REG		(MT76XX_MEMCTRL_BASE + 0x4c)
-#define DDR_CFG4_REG		(MT76XX_MEMCTRL_BASE + 0x50)
-
-#ifndef __ASSEMBLY__
-/* Prototypes */
-void ddr_calibrate(void);
-#endif
-
-#endif
diff --git a/arch/mips/mach-mtmips/spl.c b/arch/mips/mach-mtmips/spl.c
new file mode 100644
index 0000000..2a24af7
--- /dev/null
+++ b/arch/mips/mach-mtmips/spl.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <common.h>
+#include <fdt.h>
+#include <spl.h>
+#include <asm/sections.h>
+#include <linux/sizes.h>
+#include <mach/serial.h>
+
+void __noreturn board_init_f(ulong dummy)
+{
+	spl_init();
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+	/*
+	 * mtmips_spl_serial_init() is useful if debug uart is enabled,
+	 * or DM based serial is not enabled.
+	 */
+	mtmips_spl_serial_init();
+	preloader_console_init();
+#endif
+
+	board_init_r(NULL, 0);
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	spl_boot_list[0] = BOOT_DEVICE_NOR;
+}
+
+unsigned long spl_nor_get_uboot_base(void)
+{
+	void *uboot_base = __image_copy_end;
+
+	if (fdt_magic(uboot_base) == FDT_MAGIC)
+		return (unsigned long)uboot_base + fdt_totalsize(uboot_base);
+
+	return (unsigned long)uboot_base;
+}
diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
new file mode 100644
index 0000000..2aebfab
--- /dev/null
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+/ {
+	aliases {
+		spi0 = &qspi0;
+		spi2 = &qspi2;
+	};
+};
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index df9f183..4bccfbe 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -226,6 +226,10 @@
 		compatible = "denx,u-boot-acpi-test";
 	};
 
+	acpi-test2 {
+		compatible = "denx,u-boot-acpi-test";
+	};
+
 	clocks {
 		clk_fixed: clk-fixed {
 			compatible = "fixed-clock";
diff --git a/arch/sandbox/include/asm/global_data.h b/arch/sandbox/include/asm/global_data.h
index f4ce72d..f95ddb0 100644
--- a/arch/sandbox/include/asm/global_data.h
+++ b/arch/sandbox/include/asm/global_data.h
@@ -13,6 +13,7 @@
 struct arch_global_data {
 	uint8_t		*ram_buf;	/* emulated RAM buffer */
 	void		*text_base;	/* pointer to base of text region */
+	ulong acpi_start;		/* Start address of ACPI tables */
 };
 
 #include <asm-generic/global_data.h>
diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 17cf168..7ef169b 100644
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c
@@ -566,6 +566,8 @@
 	struct udevice *dev, *itss;
 	int ret;
 
+	if (!ll_boot_init())
+		return 0;
 	/*
 	 * This must be called before any devices are probed. Put any probing
 	 * into arch_fsps_preinit() above.
diff --git a/arch/x86/cpu/coreboot/tables.c b/arch/x86/cpu/coreboot/tables.c
index 37e0424..0f04c4f 100644
--- a/arch/x86/cpu/coreboot/tables.c
+++ b/arch/x86/cpu/coreboot/tables.c
@@ -115,20 +115,11 @@
 
 static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 {
+	unsigned char *ptr = addr;
 	struct cb_header *header;
-	unsigned char *ptr = (unsigned char *)addr;
 	int i;
 
-	for (i = 0; i < len; i += 16, ptr += 16) {
-		header = (struct cb_header *)ptr;
-		if (!strncmp((const char *)header->signature, "LBIO", 4))
-			break;
-	}
-
-	/* We walked the entire space and didn't find anything. */
-	if (i >= len)
-		return -1;
-
+	header = (struct cb_header *)ptr;
 	if (!header->table_bytes)
 		return 0;
 
@@ -231,10 +222,13 @@
 
 int get_coreboot_info(struct sysinfo_t *info)
 {
-	int ret = cb_parse_header((void *)0x00000000, 0x1000, info);
+	long addr;
+	int ret;
 
-	if (ret != 1)
-		ret = cb_parse_header((void *)0x000f0000, 0x1000, info);
+	addr = locate_coreboot_table();
+	if (addr < 0)
+		return addr;
+	ret = cb_parse_header((void *)addr, 0x1000, info);
 
-	return (ret == 1) ? 0 : -1;
+	return ret == 1 ? 0 : -ENOENT;
 }
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index cec04b4..8526e85 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -239,8 +239,10 @@
 	struct udevice *dev;
 	int ret;
 
-	if (!ll_boot_init())
+	if (!ll_boot_init()) {
+		uclass_first_device(UCLASS_PCI, &dev);
 		return 0;
+	}
 
 	ret = x86_init_cpus();
 	if (ret)
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index c8da7f1..0312a26 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -447,10 +447,37 @@
 	return 0;
 }
 
+long detect_coreboot_table_at(ulong start, ulong size)
+{
+	u32 *ptr, *end;
+
+	size /= 4;
+	for (ptr = (void *)start, end = ptr + size; ptr < end; ptr += 4) {
+		if (*ptr == 0x4f49424c) /* "LBIO" */
+			return (long)ptr;
+	}
+
+	return -ENOENT;
+}
+
+long locate_coreboot_table(void)
+{
+	long addr;
+
+	/* We look for LBIO in the first 4K of RAM and again at 960KB */
+	addr = detect_coreboot_table_at(0x0, 0x1000);
+	if (addr < 0)
+		addr = detect_coreboot_table_at(0xf0000, 0x1000);
+
+	return addr;
+}
+
 int x86_cpu_reinit_f(void)
 {
 	setup_identity();
 	setup_pci_ram_top();
+	if (locate_coreboot_table() >= 0)
+		gd->flags |= GD_FLG_SKIP_LL_INIT;
 
 	return 0;
 }
diff --git a/arch/x86/cpu/i386/interrupt.c b/arch/x86/cpu/i386/interrupt.c
index 4c7e9ea..e67a116 100644
--- a/arch/x86/cpu/i386/interrupt.c
+++ b/arch/x86/cpu/i386/interrupt.c
@@ -264,6 +264,9 @@
 	struct udevice *dev;
 	int ret;
 
+	if (!ll_boot_init())
+		return 0;
+
 	/* Try to set up the interrupt router, but don't require one */
 	ret = irq_first_device_type(X86_IRQT_BASE, &dev);
 	if (ret && ret != -ENODEV)
@@ -295,8 +298,7 @@
 	 * TODO(sjg@chromium.org): But we don't handle these correctly when
 	 * booted from EFI.
 	 */
-	if (ll_boot_init())
-		enable_interrupts();
+	enable_interrupts();
 #endif
 
 	return 0;
diff --git a/arch/x86/cpu/start_from_spl.S b/arch/x86/cpu/start_from_spl.S
index 22cab2d..905c825 100644
--- a/arch/x86/cpu/start_from_spl.S
+++ b/arch/x86/cpu/start_from_spl.S
@@ -14,18 +14,30 @@
 .globl _start
 .type _start, @function
 _start:
-	/* Set up memory using the existing stack */
+	/*
+	 * If running from coreboot, CAR is no-longer available. Use the
+	 * existing stack, which is large enough.
+	 */
+	call	locate_coreboot_table
+	cmp	$0, %eax
+	jge	use_existing_stack
+
 	movl	$(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - 4), %eax
 #ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE
 	subl	$CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %eax
 #endif
+	jmp	2f
 	/*
-	 * We don't subject CONFIG_DCACHE_RAM_MRC_VAR_SIZE since memory is
+	 * We don't subtract CONFIG_DCACHE_RAM_MRC_VAR_SIZE since memory is
 	 * already set up. This has the happy side-effect of putting gd in a
 	 * new place separate from SPL, so the memset() in
 	 * board_init_f_init_reserve() does not cause any problems (otherwise
 	 * it would zero out the gd and crash)
 	 */
+	/* Set up memory using the existing stack */
+use_existing_stack:
+	mov	%esp, %eax
+2:
 	call	board_init_f_alloc_reserve
 	mov	%eax, %esp
 
diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h
index 61de0077..268284f 100644
--- a/arch/x86/include/asm/coreboot_tables.h
+++ b/arch/x86/include/asm/coreboot_tables.h
@@ -343,4 +343,11 @@
  */
 void write_coreboot_table(u32 addr, struct memory_area *cfg_tables);
 
+/**
+ * locate_coreboot_table() - Try to find coreboot tables at standard locations
+ *
+ * @return address of table that was found, or -ve error number
+ */
+long locate_coreboot_table(void);
+
 #endif
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index f4c1839..4aee2f3 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -123,6 +123,7 @@
 #ifdef CONFIG_FSP_VERSION2
 	struct fsp_header *fsp_s_hdr;	/* Pointer to FSP-S header */
 #endif
+	ulong acpi_start;		/* Start address of ACPI tables */
 };
 
 #endif
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 9346e16..13f1409 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -10,6 +10,7 @@
 #include <cpu.h>
 #include <dm.h>
 #include <dm/uclass-internal.h>
+#include <mapmem.h>
 #include <serial.h>
 #include <version.h>
 #include <acpi/acpi_table.h>
@@ -19,6 +20,7 @@
 #include <asm/mpspec.h>
 #include <asm/tables.h>
 #include <asm/arch/global_nvs.h>
+#include <dm/acpi.h>
 
 /*
  * IASL compiles the dsdt entries and writes the hex values
@@ -29,139 +31,6 @@
 /* ACPI RSDP address to be used in boot parameters */
 static ulong acpi_rsdp_addr;
 
-static void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt,
-			    struct acpi_xsdt *xsdt)
-{
-	memset(rsdp, 0, sizeof(struct acpi_rsdp));
-
-	memcpy(rsdp->signature, RSDP_SIG, 8);
-	memcpy(rsdp->oem_id, OEM_ID, 6);
-
-	rsdp->length = sizeof(struct acpi_rsdp);
-	rsdp->rsdt_address = (u32)rsdt;
-
-	/*
-	 * Revision: ACPI 1.0: 0, ACPI 2.0/3.0/4.0: 2
-	 *
-	 * Some OSes expect an XSDT to be present for RSD PTR revisions >= 2.
-	 * If we don't have an ACPI XSDT, force ACPI 1.0 (and thus RSD PTR
-	 * revision 0)
-	 */
-	if (xsdt == NULL) {
-		rsdp->revision = ACPI_RSDP_REV_ACPI_1_0;
-	} else {
-		rsdp->xsdt_address = (u64)(u32)xsdt;
-		rsdp->revision = ACPI_RSDP_REV_ACPI_2_0;
-	}
-
-	/* Calculate checksums */
-	rsdp->checksum = table_compute_checksum((void *)rsdp, 20);
-	rsdp->ext_checksum = table_compute_checksum((void *)rsdp,
-			sizeof(struct acpi_rsdp));
-}
-
-void acpi_fill_header(struct acpi_table_header *header, char *signature)
-{
-	memcpy(header->signature, signature, 4);
-	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
-	header->oem_revision = U_BOOT_BUILD_DATE;
-	memcpy(header->aslc_id, ASLC_ID, 4);
-}
-
-static void acpi_write_rsdt(struct acpi_rsdt *rsdt)
-{
-	struct acpi_table_header *header = &(rsdt->header);
-
-	/* Fill out header fields */
-	acpi_fill_header(header, "RSDT");
-	header->length = sizeof(struct acpi_rsdt);
-	header->revision = 1;
-
-	/* Entries are filled in later, we come with an empty set */
-
-	/* Fix checksum */
-	header->checksum = table_compute_checksum((void *)rsdt,
-			sizeof(struct acpi_rsdt));
-}
-
-static void acpi_write_xsdt(struct acpi_xsdt *xsdt)
-{
-	struct acpi_table_header *header = &(xsdt->header);
-
-	/* Fill out header fields */
-	acpi_fill_header(header, "XSDT");
-	header->length = sizeof(struct acpi_xsdt);
-	header->revision = 1;
-
-	/* Entries are filled in later, we come with an empty set */
-
-	/* Fix checksum */
-	header->checksum = table_compute_checksum((void *)xsdt,
-			sizeof(struct acpi_xsdt));
-}
-
-/**
- * Add an ACPI table to the RSDT (and XSDT) structure, recalculate length
- * and checksum.
- */
-static void acpi_add_table(struct acpi_rsdp *rsdp, void *table)
-{
-	int i, entries_num;
-	struct acpi_rsdt *rsdt;
-	struct acpi_xsdt *xsdt;
-
-	/* The RSDT is mandatory while the XSDT is not */
-	rsdt = (struct acpi_rsdt *)rsdp->rsdt_address;
-
-	/* This should always be MAX_ACPI_TABLES */
-	entries_num = ARRAY_SIZE(rsdt->entry);
-
-	for (i = 0; i < entries_num; i++) {
-		if (rsdt->entry[i] == 0)
-			break;
-	}
-
-	if (i >= entries_num) {
-		debug("ACPI: Error: too many tables\n");
-		return;
-	}
-
-	/* Add table to the RSDT */
-	rsdt->entry[i] = (u32)table;
-
-	/* Fix RSDT length or the kernel will assume invalid entries */
-	rsdt->header.length = sizeof(struct acpi_table_header) +
-				sizeof(u32) * (i + 1);
-
-	/* Re-calculate checksum */
-	rsdt->header.checksum = 0;
-	rsdt->header.checksum = table_compute_checksum((u8 *)rsdt,
-			rsdt->header.length);
-
-	/* The RSDT is mandatory while the XSDT is not */
-	if (!rsdp->xsdt_address)
-		return;
-
-	/*
-	 * And now the same thing for the XSDT. We use the same index as for
-	 * now we want the XSDT and RSDT to always be in sync in U-Boot
-	 */
-	xsdt = (struct acpi_xsdt *)((u32)rsdp->xsdt_address);
-
-	/* Add table to the XSDT */
-	xsdt->entry[i] = (u64)(u32)table;
-
-	/* Fix XSDT length */
-	xsdt->header.length = sizeof(struct acpi_table_header) +
-				sizeof(u64) * (i + 1);
-
-	/* Re-calculate checksum */
-	xsdt->header.checksum = 0;
-	xsdt->header.checksum = table_compute_checksum((u8 *)xsdt,
-			xsdt->header.length);
-}
-
 static void acpi_create_facs(struct acpi_facs *facs)
 {
 	memset((void *)facs, 0, sizeof(struct acpi_facs));
@@ -487,12 +356,9 @@
 /*
  * QEMU's version of write_acpi_tables is defined in drivers/misc/qfw.c
  */
-ulong write_acpi_tables(ulong start)
+ulong write_acpi_tables(ulong start_addr)
 {
-	u32 current;
-	struct acpi_rsdp *rsdp;
-	struct acpi_rsdt *rsdt;
-	struct acpi_xsdt *xsdt;
+	struct acpi_ctx sctx, *ctx = &sctx;
 	struct acpi_facs *facs;
 	struct acpi_table_header *dsdt;
 	struct acpi_fadt *fadt;
@@ -500,60 +366,39 @@
 	struct acpi_madt *madt;
 	struct acpi_csrt *csrt;
 	struct acpi_spcr *spcr;
+	void *start;
+	ulong addr;
 	int i;
 
-	current = start;
+	start = map_sysmem(start_addr, 0);
 
-	/* Align ACPI tables to 16 byte */
-	current = ALIGN(current, 16);
+	debug("ACPI: Writing ACPI tables at %lx\n", start_addr);
 
-	debug("ACPI: Writing ACPI tables at %lx\n", start);
-
-	/* We need at least an RSDP and an RSDT Table */
-	rsdp = (struct acpi_rsdp *)current;
-	current += sizeof(struct acpi_rsdp);
-	current = ALIGN(current, 16);
-	rsdt = (struct acpi_rsdt *)current;
-	current += sizeof(struct acpi_rsdt);
-	current = ALIGN(current, 16);
-	xsdt = (struct acpi_xsdt *)current;
-	current += sizeof(struct acpi_xsdt);
-	/*
-	 * Per ACPI spec, the FACS table address must be aligned to a 64 byte
-	 * boundary (Windows checks this, but Linux does not).
-	 */
-	current = ALIGN(current, 64);
-
-	/* clear all table memory */
-	memset((void *)start, 0, current - start);
-
-	acpi_write_rsdp(rsdp, rsdt, xsdt);
-	acpi_write_rsdt(rsdt);
-	acpi_write_xsdt(xsdt);
+	acpi_setup_base_tables(ctx, start);
 
 	debug("ACPI:    * FACS\n");
-	facs = (struct acpi_facs *)current;
-	current += sizeof(struct acpi_facs);
-	current = ALIGN(current, 16);
+	facs = ctx->current;
+	acpi_inc_align(ctx, sizeof(struct acpi_facs));
 
 	acpi_create_facs(facs);
 
 	debug("ACPI:    * DSDT\n");
-	dsdt = (struct acpi_table_header *)current;
+	dsdt = ctx->current;
 	memcpy(dsdt, &AmlCode, sizeof(struct acpi_table_header));
-	current += sizeof(struct acpi_table_header);
-	memcpy((char *)current,
+	acpi_inc(ctx, sizeof(struct acpi_table_header));
+	memcpy(ctx->current,
 	       (char *)&AmlCode + sizeof(struct acpi_table_header),
 	       dsdt->length - sizeof(struct acpi_table_header));
-	current += dsdt->length - sizeof(struct acpi_table_header);
-	current = ALIGN(current, 16);
+	acpi_inc_align(ctx, dsdt->length - sizeof(struct acpi_table_header));
 
 	/* Pack GNVS into the ACPI table area */
 	for (i = 0; i < dsdt->length; i++) {
 		u32 *gnvs = (u32 *)((u32)dsdt + i);
 		if (*gnvs == ACPI_GNVS_ADDR) {
-			debug("Fix up global NVS in DSDT to 0x%08x\n", current);
-			*gnvs = current;
+			ulong addr = (ulong)map_to_sysmem(ctx->current);
+
+			debug("Fix up global NVS in DSDT to %#08lx\n", addr);
+			*gnvs = addr;
 			break;
 		}
 	}
@@ -563,51 +408,48 @@
 	dsdt->checksum = table_compute_checksum((void *)dsdt, dsdt->length);
 
 	/* Fill in platform-specific global NVS variables */
-	acpi_create_gnvs((struct acpi_global_nvs *)current);
-	current += sizeof(struct acpi_global_nvs);
-	current = ALIGN(current, 16);
+	acpi_create_gnvs(ctx->current);
+	acpi_inc_align(ctx, sizeof(struct acpi_global_nvs));
 
 	debug("ACPI:    * FADT\n");
-	fadt = (struct acpi_fadt *)current;
-	current += sizeof(struct acpi_fadt);
-	current = ALIGN(current, 16);
+	fadt = ctx->current;
+	acpi_inc_align(ctx, sizeof(struct acpi_fadt));
 	acpi_create_fadt(fadt, facs, dsdt);
-	acpi_add_table(rsdp, fadt);
+	acpi_add_table(ctx, fadt);
 
 	debug("ACPI:    * MADT\n");
-	madt = (struct acpi_madt *)current;
+	madt = ctx->current;
 	acpi_create_madt(madt);
-	current += madt->header.length;
-	acpi_add_table(rsdp, madt);
-	current = ALIGN(current, 16);
+	acpi_inc_align(ctx, madt->header.length);
+	acpi_add_table(ctx, madt);
 
 	debug("ACPI:    * MCFG\n");
-	mcfg = (struct acpi_mcfg *)current;
+	mcfg = ctx->current;
 	acpi_create_mcfg(mcfg);
-	current += mcfg->header.length;
-	acpi_add_table(rsdp, mcfg);
-	current = ALIGN(current, 16);
+	acpi_inc_align(ctx, mcfg->header.length);
+	acpi_add_table(ctx, mcfg);
 
 	debug("ACPI:    * CSRT\n");
-	csrt = (struct acpi_csrt *)current;
+	csrt = ctx->current;
 	acpi_create_csrt(csrt);
-	current += csrt->header.length;
-	acpi_add_table(rsdp, csrt);
-	current = ALIGN(current, 16);
+	acpi_inc_align(ctx, csrt->header.length);
+	acpi_add_table(ctx, csrt);
 
 	debug("ACPI:    * SPCR\n");
-	spcr = (struct acpi_spcr *)current;
+	spcr = ctx->current;
 	acpi_create_spcr(spcr);
-	current += spcr->header.length;
-	acpi_add_table(rsdp, spcr);
-	current = ALIGN(current, 16);
+	acpi_inc_align(ctx, spcr->header.length);
+	acpi_add_table(ctx, spcr);
 
-	debug("current = %x\n", current);
+	acpi_write_dev_tables(ctx);
 
-	acpi_rsdp_addr = (unsigned long)rsdp;
+	addr = map_to_sysmem(ctx->current);
+	debug("current = %lx\n", addr);
+
+	acpi_rsdp_addr = (unsigned long)ctx->rsdp;
 	debug("ACPI: done\n");
 
-	return current;
+	return addr;
 }
 
 ulong acpi_get_rsdp_addr(void)
diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c
index 9ce0ddf..15e82de 100644
--- a/arch/x86/lib/fsp/fsp_dram.c
+++ b/arch/x86/lib/fsp/fsp_dram.c
@@ -44,6 +44,14 @@
 	phys_addr_t low_end;
 	uint bank;
 
+	if (!ll_boot_init()) {
+		gd->bd->bi_dram[0].start = 0;
+		gd->bd->bi_dram[0].size = gd->ram_size;
+
+		mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size);
+		return 0;
+	}
+
 	low_end = 0;
 	for (bank = 1, hdr = gd->arch.hob_list;
 	     bank < CONFIG_NR_DRAM_BANKS && !end_of_hob(hdr);
diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c
index 226c7e6..98b7622 100644
--- a/arch/x86/lib/fsp/fsp_graphics.c
+++ b/arch/x86/lib/fsp/fsp_graphics.c
@@ -78,6 +78,9 @@
 	struct vesa_mode_info *vesa = &mode_info.vesa;
 	int ret;
 
+	if (!ll_boot_init())
+		return 0;
+
 	printf("Video: ");
 
 	/* Initialize vesa_mode_info structure */
diff --git a/arch/x86/lib/fsp2/fsp_dram.c b/arch/x86/lib/fsp2/fsp_dram.c
index c8f2c09..3869c53 100644
--- a/arch/x86/lib/fsp2/fsp_dram.c
+++ b/arch/x86/lib/fsp2/fsp_dram.c
@@ -12,11 +12,18 @@
 #include <asm/fsp/fsp_support.h>
 #include <asm/fsp2/fsp_api.h>
 #include <asm/fsp2/fsp_internal.h>
+#include <linux/sizes.h>
 
 int dram_init(void)
 {
 	int ret;
 
+	if (!ll_boot_init()) {
+		/* Use a small and safe amount of 1GB */
+		gd->ram_size = SZ_1G;
+
+		return 0;
+	}
 	if (spl_phase() == PHASE_SPL) {
 #ifdef CONFIG_HAVE_ACPI_RESUME
 		bool s3wake = gd->arch.prev_sleep_state == ACPI_S3;
@@ -68,6 +75,9 @@
 
 ulong board_get_usable_ram_top(ulong total_size)
 {
+	if (!ll_boot_init())
+		return gd->ram_size;
+
 #if CONFIG_IS_ENABLED(HANDOFF)
 	struct spl_handoff *ho = gd->spl_handoff;
 
diff --git a/arch/x86/lib/fsp2/fsp_init.c b/arch/x86/lib/fsp2/fsp_init.c
index da9bd6b..c7dc2ea 100644
--- a/arch/x86/lib/fsp2/fsp_init.c
+++ b/arch/x86/lib/fsp2/fsp_init.c
@@ -23,7 +23,7 @@
 	int ret;
 
 	/* Make sure pads are set up early in U-Boot */
-	if (spl_phase() != PHASE_BOARD_F)
+	if (!ll_boot_init() || spl_phase() != PHASE_BOARD_F)
 		return 0;
 
 	/* Probe all pinctrl devices to set up the pads */
diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c
index 5bb55e2..d906b52 100644
--- a/arch/x86/lib/init_helpers.c
+++ b/arch/x86/lib/init_helpers.c
@@ -30,6 +30,9 @@
 			return ret;
 	}
 
+	if (!ll_boot_init())
+		return 0;
+
 	/* Initialise the CPU cache(s) */
 	return init_cache();
 }
diff --git a/board/bitmain/antminer_s9/Makefile b/board/bitmain/antminer_s9/Makefile
index 93a1e77..1af01d6 100644
--- a/board/bitmain/antminer_s9/Makefile
+++ b/board/bitmain/antminer_s9/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 
 obj-y	:= board.o
+obj-y	+= ../../xilinx/common/board.o
 
 # Remove quotes
 hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
diff --git a/board/freescale/ls1028a/MAINTAINERS b/board/freescale/ls1028a/MAINTAINERS
index 2c28825..5b7a8db 100644
--- a/board/freescale/ls1028a/MAINTAINERS
+++ b/board/freescale/ls1028a/MAINTAINERS
@@ -8,6 +8,7 @@
 F:	include/configs/ls1028a_common.h
 F:	include/configs/ls1028aqds.h
 F:	configs/ls1028aqds_tfa_defconfig
+F:	configs/ls1028aqds_tfa_lpuart_defconfig
 
 LS1028ARDB BOARD
 M:	Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c
index 0b7504a..1e2973f 100644
--- a/board/freescale/ls1028a/ls1028a.c
+++ b/board/freescale/ls1028a/ls1028a.c
@@ -31,6 +31,7 @@
 
 int config_board_mux(void)
 {
+#ifndef CONFIG_LPUART
 #if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
 	u8 reg;
 
@@ -55,8 +56,17 @@
 	reg &= ~(0xc0);
 	QIXIS_WRITE(brdcfg[15], reg);
 #endif
+#endif
+
 	return 0;
 }
+
+#ifdef CONFIG_LPUART
+u32 get_lpuart_clk(void)
+{
+	return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV;
+}
+#endif
 
 int board_init(void)
 {
@@ -120,11 +130,33 @@
 
 int board_early_init_f(void)
 {
+#ifdef CONFIG_LPUART
+	u8 uart;
+#endif
+
 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 	i2c_early_init_f();
 #endif
 
 	fsl_lsch3_early_init_f();
+
+#ifdef CONFIG_LPUART
+	/*
+	 * Field| Function
+	 * --------------------------------------------------------------
+	 * 7-6  | Controls I2C3 routing (net CFG_MUX_I2C3):
+	 * I2C3 | 11= Routes {SCL, SDA} to LPUART1 header as {SOUT, SIN}.
+	 * --------------------------------------------------------------
+	 * 5-4  | Controls I2C4 routing (net CFG_MUX_I2C4):
+	 * I2C4 |11= Routes {SCL, SDA} to LPUART1 header as {CTS_B, RTS_B}.
+	 */
+	/* use lpuart0 as system console */
+	uart = QIXIS_READ(brdcfg[13]);
+	uart &= ~CFG_LPUART_MUX_MASK;
+	uart |= CFG_LPUART_EN;
+	QIXIS_WRITE(brdcfg[13], uart);
+#endif
+
 	return 0;
 }
 
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index 9bc78d6..26a1929 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -285,8 +285,10 @@
 	ft_cpu_setup(blob, bd);
 
 #ifdef CONFIG_SYS_DPAA_FMAN
+#ifndef CONFIG_DM_ETH
 	fdt_fixup_fman_ethernet(blob);
 #endif
+#endif
 
 	fdt_fixup_icid(blob);
 
diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c
index 8c0abb6..71ace19 100644
--- a/board/freescale/ls1046afrwy/ls1046afrwy.c
+++ b/board/freescale/ls1046afrwy/ls1046afrwy.c
@@ -232,8 +232,10 @@
 	ft_cpu_setup(blob, bd);
 
 #ifdef CONFIG_SYS_DPAA_FMAN
+#ifndef CONFIG_DM_ETH
 	fdt_fixup_fman_ethernet(blob);
 #endif
+#endif
 
 	fdt_fixup_icid(blob);
 
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c
index cabd7ee..e6648e9 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -462,7 +462,9 @@
 	ft_cpu_setup(blob, bd);
 
 #ifdef CONFIG_SYS_DPAA_FMAN
+#ifndef CONFIG_DM_ETH
 	fdt_fixup_fman_ethernet(blob);
+#endif
 	fdt_fixup_board_enet(blob);
 #endif
 
diff --git a/board/freescale/ls1046ardb/ddr.h b/board/freescale/ls1046ardb/ddr.h
index 3b4d44d..05baef23 100644
--- a/board/freescale/ls1046ardb/ddr.h
+++ b/board/freescale/ls1046ardb/ddr.h
@@ -32,7 +32,7 @@
 	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
 	{2,  1666, 0, 8,     7, 0x08090A0C, 0x0D0F100B,},
 	{2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
-	{2,  2300, 0, 8,     9, 0x0A0B0C10, 0x1213140E,},
+	{2,  2300, 0, 8,     7, 0x08090A0E, 0x1011120C,},
 	{}
 };
 
diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c
index cc6bd88..5308cb2 100644
--- a/board/freescale/ls1046ardb/ls1046ardb.c
+++ b/board/freescale/ls1046ardb/ls1046ardb.c
@@ -172,8 +172,10 @@
 	ft_cpu_setup(blob, bd);
 
 #ifdef CONFIG_SYS_DPAA_FMAN
+#ifndef CONFIG_DM_ETH
 	fdt_fixup_fman_ethernet(blob);
 #endif
+#endif
 
 	fdt_fixup_icid(blob);
 
diff --git a/board/freescale/ls1088a/eth_ls1088ardb.c b/board/freescale/ls1088a/eth_ls1088ardb.c
index 01f56db..f56ce7d 100644
--- a/board/freescale/ls1088a/eth_ls1088ardb.c
+++ b/board/freescale/ls1088a/eth_ls1088ardb.c
@@ -18,6 +18,7 @@
 #include <fsl-mc/fsl_mc.h>
 #include <fsl-mc/ldpaa_wriop.h>
 
+#ifndef CONFIG_DM_ETH
 int board_eth_init(bd_t *bis)
 {
 #if defined(CONFIG_FSL_MC_ENET)
@@ -95,6 +96,7 @@
 
 	return pci_eth_init(bis);
 }
+#endif
 
 #if defined(CONFIG_RESET_PHY_R)
 void reset_phy(void)
diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c
index 0bd397a..225e787 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -801,6 +801,11 @@
 #ifdef CONFIG_FSL_LS_PPA
 	ppa_init();
 #endif
+
+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
+	pci_init();
+#endif
+
 	return 0;
 }
 
diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c
index b0f276e..f0f6ca5 100644
--- a/board/freescale/ls2080ardb/eth_ls2080rdb.c
+++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c
@@ -23,6 +23,7 @@
 
 int board_eth_init(bd_t *bis)
 {
+#ifndef CONFIG_DM_ETH
 #if defined(CONFIG_FSL_MC_ENET)
 	int i, interface;
 	struct memac_mdio_info mdio_info;
@@ -99,6 +100,7 @@
 
 	cpu_eth_init(bis);
 #endif /* CONFIG_FSL_MC_ENET */
+#endif /* !CONFIG_DM_ETH */
 
 #ifdef CONFIG_PHY_AQUANTIA
 	/*
@@ -112,7 +114,12 @@
 	gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
 	gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
 #endif
+
+#ifdef CONFIG_DM_ETH
+	return 0;
+#else
 	return pci_eth_init(bis);
+#endif
 }
 
 #if defined(CONFIG_RESET_PHY_R)
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index 282aaf4..5e2fc7c 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -244,6 +244,10 @@
 	sec_init();
 #endif
 
+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
+	pci_init();
+#endif
+
 	return 0;
 }
 
diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index 23ea1b6..0d94107 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -29,14 +29,11 @@
 #include "../common/vid.h"
 #include <fsl_immap.h>
 #include <asm/arch-fsl-layerscape/fsl_icid.h>
-#include <asm/gic-v3.h>
-#include <cpu_func.h>
 
 #ifdef CONFIG_EMC2305
 #include "../common/emc2305.h"
 #endif
 
-#define GIC_LPI_SIZE                             0x200000
 #ifdef CONFIG_TARGET_LX2160AQDS
 #define CFG_MUX_I2C_SDHC(reg, value)		((reg & 0x3f) | value)
 #define SET_CFG_MUX1_SDHC1_SDHC(reg)		(reg & 0x3f)
@@ -644,21 +641,6 @@
 }
 #endif
 
-#ifdef CONFIG_GIC_V3_ITS
-void fdt_fixup_gic_lpi_memory(void *blob, u64 gic_lpi_base)
-{
-	u32 phandle;
-	int err;
-	struct fdt_memory gic_lpi;
-
-	gic_lpi.start = gic_lpi_base;
-	gic_lpi.end = gic_lpi_base + GIC_LPI_SIZE - 1;
-	err = fdtdec_add_reserved_memory(blob, "gic-lpi", &gic_lpi, &phandle);
-	if (err < 0)
-		debug("failed to add reserved memory: %d\n", err);
-}
-#endif
-
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
@@ -670,7 +652,6 @@
 	u64 mc_memory_base = 0;
 	u64 mc_memory_size = 0;
 	u16 total_memory_banks;
-	u64 __maybe_unused gic_lpi_base;
 
 	ft_cpu_setup(blob, bd);
 
@@ -690,12 +671,6 @@
 		size[i] = gd->bd->bi_dram[i].size;
 	}
 
-#ifdef CONFIG_GIC_V3_ITS
-	gic_lpi_base = gd->arch.resv_ram - GIC_LPI_SIZE;
-	gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
-	fdt_fixup_gic_lpi_memory(blob, gic_lpi_base);
-#endif
-
 #ifdef CONFIG_RESV_RAM
 	/* reduce size if reserved memory is within this bank */
 	if (gd->arch.resv_ram >= base[0] &&
diff --git a/board/gardena/smart-gateway-mt7688/board.c b/board/gardena/smart-gateway-mt7688/board.c
index 48cf309..776afa4 100644
--- a/board/gardena/smart-gateway-mt7688/board.c
+++ b/board/gardena/smart-gateway-mt7688/board.c
@@ -295,8 +295,10 @@
 	return ret;
 }
 
+#ifndef CONFIG_SPL_BUILD
 U_BOOT_CMD(
 	fd_write,	1,	0,	do_fd_write,
 	"Write test factory-data values to SPI NOR",
 	"\n"
 );
+#endif
diff --git a/board/mediatek/mt7628/Kconfig b/board/mediatek/mt7628/Kconfig
new file mode 100644
index 0000000..d6b6f9d
--- /dev/null
+++ b/board/mediatek/mt7628/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_MT7628_RFB
+
+config SYS_BOARD
+	default "mt7628"
+
+config SYS_VENDOR
+	default "mediatek"
+
+config SYS_CONFIG_NAME
+	default "mt7628"
+
+endif
diff --git a/board/mediatek/mt7628/MAINTAINERS b/board/mediatek/mt7628/MAINTAINERS
new file mode 100644
index 0000000..032fd0e
--- /dev/null
+++ b/board/mediatek/mt7628/MAINTAINERS
@@ -0,0 +1,7 @@
+MT7628_RFB BOARD
+M:	Weijie Gao <weijie.gao@mediatek.com>
+S:	Maintained
+F:	board/mediatek/mt7628
+F:	include/configs/mt7628.h
+F:	configs/mt7628_rfb_defconfig
+F:	arch/mips/dts/mediatek,mt7628-rfb.dts
diff --git a/board/mediatek/mt7628/Makefile b/board/mediatek/mt7628/Makefile
new file mode 100644
index 0000000..db129c5
--- /dev/null
+++ b/board/mediatek/mt7628/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += board.o
diff --git a/board/mediatek/mt7628/board.c b/board/mediatek/mt7628/board.c
new file mode 100644
index 0000000..f837a06
--- /dev/null
+++ b/board/mediatek/mt7628/board.c
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <common.h>
diff --git a/board/renesas/salvator-x/MAINTAINERS b/board/renesas/salvator-x/MAINTAINERS
index 542f7cc..7335bc3 100644
--- a/board/renesas/salvator-x/MAINTAINERS
+++ b/board/renesas/salvator-x/MAINTAINERS
@@ -3,6 +3,4 @@
 S:	Maintained
 F:	board/renesas/salvator-x/
 F:	include/configs/salvator-x.h
-F:	configs/r8a7795_salvator-x_defconfig
-F:	configs/r8a7796_salvator-x_defconfig
-F:	configs/r8a77965_salvator-x_defconfig
+F:	configs/rcar3_salvator-x_defconfig
diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c
index 058fa6f..91c3728 100644
--- a/board/renesas/salvator-x/salvator-x.c
+++ b/board/renesas/salvator-x/salvator-x.c
@@ -93,11 +93,11 @@
 	u32 cpu_type = rmobile_get_cpu_type();
 
 	if ((cpu_type == RMOBILE_CPU_TYPE_R8A7795) &&
-	    !strcmp(name, "r8a7795-salvator-x-u-boot"))
+	    !strcmp(name, "r8a77950-salvator-x-u-boot"))
 		return 0;
 
 	if ((cpu_type == RMOBILE_CPU_TYPE_R8A7796) &&
-	    !strcmp(name, "r8a7796-salvator-x-u-boot"))
+	    !strcmp(name, "r8a77960-salvator-x-u-boot"))
 		return 0;
 
 	if ((cpu_type == RMOBILE_CPU_TYPE_R8A77965) &&
diff --git a/board/renesas/ulcb/MAINTAINERS b/board/renesas/ulcb/MAINTAINERS
index 8549f54..564eb56 100644
--- a/board/renesas/ulcb/MAINTAINERS
+++ b/board/renesas/ulcb/MAINTAINERS
@@ -3,6 +3,4 @@
 S:	Maintained
 F:	board/renesas/ulcb/
 F:	include/configs/ulcb.h
-F:	configs/r8a7795_ulcb_defconfig
-F:	configs/r8a7796_ulcb_defconfig
-F:	configs/r8a77965_ulcb_defconfig
+F:	configs/rcar3_ulcb_defconfig
diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c
index bcae6ff..b91f940 100644
--- a/board/renesas/ulcb/ulcb.c
+++ b/board/renesas/ulcb/ulcb.c
@@ -75,15 +75,15 @@
 	u32 cpu_type = rmobile_get_cpu_type();
 
 	if ((cpu_type == RMOBILE_CPU_TYPE_R8A7795) &&
-	    !strcmp(name, "r8a7795-h3ulcb-u-boot"))
+	    !strcmp(name, "r8a77950-ulcb-u-boot"))
 		return 0;
 
 	if ((cpu_type == RMOBILE_CPU_TYPE_R8A7796) &&
-	    !strcmp(name, "r8a7796-m3ulcb-u-boot"))
+	    !strcmp(name, "r8a77960-ulcb-u-boot"))
 		return 0;
 
 	if ((cpu_type == RMOBILE_CPU_TYPE_R8A77965) &&
-	    !strcmp(name, "r8a77965-m3nulcb-u-boot"))
+	    !strcmp(name, "r8a77965-ulcb-u-boot"))
 		return 0;
 
 	return -1;
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index 5ca2147..75661f3 100644
--- a/board/sifive/fu540/Kconfig
+++ b/board/sifive/fu540/Kconfig
@@ -26,6 +26,7 @@
 	imply CMD_FS_GENERIC
 	imply CMD_NET
 	imply CMD_PING
+	imply CMD_SF
 	imply CLK_SIFIVE
 	imply CLK_SIFIVE_FU540_PRCI
 	imply DOS_PARTITION
@@ -40,6 +41,8 @@
 	imply SIFIVE_SERIAL
 	imply SPI
 	imply SPI_SIFIVE
+	imply SPI_FLASH
+	imply SPI_FLASH_ISSI
 	imply MMC
 	imply MMC_SPI
 	imply MMC_BROKEN_CD
diff --git a/board/synopsys/hsdk/Kconfig b/board/synopsys/hsdk/Kconfig
index e8c00a6..d9c0e27 100644
--- a/board/synopsys/hsdk/Kconfig
+++ b/board/synopsys/hsdk/Kconfig
@@ -7,6 +7,24 @@
 	default "synopsys"
 
 config SYS_CONFIG_NAME
-	default "hsdk"
+	default "hsdk" if BOARD_HSDK
+	default "hsdk-4xd" if BOARD_HSDK_4XD
+
+choice
+	prompt "HSDK board type"
+	default BOARD_HSDK
+
+config BOARD_HSDK
+	bool "ARC HS Development Kit"
+	help
+	  ARC HS Development Kit based on quard core ARC HS38 processor
+
+config BOARD_HSDK_4XD
+	bool "ARC HS4x/HS4xD Development Kit"
+	help
+	  ARC HS4x/HS4xD Development Kit based on quard core ARC HS48/HS47D
+	  processor
+
+endchoice
 
 endif
diff --git a/board/synopsys/hsdk/MAINTAINERS b/board/synopsys/hsdk/MAINTAINERS
index e22bd1e..73f71fd 100644
--- a/board/synopsys/hsdk/MAINTAINERS
+++ b/board/synopsys/hsdk/MAINTAINERS
@@ -1,5 +1,8 @@
-HSDK BOARD
+HSDK BOARDs
 M:	Eugeniy Paltsev <paltsev@synopsys.com>
 S:	Maintained
 F:	board/synopsys/hsdk/
 F:	configs/hsdk_defconfig
+F:	configs/hsdk_4xd_defconfig
+F:	include/configs/hsdk-4xd.h
+F:	include/configs/hsdk.h
diff --git a/board/synopsys/hsdk/config.mk b/board/synopsys/hsdk/config.mk
index 5ae22fa..def944a 100644
--- a/board/synopsys/hsdk/config.mk
+++ b/board/synopsys/hsdk/config.mk
@@ -2,6 +2,7 @@
 #
 # Copyright (C) 2018 Synopsys, Inc. All rights reserved.
 
+ifdef CONFIG_BOARD_HSDK
 PLATFORM_CPPFLAGS += -mcpu=hs38_linux -mlittle-endian -matomic -mll64 \
                      -mdiv-rem -mswap -mnorm -mmpy-option=9 -mbarrel-shifter \
                      -mfpu=fpud_all
@@ -13,3 +14,18 @@
 	$(Q)tools/mkimage -T script -C none -n 'uboot update script' \
 		-d $(srctree)/u-boot-update.txt \
 		$(srctree)/u-boot-update.scr &> /dev/null
+endif
+
+ifdef CONFIG_BOARD_HSDK_4XD
+PLATFORM_CPPFLAGS += -mcpu=hs4x_rel31 -mlittle-endian -matomic -mll64 \
+                     -mdiv-rem -mswap -mnorm -mmpy-option=9 -mbarrel-shifter \
+                     -mfpu=fpud_all
+
+bsp-generate: u-boot u-boot.bin
+	$(Q)python3 $(srctree)/board/$(BOARDDIR)/headerize-hsdk.py \
+		--arc-id 0x54 --image $(srctree)/u-boot.bin \
+		--elf $(srctree)/u-boot
+	$(Q)tools/mkimage -T script -C none -n 'uboot update script' \
+		-d $(srctree)/u-boot-update.txt \
+		$(srctree)/u-boot-update.scr &> /dev/null
+endif
diff --git a/board/synopsys/hsdk/headerize-hsdk.py b/board/synopsys/hsdk/headerize-hsdk.py
index fce7497..7b047cf 100644
--- a/board/synopsys/hsdk/headerize-hsdk.py
+++ b/board/synopsys/hsdk/headerize-hsdk.py
@@ -27,7 +27,7 @@
 
 
 def arg_verify(uboot_bin_filename, uboot_elf_filename, arc_id):
-    if arc_id not in [0x52, 0x53]:
+    if arc_id not in [0x52, 0x53, 0x54]:
         print("unknown ARC ID: " + hex(arc_id))
         sys.exit(2)
 
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index 67a29e3..a3e0563 100644
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -40,6 +40,9 @@
 #define CREG_BASE		(ARC_PERIPHERAL_BASE + 0x1000)
 #define CREG_CPU_START		(CREG_BASE + 0x400)
 #define CREG_CPU_START_MASK	0xF
+#define CREG_CPU_START_POL	BIT(4)
+
+#define CREG_CPU_0_ENTRY	(CREG_BASE + 0x404)
 
 #define SDIO_BASE		(ARC_PERIPHERAL_BASE + 0xA000)
 #define SDIO_UHS_REG_EXT	(SDIO_BASE + 0x108)
@@ -79,6 +82,9 @@
 	u32_env nvlim;
 	u32_env icache;
 	u32_env dcache;
+	u32_env csm_location;
+	u32_env l2_cache;
+	u32_env haps_apb;
 };
 
 /*
@@ -128,6 +134,11 @@
 	{ "non_volatile_limit", ENV_HEX, true, 0, 0xF,	&env_common.nvlim },
 	{ "icache_ena",	ENV_HEX, true,	0, 1,		&env_common.icache },
 	{ "dcache_ena",	ENV_HEX, true,	0, 1,		&env_common.dcache },
+#if defined(CONFIG_BOARD_HSDK_4XD)
+	{ "l2_cache_ena",	ENV_HEX, true,	0, 1,		&env_common.l2_cache },
+	{ "csm_location",	ENV_HEX, true,	0, NO_CCM,	&env_common.csm_location },
+	{ "haps_apb_location",	ENV_HEX, true,	0, 1,		&env_common.haps_apb },
+#endif /* CONFIG_BOARD_HSDK_4XD */
 	{}
 };
 
@@ -154,6 +165,61 @@
 	{}
 };
 
+enum board_type {
+	T_BOARD_NONE,
+	T_BOARD_HSDK,
+	T_BOARD_HSDK_4XD
+};
+
+static inline enum board_type get_board_type_runtime(void)
+{
+	u32 arc_id = read_aux_reg(ARC_AUX_IDENTITY) & 0xFF;
+
+	if (arc_id == 0x52)
+		return T_BOARD_HSDK;
+	else if (arc_id == 0x54)
+		return T_BOARD_HSDK_4XD;
+	else
+		return T_BOARD_NONE;
+}
+
+static inline enum board_type get_board_type_config(void)
+{
+	if (IS_ENABLED(CONFIG_BOARD_HSDK))
+		return T_BOARD_HSDK;
+	else if (IS_ENABLED(CONFIG_BOARD_HSDK_4XD))
+		return T_BOARD_HSDK_4XD;
+	else
+		return T_BOARD_NONE;
+}
+
+static bool is_board_match_runtime(enum board_type type_req)
+{
+	return get_board_type_runtime() == type_req;
+}
+
+static bool is_board_match_config(enum board_type type_req)
+{
+	return get_board_type_config() == type_req;
+}
+
+static const char * board_name(enum board_type type)
+{
+	switch (type) {
+		case T_BOARD_HSDK:
+			return "ARC HS Development Kit";
+		case T_BOARD_HSDK_4XD:
+			return "ARC HS4x/HS4xD Development Kit";
+		default:
+			return "?";
+	}
+}
+
+static bool board_mismatch(void)
+{
+	return get_board_type_config() != get_board_type_runtime();
+}
+
 static void sync_cross_cpu_data(void)
 {
 	u32 value;
@@ -221,10 +287,48 @@
 
 	flush_dcache_all();
 	write_aux_reg(ARC_AUX_NON_VOLATILE_LIMIT, val);
-	write_aux_reg(AUX_AUX_CACHE_LIMIT, val);
+	/* AUX_AUX_CACHE_LIMIT reg is missing starting from HS48 */
+	if (is_board_match_runtime(T_BOARD_HSDK))
+		write_aux_reg(AUX_AUX_CACHE_LIMIT, val);
 	flush_n_invalidate_dcache_all();
 }
 
+static void init_cluster_slc(void)
+{
+	/* ARC HS38 doesn't support SLC disabling */
+	if (!is_board_match_config(T_BOARD_HSDK_4XD))
+		return;
+
+	if (env_common.l2_cache.val)
+		slc_enable();
+	else
+		slc_disable();
+}
+
+#define CREG_CSM_BASE		(CREG_BASE + 0x210)
+
+static void init_cluster_csm(void)
+{
+	/* ARC HS38 in HSDK SoC doesn't include CSM */
+	if (!is_board_match_config(T_BOARD_HSDK_4XD))
+		return;
+
+	if (env_common.csm_location.val == NO_CCM) {
+		write_aux_reg(ARC_AUX_CSM_ENABLE, 0);
+	} else {
+		/*
+		 * CSM base address is 256kByte aligned but we allow to map
+		 * CSM only to aperture start (256MByte aligned)
+		 * The field in CREG_CSM_BASE is in 17:2 bits itself so we need
+		 * to shift it.
+		 */
+		u32 csm_base = (env_common.csm_location.val * SZ_1K) << 2;
+
+		write_aux_reg(ARC_AUX_CSM_ENABLE, 1);
+		writel(csm_base, (void __iomem *)CREG_CSM_BASE);
+	}
+}
+
 static void init_master_icache(void)
 {
 	if (icache_status()) {
@@ -279,25 +383,36 @@
 	__builtin_arc_flag(1);
 }
 
-static void smp_kick_cpu_x(u32 cpu_id)
+static u32 get_masked_cpu_ctart_reg(void)
 {
 	int cmd = readl((void __iomem *)CREG_CPU_START);
 
+	/*
+	 * Quirk for HSDK-4xD - due to HW issues HSDK can use any pulse polarity
+	 * and HSDK-4xD require active low polarity of cpu_start pulse.
+	 */
+	cmd &= ~CREG_CPU_START_POL;
+
+	cmd &= ~CREG_CPU_START_MASK;
+
+	return cmd;
+}
+
+static void smp_kick_cpu_x(u32 cpu_id)
+{
+	int cmd;
+
 	if (cpu_id > NR_CPUS)
 		return;
 
-	cmd &= ~CREG_CPU_START_MASK;
+	cmd = get_masked_cpu_ctart_reg();
 	cmd |= (1 << cpu_id);
 	writel(cmd, (void __iomem *)CREG_CPU_START);
 }
 
 static u32 prepare_cpu_ctart_reg(void)
 {
-	int cmd = readl((void __iomem *)CREG_CPU_START);
-
-	cmd &= ~CREG_CPU_START_MASK;
-
-	return cmd | env_common.core_mask.val;
+	return get_masked_cpu_ctart_reg() | env_common.core_mask.val;
 }
 
 /* slave CPU entry for configuration */
@@ -560,6 +675,61 @@
 	writel(UPDATE_VAL, CREG_PAE_UPDT);
 }
 
+/*
+ * For HSDK-4xD we do additional AXI bridge tweaking in hsdk_init command:
+ * - we shrink IOC region.
+ * - we configure HS CORE SLV1 aperture depending on haps_apb_location
+ *   environment variable.
+ *
+ * As we've already configured AXI bridge in init_memory_bridge we don't
+ * do full configuration here but reconfigure changed part.
+ *
+ * m	master		AXI_M_m_SLV0	AXI_M_m_SLV1	AXI_M_m_OFFSET0	AXI_M_m_OFFSET1
+ * 0	HS (CBU)	0x11111111	0x63111111	0xFEDCBA98	0x0E543210	[haps_apb_location = 0]
+ * 0	HS (CBU)	0x11111111	0x61111111	0xFEDCBA98	0x06543210	[haps_apb_location = 1]
+ * 1	HS (RTT)	0x77777777	0x77777777	0xFEDCBA98	0x76543210
+ * 2	AXI Tunnel	0x88888888	0x88888888	0xFEDCBA98	0x76543210
+ * 3	HDMI-VIDEO	0x77777777	0x77777777	0xFEDCBA98	0x76543210
+ * 4	HDMI-ADUIO	0x77777777	0x77777777	0xFEDCBA98	0x76543210
+ * 5	USB-HOST	0x77777777	0x77779999	0xFEDCBA98	0x7654BA98
+ * 6	ETHERNET	0x77777777	0x77779999	0xFEDCBA98	0x7654BA98
+ * 7	SDIO		0x77777777	0x77779999	0xFEDCBA98	0x7654BA98
+ * 8	GPU		0x77777777	0x77777777	0xFEDCBA98	0x76543210
+ * 9	DMAC (port #1)	0x77777777	0x77777777	0xFEDCBA98	0x76543210
+ * 10	DMAC (port #2)	0x77777777	0x77777777	0xFEDCBA98	0x76543210
+ * 11	DVFS		0x00000000	0x60000000	0x00000000	0x00000000
+ */
+void tweak_memory_bridge_cfg(void)
+{
+	/*
+	 * Only HSDK-4xD requre additional AXI bridge tweaking depending on
+	 * haps_apb_location environment variable
+	 */
+	if (!is_board_match_config(T_BOARD_HSDK_4XD))
+		return;
+
+	if (env_common.haps_apb.val) {
+		writel(0x61111111, CREG_AXI_M_SLV1(M_HS_CORE));
+		writel(0x06543210, CREG_AXI_M_OFT1(M_HS_CORE));
+	} else {
+		writel(0x63111111, CREG_AXI_M_SLV1(M_HS_CORE));
+		writel(0x0E543210, CREG_AXI_M_OFT1(M_HS_CORE));
+	}
+	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_CORE));
+
+	writel(0x77779999, CREG_AXI_M_SLV1(M_USB_HOST));
+	writel(0x7654BA98, CREG_AXI_M_OFT1(M_USB_HOST));
+	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_USB_HOST));
+
+	writel(0x77779999, CREG_AXI_M_SLV1(M_ETHERNET));;
+	writel(0x7654BA98, CREG_AXI_M_OFT1(M_ETHERNET));
+	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_ETHERNET));
+
+	writel(0x77779999, CREG_AXI_M_SLV1(M_SDIO));
+	writel(0x7654BA98, CREG_AXI_M_OFT1(M_SDIO));
+	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO));
+}
+
 static void setup_clocks(void)
 {
 	ulong rate;
@@ -593,6 +763,9 @@
 	 * cores.
 	 */
 	init_cluster_nvlim();
+	init_cluster_csm();
+	init_cluster_slc();
+	tweak_memory_bridge_cfg();
 }
 
 static int check_master_cpu_id(void)
@@ -758,6 +931,11 @@
 {
 	int ret;
 
+	if (board_mismatch()) {
+		printf("ERR: U-boot is not configured for this board!\n");
+		return CMD_RET_FAILURE;
+	}
+
 	/*
 	 * Check for 'halt' parameter. 'halt' = enter halt-mode just before
 	 * starting the application; can be used for debug.
@@ -793,20 +971,45 @@
 	"hsdk_go halt - Boot stand-alone application on HSDK, halt CPU just before application run\n"
 );
 
+/*
+ * We may simply use static variable here to store init status, but we also want
+ * to avoid the situation when we reload U-boot via MDB after previous
+ * init is done but HW reset (board reset) isn't done. So let's store the
+ * init status in any unused register (i.e CREG_CPU_0_ENTRY) so status will
+ * survive after U-boot is reloaded via MDB.
+ */
+#define INIT_MARKER_REGISTER		((void __iomem *)CREG_CPU_0_ENTRY)
+/* must be equal to INIT_MARKER_REGISTER reset value */
+#define INIT_MARKER_PENDING		0
+
+static bool init_marker_get(void)
+{
+	return readl(INIT_MARKER_REGISTER) != INIT_MARKER_PENDING;
+}
+
+static void init_mark_done(void)
+{
+	writel(~INIT_MARKER_PENDING, INIT_MARKER_REGISTER);
+}
+
 static int do_hsdk_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 {
-	static bool done = false;
 	int ret;
 
+	if (board_mismatch()) {
+		printf("ERR: U-boot is not configured for this board!\n");
+		return CMD_RET_FAILURE;
+	}
+
 	/* hsdk_init can be run only once */
-	if (done) {
+	if (init_marker_get()) {
 		printf("HSDK HW is already initialized! Please reset the board if you want to change the configuration.\n");
 		return CMD_RET_FAILURE;
 	}
 
 	ret = prepare_cpus();
 	if (!ret)
-		done = true;
+		init_mark_done();
 
 	return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
 }
@@ -911,10 +1114,13 @@
 	soc_clk_ctl("eth-clk", NULL, CLK_PRINT | CLK_MHZ);
 	soc_clk_ctl("usb-clk", NULL, CLK_PRINT | CLK_MHZ);
 	soc_clk_ctl("sdio-clk", NULL, CLK_PRINT | CLK_MHZ);
-/*	soc_clk_ctl("hdmi-sys-clk", NULL, CLK_PRINT | CLK_MHZ); */
+	if (is_board_match_runtime(T_BOARD_HSDK_4XD))
+		soc_clk_ctl("hdmi-sys-clk", NULL, CLK_PRINT | CLK_MHZ);
 	soc_clk_ctl("gfx-core-clk", NULL, CLK_PRINT | CLK_MHZ);
-	soc_clk_ctl("gfx-dma-clk", NULL, CLK_PRINT | CLK_MHZ);
-	soc_clk_ctl("gfx-cfg-clk", NULL, CLK_PRINT | CLK_MHZ);
+	if (is_board_match_runtime(T_BOARD_HSDK)) {
+		soc_clk_ctl("gfx-dma-clk", NULL, CLK_PRINT | CLK_MHZ);
+		soc_clk_ctl("gfx-cfg-clk", NULL, CLK_PRINT | CLK_MHZ);
+	}
 	soc_clk_ctl("dmac-core-clk", NULL, CLK_PRINT | CLK_MHZ);
 	soc_clk_ctl("dmac-cfg-clk", NULL, CLK_PRINT | CLK_MHZ);
 	soc_clk_ctl("sdio-ref-clk", NULL, CLK_PRINT | CLK_MHZ);
@@ -929,15 +1135,19 @@
 	printf("\n");
 
 	/* HDMI clock domain */
-/*	soc_clk_ctl("hdmi-pll", NULL, CLK_PRINT | CLK_MHZ); */
-/*	soc_clk_ctl("hdmi-clk", NULL, CLK_PRINT | CLK_MHZ); */
-/*	printf("\n"); */
+	if (is_board_match_runtime(T_BOARD_HSDK_4XD)) {
+		soc_clk_ctl("hdmi-pll", NULL, CLK_PRINT | CLK_MHZ);
+		soc_clk_ctl("hdmi-clk", NULL, CLK_PRINT | CLK_MHZ);
+		printf("\n");
+	}
 
 	/* TUN clock domain */
 	soc_clk_ctl("tun-pll", NULL, CLK_PRINT | CLK_MHZ);
 	soc_clk_ctl("tun-clk", NULL, CLK_PRINT | CLK_MHZ);
 	soc_clk_ctl("rom-clk", NULL, CLK_PRINT | CLK_MHZ);
 	soc_clk_ctl("pwm-clk", NULL, CLK_PRINT | CLK_MHZ);
+	if (is_board_match_runtime(T_BOARD_HSDK_4XD))
+		soc_clk_ctl("timer-clk", NULL, CLK_PRINT | CLK_MHZ);
 	printf("\n");
 
 	return CMD_RET_SUCCESS;
@@ -1031,6 +1241,11 @@
 
 int checkboard(void)
 {
-	puts("Board: Synopsys ARC HS Development Kit\n");
+	printf("Board: Synopsys %s\n", board_name(get_board_type_runtime()));
+
+	if (board_mismatch())
+		printf("WARN: U-boot is configured NOT for this board but for %s!\n",
+		       board_name(get_board_type_config()));
+
 	return 0;
 };
diff --git a/board/topic/zynq/Makefile b/board/topic/zynq/Makefile
index becadd2..cc100b0 100644
--- a/board/topic/zynq/Makefile
+++ b/board/topic/zynq/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 obj-y	:= board.o
+obj-y	+= ../../xilinx/common/board.o
 
 # Remove quotes
 hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
diff --git a/board/vocore/vocore2/Kconfig b/board/vocore/vocore2/Kconfig
new file mode 100644
index 0000000..baeff31
--- /dev/null
+++ b/board/vocore/vocore2/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_VOCORE2
+
+config SYS_BOARD
+	default "vocore2"
+
+config SYS_VENDOR
+	default "vocore"
+
+config SYS_CONFIG_NAME
+	default "vocore2"
+
+endif
diff --git a/board/vocore/vocore2/MAINTAINERS b/board/vocore/vocore2/MAINTAINERS
new file mode 100644
index 0000000..8472351
--- /dev/null
+++ b/board/vocore/vocore2/MAINTAINERS
@@ -0,0 +1,7 @@
+VOCORE_VOCORE2 BOARD
+M:	Mauro Condarelli <mc5686@mclink.it>
+S:	Maintained
+F: board/vocore/vocore2
+F: include/configs/vocore2.h
+F: configs/vocore2_defconfig
+F: arch/mips/dts/vocore_vocore2.dts
diff --git a/board/vocore/vocore2/Makefile b/board/vocore/vocore2/Makefile
new file mode 100644
index 0000000..70cd7a8
--- /dev/null
+++ b/board/vocore/vocore2/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += board.o
diff --git a/board/vocore/vocore2/board.c b/board/vocore/vocore2/board.c
new file mode 100644
index 0000000..27e42d1
--- /dev/null
+++ b/board/vocore/vocore2/board.c
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Mauro Condarelli <mc5686@mclink.it>
+ *
+ * Nothing actually needed here
+ */
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index e83c692..294a59d 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -8,6 +8,8 @@
 #include <asm/sections.h>
 #include <dm/uclass.h>
 #include <i2c.h>
+#include <linux/sizes.h>
+#include "board.h"
 
 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 {
@@ -71,3 +73,16 @@
 	return NULL;
 }
 #endif
+
+int board_late_init_xilinx(void)
+{
+	ulong initrd_hi;
+
+	env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
+
+	initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
+	initrd_hi = round_down(initrd_hi, SZ_16M);
+	env_set_addr("initrd_high", (void *)initrd_hi);
+
+	return 0;
+}
diff --git a/board/xilinx/common/board.h b/board/xilinx/common/board.h
new file mode 100644
index 0000000..180dfbc
--- /dev/null
+++ b/board/xilinx/common/board.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2020 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#ifndef _BOARD_XILINX_COMMON_BOARD_H
+#define _BOARD_XILINX_COMMON_BOARD_H
+
+int board_late_init_xilinx(void);
+
+#endif /* BOARD_XILINX_COMMON_BOARD_H */
diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
index 75aedb0..483e3ce 100644
--- a/board/xilinx/versal/board.c
+++ b/board/xilinx/versal/board.c
@@ -16,7 +16,7 @@
 #include <dm/device.h>
 #include <dm/uclass.h>
 #include <versalpl.h>
-#include <linux/sizes.h>
+#include "../common/board.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -82,9 +82,23 @@
 	return 0;
 }
 
-int board_late_init(void)
+static u8 versal_get_bootmode(void)
 {
+	u8 bootmode;
 	u32 reg = 0;
+
+	reg = readl(&crp_base->boot_mode_usr);
+
+	if (reg >> BOOT_MODE_ALT_SHIFT)
+		reg >>= BOOT_MODE_ALT_SHIFT;
+
+	bootmode = reg & BOOT_MODES_MASK;
+
+	return bootmode;
+}
+
+int board_late_init(void)
+{
 	u8 bootmode;
 	struct udevice *dev;
 	int bootseq = -1;
@@ -93,19 +107,13 @@
 	const char *mode;
 	char *new_targets;
 	char *env_targets;
-	ulong initrd_hi;
 
 	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 		debug("Saved variables - Skipping\n");
 		return 0;
 	}
 
-	reg = readl(&crp_base->boot_mode_usr);
-
-	if (reg >> BOOT_MODE_ALT_SHIFT)
-		reg >>= BOOT_MODE_ALT_SHIFT;
-
-	bootmode = reg & BOOT_MODES_MASK;
+	bootmode = versal_get_bootmode();
 
 	puts("Bootmode: ");
 	switch (bootmode) {
@@ -200,13 +208,7 @@
 
 	env_set("boot_targets", new_targets);
 
-	initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
-	initrd_hi = round_down(initrd_hi, SZ_16M);
-	env_set_addr("initrd_high", (void *)initrd_hi);
-
-	env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
-
-	return 0;
+	return board_late_init_xilinx();
 }
 
 int dram_init_banksize(void)
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 420a5ca..2164eac 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -17,6 +17,7 @@
 #include <zynqpl.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
+#include "../common/board.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -76,9 +77,7 @@
 
 	env_set("boot_targets", new_targets);
 
-	env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
-
-	return 0;
+	return board_late_init_xilinx();
 }
 
 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
diff --git a/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c
index 4805e5a..383e3d0 100644
--- a/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c
@@ -363,6 +363,7 @@
 	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
 	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
 	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
 	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U);
 	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U);
 	psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U);
@@ -408,7 +409,7 @@
 	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
 	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
 	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
-	psu_mask_write(0xFF180204, 0x7B3F003FU, 0x52240000U);
+	psu_mask_write(0xFF180204, 0x7B3F007FU, 0x52240000U);
 	psu_mask_write(0xFF180208, 0xFFFFE000U, 0x00B02000U);
 	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
 	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 3c92b1a..a2a0d56 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -26,7 +26,7 @@
 #include <zynqmppl.h>
 #include <zynqmp_firmware.h>
 #include <g_dnl.h>
-#include <linux/sizes.h>
+#include "../common/board.h"
 
 #include "pm_cfg_obj.h"
 
@@ -552,9 +552,26 @@
 	return 0;
 }
 
-int board_late_init(void)
+static u8 zynqmp_get_bootmode(void)
 {
+	u8 bootmode;
 	u32 reg = 0;
+	int ret;
+
+	ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
+	if (ret)
+		return -EINVAL;
+
+	if (reg >> BOOT_MODE_ALT_SHIFT)
+		reg >>= BOOT_MODE_ALT_SHIFT;
+
+	bootmode = reg & BOOT_MODES_MASK;
+
+	return bootmode;
+}
+
+int board_late_init(void)
+{
 	u8 bootmode;
 	struct udevice *dev;
 	int bootseq = -1;
@@ -564,7 +581,6 @@
 	char *new_targets;
 	char *env_targets;
 	int ret;
-	ulong initrd_hi;
 
 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
 	usb_ether_init();
@@ -579,14 +595,7 @@
 	if (ret)
 		return ret;
 
-	ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
-	if (ret)
-		return -EINVAL;
-
-	if (reg >> BOOT_MODE_ALT_SHIFT)
-		reg >>= BOOT_MODE_ALT_SHIFT;
-
-	bootmode = reg & BOOT_MODES_MASK;
+	bootmode = zynqmp_get_bootmode();
 
 	puts("Bootmode: ");
 	switch (bootmode) {
@@ -691,15 +700,9 @@
 
 	env_set("boot_targets", new_targets);
 
-	initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
-	initrd_hi = round_down(initrd_hi, SZ_16M);
-	env_set_addr("initrd_high", (void *)initrd_hi);
-
-	env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
-
 	reset_reason();
 
-	return 0;
+	return board_late_init_xilinx();
 }
 #endif
 
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 6ce9e55..157a330 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -190,6 +190,20 @@
 
 menu "Info commands"
 
+config CMD_ACPI
+	bool "acpi"
+	default y if ACPIGEN
+	help
+	  List and dump ACPI tables. ACPI (Advanced Configuration and Power
+	  Interface) is used mostly on x86 for providing information to the
+	  Operating System about devices in the system. The tables are set up
+	  by the firmware, typically U-Boot but possibly an earlier firmware
+	  module, if U-Boot is chain-loaded from something else. ACPI tables
+	  can also include code, to perform hardware-specific tasks required
+	  by the Operating Systems. This allows some amount of separation
+	  between the firmware and OS, and is particularly useful when you
+	  want to make hardware changes without the OS needing to be adjusted.
+
 config CMD_BDI
 	bool "bdinfo"
 	default y
diff --git a/cmd/Makefile b/cmd/Makefile
index 6692ed9..974ad48 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -11,6 +11,7 @@
 obj-y += version.o
 
 # command
+obj-$(CONFIG_CMD_ACPI) += acpi.o
 obj-$(CONFIG_CMD_AES) += aes.o
 obj-$(CONFIG_CMD_AB_SELECT) += ab_select.o
 obj-$(CONFIG_CMD_ADC) += adc.o
diff --git a/cmd/acpi.c b/cmd/acpi.c
new file mode 100644
index 0000000..203bd93
--- /dev/null
+++ b/cmd/acpi.c
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+#include <common.h>
+#include <command.h>
+#include <mapmem.h>
+#include <acpi/acpi_table.h>
+#include <asm/acpi_table.h>
+#include <dm/acpi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * dump_hdr() - Dump an ACPI header
+ *
+ * If the header is for FACS then it shows the revision information as well
+ *
+ * @hdr: ACPI header to dump
+ */
+static void dump_hdr(struct acpi_table_header *hdr)
+{
+	bool has_hdr = memcmp(hdr->signature, "FACS", ACPI_NAME_LEN);
+
+	printf("%.*s %08lx %06x", ACPI_NAME_LEN, hdr->signature,
+	       (ulong)map_to_sysmem(hdr), hdr->length);
+	if (has_hdr) {
+		printf(" (v%02d %.6s %.8s %u %.4s %d)\n", hdr->revision,
+		       hdr->oem_id, hdr->oem_table_id, hdr->oem_revision,
+		       hdr->aslc_id, hdr->aslc_revision);
+	} else {
+		printf("\n");
+	}
+}
+
+/**
+ * find_table() - Look up an ACPI table
+ *
+ * @sig: Signature of table (4 characters, upper case)
+ * @return pointer to table header, or NULL if not found
+ */
+struct acpi_table_header *find_table(const char *sig)
+{
+	struct acpi_rsdp *rsdp;
+	struct acpi_rsdt *rsdt;
+	int len, i, count;
+
+	rsdp = map_sysmem(gd->arch.acpi_start, 0);
+	if (!rsdp)
+		return NULL;
+	rsdt = map_sysmem(rsdp->rsdt_address, 0);
+	len = rsdt->header.length - sizeof(rsdt->header);
+	count = len / sizeof(u32);
+	for (i = 0; i < count; i++) {
+		struct acpi_table_header *hdr;
+
+		hdr = map_sysmem(rsdt->entry[i], 0);
+		if (!memcmp(hdr->signature, sig, ACPI_NAME_LEN))
+			return hdr;
+		if (!memcmp(hdr->signature, "FACP", ACPI_NAME_LEN)) {
+			struct acpi_fadt *fadt = (struct acpi_fadt *)hdr;
+
+			if (!memcmp(sig, "DSDT", ACPI_NAME_LEN) && fadt->dsdt)
+				return map_sysmem(fadt->dsdt, 0);
+			if (!memcmp(sig, "FACS", ACPI_NAME_LEN) &&
+			    fadt->firmware_ctrl)
+				return map_sysmem(fadt->firmware_ctrl, 0);
+		}
+	}
+
+	return NULL;
+}
+
+static int dump_table_name(const char *sig)
+{
+	struct acpi_table_header *hdr;
+
+	hdr = find_table(sig);
+	if (!hdr)
+		return -ENOENT;
+	printf("%.*s @ %08lx\n", ACPI_NAME_LEN, hdr->signature,
+	       (ulong)map_to_sysmem(hdr));
+	print_buffer(0, hdr, 1, hdr->length, 0);
+
+	return 0;
+}
+
+static void list_fadt(struct acpi_fadt *fadt)
+{
+	if (fadt->dsdt)
+		dump_hdr(map_sysmem(fadt->dsdt, 0));
+	if (fadt->firmware_ctrl)
+		dump_hdr(map_sysmem(fadt->firmware_ctrl, 0));
+}
+
+static int list_rsdt(struct acpi_rsdt *rsdt, struct acpi_xsdt *xsdt)
+{
+	int len, i, count;
+
+	dump_hdr(&rsdt->header);
+	if (xsdt)
+		dump_hdr(&xsdt->header);
+	len = rsdt->header.length - sizeof(rsdt->header);
+	count = len / sizeof(u32);
+	for (i = 0; i < count; i++) {
+		struct acpi_table_header *hdr;
+
+		if (!rsdt->entry[i])
+			break;
+		hdr = map_sysmem(rsdt->entry[i], 0);
+		dump_hdr(hdr);
+		if (!memcmp(hdr->signature, "FACP", ACPI_NAME_LEN))
+			list_fadt((struct acpi_fadt *)hdr);
+		if (xsdt) {
+			if (xsdt->entry[i] != rsdt->entry[i]) {
+				printf("   (xsdt mismatch %llx)\n",
+				       xsdt->entry[i]);
+			}
+		}
+	}
+
+	return 0;
+}
+
+static int list_rsdp(struct acpi_rsdp *rsdp)
+{
+	struct acpi_rsdt *rsdt;
+	struct acpi_xsdt *xsdt;
+
+	printf("RSDP %08lx %06x (v%02d %.6s)\n", (ulong)map_to_sysmem(rsdp),
+	       rsdp->length, rsdp->revision, rsdp->oem_id);
+	rsdt = map_sysmem(rsdp->rsdt_address, 0);
+	xsdt = map_sysmem(rsdp->xsdt_address, 0);
+	list_rsdt(rsdt, xsdt);
+
+	return 0;
+}
+
+static int do_acpi_list(cmd_tbl_t *cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	struct acpi_rsdp *rsdp;
+
+	rsdp = map_sysmem(gd->arch.acpi_start, 0);
+	if (!rsdp) {
+		printf("No ACPI tables present\n");
+		return 0;
+	}
+	printf("ACPI tables start at %lx\n", gd->arch.acpi_start);
+	list_rsdp(rsdp);
+
+	return 0;
+}
+
+static int do_acpi_dump(cmd_tbl_t *cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	const char *name;
+	char sig[ACPI_NAME_LEN];
+	int ret;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+	name = argv[1];
+	if (strlen(name) != ACPI_NAME_LEN) {
+		printf("Table name '%s' must be four characters\n", name);
+		return CMD_RET_FAILURE;
+	}
+	str_to_upper(name, sig, -1);
+	ret = dump_table_name(sig);
+	if (ret) {
+		printf("Table '%.*s' not found\n", ACPI_NAME_LEN, sig);
+		return CMD_RET_FAILURE;
+	}
+
+	return 0;
+}
+
+static char acpi_help_text[] =
+	"list - list ACPI tables\n"
+	"acpi dump <name> - Dump ACPI table";
+
+U_BOOT_CMD_WITH_SUBCMDS(acpi, "ACPI tables", acpi_help_text,
+	U_BOOT_SUBCMD_MKENT(list, 1, 1, do_acpi_list),
+	U_BOOT_SUBCMD_MKENT(dump, 2, 1, do_acpi_dump));
diff --git a/cmd/bedbug.c b/cmd/bedbug.c
index 9fee528..d3e3121 100644
--- a/cmd/bedbug.c
+++ b/cmd/bedbug.c
@@ -44,10 +44,10 @@
  * settings.
  * ====================================================================== */
 
-void bedbug_init (void)
+int bedbug_init(void)
 {
 	/* -------------------------------------------------- */
-	return;
+	return 0;
 }				/* bedbug_init */
 
 
diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index aaed575..54b4b8f 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -481,10 +481,8 @@
 	ret = do_bootefi_exec(handle);
 
 out:
-	if (mem_handle)
-		efi_delete_handle(mem_handle);
-	if (file_path)
-		efi_free_pool(file_path);
+	efi_delete_handle(mem_handle);
+	efi_free_pool(file_path);
 	return ret;
 }
 
diff --git a/cmd/efidebug.c b/cmd/efidebug.c
index 02ef019..d4030fe 100644
--- a/cmd/efidebug.c
+++ b/cmd/efidebug.c
@@ -395,6 +395,7 @@
 	[EFI_MMAP_IO] = "IO",
 	[EFI_MMAP_IO_PORT] = "IO PORT",
 	[EFI_PAL_CODE] = "PAL",
+	[EFI_PERSISTENT_MEMORY_TYPE] = "PERSISTENT",
 };
 
 static const struct efi_mem_attrs {
@@ -482,7 +483,7 @@
 	printf("================ %.*s %.*s ==========\n",
 	       EFI_PHYS_ADDR_WIDTH, sep, EFI_PHYS_ADDR_WIDTH, sep);
 	for (i = 0, map = memmap; i < map_size / sizeof(*map); map++, i++) {
-		if (map->type < EFI_MAX_MEMORY_TYPE)
+		if (map->type < ARRAY_SIZE(efi_mem_type_string))
 			type = efi_mem_type_string[map->type];
 		else
 			type = "(unknown)";
@@ -682,13 +683,13 @@
 /**
  * show_efi_boot_opt_data() - dump UEFI load option
  *
- * @id:		load option number
+ * @varname16:	variable name
  * @data:	value of UEFI load option variable
  * @size:	size of the boot option
  *
  * Decode the value of UEFI load option variable and print information.
  */
-static void show_efi_boot_opt_data(int id, void *data, size_t size)
+static void show_efi_boot_opt_data(u16 *varname16, void *data, size_t size)
 {
 	struct efi_load_option lo;
 	char *label, *p;
@@ -705,8 +706,8 @@
 	p = label;
 	utf16_utf8_strncpy(&p, lo.label, label_len16);
 
-	printf("Boot%04X:\n", id);
-	printf("  attributes: %c%c%c (0x%08x)\n",
+	printf("%ls:\nattributes: %c%c%c (0x%08x)\n",
+	       varname16,
 	       /* ACTIVE */
 	       lo.attributes & LOAD_OPTION_ACTIVE ? 'A' : '-',
 	       /* FORCE RECONNECT */
@@ -730,37 +731,32 @@
 /**
  * show_efi_boot_opt() - dump UEFI load option
  *
- * @id:		Load option number
+ * @varname16:	variable name
  *
  * Dump information defined by UEFI load option.
  */
-static void show_efi_boot_opt(int id)
+static void show_efi_boot_opt(u16 *varname16)
 {
-	char var_name[9];
-	u16 var_name16[9], *p;
-	efi_guid_t guid;
-	void *data = NULL;
+	void *data;
 	efi_uintn_t size;
 	efi_status_t ret;
 
-	sprintf(var_name, "Boot%04X", id);
-	p = var_name16;
-	utf8_utf16_strncpy(&p, var_name, 9);
-	guid = efi_global_variable_guid;
-
 	size = 0;
-	ret = EFI_CALL(RT->get_variable(var_name16, &guid, NULL, &size, NULL));
+	ret = EFI_CALL(efi_get_variable(varname16, &efi_global_variable_guid,
+					NULL, &size, NULL));
 	if (ret == EFI_BUFFER_TOO_SMALL) {
 		data = malloc(size);
-		ret = EFI_CALL(RT->get_variable(var_name16, &guid, NULL, &size,
-						data));
+		if (!data) {
+			printf("ERROR: Out of memory\n");
+			return;
+		}
+		ret = EFI_CALL(efi_get_variable(varname16,
+						&efi_global_variable_guid,
+						NULL, &size, data));
+		if (ret == EFI_SUCCESS)
+			show_efi_boot_opt_data(varname16, data, size);
+		free(data);
 	}
-	if (ret == EFI_SUCCESS)
-		show_efi_boot_opt_data(id, data, size);
-	else if (ret == EFI_NOT_FOUND)
-		printf("Boot%04X: not found\n", id);
-
-	free(data);
 }
 
 static int u16_tohex(u16 c)
@@ -839,7 +835,7 @@
 			id = (id << 4) + digit;
 		}
 		if (i == 4 && !var_name16[8])
-			show_efi_boot_opt(id);
+			show_efi_boot_opt(var_name16);
 	}
 
 	free(var_name16);
@@ -856,8 +852,7 @@
  */
 static int show_efi_boot_order(void)
 {
-	efi_guid_t guid;
-	u16 *bootorder = NULL;
+	u16 *bootorder;
 	efi_uintn_t size;
 	int num, i;
 	char var_name[9];
@@ -868,20 +863,25 @@
 	size_t label_len16, label_len;
 	efi_status_t ret;
 
-	guid = efi_global_variable_guid;
 	size = 0;
-	ret = EFI_CALL(RT->get_variable(L"BootOrder", &guid, NULL, &size,
-					NULL));
-	if (ret == EFI_BUFFER_TOO_SMALL) {
-		bootorder = malloc(size);
-		ret = EFI_CALL(RT->get_variable(L"BootOrder", &guid, NULL,
-						&size, bootorder));
+	ret = EFI_CALL(RT->get_variable(L"BootOrder", &efi_global_variable_guid,
+					NULL, &size, NULL));
+	if (ret != EFI_BUFFER_TOO_SMALL) {
+		if (ret == EFI_NOT_FOUND) {
+			printf("BootOrder not defined\n");
+			return CMD_RET_SUCCESS;
+		} else {
+			return CMD_RET_FAILURE;
+		}
 	}
-	if (ret == EFI_NOT_FOUND) {
-		printf("BootOrder not defined\n");
-		ret = CMD_RET_SUCCESS;
-		goto out;
-	} else if (ret != EFI_SUCCESS) {
+	bootorder = malloc(size);
+	if (!bootorder) {
+		printf("ERROR: Out of memory\n");
+		return CMD_RET_FAILURE;
+	}
+	ret = EFI_CALL(efi_get_variable(L"BootOrder", &efi_global_variable_guid,
+					NULL, &size, bootorder));
+	if (ret != EFI_SUCCESS) {
 		ret = CMD_RET_FAILURE;
 		goto out;
 	}
@@ -893,11 +893,11 @@
 		utf8_utf16_strncpy(&p16, var_name, 9);
 
 		size = 0;
-		ret = EFI_CALL(RT->get_variable(var_name16, &guid, NULL, &size,
-						NULL));
+		ret = EFI_CALL(efi_get_variable(var_name16,
+						&efi_global_variable_guid, NULL,
+						&size, NULL));
 		if (ret != EFI_BUFFER_TOO_SMALL) {
-			printf("%2d: Boot%04X: (not defined)\n",
-			       i + 1, bootorder[i]);
+			printf("%2d: %s: (not defined)\n", i + 1, var_name);
 			continue;
 		}
 
@@ -906,8 +906,9 @@
 			ret = CMD_RET_FAILURE;
 			goto out;
 		}
-		ret = EFI_CALL(RT->get_variable(var_name16, &guid, NULL, &size,
-						data));
+		ret = EFI_CALL(efi_get_variable(var_name16,
+						&efi_global_variable_guid, NULL,
+						&size, data));
 		if (ret != EFI_SUCCESS) {
 			free(data);
 			ret = CMD_RET_FAILURE;
@@ -926,7 +927,7 @@
 		}
 		p = label;
 		utf16_utf8_strncpy(&p, lo.label, label_len16);
-		printf("%2d: Boot%04X: %s\n", i + 1, bootorder[i], label);
+		printf("%2d: %s: %s\n", i + 1, var_name, label);
 		free(label);
 
 		free(data);
diff --git a/cmd/gpt.c b/cmd/gpt.c
index efaf1bc..b8d11c1 100644
--- a/cmd/gpt.c
+++ b/cmd/gpt.c
@@ -245,7 +245,7 @@
 		printf("Block size %lu, name %s\n", curr->gpt_part_info.blksz,
 		       curr->gpt_part_info.name);
 		printf("Type %s, bootable %d\n", curr->gpt_part_info.type,
-		       curr->gpt_part_info.bootable);
+		       curr->gpt_part_info.bootable & PART_BOOTABLE);
 #ifdef CONFIG_PARTITION_UUIDS
 		printf("UUID %s\n", curr->gpt_part_info.uuid);
 #endif
@@ -535,7 +535,7 @@
 
 		/* bootable */
 		if (found_key(tok, "bootable"))
-			parts[i].bootable = 1;
+			parts[i].bootable = PART_BOOTABLE;
 	}
 
 	*parts_count = p_count;
@@ -772,11 +772,9 @@
  out:
 	del_gpt_info();
 #ifdef CONFIG_RANDOM_UUID
-	if (str_disk_guid)
-		free(str_disk_guid);
+	free(str_disk_guid);
 #endif
-	if (new_partitions)
-		free(new_partitions);
+	free(new_partitions);
 	free(partitions_list);
 	return ret;
 }
diff --git a/cmd/mem.c b/cmd/mem.c
index 0bfb608..009b7b5 100644
--- a/cmd/mem.c
+++ b/cmd/mem.c
@@ -1144,10 +1144,8 @@
 	unsigned char *buf8;
 	unsigned int i;
 
-	if (argc < 3 || argc > 4) {
-		printf("usage: %s <addr> <len> [<seed>]\n", argv[0]);
-		return 0;
-	}
+	if (argc < 3 || argc > 4)
+		return CMD_RET_USAGE;
 
 	len = simple_strtoul(argv[2], NULL, 16);
 	addr = simple_strtoul(argv[1], NULL, 16);
@@ -1174,7 +1172,8 @@
 
 	unmap_sysmem(start);
 	printf("%lu bytes filled with random data\n", len);
-	return 1;
+
+	return CMD_RET_SUCCESS;
 }
 #endif
 
diff --git a/common/Makefile b/common/Makefile
index 3471c47..2e7a090 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -110,6 +110,7 @@
 obj-$(CONFIG_ANDROID_AB) += android_ab.o
 obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o image-android-dt.o
 obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += image-fdt.o
+obj-$(CONFIG_$(SPL_TPL_)FIT_SIGNATURE) += fdt_region.o
 obj-$(CONFIG_$(SPL_TPL_)FIT) += image-fit.o
 obj-$(CONFIG_$(SPL_)MULTI_DTB_FIT) += boot_fit.o common_fit.o
 obj-$(CONFIG_$(SPL_TPL_)IMAGE_SIGN_INFO) += image-sig.o
diff --git a/common/board_r.c b/common/board_r.c
index 0bbeaa7..d9015cd 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -518,15 +518,6 @@
 }
 #endif
 
-/* enable exceptions */
-#ifdef CONFIG_ARM
-static int initr_enable_interrupts(void)
-{
-	enable_interrupts();
-	return 0;
-}
-#endif
-
 #ifdef CONFIG_CMD_NET
 static int initr_ethaddr(void)
 {
@@ -646,15 +637,6 @@
 }
 #endif
 
-#ifdef CONFIG_CMD_BEDBUG
-static int initr_bedbug(void)
-{
-	bedbug_init();
-
-	return 0;
-}
-#endif
-
 static int run_main_loop(void)
 {
 #ifdef CONFIG_SANDBOX
@@ -813,9 +795,6 @@
 	initr_kgdb,
 #endif
 	interrupt_init,
-#ifdef CONFIG_ARM
-	initr_enable_interrupts,
-#endif
 #if defined(CONFIG_MICROBLAZE) || defined(CONFIG_M68K)
 	timer_init,		/* initialize timer */
 #endif
@@ -860,7 +839,7 @@
 #endif
 #ifdef CONFIG_CMD_BEDBUG
 	INIT_FUNC_WATCHDOG_RESET
-	initr_bedbug,
+	bedbug_init,
 #endif
 #if defined(CONFIG_PRAM)
 	initr_mem,
diff --git a/common/cli_hush.c b/common/cli_hush.c
index cf1e273..a62af07 100644
--- a/common/cli_hush.c
+++ b/common/cli_hush.c
@@ -1849,8 +1849,7 @@
 				continue;
 			} else {
 				/* insert new value from list for variable */
-				if (pi->progs->argv[0])
-					free(pi->progs->argv[0]);
+				free(pi->progs->argv[0]);
 				pi->progs->argv[0] = *list++;
 #ifndef __U_BOOT__
 				pi->progs->glob_result.gl_pathv[0] =
diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index db5ab55..e8f07f1 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -280,6 +280,7 @@
 	    |             Unused space (may be 0 bytes long)                .
 	    .                                                               .
 	    .                                                               |
+
 nextchunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
     `foot:' |             Size of chunk, in bytes                           |
 	    +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -574,6 +575,10 @@
 static inline void malloc_bin_reloc(void) {}
 #endif
 
+#ifdef CONFIG_SYS_MALLOC_DEFAULT_TO_INIT
+static void malloc_init(void);
+#endif
+
 ulong mem_malloc_start = 0;
 ulong mem_malloc_end = 0;
 ulong mem_malloc_brk = 0;
@@ -604,6 +609,10 @@
 	mem_malloc_end = start + size;
 	mem_malloc_brk = start;
 
+#ifdef CONFIG_SYS_MALLOC_DEFAULT_TO_INIT
+	malloc_init();
+#endif
+
 	debug("using memory %#lx-%#lx for malloc()\n", mem_malloc_start,
 	      mem_malloc_end);
 #ifdef CONFIG_SYS_MALLOC_CLEAR_ON_INIT
@@ -708,7 +717,36 @@
 static unsigned long max_mmapped_mem = 0;
 #endif
 
+#ifdef CONFIG_SYS_MALLOC_DEFAULT_TO_INIT
+static void malloc_init(void)
+{
+	int i, j;
+
+	debug("bins (av_ array) are at %p\n", (void *)av_);
+
+	av_[0] = NULL; av_[1] = NULL;
+	for (i = 2, j = 2; i < NAV * 2 + 2; i += 2, j++) {
+		av_[i] = bin_at(j - 2);
+		av_[i + 1] = bin_at(j - 2);
 
+		/* Just print the first few bins so that
+		 * we can see there are alright.
+		 */
+		if (i < 10)
+			debug("av_[%d]=%lx av_[%d]=%lx\n",
+			      i, (ulong)av_[i],
+			      i + 1, (ulong)av_[i + 1]);
+	}
+
+	/* Init the static bookkeeping as well */
+	sbrk_base = (char *)(-1);
+	max_sbrked_mem = 0;
+	max_total_mem = 0;
+#ifdef DEBUG
+	memset((void *)&current_mallinfo, 0, sizeof(struct mallinfo));
+#endif
+}
+#endif
 
 /*
   Debugging support
@@ -1051,9 +1089,6 @@
 
 #endif /* HAVE_MMAP */
 
-
-
-
 /*
   Extend the top-most chunk by obtaining memory from system.
   Main interface to sbrk (but see also malloc_trim).
diff --git a/lib/libfdt/fdt_region.c b/common/fdt_region.c
similarity index 99%
rename from lib/libfdt/fdt_region.c
rename to common/fdt_region.c
index 7e9fa92..bf0a9be 100644
--- a/lib/libfdt/fdt_region.c
+++ b/common/fdt_region.c
@@ -6,6 +6,7 @@
  */
 
 #include <linux/libfdt_env.h>
+#include <fdt_region.h>
 
 #ifndef USE_HOSTCC
 #include <fdt.h>
diff --git a/common/image-fit-sig.c b/common/image-fit-sig.c
index 490566c..a3a0c61 100644
--- a/common/image-fit-sig.c
+++ b/common/image-fit-sig.c
@@ -11,6 +11,7 @@
 #include <malloc.h>
 DECLARE_GLOBAL_DATA_PTR;
 #endif /* !USE_HOSTCC*/
+#include <fdt_region.h>
 #include <image.h>
 #include <u-boot/rsa.h>
 #include <u-boot/rsa-checksum.h>
@@ -248,7 +249,7 @@
 				int required_keynode, int conf_noffset,
 				char **err_msgp)
 {
-	char * const exc_prop[] = {"data"};
+	char * const exc_prop[] = {"data", "data-size", "data-position"};
 	const char *prop, *end, *name;
 	struct image_sign_info info;
 	const uint32_t *strings;
diff --git a/common/log.c b/common/log.c
index ffb3cd6..c5b9b48 100644
--- a/common/log.c
+++ b/common/log.c
@@ -233,7 +233,7 @@
 	ldev = log_device_find_by_name(drv_name);
 	if (!ldev)
 		return -ENOENT;
-	filt = (struct log_filter *)calloc(1, sizeof(*filt));
+	filt = calloc(1, sizeof(*filt));
 	if (!filt)
 		return -ENOMEM;
 
diff --git a/common/spl/Makefile b/common/spl/Makefile
index eaa57f5..c576a78 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -10,6 +10,7 @@
 obj-$(CONFIG_$(SPL_TPL_)FRAMEWORK) += spl.o
 obj-$(CONFIG_$(SPL_TPL_)BOOTROM_SUPPORT) += spl_bootrom.o
 obj-$(CONFIG_$(SPL_TPL_)LOAD_FIT) += spl_fit.o
+obj-$(CONFIG_$(SPL_TPL_)LEGACY_IMAGE_SUPPORT) += spl_legacy.o
 obj-$(CONFIG_$(SPL_TPL_)NOR_SUPPORT) += spl_nor.o
 obj-$(CONFIG_$(SPL_TPL_)XIP_SUPPORT) += spl_xip.o
 obj-$(CONFIG_$(SPL_TPL_)YMODEM_SUPPORT) += spl_ymodem.o
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 932e6ab..b0f0e15 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -254,6 +254,14 @@
 }
 #endif
 
+__weak int spl_parse_legacy_header(struct spl_image_info *spl_image,
+				   const struct image_header *header)
+{
+	/* LEGACY image not supported */
+	debug("Legacy boot image support not enabled, proceeding to other boot methods\n");
+	return -EINVAL;
+}
+
 int spl_parse_image_header(struct spl_image_info *spl_image,
 			   const struct image_header *header)
 {
@@ -264,51 +272,11 @@
 		return ret;
 #endif
 	if (image_get_magic(header) == IH_MAGIC) {
-#ifdef CONFIG_SPL_LEGACY_IMAGE_SUPPORT
-		u32 header_size = sizeof(struct image_header);
+		int ret;
 
-#ifdef CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK
-		/* check uImage header CRC */
-		if (!image_check_hcrc(header)) {
-			puts("SPL: Image header CRC check failed!\n");
-			return -EINVAL;
-		}
-#endif
-
-		if (spl_image->flags & SPL_COPY_PAYLOAD_ONLY) {
-			/*
-			 * On some system (e.g. powerpc), the load-address and
-			 * entry-point is located at address 0. We can't load
-			 * to 0-0x40. So skip header in this case.
-			 */
-			spl_image->load_addr = image_get_load(header);
-			spl_image->entry_point = image_get_ep(header);
-			spl_image->size = image_get_data_size(header);
-		} else {
-			spl_image->entry_point = image_get_ep(header);
-			/* Load including the header */
-			spl_image->load_addr = image_get_load(header) -
-				header_size;
-			spl_image->size = image_get_data_size(header) +
-				header_size;
-		}
-#ifdef CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK
-		/* store uImage data length and CRC to check later */
-		spl_image->dcrc_data = image_get_load(header);
-		spl_image->dcrc_length = image_get_data_size(header);
-		spl_image->dcrc = image_get_dcrc(header);
-#endif
-
-		spl_image->os = image_get_os(header);
-		spl_image->name = image_get_name(header);
-		debug(SPL_TPL_PROMPT
-		      "payload image: %32s load addr: 0x%lx size: %d\n",
-		      spl_image->name, spl_image->load_addr, spl_image->size);
-#else
-		/* LEGACY image not supported */
-		debug("Legacy boot image support not enabled, proceeding to other boot methods\n");
-		return -EINVAL;
-#endif
+		ret = spl_parse_legacy_header(spl_image, header);
+		if (ret)
+			return ret;
 	} else {
 #ifdef CONFIG_SPL_PANIC_ON_RAW_IMAGE
 		/*
diff --git a/common/spl/spl_legacy.c b/common/spl/spl_legacy.c
new file mode 100644
index 0000000..29d3ec7
--- /dev/null
+++ b/common/spl/spl_legacy.c
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spl.h>
+
+#include <lzma/LzmaTypes.h>
+#include <lzma/LzmaDec.h>
+#include <lzma/LzmaTools.h>
+
+#define LZMA_LEN	(1 << 20)
+
+int spl_parse_legacy_header(struct spl_image_info *spl_image,
+			    const struct image_header *header)
+{
+	u32 header_size = sizeof(struct image_header);
+
+	/* check uImage header CRC */
+	if (IS_ENABLED(CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK) &&
+	    !image_check_hcrc(header)) {
+		puts("SPL: Image header CRC check failed!\n");
+		return -EINVAL;
+	}
+
+	if (spl_image->flags & SPL_COPY_PAYLOAD_ONLY) {
+		/*
+		 * On some system (e.g. powerpc), the load-address and
+		 * entry-point is located at address 0. We can't load
+		 * to 0-0x40. So skip header in this case.
+		 */
+		spl_image->load_addr = image_get_load(header);
+		spl_image->entry_point = image_get_ep(header);
+		spl_image->size = image_get_data_size(header);
+	} else {
+		spl_image->entry_point = image_get_ep(header);
+		/* Load including the header */
+		spl_image->load_addr = image_get_load(header) -
+			header_size;
+		spl_image->size = image_get_data_size(header) +
+			header_size;
+	}
+
+#ifdef CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK
+	/* store uImage data length and CRC to check later */
+	spl_image->dcrc_data = image_get_load(header);
+	spl_image->dcrc_length = image_get_data_size(header);
+	spl_image->dcrc = image_get_dcrc(header);
+#endif
+
+	spl_image->os = image_get_os(header);
+	spl_image->name = image_get_name(header);
+	debug(SPL_TPL_PROMPT
+	      "payload image: %32s load addr: 0x%lx size: %d\n",
+	      spl_image->name, spl_image->load_addr, spl_image->size);
+
+	return 0;
+}
+
+/*
+ * This function is added explicitly to avoid code size increase, when
+ * no compression method is enabled. The compiler will optimize the
+ * following switch/case statement in spl_load_legacy_img() away due to
+ * Dead Code Elimination.
+ */
+static inline int spl_image_get_comp(const struct image_header *hdr)
+{
+	if (IS_ENABLED(CONFIG_SPL_LZMA))
+		return image_get_comp(hdr);
+
+	return IH_COMP_NONE;
+}
+
+int spl_load_legacy_img(struct spl_image_info *spl_image,
+			struct spl_load_info *load, ulong header)
+{
+	__maybe_unused SizeT lzma_len;
+	__maybe_unused void *src;
+	struct image_header hdr;
+	ulong dataptr;
+	int ret;
+
+	/* Read header into local struct */
+	load->read(load, header, sizeof(hdr), &hdr);
+
+	ret = spl_parse_image_header(spl_image, &hdr);
+	if (ret)
+		return ret;
+
+	dataptr = header + sizeof(hdr);
+
+	/* Read image */
+	switch (spl_image_get_comp(&hdr)) {
+	case IH_COMP_NONE:
+		load->read(load, dataptr, spl_image->size,
+			   (void *)(unsigned long)spl_image->load_addr);
+		break;
+
+	case IH_COMP_LZMA:
+		lzma_len = LZMA_LEN;
+
+		debug("LZMA: Decompressing %08lx to %08lx\n",
+		      dataptr, spl_image->load_addr);
+		src = malloc(spl_image->size);
+		if (!src) {
+			printf("Unable to allocate %d bytes for LZMA\n",
+			       spl_image->size);
+			return -ENOMEM;
+		}
+
+		load->read(load, dataptr, spl_image->size, src);
+		ret = lzmaBuffToBuffDecompress((void *)spl_image->load_addr,
+					       &lzma_len, src, spl_image->size);
+		if (ret) {
+			printf("LZMA decompression error: %d\n", ret);
+			return ret;
+		}
+
+		spl_image->size = lzma_len;
+		break;
+
+	default:
+		debug("Compression method %s is not supported\n",
+		      genimg_get_comp_short_name(image_get_comp(&hdr)));
+		return -EINVAL;
+	}
+
+	return 0;
+}
diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c
index b1e79b9..3f03ffe 100644
--- a/common/spl/spl_nor.c
+++ b/common/spl/spl_nor.c
@@ -24,7 +24,6 @@
 static int spl_nor_load_image(struct spl_image_info *spl_image,
 			      struct spl_boot_device *bootdev)
 {
-	int ret;
 	__maybe_unused const struct image_header *header;
 	__maybe_unused struct spl_load_info load;
 
@@ -43,6 +42,8 @@
 		header = (const struct image_header *)CONFIG_SYS_OS_BASE;
 #ifdef CONFIG_SPL_LOAD_FIT
 		if (image_get_magic(header) == FDT_MAGIC) {
+			int ret;
+
 			debug("Found FIT\n");
 			load.bl_len = 1;
 			load.read = spl_nor_load_read;
@@ -61,6 +62,7 @@
 #endif
 		if (image_get_os(header) == IH_OS_LINUX) {
 			/* happy - was a Linux */
+			int ret;
 
 			ret = spl_parse_image_header(spl_image, header);
 			if (ret)
@@ -93,11 +95,9 @@
 		debug("Found FIT format U-Boot\n");
 		load.bl_len = 1;
 		load.read = spl_nor_load_read;
-		ret = spl_load_simple_fit(spl_image, &load,
-					  spl_nor_get_uboot_base(),
-					  (void *)header);
-
-		return ret;
+		return spl_load_simple_fit(spl_image, &load,
+					   spl_nor_get_uboot_base(),
+					   (void *)header);
 	}
 #endif
 	if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) {
@@ -107,14 +107,13 @@
 					      spl_nor_get_uboot_base());
 	}
 
-	ret = spl_parse_image_header(spl_image,
-			(const struct image_header *)spl_nor_get_uboot_base());
-	if (ret)
-		return ret;
-
-	memcpy((void *)(unsigned long)spl_image->load_addr,
-	       (void *)(spl_nor_get_uboot_base() + sizeof(struct image_header)),
-	       spl_image->size);
+	/* Legacy image handling */
+	if (IS_ENABLED(CONFIG_SPL_LEGACY_IMAGE_SUPPORT)) {
+		load.bl_len = 1;
+		load.read = spl_nor_load_read;
+		return spl_load_legacy_img(spl_image, &load,
+					   spl_nor_get_uboot_base());
+	}
 
 	return 0;
 }
diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig
index bb68698..e1b6677 100644
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -17,7 +17,6 @@
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino"
 CONFIG_DFU_RAM=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
index 40b3883..3e0a53f 100644
--- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
+++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
@@ -15,11 +15,11 @@
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2-emmc"
 CONFIG_SCSI_AHCI=y
 CONFIG_DFU_RAM=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig
index 2b082ca..6935fc6 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -13,11 +13,12 @@
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2"
 CONFIG_SCSI_AHCI=y
 CONFIG_DFU_RAM=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig
index 975df4e..950c948 100644
--- a/configs/A20-OLinuXino-Lime_defconfig
+++ b/configs/A20-OLinuXino-Lime_defconfig
@@ -11,6 +11,7 @@
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime"
 CONFIG_SCSI_AHCI=y
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
index 0ccb609..3317ace 100644
--- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig
+++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
@@ -13,6 +13,7 @@
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro-emmc"
 CONFIG_SCSI_AHCI=y
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
index 0a68fd9..d5bb51f 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -14,6 +14,7 @@
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro"
 CONFIG_SCSI_AHCI=y
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
index 5b5ed3b..56f6ad8 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -15,6 +15,8 @@
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som-evb"
 CONFIG_SCSI_AHCI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
index ee3b752..005c152 100644
--- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
+++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
@@ -13,13 +13,13 @@
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C_SUPPORT=y
-# CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som204-evb-emmc"
 CONFIG_SCSI_AHCI=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_PHY_ADDR=3
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
diff --git a/configs/A20-Olimex-SOM204-EVB_defconfig b/configs/A20-Olimex-SOM204-EVB_defconfig
index 0272911..b699af5 100644
--- a/configs/A20-Olimex-SOM204-EVB_defconfig
+++ b/configs/A20-Olimex-SOM204-EVB_defconfig
@@ -12,13 +12,13 @@
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C_SUPPORT=y
-# CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som204-evb"
 CONFIG_SCSI_AHCI=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_PHY_ADDR=3
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
diff --git a/configs/B4420QDS_NAND_defconfig b/configs/B4420QDS_NAND_defconfig
index aeb22f1..6fcb51a 100644
--- a/configs/B4420QDS_NAND_defconfig
+++ b/configs/B4420QDS_NAND_defconfig
@@ -7,9 +7,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_B4420QDS=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -53,6 +53,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/B4420QDS_SPIFLASH_defconfig b/configs/B4420QDS_SPIFLASH_defconfig
index 0745007..5dc72cb 100644
--- a/configs/B4420QDS_SPIFLASH_defconfig
+++ b/configs/B4420QDS_SPIFLASH_defconfig
@@ -1,8 +1,8 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF40000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_B4420QDS=y
 CONFIG_FIT=y
@@ -39,6 +39,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/B4420QDS_defconfig b/configs/B4420QDS_defconfig
index c982dd6..5f9a88a 100644
--- a/configs/B4420QDS_defconfig
+++ b/configs/B4420QDS_defconfig
@@ -37,6 +37,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/B4860QDS_NAND_defconfig b/configs/B4860QDS_NAND_defconfig
index b26d458..0874acd 100644
--- a/configs/B4860QDS_NAND_defconfig
+++ b/configs/B4860QDS_NAND_defconfig
@@ -7,9 +7,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_B4860QDS=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -53,6 +53,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/B4860QDS_SECURE_BOOT_defconfig b/configs/B4860QDS_SECURE_BOOT_defconfig
index 9ead606..4d7bf5d 100644
--- a/configs/B4860QDS_SECURE_BOOT_defconfig
+++ b/configs/B4860QDS_SECURE_BOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_B4860QDS=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -37,6 +37,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/B4860QDS_SPIFLASH_defconfig b/configs/B4860QDS_SPIFLASH_defconfig
index 1d4fac8..5660765 100644
--- a/configs/B4860QDS_SPIFLASH_defconfig
+++ b/configs/B4860QDS_SPIFLASH_defconfig
@@ -1,8 +1,8 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF40000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_B4860QDS=y
 CONFIG_FIT=y
@@ -39,6 +39,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
index 11c59c8..58195ad 100644
--- a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
@@ -33,6 +33,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/B4860QDS_defconfig b/configs/B4860QDS_defconfig
index aa11996..68ff6ed 100644
--- a/configs/B4860QDS_defconfig
+++ b/configs/B4860QDS_defconfig
@@ -37,6 +37,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
index 49cee6d..64f6dad 100644
--- a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
+++ b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
@@ -4,9 +4,9 @@
 CONFIG_ENV_OFFSET=0xE0000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFFE000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9131RDB=y
-CONFIG_SPL_TEXT_BASE=0xFFFFE000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -43,7 +43,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 # CONFIG_PCI is not set
diff --git a/configs/BSC9131RDB_NAND_defconfig b/configs/BSC9131RDB_NAND_defconfig
index f212dc8..eda1ac4 100644
--- a/configs/BSC9131RDB_NAND_defconfig
+++ b/configs/BSC9131RDB_NAND_defconfig
@@ -4,9 +4,9 @@
 CONFIG_ENV_OFFSET=0xE0000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFFE000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9131RDB=y
-CONFIG_SPL_TEXT_BASE=0xFFFFE000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -42,7 +42,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 # CONFIG_PCI is not set
diff --git a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
index 958b831..8ac3315 100644
--- a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
+++ b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
@@ -1,8 +1,8 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9131RDB=y
 CONFIG_FIT=y
@@ -35,7 +35,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 # CONFIG_PCI is not set
diff --git a/configs/BSC9131RDB_SPIFLASH_defconfig b/configs/BSC9131RDB_SPIFLASH_defconfig
index 81fca1d..10d8666 100644
--- a/configs/BSC9131RDB_SPIFLASH_defconfig
+++ b/configs/BSC9131RDB_SPIFLASH_defconfig
@@ -1,8 +1,8 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9131RDB=y
 CONFIG_FIT=y
@@ -35,7 +35,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 # CONFIG_PCI is not set
diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
index 48d3b18..83300b2 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x20000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -41,7 +41,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
index c3a655b..5f85370 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
@@ -4,9 +4,9 @@
 CONFIG_ENV_OFFSET=0xE0000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFFE000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
-CONFIG_SPL_TEXT_BASE=0xFFFFE000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -50,7 +50,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
index 9884c6c..646158b 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x20000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -41,7 +41,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
index c92dd73..82f37fb 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
@@ -4,9 +4,9 @@
 CONFIG_ENV_OFFSET=0xE0000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFFE000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
-CONFIG_SPL_TEXT_BASE=0xFFFFE000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -50,7 +50,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
index 31ddd01..25ed8dc 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x8FF40000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -40,7 +40,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig
index 9dcc015..e0e441d 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig
@@ -41,7 +41,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
index 114250c..f7181d6 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x8FF40000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -40,7 +40,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig
index 7186743..0ea77dc 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig
@@ -41,7 +41,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
index 0909ce4..30bdc5d 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -41,7 +41,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
index 8d5e9f0..0e93c0d 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
@@ -41,7 +41,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
index 0086feb..ca119d0 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -41,7 +41,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
index 0766e0f..288d4cf 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
@@ -41,7 +41,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
index ebc71e4..e30dd9b 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -41,7 +41,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
index d12d663..8f4d4b8 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
@@ -1,8 +1,8 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
 CONFIG_FIT=y
@@ -42,7 +42,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
index 64c6acf..80c51aa 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -41,7 +41,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
index a62a381..fb16caa 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
@@ -1,8 +1,8 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
 CONFIG_FIT=y
@@ -42,7 +42,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig
index b309171..3b50817 100644
--- a/configs/Bananapi_defconfig
+++ b/configs/Bananapi_defconfig
@@ -12,6 +12,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi"
 CONFIG_NETCONSOLE=y
 CONFIG_SCSI_AHCI=y
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
diff --git a/configs/Bananapi_m2m_defconfig b/configs/Bananapi_m2m_defconfig
index 2649c7e..8806fe6 100644
--- a/configs/Bananapi_m2m_defconfig
+++ b/configs/Bananapi_m2m_defconfig
@@ -9,7 +9,6 @@
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 CONFIG_USB0_ID_DET="PH8"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-# CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-bananapi-m2m"
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig
index 0cec760..834d3e4 100644
--- a/configs/Bananapro_defconfig
+++ b/configs/Bananapro_defconfig
@@ -14,6 +14,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapro"
 CONFIG_NETCONSOLE=y
 CONFIG_SCSI_AHCI=y
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
diff --git a/configs/C29XPCIE_NAND_defconfig b/configs/C29XPCIE_NAND_defconfig
index f850bdf..cdcf50e 100644
--- a/configs/C29XPCIE_NAND_defconfig
+++ b/configs/C29XPCIE_NAND_defconfig
@@ -7,9 +7,9 @@
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_C29XPCIE=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -51,7 +51,15 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/C29XPCIE_NOR_SECBOOT_defconfig b/configs/C29XPCIE_NOR_SECBOOT_defconfig
index ca3065f..e43c728 100644
--- a/configs/C29XPCIE_NOR_SECBOOT_defconfig
+++ b/configs/C29XPCIE_NOR_SECBOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_C29XPCIE=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -33,7 +33,15 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
index 3e5d268..b7eb77e 100644
--- a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
+++ b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_C29XPCIE=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -35,7 +35,15 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/C29XPCIE_SPIFLASH_defconfig b/configs/C29XPCIE_SPIFLASH_defconfig
index 883c33b..9bfdcd0 100644
--- a/configs/C29XPCIE_SPIFLASH_defconfig
+++ b/configs/C29XPCIE_SPIFLASH_defconfig
@@ -1,8 +1,8 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_C29XPCIE=y
 CONFIG_FIT=y
@@ -36,7 +36,15 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/C29XPCIE_defconfig b/configs/C29XPCIE_defconfig
index b2781b8..3e7f196 100644
--- a/configs/C29XPCIE_defconfig
+++ b/configs/C29XPCIE_defconfig
@@ -34,7 +34,15 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig
index f9026a4..d9223a0 100644
--- a/configs/CSQ_CS908_defconfig
+++ b/configs/CSQ_CS908_defconfig
@@ -7,6 +7,7 @@
 CONFIG_USB2_VBUS_PIN=""
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-cs908"
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
index f70f92e..71f62b5 100644
--- a/configs/Colombus_defconfig
+++ b/configs/Colombus_defconfig
@@ -17,6 +17,7 @@
 CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-colombus"
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig
index 0c7aafd..aa7a9d4 100644
--- a/configs/Cubieboard2_defconfig
+++ b/configs/Cubieboard2_defconfig
@@ -10,6 +10,7 @@
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2"
 CONFIG_SCSI_AHCI=y
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig
index 32c44ff..c0d75ba 100644
--- a/configs/Cubietruck_defconfig
+++ b/configs/Cubietruck_defconfig
@@ -15,11 +15,11 @@
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubietruck"
 CONFIG_SCSI_AHCI=y
 CONFIG_DFU_RAM=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig
index 15984ec..6798698 100644
--- a/configs/Hummingbird_A31_defconfig
+++ b/configs/Hummingbird_A31_defconfig
@@ -9,6 +9,7 @@
 CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-hummingbird"
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
diff --git a/configs/Itead_Ibox_A20_defconfig b/configs/Itead_Ibox_A20_defconfig
index 9ddfb6f..a232bc3 100644
--- a/configs/Itead_Ibox_A20_defconfig
+++ b/configs/Itead_Ibox_A20_defconfig
@@ -10,6 +10,7 @@
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-itead-ibox"
 CONFIG_SCSI_AHCI=y
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig
index c3cb365..34db56f 100644
--- a/configs/Lamobo_R1_defconfig
+++ b/configs/Lamobo_R1_defconfig
@@ -14,6 +14,7 @@
 CONFIG_SCSI_AHCI=y
 CONFIG_B53_SWITCH=y
 CONFIG_B53_PHY_PORTS=0x1f
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig
index 7377deb..72690e2 100644
--- a/configs/Linksprite_pcDuino3_Nano_defconfig
+++ b/configs/Linksprite_pcDuino3_Nano_defconfig
@@ -12,6 +12,7 @@
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3-nano"
 CONFIG_SCSI_AHCI=y
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig
index ad78152..172a2e8 100644
--- a/configs/Linksprite_pcDuino3_defconfig
+++ b/configs/Linksprite_pcDuino3_defconfig
@@ -10,6 +10,7 @@
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
 CONFIG_SCSI_AHCI=y
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
diff --git a/configs/M52277EVB_stmicro_defconfig b/configs/M52277EVB_stmicro_defconfig
index 027e6f7..1a89934 100644
--- a/configs/M52277EVB_stmicro_defconfig
+++ b/configs/M52277EVB_stmicro_defconfig
@@ -1,8 +1,8 @@
 CONFIG_M68K=y
 CONFIG_SYS_TEXT_BASE=0x43E00000
 CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x30000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_TARGET_M52277EVB=y
 CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT"
 CONFIG_BOOTDELAY=3
diff --git a/configs/M54418TWR_defconfig b/configs/M54418TWR_defconfig
index 249718d..4cecb5a 100644
--- a/configs/M54418TWR_defconfig
+++ b/configs/M54418TWR_defconfig
@@ -1,8 +1,8 @@
 CONFIG_M68K=y
 CONFIG_SYS_TEXT_BASE=0x47E00000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x40000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_TARGET_M54418TWR=y
 CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000"
 CONFIG_USE_BOOTARGS=y
diff --git a/configs/M54418TWR_serial_mii_defconfig b/configs/M54418TWR_serial_mii_defconfig
index 5085bb3..014cc25 100644
--- a/configs/M54418TWR_serial_mii_defconfig
+++ b/configs/M54418TWR_serial_mii_defconfig
@@ -1,8 +1,8 @@
 CONFIG_M68K=y
 CONFIG_SYS_TEXT_BASE=0x47E00000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x40000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_TARGET_M54418TWR=y
 CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=25000000"
 CONFIG_USE_BOOTARGS=y
diff --git a/configs/M54418TWR_serial_rmii_defconfig b/configs/M54418TWR_serial_rmii_defconfig
index 42201cc..18e7fe9 100644
--- a/configs/M54418TWR_serial_rmii_defconfig
+++ b/configs/M54418TWR_serial_rmii_defconfig
@@ -1,8 +1,8 @@
 CONFIG_M68K=y
 CONFIG_SYS_TEXT_BASE=0x47E00000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x40000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_TARGET_M54418TWR=y
 CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000"
 CONFIG_USE_BOOTARGS=y
diff --git a/configs/M54451EVB_stmicro_defconfig b/configs/M54451EVB_stmicro_defconfig
index 4bf3fc1..f9aa2d0 100644
--- a/configs/M54451EVB_stmicro_defconfig
+++ b/configs/M54451EVB_stmicro_defconfig
@@ -1,8 +1,8 @@
 CONFIG_M68K=y
 CONFIG_SYS_TEXT_BASE=0x47E00000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x20000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_TARGET_M54451EVB=y
 CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT,SYS_INPUT_CLKSRC=24000000"
 CONFIG_BOOTDELAY=1
diff --git a/configs/M54455EVB_stm33_defconfig b/configs/M54455EVB_stm33_defconfig
index 55d4bc3..83fdaf7 100644
--- a/configs/M54455EVB_stm33_defconfig
+++ b/configs/M54455EVB_stm33_defconfig
@@ -1,8 +1,8 @@
 CONFIG_M68K=y
 CONFIG_SYS_TEXT_BASE=0x4FE00000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x30000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_TARGET_M54455EVB=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_STMICRO_BOOT,CF_SBF,SYS_INPUT_CLKSRC=33333333"
 CONFIG_BOOTDELAY=1
diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig
index dc9ebb8..da41543 100644
--- a/configs/MPC8308RDB_defconfig
+++ b/configs/MPC8308RDB_defconfig
@@ -136,7 +136,15 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig
index 07ebb27..d4db18f 100644
--- a/configs/MPC8313ERDB_33_defconfig
+++ b/configs/MPC8313ERDB_33_defconfig
@@ -154,7 +154,15 @@
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig
index 432193b..b381309 100644
--- a/configs/MPC8313ERDB_66_defconfig
+++ b/configs/MPC8313ERDB_66_defconfig
@@ -153,7 +153,15 @@
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig
index af09f16..30feda2 100644
--- a/configs/MPC8313ERDB_NAND_33_defconfig
+++ b/configs/MPC8313ERDB_NAND_33_defconfig
@@ -6,6 +6,7 @@
 CONFIG_SPL=y
 CONFIG_ENV_OFFSET_REDUND=0x90000
 CONFIG_SYS_CLK_FREQ=33333333
+CONFIG_SPL_TEXT_BASE=0xFFF00000
 CONFIG_MPC83xx=y
 CONFIG_HIGH_BATS=y
 CONFIG_TARGET_MPC8313ERDB_NAND=y
@@ -128,7 +129,6 @@
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_LCRR_EADC_1=y
 CONFIG_LCRR_CLKDIV_4=y
-CONFIG_SPL_TEXT_BASE=0xFFF00000
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"
@@ -163,7 +163,15 @@
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig
index f2d8a65..f7c83fb 100644
--- a/configs/MPC8313ERDB_NAND_66_defconfig
+++ b/configs/MPC8313ERDB_NAND_66_defconfig
@@ -6,6 +6,7 @@
 CONFIG_SPL=y
 CONFIG_ENV_OFFSET_REDUND=0x90000
 CONFIG_SYS_CLK_FREQ=66666667
+CONFIG_SPL_TEXT_BASE=0xFFF00000
 CONFIG_MPC83xx=y
 CONFIG_HIGH_BATS=y
 CONFIG_TARGET_MPC8313ERDB_NAND=y
@@ -127,7 +128,6 @@
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_LCRR_EADC_1=y
 CONFIG_LCRR_CLKDIV_4=y
-CONFIG_SPL_TEXT_BASE=0xFFF00000
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"
@@ -162,7 +162,15 @@
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig
index da6bc1d..bbb79df 100644
--- a/configs/MPC8315ERDB_defconfig
+++ b/configs/MPC8315ERDB_defconfig
@@ -138,7 +138,15 @@
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig
index fd4e6ec..a3f3a40 100644
--- a/configs/MPC8349EMDS_PCI64_defconfig
+++ b/configs/MPC8349EMDS_PCI64_defconfig
@@ -103,6 +103,14 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_TSEC_ENET=y
 # CONFIG_PCI is not set
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig
index 1a61893..59611af 100644
--- a/configs/MPC8349EMDS_SDRAM_defconfig
+++ b/configs/MPC8349EMDS_SDRAM_defconfig
@@ -112,7 +112,15 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_TSEC_ENET=y
 # CONFIG_PCI is not set
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig
index 1351d96..4b28bf8 100644
--- a/configs/MPC8349EMDS_SLAVE_defconfig
+++ b/configs/MPC8349EMDS_SLAVE_defconfig
@@ -103,6 +103,14 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_TSEC_ENET=y
 # CONFIG_PCI is not set
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig
index 5a8692f..2860c53 100644
--- a/configs/MPC8349EMDS_defconfig
+++ b/configs/MPC8349EMDS_defconfig
@@ -104,7 +104,15 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_TSEC_ENET=y
 # CONFIG_PCI is not set
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig
index c4d41c6..6124458 100644
--- a/configs/MPC8349ITXGP_defconfig
+++ b/configs/MPC8349ITXGP_defconfig
@@ -172,7 +172,15 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig
index d5e253b..a1d2a89 100644
--- a/configs/MPC8349ITX_LOWBOOT_defconfig
+++ b/configs/MPC8349ITX_LOWBOOT_defconfig
@@ -177,7 +177,15 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig
index 0517fc6..1147fad 100644
--- a/configs/MPC8349ITX_defconfig
+++ b/configs/MPC8349ITX_defconfig
@@ -176,7 +176,15 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig
index 6aa991a..89e619f 100644
--- a/configs/MPC837XEMDS_HOST_defconfig
+++ b/configs/MPC837XEMDS_HOST_defconfig
@@ -171,7 +171,15 @@
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC837XEMDS_SLAVE_defconfig b/configs/MPC837XEMDS_SLAVE_defconfig
index 1cce99d..f9a3910 100644
--- a/configs/MPC837XEMDS_SLAVE_defconfig
+++ b/configs/MPC837XEMDS_SLAVE_defconfig
@@ -128,6 +128,14 @@
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_TSEC_ENET=y
 # CONFIG_PCI is not set
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig
index ebba5a2..11b185d 100644
--- a/configs/MPC837XEMDS_defconfig
+++ b/configs/MPC837XEMDS_defconfig
@@ -149,7 +149,15 @@
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 # CONFIG_PCI is not set
diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig
index 39c5096..87fe4fc 100644
--- a/configs/MPC837XERDB_SLAVE_defconfig
+++ b/configs/MPC837XERDB_SLAVE_defconfig
@@ -125,6 +125,14 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
index fd8335e..0b40360 100644
--- a/configs/MPC837XERDB_defconfig
+++ b/configs/MPC837XERDB_defconfig
@@ -168,7 +168,15 @@
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
diff --git a/configs/MPC8536DS_36BIT_defconfig b/configs/MPC8536DS_36BIT_defconfig
index a08e096..e60890e 100644
--- a/configs/MPC8536DS_36BIT_defconfig
+++ b/configs/MPC8536DS_36BIT_defconfig
@@ -39,7 +39,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/MPC8536DS_SDCARD_defconfig b/configs/MPC8536DS_SDCARD_defconfig
index 1795a25..9f65366 100644
--- a/configs/MPC8536DS_SDCARD_defconfig
+++ b/configs/MPC8536DS_SDCARD_defconfig
@@ -38,7 +38,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/MPC8536DS_SPIFLASH_defconfig b/configs/MPC8536DS_SPIFLASH_defconfig
index eafd354..866d719 100644
--- a/configs/MPC8536DS_SPIFLASH_defconfig
+++ b/configs/MPC8536DS_SPIFLASH_defconfig
@@ -1,8 +1,8 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xf8f40000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0xF0000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_MPC8536DS=y
@@ -39,7 +39,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/MPC8536DS_defconfig b/configs/MPC8536DS_defconfig
index 8756310..9366e7a 100644
--- a/configs/MPC8536DS_defconfig
+++ b/configs/MPC8536DS_defconfig
@@ -38,7 +38,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/MPC8541CDS_defconfig b/configs/MPC8541CDS_defconfig
index 7017f7f..5c25c4f 100644
--- a/configs/MPC8541CDS_defconfig
+++ b/configs/MPC8541CDS_defconfig
@@ -23,7 +23,15 @@
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_CONS_INDEX=2
diff --git a/configs/MPC8541CDS_legacy_defconfig b/configs/MPC8541CDS_legacy_defconfig
index a62d366..5b5abbe 100644
--- a/configs/MPC8541CDS_legacy_defconfig
+++ b/configs/MPC8541CDS_legacy_defconfig
@@ -24,7 +24,15 @@
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_CONS_INDEX=2
diff --git a/configs/MPC8544DS_defconfig b/configs/MPC8544DS_defconfig
index fb1ed08..c2c70d3 100644
--- a/configs/MPC8544DS_defconfig
+++ b/configs/MPC8544DS_defconfig
@@ -28,7 +28,15 @@
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig
index a870010..2203440 100644
--- a/configs/MPC8548CDS_36BIT_defconfig
+++ b/configs/MPC8548CDS_36BIT_defconfig
@@ -27,7 +27,15 @@
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig
index 42c31d4..b4ac4f1 100644
--- a/configs/MPC8548CDS_defconfig
+++ b/configs/MPC8548CDS_defconfig
@@ -26,7 +26,15 @@
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig
index 263f24c..9b6f8be 100644
--- a/configs/MPC8548CDS_legacy_defconfig
+++ b/configs/MPC8548CDS_legacy_defconfig
@@ -26,7 +26,15 @@
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/MPC8555CDS_defconfig b/configs/MPC8555CDS_defconfig
index b639175..dcf7091 100644
--- a/configs/MPC8555CDS_defconfig
+++ b/configs/MPC8555CDS_defconfig
@@ -23,7 +23,15 @@
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_CONS_INDEX=2
diff --git a/configs/MPC8555CDS_legacy_defconfig b/configs/MPC8555CDS_legacy_defconfig
index 51710bb..7e369f1 100644
--- a/configs/MPC8555CDS_legacy_defconfig
+++ b/configs/MPC8555CDS_legacy_defconfig
@@ -24,7 +24,15 @@
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_CONS_INDEX=2
diff --git a/configs/MPC8568MDS_defconfig b/configs/MPC8568MDS_defconfig
index 24bc0d5..820bd72 100644
--- a/configs/MPC8568MDS_defconfig
+++ b/configs/MPC8568MDS_defconfig
@@ -25,7 +25,15 @@
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_QE=y
diff --git a/configs/MPC8572DS_36BIT_defconfig b/configs/MPC8572DS_36BIT_defconfig
index bbb4987..50912bf 100644
--- a/configs/MPC8572DS_36BIT_defconfig
+++ b/configs/MPC8572DS_36BIT_defconfig
@@ -33,7 +33,15 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/MPC8572DS_defconfig b/configs/MPC8572DS_defconfig
index 1a32f25..fea1e28 100644
--- a/configs/MPC8572DS_defconfig
+++ b/configs/MPC8572DS_defconfig
@@ -32,7 +32,15 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/MPC8641HPCN_36BIT_defconfig b/configs/MPC8641HPCN_36BIT_defconfig
index 249cdda..1e64367 100644
--- a/configs/MPC8641HPCN_36BIT_defconfig
+++ b/configs/MPC8641HPCN_36BIT_defconfig
@@ -27,7 +27,15 @@
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8641HPCN_defconfig b/configs/MPC8641HPCN_defconfig
index f87c616..7ce7891 100644
--- a/configs/MPC8641HPCN_defconfig
+++ b/configs/MPC8641HPCN_defconfig
@@ -27,7 +27,15 @@
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig
index babe9f1..cd652b3 100644
--- a/configs/Mele_A1000G_quad_defconfig
+++ b/configs/Mele_A1000G_quad_defconfig
@@ -8,6 +8,7 @@
 CONFIG_USB2_VBUS_PIN=""
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mele-a1000g-quad"
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
diff --git a/configs/Mele_I7_defconfig b/configs/Mele_I7_defconfig
index 1282d87..bedddf1 100644
--- a/configs/Mele_I7_defconfig
+++ b/configs/Mele_I7_defconfig
@@ -7,6 +7,7 @@
 CONFIG_USB2_VBUS_PIN=""
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-i7"
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig
index 60d15ab..1686463 100644
--- a/configs/Mele_M3_defconfig
+++ b/configs/Mele_M3_defconfig
@@ -10,6 +10,7 @@
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3"
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig
index 8900c7a..1c6ab3a 100644
--- a/configs/Mele_M5_defconfig
+++ b/configs/Mele_M5_defconfig
@@ -11,6 +11,7 @@
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m5"
 CONFIG_SCSI_AHCI=y
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig
index b1b3b7a..f7bd7fc 100644
--- a/configs/Mele_M9_defconfig
+++ b/configs/Mele_M9_defconfig
@@ -7,6 +7,7 @@
 CONFIG_USB2_VBUS_PIN=""
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-m9"
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig
index af8c17d..32135f3 100644
--- a/configs/Orangepi_defconfig
+++ b/configs/Orangepi_defconfig
@@ -14,6 +14,7 @@
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi"
 CONFIG_SCSI_AHCI=y
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig
index 43ee76f..a48939b 100644
--- a/configs/Orangepi_mini_defconfig
+++ b/configs/Orangepi_mini_defconfig
@@ -16,6 +16,7 @@
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi-mini"
 CONFIG_SCSI_AHCI=y
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
diff --git a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
index 5269b6e..c104452 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -39,7 +39,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig
index 4b2b8c4..74294fc 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig
@@ -7,9 +7,9 @@
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_PHYS_64BIT=y
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
@@ -58,7 +58,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
index 5e9f964..723f6ca 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -38,7 +38,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig
index 6f328a5..d43ad79 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig
@@ -39,7 +39,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
index 83ad24a..ddb7e60 100644
--- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
@@ -8,9 +8,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xD0001000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
-CONFIG_SPL_TEXT_BASE=0xD0001000
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -52,7 +52,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
index a225dda..9987cde 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -40,7 +40,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
index 08d8864..12a073d 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
@@ -3,16 +3,16 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xD0001000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
-CONFIG_SPL_TEXT_BASE=0xD0001000
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -54,7 +54,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
index 6ef8080..9691fd2 100644
--- a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -38,7 +38,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig
index 796e112..67cba6a 100644
--- a/configs/P1010RDB-PA_NAND_defconfig
+++ b/configs/P1010RDB-PA_NAND_defconfig
@@ -7,9 +7,9 @@
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -57,7 +57,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
index ba4bcdf..4935126 100644
--- a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -36,7 +36,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig
index 73dbb86..05ec024 100644
--- a/configs/P1010RDB-PA_NOR_defconfig
+++ b/configs/P1010RDB-PA_NOR_defconfig
@@ -38,7 +38,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig
index 947bd22..95a15f7 100644
--- a/configs/P1010RDB-PA_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_SDCARD_defconfig
@@ -8,9 +8,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xD0001000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
-CONFIG_SPL_TEXT_BASE=0xD0001000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -51,7 +51,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
index 8f1f8a9..b31bdff 100644
--- a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -39,7 +39,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig
index bd6d1ea..a7dd582 100644
--- a/configs/P1010RDB-PA_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_defconfig
@@ -3,16 +3,16 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xD0001000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
-CONFIG_SPL_TEXT_BASE=0xD0001000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -53,7 +53,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
index bbd2f26..66bdebb 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -39,7 +39,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig
index 1461b89..6e71c2a 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig
@@ -7,9 +7,9 @@
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_PHYS_64BIT=y
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
@@ -58,7 +58,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
index 31550bb..f2e4066 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -38,7 +38,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig
index c857c8d..79e4117 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig
@@ -39,7 +39,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
index f79796a..083fe79 100644
--- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
@@ -8,9 +8,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xD0001000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
-CONFIG_SPL_TEXT_BASE=0xD0001000
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -52,7 +52,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
index 4bcb9ce..50b5c5f 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -40,7 +40,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
index c4c3c44..6247d47 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
@@ -3,16 +3,16 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xD0001000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
-CONFIG_SPL_TEXT_BASE=0xD0001000
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -54,7 +54,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
index 593e866..17708de 100644
--- a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -38,7 +38,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig
index 8378eed..12c7491 100644
--- a/configs/P1010RDB-PB_NAND_defconfig
+++ b/configs/P1010RDB-PB_NAND_defconfig
@@ -7,9 +7,9 @@
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -57,7 +57,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
index 3be6893..be455a0 100644
--- a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -37,7 +37,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig
index 764017a..943ca96 100644
--- a/configs/P1010RDB-PB_NOR_defconfig
+++ b/configs/P1010RDB-PB_NOR_defconfig
@@ -38,7 +38,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig
index 437858b8..3548b95 100644
--- a/configs/P1010RDB-PB_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_SDCARD_defconfig
@@ -8,9 +8,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xD0001000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
-CONFIG_SPL_TEXT_BASE=0xD0001000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -51,7 +51,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
index 586ed29..ce3d7c4 100644
--- a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -39,7 +39,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig
index 7f222db..b54cf2b 100644
--- a/configs/P1010RDB-PB_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_defconfig
@@ -3,16 +3,16 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xD0001000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
-CONFIG_SPL_TEXT_BASE=0xD0001000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -53,7 +53,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
index 2276b48..91d46e4 100644
--- a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
@@ -7,10 +7,10 @@
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020MBG=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -46,7 +46,15 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1020MBG-PC_36BIT_defconfig b/configs/P1020MBG-PC_36BIT_defconfig
index 9d0e4c5..7930af3 100644
--- a/configs/P1020MBG-PC_36BIT_defconfig
+++ b/configs/P1020MBG-PC_36BIT_defconfig
@@ -34,7 +34,15 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1020MBG-PC_SDCARD_defconfig b/configs/P1020MBG-PC_SDCARD_defconfig
index 811e11e..708a4bb 100644
--- a/configs/P1020MBG-PC_SDCARD_defconfig
+++ b/configs/P1020MBG-PC_SDCARD_defconfig
@@ -7,10 +7,10 @@
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020MBG=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -45,7 +45,15 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1020MBG-PC_defconfig b/configs/P1020MBG-PC_defconfig
index 06d50d0..4ff3712 100644
--- a/configs/P1020MBG-PC_defconfig
+++ b/configs/P1020MBG-PC_defconfig
@@ -33,7 +33,15 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
index fadb446..2396d91 100644
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -6,10 +6,10 @@
 CONFIG_TPL_LIBCOMMON_SUPPORT=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PC=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_PHYS_64BIT=y
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
@@ -61,7 +61,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
index f79176e..745200d 100644
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
@@ -7,10 +7,10 @@
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PC=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -56,7 +56,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
index f9f5ab4..3eadd3d 100644
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -3,16 +3,16 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PC=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -58,7 +58,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
index 6cab654..9b7901f 100644
--- a/configs/P1020RDB-PC_36BIT_defconfig
+++ b/configs/P1020RDB-PC_36BIT_defconfig
@@ -45,7 +45,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
index 723d150..e99709a 100644
--- a/configs/P1020RDB-PC_NAND_defconfig
+++ b/configs/P1020RDB-PC_NAND_defconfig
@@ -6,10 +6,10 @@
 CONFIG_TPL_LIBCOMMON_SUPPORT=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PC=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -60,7 +60,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
index 0829ade..ef007e5 100644
--- a/configs/P1020RDB-PC_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_SDCARD_defconfig
@@ -7,10 +7,10 @@
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PC=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -55,7 +55,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
index 8d1e989..c8b0923 100644
--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig
@@ -3,16 +3,16 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PC=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -57,7 +57,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
index e337ceb..1a30c97 100644
--- a/configs/P1020RDB-PC_defconfig
+++ b/configs/P1020RDB-PC_defconfig
@@ -44,7 +44,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
index e5ee950..e1858e4 100644
--- a/configs/P1020RDB-PD_NAND_defconfig
+++ b/configs/P1020RDB-PD_NAND_defconfig
@@ -6,10 +6,10 @@
 CONFIG_TPL_LIBCOMMON_SUPPORT=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PD=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -64,7 +64,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
index ba9bea5..e24c89f 100644
--- a/configs/P1020RDB-PD_SDCARD_defconfig
+++ b/configs/P1020RDB-PD_SDCARD_defconfig
@@ -7,10 +7,10 @@
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PD=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -59,7 +59,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
index d3a54f7..c89201f 100644
--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig
@@ -3,16 +3,16 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PD=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -61,7 +61,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
index fffdcc8..c79d599 100644
--- a/configs/P1020RDB-PD_defconfig
+++ b/configs/P1020RDB-PD_defconfig
@@ -48,7 +48,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
index 2dc7593..4b00005 100644
--- a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
@@ -7,10 +7,10 @@
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020UTM=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -46,7 +46,15 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1020UTM-PC_36BIT_defconfig b/configs/P1020UTM-PC_36BIT_defconfig
index 793ab15..968d3ed 100644
--- a/configs/P1020UTM-PC_36BIT_defconfig
+++ b/configs/P1020UTM-PC_36BIT_defconfig
@@ -34,7 +34,15 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1020UTM-PC_SDCARD_defconfig b/configs/P1020UTM-PC_SDCARD_defconfig
index 2cd958a..93302a1 100644
--- a/configs/P1020UTM-PC_SDCARD_defconfig
+++ b/configs/P1020UTM-PC_SDCARD_defconfig
@@ -7,10 +7,10 @@
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020UTM=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -45,7 +45,15 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1020UTM-PC_defconfig b/configs/P1020UTM-PC_defconfig
index bd366e9..c41ac7b 100644
--- a/configs/P1020UTM-PC_defconfig
+++ b/configs/P1020UTM-PC_defconfig
@@ -33,7 +33,15 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1021RDB-PC_36BIT_NAND_defconfig b/configs/P1021RDB-PC_36BIT_NAND_defconfig
index bd341ff..ba1d836 100644
--- a/configs/P1021RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1021RDB-PC_36BIT_NAND_defconfig
@@ -6,10 +6,10 @@
 CONFIG_TPL_LIBCOMMON_SUPPORT=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1021RDB=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_PHYS_64BIT=y
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
@@ -62,7 +62,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
index 5e81cfe..30b8372 100644
--- a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
@@ -7,10 +7,10 @@
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1021RDB=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -57,7 +57,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
index 9e40031..37bc209 100644
--- a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
@@ -3,16 +3,16 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1021RDB=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -59,7 +59,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1021RDB-PC_36BIT_defconfig b/configs/P1021RDB-PC_36BIT_defconfig
index 28609f3..ca1be9c 100644
--- a/configs/P1021RDB-PC_36BIT_defconfig
+++ b/configs/P1021RDB-PC_36BIT_defconfig
@@ -45,7 +45,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1021RDB-PC_NAND_defconfig b/configs/P1021RDB-PC_NAND_defconfig
index 4140e04..1b38da4 100644
--- a/configs/P1021RDB-PC_NAND_defconfig
+++ b/configs/P1021RDB-PC_NAND_defconfig
@@ -6,10 +6,10 @@
 CONFIG_TPL_LIBCOMMON_SUPPORT=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1021RDB=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -61,7 +61,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1021RDB-PC_SDCARD_defconfig b/configs/P1021RDB-PC_SDCARD_defconfig
index 5231aae..242b9eb 100644
--- a/configs/P1021RDB-PC_SDCARD_defconfig
+++ b/configs/P1021RDB-PC_SDCARD_defconfig
@@ -7,10 +7,10 @@
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1021RDB=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -56,7 +56,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1021RDB-PC_SPIFLASH_defconfig b/configs/P1021RDB-PC_SPIFLASH_defconfig
index e277ab4..6792e3f 100644
--- a/configs/P1021RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1021RDB-PC_SPIFLASH_defconfig
@@ -3,16 +3,16 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1021RDB=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -58,7 +58,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1021RDB-PC_defconfig b/configs/P1021RDB-PC_defconfig
index 4abebb5..54010af 100644
--- a/configs/P1021RDB-PC_defconfig
+++ b/configs/P1021RDB-PC_defconfig
@@ -44,7 +44,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1022DS_36BIT_NAND_defconfig b/configs/P1022DS_36BIT_NAND_defconfig
index 8ad9397..2bfda3e 100644
--- a/configs/P1022DS_36BIT_NAND_defconfig
+++ b/configs/P1022DS_36BIT_NAND_defconfig
@@ -6,9 +6,9 @@
 CONFIG_TPL_LIBCOMMON_SUPPORT=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1022DS=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_PHYS_64BIT=y
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
@@ -59,7 +59,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1022DS_36BIT_SDCARD_defconfig b/configs/P1022DS_36BIT_SDCARD_defconfig
index 5e81825..9cc2140 100644
--- a/configs/P1022DS_36BIT_SDCARD_defconfig
+++ b/configs/P1022DS_36BIT_SDCARD_defconfig
@@ -7,9 +7,9 @@
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1022DS=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -53,7 +53,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1022DS_36BIT_SPIFLASH_defconfig b/configs/P1022DS_36BIT_SPIFLASH_defconfig
index fea76c4..80d3a88 100644
--- a/configs/P1022DS_36BIT_SPIFLASH_defconfig
+++ b/configs/P1022DS_36BIT_SPIFLASH_defconfig
@@ -3,15 +3,15 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1022DS=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -55,7 +55,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1022DS_36BIT_defconfig b/configs/P1022DS_36BIT_defconfig
index 9e0eb0a..1048b53 100644
--- a/configs/P1022DS_36BIT_defconfig
+++ b/configs/P1022DS_36BIT_defconfig
@@ -41,7 +41,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1022DS_NAND_defconfig b/configs/P1022DS_NAND_defconfig
index f104527..7975487 100644
--- a/configs/P1022DS_NAND_defconfig
+++ b/configs/P1022DS_NAND_defconfig
@@ -6,9 +6,9 @@
 CONFIG_TPL_LIBCOMMON_SUPPORT=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1022DS=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -58,7 +58,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1022DS_SDCARD_defconfig b/configs/P1022DS_SDCARD_defconfig
index 0db9171..4e80b88 100644
--- a/configs/P1022DS_SDCARD_defconfig
+++ b/configs/P1022DS_SDCARD_defconfig
@@ -7,9 +7,9 @@
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1022DS=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -52,7 +52,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1022DS_SPIFLASH_defconfig b/configs/P1022DS_SPIFLASH_defconfig
index d41e8a8..e55f05c 100644
--- a/configs/P1022DS_SPIFLASH_defconfig
+++ b/configs/P1022DS_SPIFLASH_defconfig
@@ -3,15 +3,15 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1022DS=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -54,7 +54,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1022DS_defconfig b/configs/P1022DS_defconfig
index cee5e59..c611ce4 100644
--- a/configs/P1022DS_defconfig
+++ b/configs/P1022DS_defconfig
@@ -40,7 +40,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1023RDB_defconfig b/configs/P1023RDB_defconfig
index a279a74..0c10bc0 100644
--- a/configs/P1023RDB_defconfig
+++ b/configs/P1023RDB_defconfig
@@ -37,6 +37,7 @@
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P1024RDB_36BIT_defconfig b/configs/P1024RDB_36BIT_defconfig
index 4f32964..5116fac 100644
--- a/configs/P1024RDB_36BIT_defconfig
+++ b/configs/P1024RDB_36BIT_defconfig
@@ -40,7 +40,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1024RDB_NAND_defconfig b/configs/P1024RDB_NAND_defconfig
index d595553..2e2eda7 100644
--- a/configs/P1024RDB_NAND_defconfig
+++ b/configs/P1024RDB_NAND_defconfig
@@ -6,10 +6,10 @@
 CONFIG_TPL_LIBCOMMON_SUPPORT=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1024RDB=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -56,7 +56,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1024RDB_SDCARD_defconfig b/configs/P1024RDB_SDCARD_defconfig
index bd443c9..69a3718 100644
--- a/configs/P1024RDB_SDCARD_defconfig
+++ b/configs/P1024RDB_SDCARD_defconfig
@@ -7,10 +7,10 @@
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1024RDB=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -50,7 +50,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1024RDB_SPIFLASH_defconfig b/configs/P1024RDB_SPIFLASH_defconfig
index 1c8abd6..a09696c 100644
--- a/configs/P1024RDB_SPIFLASH_defconfig
+++ b/configs/P1024RDB_SPIFLASH_defconfig
@@ -3,16 +3,16 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1024RDB=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -52,7 +52,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1024RDB_defconfig b/configs/P1024RDB_defconfig
index f38424f..72665c4 100644
--- a/configs/P1024RDB_defconfig
+++ b/configs/P1024RDB_defconfig
@@ -39,7 +39,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1025RDB_36BIT_defconfig b/configs/P1025RDB_36BIT_defconfig
index dbd9f7d..8eaddb1 100644
--- a/configs/P1025RDB_36BIT_defconfig
+++ b/configs/P1025RDB_36BIT_defconfig
@@ -41,7 +41,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1025RDB_NAND_defconfig b/configs/P1025RDB_NAND_defconfig
index 36c73a6..bbeb396 100644
--- a/configs/P1025RDB_NAND_defconfig
+++ b/configs/P1025RDB_NAND_defconfig
@@ -6,10 +6,10 @@
 CONFIG_TPL_LIBCOMMON_SUPPORT=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1025RDB=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -58,7 +58,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1025RDB_SDCARD_defconfig b/configs/P1025RDB_SDCARD_defconfig
index d73e41d..bc88a27 100644
--- a/configs/P1025RDB_SDCARD_defconfig
+++ b/configs/P1025RDB_SDCARD_defconfig
@@ -7,10 +7,10 @@
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1025RDB=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -51,7 +51,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1025RDB_SPIFLASH_defconfig b/configs/P1025RDB_SPIFLASH_defconfig
index f8feeb1..6dba8c5 100644
--- a/configs/P1025RDB_SPIFLASH_defconfig
+++ b/configs/P1025RDB_SPIFLASH_defconfig
@@ -3,16 +3,16 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1025RDB=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -54,7 +54,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P1025RDB_defconfig b/configs/P1025RDB_defconfig
index e2f5e4b..92dc97a 100644
--- a/configs/P1025RDB_defconfig
+++ b/configs/P1025RDB_defconfig
@@ -40,7 +40,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index e2c647d..b419367 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig
@@ -6,10 +6,10 @@
 CONFIG_TPL_LIBCOMMON_SUPPORT=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P2020RDB=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_PHYS_64BIT=y
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
@@ -66,7 +66,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index 04f2fc9..0afddc2 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
@@ -7,10 +7,10 @@
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P2020RDB=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -61,7 +61,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index 03e5c7e..1a700a8 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -3,16 +3,16 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P2020RDB=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -63,7 +63,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
index 8655b15..8b98cb8 100644
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ b/configs/P2020RDB-PC_36BIT_defconfig
@@ -50,7 +50,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
index 4e2b4e2..b1a26af 100644
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ b/configs/P2020RDB-PC_NAND_defconfig
@@ -6,10 +6,10 @@
 CONFIG_TPL_LIBCOMMON_SUPPORT=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P2020RDB=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -65,7 +65,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
index d1f3197..c76958e 100644
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_SDCARD_defconfig
@@ -7,10 +7,10 @@
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P2020RDB=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -60,7 +60,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
index b38940d..0892596 100644
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig
@@ -3,16 +3,16 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P2020RDB=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -62,7 +62,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
index d681e59..e37ca66 100644
--- a/configs/P2020RDB-PC_defconfig
+++ b/configs/P2020RDB-PC_defconfig
@@ -49,7 +49,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index 110e50b..0399a27 100644
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig
@@ -45,6 +45,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index c47c601..0b53a05 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig
@@ -44,6 +44,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P2041RDB_SECURE_BOOT_defconfig b/configs/P2041RDB_SECURE_BOOT_defconfig
index 08e9ca2..af33f9d 100644
--- a/configs/P2041RDB_SECURE_BOOT_defconfig
+++ b/configs/P2041RDB_SECURE_BOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P2041RDB=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -38,6 +38,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index 40eafa7..8c2e20e 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -1,8 +1,8 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF40000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
@@ -45,6 +45,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
index ce354ae..dd5f2a4 100644
--- a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
@@ -34,6 +34,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index 3a79fc6..6836d42 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -43,6 +43,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P3041DS_NAND_SECURE_BOOT_defconfig b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
index dc0567c..8ab2537 100644
--- a/configs/P3041DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x20000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P3041DS=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -40,6 +40,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig
index 473ad5b..eb000c8 100644
--- a/configs/P3041DS_NAND_defconfig
+++ b/configs/P3041DS_NAND_defconfig
@@ -45,6 +45,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig
index 806653e..ade8b58 100644
--- a/configs/P3041DS_SDCARD_defconfig
+++ b/configs/P3041DS_SDCARD_defconfig
@@ -44,6 +44,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P3041DS_SECURE_BOOT_defconfig b/configs/P3041DS_SECURE_BOOT_defconfig
index fb2b120..d6cabeb 100644
--- a/configs/P3041DS_SECURE_BOOT_defconfig
+++ b/configs/P3041DS_SECURE_BOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P3041DS=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -38,6 +38,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig
index cbafc9c..0bb7288 100644
--- a/configs/P3041DS_SPIFLASH_defconfig
+++ b/configs/P3041DS_SPIFLASH_defconfig
@@ -1,8 +1,8 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF40000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P3041DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
@@ -45,6 +45,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
index a8e4512..c34311b 100644
--- a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
@@ -34,6 +34,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig
index e009585..428d9e3 100644
--- a/configs/P3041DS_defconfig
+++ b/configs/P3041DS_defconfig
@@ -43,6 +43,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig
index da92959..1318e26 100644
--- a/configs/P4080DS_SDCARD_defconfig
+++ b/configs/P4080DS_SDCARD_defconfig
@@ -43,6 +43,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P4080DS_SECURE_BOOT_defconfig b/configs/P4080DS_SECURE_BOOT_defconfig
index 281bba1..22a6ebe 100644
--- a/configs/P4080DS_SECURE_BOOT_defconfig
+++ b/configs/P4080DS_SECURE_BOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P4080DS=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -37,6 +37,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig
index 9ed25c1..f19ace2 100644
--- a/configs/P4080DS_SPIFLASH_defconfig
+++ b/configs/P4080DS_SPIFLASH_defconfig
@@ -1,8 +1,8 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF40000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P4080DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
@@ -44,6 +44,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
index a090bed..a740bc4 100644
--- a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
@@ -32,6 +32,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig
index fcefd8d..31e91c1 100644
--- a/configs/P4080DS_defconfig
+++ b/configs/P4080DS_defconfig
@@ -42,6 +42,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
index 19ba105..52efa92 100644
--- a/configs/P5020DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x20000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5020DS=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -41,6 +41,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P5020DS_NAND_defconfig b/configs/P5020DS_NAND_defconfig
index 4cba3e8..baf7d83 100644
--- a/configs/P5020DS_NAND_defconfig
+++ b/configs/P5020DS_NAND_defconfig
@@ -41,6 +41,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P5020DS_SDCARD_defconfig b/configs/P5020DS_SDCARD_defconfig
index 5cfbc6e..c5b4241 100644
--- a/configs/P5020DS_SDCARD_defconfig
+++ b/configs/P5020DS_SDCARD_defconfig
@@ -39,6 +39,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P5020DS_SECURE_BOOT_defconfig b/configs/P5020DS_SECURE_BOOT_defconfig
index 5c6f405..c08f9ff 100644
--- a/configs/P5020DS_SECURE_BOOT_defconfig
+++ b/configs/P5020DS_SECURE_BOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5020DS=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -38,6 +38,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P5020DS_SPIFLASH_defconfig b/configs/P5020DS_SPIFLASH_defconfig
index 8074e09..03d7a16 100644
--- a/configs/P5020DS_SPIFLASH_defconfig
+++ b/configs/P5020DS_SPIFLASH_defconfig
@@ -1,8 +1,8 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF40000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5020DS=y
 CONFIG_FIT=y
@@ -40,6 +40,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
index 8921201..7569364 100644
--- a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
@@ -34,6 +34,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P5020DS_defconfig b/configs/P5020DS_defconfig
index 8bd419b..a1b410c 100644
--- a/configs/P5020DS_defconfig
+++ b/configs/P5020DS_defconfig
@@ -38,6 +38,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
index 6a69842..beab855 100644
--- a/configs/P5040DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x20000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5040DS=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -41,6 +41,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig
index 4c3f705..8be7d90 100644
--- a/configs/P5040DS_NAND_defconfig
+++ b/configs/P5040DS_NAND_defconfig
@@ -46,6 +46,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig
index 3874e06..134ea01 100644
--- a/configs/P5040DS_SDCARD_defconfig
+++ b/configs/P5040DS_SDCARD_defconfig
@@ -44,6 +44,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P5040DS_SECURE_BOOT_defconfig b/configs/P5040DS_SECURE_BOOT_defconfig
index 554a8c1..5d48206 100644
--- a/configs/P5040DS_SECURE_BOOT_defconfig
+++ b/configs/P5040DS_SECURE_BOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5040DS=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -38,6 +38,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig
index 09c13fe..2dacecc 100644
--- a/configs/P5040DS_SPIFLASH_defconfig
+++ b/configs/P5040DS_SPIFLASH_defconfig
@@ -1,8 +1,8 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF40000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5040DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
@@ -45,6 +45,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig
index d531401..14a97f8 100644
--- a/configs/P5040DS_defconfig
+++ b/configs/P5040DS_defconfig
@@ -43,6 +43,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig
index 379a4c2..4b3c729 100644
--- a/configs/SBx81LIFKW_defconfig
+++ b/configs/SBx81LIFKW_defconfig
@@ -5,8 +5,8 @@
 CONFIG_SYS_TEXT_BASE=0x00600000
 CONFIG_TARGET_SBx81LIFKW=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_IDENT_STRING="\nSBx81LIFKW"
 # CONFIG_SYS_MALLOC_F is not set
diff --git a/configs/SBx81LIFXCAT_defconfig b/configs/SBx81LIFXCAT_defconfig
index d5b73b9..fdbde49 100644
--- a/configs/SBx81LIFXCAT_defconfig
+++ b/configs/SBx81LIFXCAT_defconfig
@@ -5,8 +5,8 @@
 CONFIG_SYS_TEXT_BASE=0x00600000
 CONFIG_TARGET_SBx81LIFXCAT=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_IDENT_STRING="\nSBx81LIFXCAT"
 # CONFIG_SYS_MALLOC_F is not set
diff --git a/configs/Sinlinx_SinA31s_defconfig b/configs/Sinlinx_SinA31s_defconfig
index 74fb9e3..461a28f 100644
--- a/configs/Sinlinx_SinA31s_defconfig
+++ b/configs/Sinlinx_SinA31s_defconfig
@@ -11,6 +11,7 @@
 CONFIG_USB2_VBUS_PIN=""
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sina31s"
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
index 9f29870..277598e 100644
--- a/configs/Sinlinx_SinA33_defconfig
+++ b/configs/Sinlinx_SinA33_defconfig
@@ -13,7 +13,6 @@
 CONFIG_VIDEO_LCD_BL_PWM="PH0"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_CMD_DFU=y
-# CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33"
 CONFIG_DFU_RAM=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
diff --git a/configs/Sinovoip_BPI_M2_defconfig b/configs/Sinovoip_BPI_M2_defconfig
index b2ecf4e..10bdf20 100644
--- a/configs/Sinovoip_BPI_M2_defconfig
+++ b/configs/Sinovoip_BPI_M2_defconfig
@@ -7,6 +7,7 @@
 CONFIG_USB2_VBUS_PIN=""
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sinovoip-bpi-m2"
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
diff --git a/configs/T1023RDB_NAND_defconfig b/configs/T1023RDB_NAND_defconfig
index bfc1a49..ca74b88 100644
--- a/configs/T1023RDB_NAND_defconfig
+++ b/configs/T1023RDB_NAND_defconfig
@@ -7,9 +7,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1023RDB=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -62,6 +62,7 @@
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T1023RDB_SDCARD_defconfig b/configs/T1023RDB_SDCARD_defconfig
index 772dcaa..4edc69a 100644
--- a/configs/T1023RDB_SDCARD_defconfig
+++ b/configs/T1023RDB_SDCARD_defconfig
@@ -8,9 +8,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1023RDB=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -59,6 +59,7 @@
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T1023RDB_SECURE_BOOT_defconfig b/configs/T1023RDB_SECURE_BOOT_defconfig
index b0079f4..5ddaac6 100644
--- a/configs/T1023RDB_SECURE_BOOT_defconfig
+++ b/configs/T1023RDB_SECURE_BOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1023RDB=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -46,6 +46,7 @@
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T1023RDB_SPIFLASH_defconfig b/configs/T1023RDB_SPIFLASH_defconfig
index 540d8c1..b489a80 100644
--- a/configs/T1023RDB_SPIFLASH_defconfig
+++ b/configs/T1023RDB_SPIFLASH_defconfig
@@ -3,16 +3,16 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1023RDB=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -62,6 +62,7 @@
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T1023RDB_defconfig b/configs/T1023RDB_defconfig
index ede4cca..b8ffebc 100644
--- a/configs/T1023RDB_defconfig
+++ b/configs/T1023RDB_defconfig
@@ -46,6 +46,7 @@
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
index bb22d4e..2199abc 100644
--- a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
+++ b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024QDS=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -48,6 +48,10 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1024QDS_DDR4_defconfig b/configs/T1024QDS_DDR4_defconfig
index d21bfb4..0a52af4 100644
--- a/configs/T1024QDS_DDR4_defconfig
+++ b/configs/T1024QDS_DDR4_defconfig
@@ -48,6 +48,10 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
diff --git a/configs/T1024QDS_NAND_defconfig b/configs/T1024QDS_NAND_defconfig
index fa4a899..9db39b1 100644
--- a/configs/T1024QDS_NAND_defconfig
+++ b/configs/T1024QDS_NAND_defconfig
@@ -7,9 +7,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024QDS=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -65,6 +65,10 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1024QDS_SDCARD_defconfig b/configs/T1024QDS_SDCARD_defconfig
index 54b3623..679f2ad 100644
--- a/configs/T1024QDS_SDCARD_defconfig
+++ b/configs/T1024QDS_SDCARD_defconfig
@@ -8,9 +8,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024QDS=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -62,6 +62,10 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1024QDS_SECURE_BOOT_defconfig b/configs/T1024QDS_SECURE_BOOT_defconfig
index f0c1b37..cc080c7 100644
--- a/configs/T1024QDS_SECURE_BOOT_defconfig
+++ b/configs/T1024QDS_SECURE_BOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024QDS=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -49,6 +49,10 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1024QDS_SPIFLASH_defconfig b/configs/T1024QDS_SPIFLASH_defconfig
index 53fd5690..01bc511 100644
--- a/configs/T1024QDS_SPIFLASH_defconfig
+++ b/configs/T1024QDS_SPIFLASH_defconfig
@@ -3,16 +3,16 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024QDS=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -65,6 +65,10 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1024QDS_defconfig b/configs/T1024QDS_defconfig
index 3517cfd..6ebffb8 100644
--- a/configs/T1024QDS_defconfig
+++ b/configs/T1024QDS_defconfig
@@ -49,6 +49,10 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index d75e5ec..c2c73a7 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -7,9 +7,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024RDB=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -68,6 +68,7 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index 95d30f1..3ded897 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -8,9 +8,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024RDB=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -65,6 +65,7 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig
index e924e74..1d221db 100644
--- a/configs/T1024RDB_SECURE_BOOT_defconfig
+++ b/configs/T1024RDB_SECURE_BOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024RDB=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -48,6 +48,7 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index 4068b6c..123d8dd 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -3,16 +3,16 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024RDB=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -68,6 +68,7 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index ad4ba96..dc6b62c 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -53,6 +53,7 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T1040D4RDB_NAND_defconfig b/configs/T1040D4RDB_NAND_defconfig
index 8e11e7e..87b2a76 100644
--- a/configs/T1040D4RDB_NAND_defconfig
+++ b/configs/T1040D4RDB_NAND_defconfig
@@ -7,9 +7,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1040D4RDB=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -60,6 +60,8 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1040D4RDB_SDCARD_defconfig b/configs/T1040D4RDB_SDCARD_defconfig
index 0e5b6a5..4b9e428 100644
--- a/configs/T1040D4RDB_SDCARD_defconfig
+++ b/configs/T1040D4RDB_SDCARD_defconfig
@@ -8,9 +8,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1040D4RDB=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -57,6 +57,8 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1040D4RDB_SECURE_BOOT_defconfig b/configs/T1040D4RDB_SECURE_BOOT_defconfig
index 9992ad7..7adffb7 100644
--- a/configs/T1040D4RDB_SECURE_BOOT_defconfig
+++ b/configs/T1040D4RDB_SECURE_BOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1040D4RDB=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -43,6 +43,8 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1040D4RDB_SPIFLASH_defconfig b/configs/T1040D4RDB_SPIFLASH_defconfig
index 5b9c3cb..2320b72 100644
--- a/configs/T1040D4RDB_SPIFLASH_defconfig
+++ b/configs/T1040D4RDB_SPIFLASH_defconfig
@@ -3,16 +3,16 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1040D4RDB=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -60,6 +60,8 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1040D4RDB_defconfig b/configs/T1040D4RDB_defconfig
index 8177b16..eb25930 100644
--- a/configs/T1040D4RDB_defconfig
+++ b/configs/T1040D4RDB_defconfig
@@ -44,6 +44,8 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1040QDS_DDR4_defconfig b/configs/T1040QDS_DDR4_defconfig
index 9cb012c..a575b6f 100644
--- a/configs/T1040QDS_DDR4_defconfig
+++ b/configs/T1040QDS_DDR4_defconfig
@@ -49,6 +49,10 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1040QDS_SECURE_BOOT_defconfig b/configs/T1040QDS_SECURE_BOOT_defconfig
index ddde260..e616f0d 100644
--- a/configs/T1040QDS_SECURE_BOOT_defconfig
+++ b/configs/T1040QDS_SECURE_BOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1040QDS=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -49,6 +49,10 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1040QDS_defconfig b/configs/T1040QDS_defconfig
index 94c02a9..0b1c7cd 100644
--- a/configs/T1040QDS_defconfig
+++ b/configs/T1040QDS_defconfig
@@ -50,6 +50,10 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1040RDB_NAND_defconfig b/configs/T1040RDB_NAND_defconfig
index 381801e..7cf9847 100644
--- a/configs/T1040RDB_NAND_defconfig
+++ b/configs/T1040RDB_NAND_defconfig
@@ -7,9 +7,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1040RDB=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -61,6 +61,8 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1040RDB_SDCARD_defconfig b/configs/T1040RDB_SDCARD_defconfig
index 1eeba5d..321260f 100644
--- a/configs/T1040RDB_SDCARD_defconfig
+++ b/configs/T1040RDB_SDCARD_defconfig
@@ -8,9 +8,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1040RDB=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -58,6 +58,8 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1040RDB_SECURE_BOOT_defconfig b/configs/T1040RDB_SECURE_BOOT_defconfig
index f0705ce..910b984 100644
--- a/configs/T1040RDB_SECURE_BOOT_defconfig
+++ b/configs/T1040RDB_SECURE_BOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1040RDB=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -44,6 +44,8 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1040RDB_SPIFLASH_defconfig b/configs/T1040RDB_SPIFLASH_defconfig
index cd30d8a..65ab4e0 100644
--- a/configs/T1040RDB_SPIFLASH_defconfig
+++ b/configs/T1040RDB_SPIFLASH_defconfig
@@ -3,16 +3,16 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1040RDB=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -61,6 +61,8 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1040RDB_defconfig b/configs/T1040RDB_defconfig
index f5c2c17..e8c5393 100644
--- a/configs/T1040RDB_defconfig
+++ b/configs/T1040RDB_defconfig
@@ -45,6 +45,8 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index 05544f0..f5a3c44 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -7,9 +7,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042D4RDB=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -65,6 +65,8 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index f8f5998..18e51b1 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -8,9 +8,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042D4RDB=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -62,6 +62,8 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1042D4RDB_SECURE_BOOT_defconfig b/configs/T1042D4RDB_SECURE_BOOT_defconfig
index 066ac3f..f460b17 100644
--- a/configs/T1042D4RDB_SECURE_BOOT_defconfig
+++ b/configs/T1042D4RDB_SECURE_BOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042D4RDB=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -44,6 +44,8 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index ebb62df..093d233 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -3,16 +3,16 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042D4RDB=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -65,6 +65,8 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index 4e66073..95160cd 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -50,6 +50,8 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
index 5b076ea..167325f 100644
--- a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
+++ b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
@@ -2,14 +2,14 @@
 CONFIG_SYS_TEXT_BASE=0x30001000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042RDB_PI=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -65,6 +65,8 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1042RDB_PI_NAND_defconfig b/configs/T1042RDB_PI_NAND_defconfig
index 49baa03..90bbee2 100644
--- a/configs/T1042RDB_PI_NAND_defconfig
+++ b/configs/T1042RDB_PI_NAND_defconfig
@@ -7,9 +7,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042RDB_PI=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -63,6 +63,8 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1042RDB_PI_SDCARD_defconfig b/configs/T1042RDB_PI_SDCARD_defconfig
index c9a27c3..ae664df 100644
--- a/configs/T1042RDB_PI_SDCARD_defconfig
+++ b/configs/T1042RDB_PI_SDCARD_defconfig
@@ -8,9 +8,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042RDB_PI=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -60,6 +60,8 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1042RDB_PI_SPIFLASH_defconfig b/configs/T1042RDB_PI_SPIFLASH_defconfig
index aef96d0..ef65465 100644
--- a/configs/T1042RDB_PI_SPIFLASH_defconfig
+++ b/configs/T1042RDB_PI_SPIFLASH_defconfig
@@ -3,16 +3,16 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042RDB_PI=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -63,6 +63,8 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1042RDB_PI_defconfig b/configs/T1042RDB_PI_defconfig
index 727d1f2..07ad865 100644
--- a/configs/T1042RDB_PI_defconfig
+++ b/configs/T1042RDB_PI_defconfig
@@ -47,6 +47,8 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1042RDB_SECURE_BOOT_defconfig b/configs/T1042RDB_SECURE_BOOT_defconfig
index 2184218..c5f39e8 100644
--- a/configs/T1042RDB_SECURE_BOOT_defconfig
+++ b/configs/T1042RDB_SECURE_BOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042RDB=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -43,6 +43,8 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1042RDB_defconfig b/configs/T1042RDB_defconfig
index cf8ae99..c94730d 100644
--- a/configs/T1042RDB_defconfig
+++ b/configs/T1042RDB_defconfig
@@ -44,6 +44,8 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index 2c3a2ed..dc83664 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -7,9 +7,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -64,6 +64,9 @@
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index a7c2fa8..24359ed 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -8,9 +8,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -61,6 +61,9 @@
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig
index ef5aa48..cc2449a 100644
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ b/configs/T2080QDS_SECURE_BOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
@@ -48,6 +48,9 @@
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index 1848a79..5d15960 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -3,16 +3,16 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -64,6 +64,9 @@
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
index a6c3215..c3fef7a 100644
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
@@ -41,6 +41,9 @@
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index 18d0a50..9cf2815 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -49,6 +49,9 @@
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index ca96fb8..292a3be 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -7,9 +7,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -66,6 +66,7 @@
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_FW_IN_NAND=y
+CONFIG_PHY_REALTEK=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index 1c21dc6..b53a0ad 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -8,9 +8,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -63,6 +63,7 @@
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_FW_IN_MMC=y
+CONFIG_PHY_REALTEK=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T2080RDB_SECURE_BOOT_defconfig b/configs/T2080RDB_SECURE_BOOT_defconfig
index 44dbfb0..a1f8d3d 100644
--- a/configs/T2080RDB_SECURE_BOOT_defconfig
+++ b/configs/T2080RDB_SECURE_BOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -45,6 +45,7 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
+CONFIG_PHY_REALTEK=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index 8c45787..ddf273f 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -3,16 +3,16 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -66,6 +66,7 @@
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_FW_IN_SPIFLASH=y
+CONFIG_PHY_REALTEK=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
index e6de728..6c16bfa 100644
--- a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
@@ -38,6 +38,7 @@
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_FW_IN_REMOTE=y
+CONFIG_PHY_REALTEK=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index ea43eb5..c81f546 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -50,6 +50,7 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
+CONFIG_PHY_REALTEK=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T2081QDS_NAND_defconfig b/configs/T2081QDS_NAND_defconfig
index 2e0e05e..85381c6 100644
--- a/configs/T2081QDS_NAND_defconfig
+++ b/configs/T2081QDS_NAND_defconfig
@@ -7,9 +7,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2081QDS=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -60,6 +60,9 @@
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T2081QDS_SDCARD_defconfig b/configs/T2081QDS_SDCARD_defconfig
index 4104885..bbc8b76 100644
--- a/configs/T2081QDS_SDCARD_defconfig
+++ b/configs/T2081QDS_SDCARD_defconfig
@@ -8,9 +8,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2081QDS=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -57,6 +57,9 @@
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T2081QDS_SPIFLASH_defconfig b/configs/T2081QDS_SPIFLASH_defconfig
index 242b11c..b02505b 100644
--- a/configs/T2081QDS_SPIFLASH_defconfig
+++ b/configs/T2081QDS_SPIFLASH_defconfig
@@ -3,16 +3,16 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2081QDS=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -60,6 +60,9 @@
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
index 8d00ad6..a10f39b 100644
--- a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
@@ -36,6 +36,9 @@
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T2081QDS_defconfig b/configs/T2081QDS_defconfig
index bfa40b5..22ca083 100644
--- a/configs/T2081QDS_defconfig
+++ b/configs/T2081QDS_defconfig
@@ -44,6 +44,9 @@
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T4160QDS_NAND_defconfig b/configs/T4160QDS_NAND_defconfig
index 05e4a61..ddff896 100644
--- a/configs/T4160QDS_NAND_defconfig
+++ b/configs/T4160QDS_NAND_defconfig
@@ -7,9 +7,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T4160QDS=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -53,6 +53,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T4160QDS_SDCARD_defconfig b/configs/T4160QDS_SDCARD_defconfig
index fe12693..5d25353 100644
--- a/configs/T4160QDS_SDCARD_defconfig
+++ b/configs/T4160QDS_SDCARD_defconfig
@@ -8,9 +8,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T4160QDS=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -50,6 +50,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T4160QDS_SECURE_BOOT_defconfig b/configs/T4160QDS_SECURE_BOOT_defconfig
index 8e003ed..8934c3e 100644
--- a/configs/T4160QDS_SECURE_BOOT_defconfig
+++ b/configs/T4160QDS_SECURE_BOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T4160QDS=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -37,6 +37,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T4160QDS_defconfig b/configs/T4160QDS_defconfig
index 37ef521..d0d12906 100644
--- a/configs/T4160QDS_defconfig
+++ b/configs/T4160QDS_defconfig
@@ -37,6 +37,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T4160RDB_defconfig b/configs/T4160RDB_defconfig
index 438052f..f3c7e1e 100644
--- a/configs/T4160RDB_defconfig
+++ b/configs/T4160RDB_defconfig
@@ -37,7 +37,10 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
 CONFIG_PHY_CORTINA=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T4240QDS_NAND_defconfig b/configs/T4240QDS_NAND_defconfig
index cfa0356..f971cee 100644
--- a/configs/T4240QDS_NAND_defconfig
+++ b/configs/T4240QDS_NAND_defconfig
@@ -7,9 +7,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T4240QDS=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -53,6 +53,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T4240QDS_SDCARD_defconfig b/configs/T4240QDS_SDCARD_defconfig
index 67efee9..5e662be 100644
--- a/configs/T4240QDS_SDCARD_defconfig
+++ b/configs/T4240QDS_SDCARD_defconfig
@@ -8,9 +8,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T4240QDS=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -50,6 +50,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T4240QDS_SECURE_BOOT_defconfig b/configs/T4240QDS_SECURE_BOOT_defconfig
index 4808a49..807d5b58 100644
--- a/configs/T4240QDS_SECURE_BOOT_defconfig
+++ b/configs/T4240QDS_SECURE_BOOT_defconfig
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T4240QDS=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -37,6 +37,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
index 29cadfa..2bc30bb 100644
--- a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
@@ -33,6 +33,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T4240QDS_defconfig b/configs/T4240QDS_defconfig
index 3d7aa9f..84341f7 100644
--- a/configs/T4240QDS_defconfig
+++ b/configs/T4240QDS_defconfig
@@ -37,6 +37,9 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index 17be2e7..646cd88 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -8,9 +8,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T4240RDB=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -54,7 +54,10 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
 CONFIG_PHY_CORTINA=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index 426ddef..d74afc7 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -42,7 +42,10 @@
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
 CONFIG_PHY_CORTINA=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig
index 8afc884..96ce4de 100644
--- a/configs/TQM834x_defconfig
+++ b/configs/TQM834x_defconfig
@@ -150,7 +150,15 @@
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/TWR-P1025_defconfig b/configs/TWR-P1025_defconfig
index c52263b..e48454a 100644
--- a/configs/TWR-P1025_defconfig
+++ b/configs/TWR-P1025_defconfig
@@ -41,7 +41,15 @@
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/UCP1020_defconfig b/configs/UCP1020_defconfig
index e0162e0..8ad1c04 100644
--- a/configs/UCP1020_defconfig
+++ b/configs/UCP1020_defconfig
@@ -40,7 +40,15 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/Wits_Pro_A20_DKT_defconfig b/configs/Wits_Pro_A20_DKT_defconfig
index 8630f39..8dbf6cd 100644
--- a/configs/Wits_Pro_A20_DKT_defconfig
+++ b/configs/Wits_Pro_A20_DKT_defconfig
@@ -14,6 +14,7 @@
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wits-pro-a20-dkt"
 CONFIG_SCSI_AHCI=y
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
diff --git a/configs/a64-olinuxino-emmc_defconfig b/configs/a64-olinuxino-emmc_defconfig
index 08687cb..b620582 100644
--- a/configs/a64-olinuxino-emmc_defconfig
+++ b/configs/a64-olinuxino-emmc_defconfig
@@ -6,7 +6,7 @@
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-olinuxino-emmc"
-CONFIG_SUN8I_EMAC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_SUN8I_EMAC=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
diff --git a/configs/adp-ae3xx_defconfig b/configs/adp-ae3xx_defconfig
index 67e9656..6216447 100644
--- a/configs/adp-ae3xx_defconfig
+++ b/configs/adp-ae3xx_defconfig
@@ -1,8 +1,8 @@
 CONFIG_NDS32=y
 CONFIG_SYS_TEXT_BASE=0x4A000000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x140000
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_TARGET_ADP_AE3XX=y
 CONFIG_FIT=y
diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig
index 7540d30..58296fd 100644
--- a/configs/ae350_rv32_spl_xip_defconfig
+++ b/configs/ae350_rv32_spl_xip_defconfig
@@ -3,8 +3,8 @@
 CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
-CONFIG_TARGET_AX25_AE350=y
 CONFIG_SPL_TEXT_BASE=0x80000000
+CONFIG_TARGET_AX25_AE350=y
 CONFIG_RISCV_SMODE=y
 CONFIG_XIP=y
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig
index 99a0035..8063b77 100644
--- a/configs/ae350_rv64_spl_xip_defconfig
+++ b/configs/ae350_rv64_spl_xip_defconfig
@@ -3,8 +3,8 @@
 CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
-CONFIG_TARGET_AX25_AE350=y
 CONFIG_SPL_TEXT_BASE=0x80000000
+CONFIG_TARGET_AX25_AE350=y
 CONFIG_ARCH_RV64I=y
 CONFIG_RISCV_SMODE=y
 CONFIG_XIP=y
diff --git a/configs/alt_defconfig b/configs/alt_defconfig
index 31e00ab..105c478 100644
--- a/configs/alt_defconfig
+++ b/configs/alt_defconfig
@@ -9,8 +9,9 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
 CONFIG_DM_GPIO=y
 CONFIG_ARCH_RMOBILE_BOARD_STRING="Alt"
 CONFIG_R8A7794=y
@@ -30,7 +31,6 @@
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
@@ -73,6 +73,7 @@
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_MTD=y
+CONFIG_BITBANGMII=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ8XXX=y
 CONFIG_DM_ETH=y
diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig
index d8a7b7d..64c1c53 100644
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig
@@ -49,6 +49,8 @@
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_SMSC=y
 CONFIG_DM_ETH=y
 CONFIG_PHY_GIGE=y
 CONFIG_MII=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 66899c2..8d8276b 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -58,6 +58,8 @@
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_SMSC=y
 CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig
index b003381..01333e7 100644
--- a/configs/am335x_guardian_defconfig
+++ b/configs/am335x_guardian_defconfig
@@ -11,9 +11,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0x44E3E000
 CONFIG_SPL=y
 CONFIG_BOOTSTAGE_STASH_ADDR=0x0
+CONFIG_ENV_OFFSET_REDUND=0x540000
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_CONSOLE_MUX=y
@@ -23,11 +23,6 @@
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_SEPARATE_BSS=y
 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_OFFSET_REDUND=0x540000
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_ENV_IS_NOWHERE=y
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_ETH_SUPPORT=y
 CONFIG_SPL_I2C_SUPPORT=y
@@ -45,7 +40,6 @@
 CONFIG_CMD_SPL_NAND_OFS=0x0
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_LED is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
@@ -53,6 +47,7 @@
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_LED is not set
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(SPL),256k(SPL.backup1),256k(SPL.backup2),256k(SPL.backup3),1m(u-boot),1m(u-boot.backup1),1m(u-boot-2),1m(u-boot-2.backup1),256k(u-boot-env),256k(u-boot-env.backup1),256k(splash-screen),-(UBI)"
@@ -61,11 +56,13 @@
 # CONFIG_ISO_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
-# CONFIG_SPL_OF_CONTROL is not set
 CONFIG_DEFAULT_DEVICE_TREE="am335x-guardian"
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_ENV_IS_NOWHERE=y
 CONFIG_SPL_DM=y
 CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_BOOTCOUNT_AM33XX=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
 CONFIG_MISC=y
@@ -97,5 +94,5 @@
 CONFIG_USB_ETHER=y
 CONFIG_SPL_WDT=y
 CONFIG_FAT_WRITE=y
-CONFIG_SPL_OF_LIBFDT=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
+CONFIG_SPL_OF_LIBFDT=y
diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig
index 1dceea5..393665f 100644
--- a/configs/am335x_hs_evm_defconfig
+++ b/configs/am335x_hs_evm_defconfig
@@ -51,6 +51,8 @@
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_SMSC=y
 CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig
index a7d76c8..a8afad9 100644
--- a/configs/am335x_hs_evm_uart_defconfig
+++ b/configs/am335x_hs_evm_uart_defconfig
@@ -53,6 +53,8 @@
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_SMSC=y
 CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
diff --git a/configs/am335x_igep003x_defconfig b/configs/am335x_igep003x_defconfig
index e0efd5b..633c35f 100644
--- a/configs/am335x_igep003x_defconfig
+++ b/configs/am335x_igep003x_defconfig
@@ -67,6 +67,7 @@
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_PHY_SMSC=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
 CONFIG_SPI=y
diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig
index b7ee1a7..c0bb093 100644
--- a/configs/am335x_shc_defconfig
+++ b/configs/am335x_shc_defconfig
@@ -49,6 +49,7 @@
 CONFIG_DM_MMC=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_SMSC=y
 CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig
index 641d15b..026a815 100644
--- a/configs/am335x_shc_ict_defconfig
+++ b/configs/am335x_shc_ict_defconfig
@@ -50,6 +50,7 @@
 CONFIG_DM_MMC=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_SMSC=y
 CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig
index 49c0966..91c1ce7 100644
--- a/configs/am335x_shc_netboot_defconfig
+++ b/configs/am335x_shc_netboot_defconfig
@@ -51,6 +51,7 @@
 CONFIG_DM_MMC=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_SMSC=y
 CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig
index a2dc081..4fa7b6d 100644
--- a/configs/am335x_shc_sdboot_defconfig
+++ b/configs/am335x_shc_sdboot_defconfig
@@ -50,6 +50,7 @@
 CONFIG_DM_MMC=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_SMSC=y
 CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig
index ecbe094..238164a 100644
--- a/configs/am335x_sl50_defconfig
+++ b/configs/am335x_sl50_defconfig
@@ -48,6 +48,7 @@
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_OMAP_HS=y
+CONFIG_PHY_SMSC=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
 CONFIG_SPI=y
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index d52745f..39facf1 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -4,8 +4,8 @@
 CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_SYS_TEXT_BASE=0x30000000
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x110000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_AM43XX=y
 CONFIG_ENV_OFFSET_REDUND=0x120000
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index 21de522..db48785 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -42,7 +42,6 @@
 CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
 CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
 CONFIG_ENV_IS_IN_FAT=y
-CONFIG_ENV_FAT_INTERFACE="mmc"
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index f0ddb02..42942e9 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -2,6 +2,7 @@
 CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_OMAP54XX=y
 CONFIG_TARGET_AM57XX_EVM=y
@@ -11,8 +12,8 @@
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_ARMV7_LPAE=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x40300000
+CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_OF_BOARD_SETUP=y
@@ -31,7 +32,6 @@
 # CONFIG_SPL_NAND_SUPPORT is not set
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_CMD_ADTIMG=y
 CONFIG_CMD_ABOOTIMG=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index 5db1877..f80ec38 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -3,6 +3,7 @@
 CONFIG_TI_SECURE_DEVICE=y
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_OMAP54XX=y
 CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
@@ -35,7 +36,6 @@
 CONFIG_SPL_DMA=y
 # CONFIG_SPL_NAND_SUPPORT is not set
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_CMD_ADTIMG=y
 CONFIG_CMD_ABOOTIMG=y
 CONFIG_CMD_BCB=y
diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig
index 5ef1518..3b155cc 100644
--- a/configs/am57xx_hs_evm_usb_defconfig
+++ b/configs/am57xx_hs_evm_usb_defconfig
@@ -4,6 +4,7 @@
 CONFIG_ISW_ENTRY_ADDR=0x40306d50
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_OMAP54XX=y
 CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
@@ -37,7 +38,6 @@
 # CONFIG_SPL_NAND_SUPPORT is not set
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_SPL_USB_GADGET=y
 CONFIG_SPL_DFU=y
 CONFIG_SPL_YMODEM_SUPPORT=y
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index 542bbd9..d74a2d0 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -7,6 +7,7 @@
 CONFIG_TARGET_AM654_A53_EVM=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x680000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
@@ -37,11 +38,9 @@
 CONFIG_SPL_MTD_SUPPORT=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 # CONFIG_SPL_SPI_FLASH_TINY is not set
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_DFU=y
@@ -50,7 +49,6 @@
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_REMOTEPROC=y
-CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
@@ -97,7 +95,7 @@
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_SPI_FLASH_MTD=y
diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig
index b795526..4fc199e 100644
--- a/configs/am65x_evm_r5_defconfig
+++ b/configs/am65x_evm_r5_defconfig
@@ -8,6 +8,7 @@
 CONFIG_K3_EARLY_CONS=y
 CONFIG_TARGET_AM654_R5_EVM=y
 CONFIG_ENV_SIZE=0x20000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
@@ -40,7 +41,6 @@
 # CONFIG_SPL_SPI_FLASH_TINY is not set
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
@@ -58,7 +58,6 @@
 CONFIG_SPL_MULTI_DTB_FIT=y
 CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
 CONFIG_ENV_IS_IN_FAT=y
-CONFIG_ENV_FAT_INTERFACE="mmc"
 CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
@@ -79,7 +78,6 @@
 CONFIG_SYS_I2C_OMAP24XX=y
 CONFIG_DM_MAILBOX=y
 CONFIG_K3_SEC_PROXY=y
-CONFIG_MISC=y
 CONFIG_K3_AVS0=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
diff --git a/configs/am65x_hs_evm_a53_defconfig b/configs/am65x_hs_evm_a53_defconfig
index 9f43cee..1179538 100644
--- a/configs/am65x_hs_evm_a53_defconfig
+++ b/configs/am65x_hs_evm_a53_defconfig
@@ -8,12 +8,14 @@
 CONFIG_TARGET_AM654_A53_EVM=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x680000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_OFFSET_REDUND=0x6A0000
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -39,11 +41,9 @@
 CONFIG_SPL_MTD_SUPPORT=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 # CONFIG_SPL_SPI_FLASH_TINY is not set
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_DFU=y
@@ -52,7 +52,6 @@
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_REMOTEPROC=y
-CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
@@ -67,7 +66,6 @@
 CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_OFFSET_REDUND=0x6A0000
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
@@ -99,7 +97,7 @@
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_SPI_FLASH_MTD=y
diff --git a/configs/am65x_hs_evm_r5_defconfig b/configs/am65x_hs_evm_r5_defconfig
index bbf50bf..b2d6386 100644
--- a/configs/am65x_hs_evm_r5_defconfig
+++ b/configs/am65x_hs_evm_r5_defconfig
@@ -9,6 +9,7 @@
 CONFIG_K3_EARLY_CONS=y
 CONFIG_TARGET_AM654_R5_EVM=y
 CONFIG_ENV_SIZE=0x20000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
@@ -42,7 +43,6 @@
 # CONFIG_SPL_SPI_FLASH_TINY is not set
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
@@ -60,7 +60,6 @@
 CONFIG_SPL_MULTI_DTB_FIT=y
 CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
 CONFIG_ENV_IS_IN_FAT=y
-CONFIG_ENV_FAT_INTERFACE="mmc"
 CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
@@ -81,7 +80,6 @@
 CONFIG_SYS_I2C_OMAP24XX=y
 CONFIG_DM_MAILBOX=y
 CONFIG_K3_SEC_PROXY=y
-CONFIG_MISC=y
 CONFIG_K3_AVS0=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
diff --git a/configs/ap121_defconfig b/configs/ap121_defconfig
index 1001cae..af83ef5 100644
--- a/configs/ap121_defconfig
+++ b/configs/ap121_defconfig
@@ -2,8 +2,8 @@
 CONFIG_SYS_TEXT_BASE=0x9F000000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x40000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xb8020000
 CONFIG_DEBUG_UART_CLOCK=25000000
diff --git a/configs/ap143_defconfig b/configs/ap143_defconfig
index 1058fc0..3d5849d 100644
--- a/configs/ap143_defconfig
+++ b/configs/ap143_defconfig
@@ -2,8 +2,8 @@
 CONFIG_SYS_TEXT_BASE=0x9F000000
 CONFIG_SYS_MALLOC_F_LEN=0x800
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x40000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xb8020000
 CONFIG_DEBUG_UART_CLOCK=25000000
diff --git a/configs/ap152_defconfig b/configs/ap152_defconfig
index 7124dcd..6ed89a2 100644
--- a/configs/ap152_defconfig
+++ b/configs/ap152_defconfig
@@ -2,8 +2,8 @@
 CONFIG_SYS_TEXT_BASE=0x9F000000
 CONFIG_SYS_MALLOC_F_LEN=0x800
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x40000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xb8020000
 CONFIG_DEBUG_UART_CLOCK=25000000
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index 12fe989..ea18ef9 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -4,17 +4,17 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_APALIS_IMX6=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFDE00
+CONFIG_TARGET_APALIS_IMX6=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 CONFIG_CMD_HDMIDETECT=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig
index 25ac75d..01990bd 100644
--- a/configs/aristainetos2_defconfig
+++ b/configs/aristainetos2_defconfig
@@ -2,8 +2,8 @@
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SYS_MALLOC_F_LEN=0xe000
-CONFIG_TARGET_ARISTAINETOS2=y
 CONFIG_ENV_OFFSET=0xD0000
+CONFIG_TARGET_ARISTAINETOS2=y
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_OFFSET_REDUND=0xE0000
diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig
index d1a20b6..318b81e 100644
--- a/configs/aristainetos2b_defconfig
+++ b/configs/aristainetos2b_defconfig
@@ -2,8 +2,8 @@
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SYS_MALLOC_F_LEN=0xe000
-CONFIG_TARGET_ARISTAINETOS2B=y
 CONFIG_ENV_OFFSET=0xD0000
+CONFIG_TARGET_ARISTAINETOS2B=y
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_OFFSET_REDUND=0xE0000
diff --git a/configs/aristainetos2bcsl_defconfig b/configs/aristainetos2bcsl_defconfig
index 712e632..0ff67a4 100644
--- a/configs/aristainetos2bcsl_defconfig
+++ b/configs/aristainetos2bcsl_defconfig
@@ -2,8 +2,8 @@
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SYS_MALLOC_F_LEN=0xe000
-CONFIG_TARGET_ARISTAINETOS2BCSL=y
 CONFIG_ENV_OFFSET=0xD0000
+CONFIG_TARGET_ARISTAINETOS2BCSL=y
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_OFFSET_REDUND=0xE0000
diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig
index 8611915..ffd4360 100644
--- a/configs/aristainetos2c_defconfig
+++ b/configs/aristainetos2c_defconfig
@@ -2,8 +2,8 @@
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SYS_MALLOC_F_LEN=0xe000
-CONFIG_TARGET_ARISTAINETOS2C=y
 CONFIG_ENV_OFFSET=0xD0000
+CONFIG_TARGET_ARISTAINETOS2C=y
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_OFFSET_REDUND=0xE0000
diff --git a/configs/armadillo-800eva_defconfig b/configs/armadillo-800eva_defconfig
index d160708..ec35221 100644
--- a/configs/armadillo-800eva_defconfig
+++ b/configs/armadillo-800eva_defconfig
@@ -36,6 +36,8 @@
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0x40000
 # CONFIG_MMC is not set
+CONFIG_BITBANGMII=y
+CONFIG_PHY_SMSC=y
 CONFIG_SH_ETHER=y
 CONFIG_SCIF_CONSOLE=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9260ek_dataflash_cs0_defconfig b/configs/at91sam9260ek_dataflash_cs0_defconfig
index 3d5176f..854ea4f 100644
--- a/configs/at91sam9260ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9260ek_dataflash_cs0_defconfig
@@ -5,8 +5,8 @@
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x4200
-CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_ENV_OFFSET=0x4200
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
diff --git a/configs/at91sam9260ek_dataflash_cs1_defconfig b/configs/at91sam9260ek_dataflash_cs1_defconfig
index a78117a..4fbcd31 100644
--- a/configs/at91sam9260ek_dataflash_cs1_defconfig
+++ b/configs/at91sam9260ek_dataflash_cs1_defconfig
@@ -5,8 +5,8 @@
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x4200
-CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_ENV_OFFSET=0x4200
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
diff --git a/configs/at91sam9261ek_dataflash_cs0_defconfig b/configs/at91sam9261ek_dataflash_cs0_defconfig
index 607d181..6585125 100644
--- a/configs/at91sam9261ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs0_defconfig
@@ -4,8 +4,8 @@
 CONFIG_TARGET_AT91SAM9261EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x4200
-CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_ENV_OFFSET=0x4200
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
diff --git a/configs/at91sam9261ek_dataflash_cs3_defconfig b/configs/at91sam9261ek_dataflash_cs3_defconfig
index 30e27a4..f04e454 100644
--- a/configs/at91sam9261ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs3_defconfig
@@ -4,8 +4,8 @@
 CONFIG_TARGET_AT91SAM9261EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x4200
-CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_ENV_OFFSET=0x4200
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig
index a03be17..bf82477 100644
--- a/configs/at91sam9263ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9263ek_dataflash_cs0_defconfig
@@ -5,8 +5,8 @@
 CONFIG_TARGET_AT91SAM9263EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x4200
-CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_ENV_OFFSET=0x4200
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig
index a03be17..bf82477 100644
--- a/configs/at91sam9263ek_dataflash_defconfig
+++ b/configs/at91sam9263ek_dataflash_defconfig
@@ -5,8 +5,8 @@
 CONFIG_TARGET_AT91SAM9263EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x4200
-CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_ENV_OFFSET=0x4200
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
diff --git a/configs/at91sam9g10ek_dataflash_cs0_defconfig b/configs/at91sam9g10ek_dataflash_cs0_defconfig
index 827ad0e..914dcde 100644
--- a/configs/at91sam9g10ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs0_defconfig
@@ -4,8 +4,8 @@
 CONFIG_TARGET_AT91SAM9261EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x4200
-CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_ENV_OFFSET=0x4200
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
diff --git a/configs/at91sam9g10ek_dataflash_cs3_defconfig b/configs/at91sam9g10ek_dataflash_cs3_defconfig
index c01f697..bc11dbb 100644
--- a/configs/at91sam9g10ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs3_defconfig
@@ -4,8 +4,8 @@
 CONFIG_TARGET_AT91SAM9261EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x4200
-CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_ENV_OFFSET=0x4200
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
diff --git a/configs/at91sam9g20ek_dataflash_cs0_defconfig b/configs/at91sam9g20ek_dataflash_cs0_defconfig
index 0a841fe..cf1f5c0 100644
--- a/configs/at91sam9g20ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9g20ek_dataflash_cs0_defconfig
@@ -5,8 +5,8 @@
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x4200
-CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_ENV_OFFSET=0x4200
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
diff --git a/configs/at91sam9g20ek_dataflash_cs1_defconfig b/configs/at91sam9g20ek_dataflash_cs1_defconfig
index 18d951a..025cd21 100644
--- a/configs/at91sam9g20ek_dataflash_cs1_defconfig
+++ b/configs/at91sam9g20ek_dataflash_cs1_defconfig
@@ -5,8 +5,8 @@
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x4200
-CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_ENV_OFFSET=0x4200
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig
index f816d27..be8ef51 100644
--- a/configs/at91sam9n12ek_spiflash_defconfig
+++ b/configs/at91sam9n12ek_spiflash_defconfig
@@ -4,8 +4,8 @@
 CONFIG_TARGET_AT91SAM9N12EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x3000
-CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x5000
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
diff --git a/configs/at91sam9rlek_dataflash_defconfig b/configs/at91sam9rlek_dataflash_defconfig
index 6c25470..e63b061 100644
--- a/configs/at91sam9rlek_dataflash_defconfig
+++ b/configs/at91sam9rlek_dataflash_defconfig
@@ -5,8 +5,8 @@
 CONFIG_TARGET_AT91SAM9RLEK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x4200
-CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_ENV_OFFSET=0x4200
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig
index 64f7fff..c43a5cb 100644
--- a/configs/at91sam9x5ek_dataflash_defconfig
+++ b/configs/at91sam9x5ek_dataflash_defconfig
@@ -4,8 +4,8 @@
 CONFIG_TARGET_AT91SAM9X5EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x4200
-CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_ENV_OFFSET=0x4200
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig
index 792d46f..f418bfb 100644
--- a/configs/at91sam9x5ek_spiflash_defconfig
+++ b/configs/at91sam9x5ek_spiflash_defconfig
@@ -4,8 +4,8 @@
 CONFIG_TARGET_AT91SAM9X5EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x3000
-CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x5000
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
diff --git a/configs/at91sam9xeek_dataflash_cs0_defconfig b/configs/at91sam9xeek_dataflash_cs0_defconfig
index d637d36..6ef2574 100644
--- a/configs/at91sam9xeek_dataflash_cs0_defconfig
+++ b/configs/at91sam9xeek_dataflash_cs0_defconfig
@@ -5,8 +5,8 @@
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x4200
-CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_ENV_OFFSET=0x4200
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
diff --git a/configs/at91sam9xeek_dataflash_cs1_defconfig b/configs/at91sam9xeek_dataflash_cs1_defconfig
index 06288ce..3e7d2be 100644
--- a/configs/at91sam9xeek_dataflash_cs1_defconfig
+++ b/configs/at91sam9xeek_dataflash_cs1_defconfig
@@ -5,8 +5,8 @@
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x4200
-CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_ENV_OFFSET=0x4200
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig
index fcfdd0d..91f74e5 100644
--- a/configs/axs101_defconfig
+++ b/configs/axs101_defconfig
@@ -28,7 +28,6 @@
 CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="axs101"
 CONFIG_ENV_IS_IN_FAT=y
-CONFIG_ENV_FAT_INTERFACE="mmc"
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig
index 29f5a2a..ab5f699 100644
--- a/configs/axs103_defconfig
+++ b/configs/axs103_defconfig
@@ -28,7 +28,6 @@
 CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="axs103"
 CONFIG_ENV_IS_IN_FAT=y
-CONFIG_ENV_FAT_INTERFACE="mmc"
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/bananapi_m1_plus_defconfig b/configs/bananapi_m1_plus_defconfig
index 3813b6e..e533555 100644
--- a/configs/bananapi_m1_plus_defconfig
+++ b/configs/bananapi_m1_plus_defconfig
@@ -12,6 +12,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi-m1-plus"
 CONFIG_NETCONSOLE=y
 CONFIG_SCSI_AHCI=y
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig
index 3b4d5de..80a817a 100644
--- a/configs/bayleybay_defconfig
+++ b/configs/bayleybay_defconfig
@@ -1,8 +1,8 @@
 CONFIG_X86=y
 CONFIG_SYS_TEXT_BASE=0xFFF00000
 CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x6FF000
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_VENDOR_INTEL=y
 CONFIG_TARGET_BAYLEYBAY=y
diff --git a/configs/bcm7445_defconfig b/configs/bcm7445_defconfig
index 20526d0..0ae0595 100644
--- a/configs/bcm7445_defconfig
+++ b/configs/bcm7445_defconfig
@@ -3,8 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0x80100000
 CONFIG_TARGET_BCM7445=y
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x1E0000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_NR_DRAM_BANKS=3
 CONFIG_ENV_OFFSET_REDUND=0x1F0000
 CONFIG_FIT=y
diff --git a/configs/bcm911360_entphn-ns_defconfig b/configs/bcm911360_entphn-ns_defconfig
index cca6558..5806971 100644
--- a/configs/bcm911360_entphn-ns_defconfig
+++ b/configs/bcm911360_entphn-ns_defconfig
@@ -21,6 +21,7 @@
 CONFIG_CMD_FAT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 # CONFIG_MMC is not set
+CONFIG_PHY_BROADCOM=y
 CONFIG_CONS_INDEX=3
 CONFIG_SYS_NS16550=y
 CONFIG_SHA1=y
diff --git a/configs/bcm911360_entphn_defconfig b/configs/bcm911360_entphn_defconfig
index 710d025..9fbaa4e 100644
--- a/configs/bcm911360_entphn_defconfig
+++ b/configs/bcm911360_entphn_defconfig
@@ -21,6 +21,7 @@
 CONFIG_CMD_FAT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 # CONFIG_MMC is not set
+CONFIG_PHY_BROADCOM=y
 CONFIG_CONS_INDEX=3
 CONFIG_SYS_NS16550=y
 CONFIG_SHA1=y
diff --git a/configs/bcm911360k_defconfig b/configs/bcm911360k_defconfig
index 6ff9bb7..33015dc 100644
--- a/configs/bcm911360k_defconfig
+++ b/configs/bcm911360k_defconfig
@@ -21,6 +21,7 @@
 CONFIG_CMD_FAT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 # CONFIG_MMC is not set
+CONFIG_PHY_BROADCOM=y
 CONFIG_CONS_INDEX=3
 CONFIG_SYS_NS16550=y
 CONFIG_SHA1=y
diff --git a/configs/bcm958300k-ns_defconfig b/configs/bcm958300k-ns_defconfig
index 19eca9d..f30f1bf 100644
--- a/configs/bcm958300k-ns_defconfig
+++ b/configs/bcm958300k-ns_defconfig
@@ -21,6 +21,7 @@
 CONFIG_CMD_FAT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 # CONFIG_MMC is not set
+CONFIG_PHY_BROADCOM=y
 CONFIG_CONS_INDEX=3
 CONFIG_SYS_NS16550=y
 CONFIG_SHA1=y
diff --git a/configs/bcm958300k_defconfig b/configs/bcm958300k_defconfig
index 6ff9bb7..33015dc 100644
--- a/configs/bcm958300k_defconfig
+++ b/configs/bcm958300k_defconfig
@@ -21,6 +21,7 @@
 CONFIG_CMD_FAT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 # CONFIG_MMC is not set
+CONFIG_PHY_BROADCOM=y
 CONFIG_CONS_INDEX=3
 CONFIG_SYS_NS16550=y
 CONFIG_SHA1=y
diff --git a/configs/bcm958305k_defconfig b/configs/bcm958305k_defconfig
index 6ff9bb7..33015dc 100644
--- a/configs/bcm958305k_defconfig
+++ b/configs/bcm958305k_defconfig
@@ -21,6 +21,7 @@
 CONFIG_CMD_FAT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 # CONFIG_MMC is not set
+CONFIG_PHY_BROADCOM=y
 CONFIG_CONS_INDEX=3
 CONFIG_SYS_NS16550=y
 CONFIG_SHA1=y
diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig
index b4fcccf..87dae59 100644
--- a/configs/birdland_bav335a_defconfig
+++ b/configs/birdland_bav335a_defconfig
@@ -51,6 +51,7 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_SMSC=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
 CONFIG_SPI=y
diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig
index b9f8bca..5ee9878 100644
--- a/configs/birdland_bav335b_defconfig
+++ b/configs/birdland_bav335b_defconfig
@@ -51,6 +51,7 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_SMSC=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
 CONFIG_SPI=y
diff --git a/configs/blanche_defconfig b/configs/blanche_defconfig
index 64b7bcc..137acce 100644
--- a/configs/blanche_defconfig
+++ b/configs/blanche_defconfig
@@ -5,8 +5,8 @@
 CONFIG_SYS_TEXT_BASE=0x00000000
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x40000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_ARCH_RMOBILE_BOARD_STRING="Blanche"
 CONFIG_R8A7792=y
diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig
index 59c2e2a..09370b7 100644
--- a/configs/brppt1_mmc_defconfig
+++ b/configs/brppt1_mmc_defconfig
@@ -46,6 +46,7 @@
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
+CONFIG_CMD_BKOPS_ENABLE=y
 CONFIG_CMD_PART=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_ITEST is not set
@@ -54,7 +55,6 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_BOOTCOUNT=y
-CONFIG_CMD_BKOPS_ENABLE=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4=y
diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig
index a8a71d1..964b22b 100644
--- a/configs/brppt1_spi_defconfig
+++ b/configs/brppt1_spi_defconfig
@@ -5,8 +5,9 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x20000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_AM33XX=y
 CONFIG_TARGET_BRPPT1=y
@@ -39,7 +40,6 @@
 # CONFIG_SPL_NAND_SUPPORT is not set
 CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
@@ -53,6 +53,7 @@
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
+CONFIG_CMD_BKOPS_ENABLE=y
 CONFIG_CMD_PART=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_ITEST is not set
@@ -61,7 +62,6 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_BOOTCOUNT=y
-CONFIG_CMD_BKOPS_ENABLE=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4=y
diff --git a/configs/brppt2_defconfig b/configs/brppt2_defconfig
index 4fde3b9..c4eb03b 100644
--- a/configs/brppt2_defconfig
+++ b/configs/brppt2_defconfig
@@ -8,10 +8,11 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x1000
-CONFIG_TARGET_BRPPT2=y
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x20000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
+CONFIG_TARGET_BRPPT2=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068
 CONFIG_NR_DRAM_BANKS=1
@@ -33,7 +34,6 @@
 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_ELF is not set
diff --git a/configs/brsmarc1_defconfig b/configs/brsmarc1_defconfig
index bb71014..a7cf98f 100644
--- a/configs/brsmarc1_defconfig
+++ b/configs/brsmarc1_defconfig
@@ -5,8 +5,9 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x20000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_AM33XX=y
 CONFIG_SYS_MPUCLK=600
@@ -38,7 +39,6 @@
 # CONFIG_SPL_NAND_SUPPORT is not set
 CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig
index 48d3498..a934336 100644
--- a/configs/cgtqmx6eval_defconfig
+++ b/configs/cgtqmx6eval_defconfig
@@ -4,10 +4,11 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_CGTQMX6EVAL=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
+CONFIG_TARGET_CGTQMX6EVAL=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
@@ -28,7 +29,6 @@
 CONFIG_SPL_FS_EXT4=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CGT-QMX6-Quad U-Boot > "
@@ -64,6 +64,7 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
 CONFIG_MII=y
 CONFIG_SPI=y
 CONFIG_MXC_SPI=y
diff --git a/configs/cherryhill_defconfig b/configs/cherryhill_defconfig
index e3c2607..c3ad39c 100644
--- a/configs/cherryhill_defconfig
+++ b/configs/cherryhill_defconfig
@@ -1,8 +1,8 @@
 CONFIG_X86=y
 CONFIG_SYS_TEXT_BASE=0xFFE00000
 CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x5F0000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig
index 4c118a6..30100a3 100644
--- a/configs/chiliboard_defconfig
+++ b/configs/chiliboard_defconfig
@@ -45,6 +45,7 @@
 CONFIG_MMC_OMAP_HS=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_SMSC=y
 CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig
index a0b1c8d..b1ad7bd 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -2,6 +2,7 @@
 # CONFIG_SPL_USE_ARCH_MEMCPY is not set
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_TEXT_BASE=0x00100000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_ROCKCHIP_RK3288=y
 # CONFIG_SPL_MMC_SUPPORT is not set
 CONFIG_TARGET_CHROMEBIT_MICKEY=y
@@ -11,8 +12,9 @@
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0xff704000
+CONFIG_SPL_PAYLOAD="u-boot.img"
+CONFIG_DEBUG_UART=y
 CONFIG_USE_PREBOOT=y
 CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-mickey.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
@@ -22,9 +24,7 @@
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
 # CONFIG_SPL_CRC32_SUPPORT is not set
-CONFIG_SPL_PAYLOAD="u-boot.img"
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig
index 439c8cb..4f606e7 100644
--- a/configs/chromebook_bob_defconfig
+++ b/configs/chromebook_bob_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_TEXT_BASE=0x00200000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_ROCKCHIP_RK3399=y
 CONFIG_ROCKCHIP_BOOT_MODE_REG=0
 CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
@@ -12,8 +13,8 @@
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0xff8c2000
+CONFIG_DEBUG_UART=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -21,7 +22,6 @@
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig
index 67713ba..2039ea6 100644
--- a/configs/chromebook_coral_defconfig
+++ b/configs/chromebook_coral_defconfig
@@ -7,6 +7,7 @@
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xde000000
 CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_SPL_TEXT_BASE=0xfef10000
 CONFIG_VENDOR_GOOGLE=y
 CONFIG_TARGET_CHROMEBOOK_CORAL=y
 CONFIG_DEBUG_UART=y
@@ -15,7 +16,6 @@
 CONFIG_INTEL_CAR_CQOS=y
 CONFIG_X86_OFFSET_U_BOOT=0xffe00000
 CONFIG_X86_OFFSET_SPL=0xffe80000
-CONFIG_SPL_TEXT_BASE=0xfef10000
 CONFIG_BOOTSTAGE=y
 CONFIG_SPL_BOOTSTAGE=y
 CONFIG_TPL_BOOTSTAGE=y
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index 7ba0c95..16eee22 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -2,6 +2,7 @@
 # CONFIG_SPL_USE_ARCH_MEMCPY is not set
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_TEXT_BASE=0x00100000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_ROCKCHIP_RK3288=y
 # CONFIG_SPL_MMC_SUPPORT is not set
 CONFIG_SPL_STACK_R_ADDR=0x80000
@@ -10,8 +11,9 @@
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0xff704000
+CONFIG_SPL_PAYLOAD="u-boot.img"
+CONFIG_DEBUG_UART=y
 CONFIG_USE_PREBOOT=y
 CONFIG_SILENT_CONSOLE=y
 CONFIG_LOG=y
@@ -24,9 +26,7 @@
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
 # CONFIG_SPL_CRC32_SUPPORT is not set
-CONFIG_SPL_PAYLOAD="u-boot.img"
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig
index 5abd690..a13f6ea 100644
--- a/configs/chromebook_link64_defconfig
+++ b/configs/chromebook_link64_defconfig
@@ -1,12 +1,13 @@
 CONFIG_X86=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_SPL_TEXT_BASE=0xfffd0000
 CONFIG_X86_RUN_64BIT=y
 CONFIG_VENDOR_GOOGLE=y
 CONFIG_TARGET_CHROMEBOOK_LINK64=y
@@ -14,7 +15,6 @@
 CONFIG_HAVE_MRC=y
 CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
-CONFIG_SPL_TEXT_BASE=0xfffd0000
 CONFIG_FIT=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_BOOTSTAGE=y
diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
index 6ef9a27..de4186c 100644
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig
@@ -2,8 +2,8 @@
 CONFIG_SYS_TEXT_BASE=0xFFF00000
 CONFIG_SYS_MALLOC_F_LEN=0x2400
 CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0x3f8
diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig
index 46e1c18..2c04154 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -2,6 +2,7 @@
 # CONFIG_SPL_USE_ARCH_MEMCPY is not set
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_TEXT_BASE=0x00100000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_ROCKCHIP_RK3288=y
 # CONFIG_SPL_MMC_SUPPORT is not set
 CONFIG_TARGET_CHROMEBOOK_MINNIE=y
@@ -11,8 +12,9 @@
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0xff704000
+CONFIG_SPL_PAYLOAD="u-boot.img"
+CONFIG_DEBUG_UART=y
 CONFIG_USE_PREBOOT=y
 CONFIG_SILENT_CONSOLE=y
 CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-minnie.dtb"
@@ -23,9 +25,7 @@
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
 # CONFIG_SPL_CRC32_SUPPORT is not set
-CONFIG_SPL_PAYLOAD="u-boot.img"
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig
index 2f101c4..fb4d880 100644
--- a/configs/chromebook_samus_defconfig
+++ b/configs/chromebook_samus_defconfig
@@ -2,8 +2,8 @@
 CONFIG_SYS_TEXT_BASE=0xFFE00000
 CONFIG_SYS_MALLOC_F_LEN=0x1d00
 CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0x3f8
diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig
index cd1cc5f..a12a04b 100644
--- a/configs/chromebook_samus_tpl_defconfig
+++ b/configs/chromebook_samus_tpl_defconfig
@@ -2,12 +2,13 @@
 CONFIG_SYS_TEXT_BASE=0xffed0000
 CONFIG_SYS_MALLOC_F_LEN=0x1a00
 CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_SPL_TEXT_BASE=0xffe70000
 CONFIG_VENDOR_GOOGLE=y
 CONFIG_TARGET_CHROMEBOOK_SAMUS_TPL=y
 CONFIG_DEBUG_UART=y
@@ -16,7 +17,6 @@
 CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_X86_OFFSET_U_BOOT=0xfff00000
-CONFIG_SPL_TEXT_BASE=0xffe70000
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_SHOW_BOOT_PROGRESS=y
diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig
index 34cf727..b4116a3 100644
--- a/configs/chromebook_speedy_defconfig
+++ b/configs/chromebook_speedy_defconfig
@@ -2,6 +2,7 @@
 # CONFIG_SPL_USE_ARCH_MEMCPY is not set
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_TEXT_BASE=0x00100000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_ROCKCHIP_RK3288=y
 # CONFIG_SPL_MMC_SUPPORT is not set
 CONFIG_TARGET_CHROMEBOOK_SPEEDY=y
@@ -11,8 +12,9 @@
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0xff704000
+CONFIG_SPL_PAYLOAD="u-boot.img"
+CONFIG_DEBUG_UART=y
 CONFIG_USE_PREBOOT=y
 CONFIG_SILENT_CONSOLE=y
 CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb"
@@ -24,9 +26,7 @@
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
 # CONFIG_SPL_CRC32_SUPPORT is not set
-CONFIG_SPL_PAYLOAD="u-boot.img"
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig
index 0c970c8..48bcd94 100644
--- a/configs/chromebox_panther_defconfig
+++ b/configs/chromebox_panther_defconfig
@@ -1,8 +1,8 @@
 CONFIG_X86=y
 CONFIG_SYS_TEXT_BASE=0xFFF00000
 CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_VENDOR_GOOGLE=y
 CONFIG_TARGET_CHROMEBOX_PANTHER=y
diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig
index 2e88880..d276619 100644
--- a/configs/cl-som-imx7_defconfig
+++ b/configs/cl-som-imx7_defconfig
@@ -5,8 +5,8 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_TARGET_CL_SOM_IMX7=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
@@ -44,6 +44,7 @@
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
+# CONFIG_CMD_MDIO is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
@@ -71,6 +72,8 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
 CONFIG_MII=y
 CONFIG_DM_REGULATOR=y
 CONFIG_SPI=y
diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig
index 1566a4f..449c3a4 100644
--- a/configs/clearfog_defconfig
+++ b/configs/clearfog_defconfig
@@ -14,9 +14,9 @@
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BASE=0xd0012000
 CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
-CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=3
 CONFIG_USE_PREBOOT=y
@@ -31,7 +31,6 @@
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_MVEBU_BUBT=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
@@ -39,6 +38,7 @@
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_MVEBU_BUBT=y
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/clearfog_gt_8k_defconfig b/configs/clearfog_gt_8k_defconfig
index 0823f34..2b6445a 100644
--- a/configs/clearfog_gt_8k_defconfig
+++ b/configs/clearfog_gt_8k_defconfig
@@ -5,8 +5,8 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_MVEBU_ARMADA_8K=y
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x180000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_DEBUG_UART_BASE=0xf0512000
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index d2de5cf..edaa8e2 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -4,10 +4,11 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_CM_FX6=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
+CONFIG_TARGET_CM_FX6=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
@@ -15,8 +16,8 @@
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 # CONFIG_CMD_BMODE is not set
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
@@ -29,7 +30,6 @@
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_SYS_PROMPT="CM-FX6 # "
 # CONFIG_CMD_XIMG is not set
@@ -78,6 +78,7 @@
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SPI_FLASH_MTD=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_DM_PMIC=y
diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig
index 6c72712..5135166 100644
--- a/configs/cm_t335_defconfig
+++ b/configs/cm_t335_defconfig
@@ -50,6 +50,7 @@
 CONFIG_MMC_OMAP_HS=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_ATHEROS=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
 CONFIG_FAT_WRITE=y
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
index 1e245c6..94b051a 100644
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig
@@ -4,8 +4,9 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_AM43XX=y
 CONFIG_TARGET_CM_T43=y
@@ -31,7 +32,6 @@
 # CONFIG_SPL_NAND_SUPPORT is not set
 CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_SYS_PROMPT="CM-T43 # "
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_EEPROM=y
@@ -68,6 +68,7 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_ATHEROS=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
 CONFIG_DM_SERIAL=y
diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig
index c9005a7d..7e99755 100644
--- a/configs/colibri-imx6ull_defconfig
+++ b/configs/colibri-imx6ull_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
-CONFIG_TARGET_COLIBRI_IMX6ULL=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x380000
+CONFIG_TARGET_COLIBRI_IMX6ULL=y
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index 82f71ec..8fbd9fc 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_COLIBRI_IMX6=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFDE00
+CONFIG_TARGET_COLIBRI_IMX6=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
index f29c56a..abf5263 100644
--- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
+++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
@@ -1,8 +1,8 @@
 CONFIG_X86=y
 CONFIG_SYS_TEXT_BASE=0xFFF00000
 CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x6EF000
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig
index 0780adb..aac0ed2 100644
--- a/configs/conga-qeval20-qa3-e3845_defconfig
+++ b/configs/conga-qeval20-qa3-e3845_defconfig
@@ -1,8 +1,8 @@
 CONFIG_X86=y
 CONFIG_SYS_TEXT_BASE=0xFFF00000
 CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x6EF000
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_VENDOR_CONGATEC=y
 CONFIG_TARGET_CONGA_QEVAL20_QA3_E3845=y
diff --git a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
index edabb84..90fe803 100644
--- a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
+++ b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
@@ -44,7 +44,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_CONS_INDEX=2
diff --git a/configs/controlcenterd_36BIT_SDCARD_defconfig b/configs/controlcenterd_36BIT_SDCARD_defconfig
index fb85188..55a46c3 100644
--- a/configs/controlcenterd_36BIT_SDCARD_defconfig
+++ b/configs/controlcenterd_36BIT_SDCARD_defconfig
@@ -44,7 +44,15 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_CONS_INDEX=2
diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig
index 524dbc2..4ac46ff 100644
--- a/configs/controlcenterdc_defconfig
+++ b/configs/controlcenterdc_defconfig
@@ -6,17 +6,18 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_CONTROLCENTERDC=y
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x30000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BASE=0xd0012000
 CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
-CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
@@ -26,7 +27,6 @@
 CONFIG_LAST_STAGE_INIT=y
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x30000
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_GO is not set
@@ -62,6 +62,7 @@
 CONFIG_MMC_SDHCI_MV=y
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_BITBANGMII=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_MVNETA=y
diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig
index 6fc90bc..aac8a39 100644
--- a/configs/cougarcanyon2_defconfig
+++ b/configs/cougarcanyon2_defconfig
@@ -1,8 +1,8 @@
 CONFIG_X86=y
 CONFIG_SYS_TEXT_BASE=0xFFE00000
 CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x5FF000
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_VENDOR_INTEL=y
 CONFIG_TARGET_COUGARCANYON2=y
diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index 6f56cb4..06d5ce4 100644
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -1,9 +1,9 @@
 CONFIG_X86=y
 CONFIG_SYS_TEXT_BASE=0xFFF00000
-CONFIG_MAX_CPUS=2
 CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x0
+CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_MAX_CPUS=2
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_VENDOR_INTEL=y
 CONFIG_TARGET_CROWNBAY=y
diff --git a/configs/crs305-1g-4s_defconfig b/configs/crs305-1g-4s_defconfig
index 257dbc1..3b513cc 100644
--- a/configs/crs305-1g-4s_defconfig
+++ b/configs/crs305-1g-4s_defconfig
@@ -5,8 +5,8 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_CRS305_1G_4S=y
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_BUILD_TARGET="u-boot.kwb"
 CONFIG_USE_PREBOOT=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig
index eea3e0a..41ed344 100644
--- a/configs/d2net_v2_defconfig
+++ b/configs/d2net_v2_defconfig
@@ -5,8 +5,8 @@
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_TARGET_NET2BIG_V2=y
 CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x70000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_IDENT_STRING=" D2 v2"
 CONFIG_SYS_EXTRA_OPTIONS="D2NET_V2"
diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig
index bee44a0..ee49ed2 100644
--- a/configs/da850evm_defconfig
+++ b/configs/da850evm_defconfig
@@ -8,8 +8,9 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x800
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x80000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
@@ -29,7 +30,6 @@
 CONFIG_SPL_SEPARATE_BSS=y
 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot > "
 CONFIG_CRC32_VERIFY=y
diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig
index 226b201..bc2c0a2 100644
--- a/configs/da850evm_nand_defconfig
+++ b/configs/da850evm_nand_defconfig
@@ -9,6 +9,7 @@
 CONFIG_SYS_MALLOC_F_LEN=0x800
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x0
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
@@ -27,7 +28,6 @@
 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
 CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot > "
 CONFIG_CRC32_VERIFY=y
diff --git a/configs/db-88f6281-bp-nand_defconfig b/configs/db-88f6281-bp-nand_defconfig
index e7a8b40..e390423 100644
--- a/configs/db-88f6281-bp-nand_defconfig
+++ b/configs/db-88f6281-bp-nand_defconfig
@@ -6,8 +6,8 @@
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_TARGET_DB_88F6281_BP=y
 CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_IDENT_STRING="\nMarvell DB-88F6281-BP"
 # CONFIG_SYS_MALLOC_F is not set
diff --git a/configs/db-88f6281-bp-spi_defconfig b/configs/db-88f6281-bp-spi_defconfig
index ec63ffb..1bef1c5 100644
--- a/configs/db-88f6281-bp-spi_defconfig
+++ b/configs/db-88f6281-bp-spi_defconfig
@@ -6,8 +6,8 @@
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_TARGET_DB_88F6281_BP=y
 CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_IDENT_STRING="\nMarvell DB-88F6281-BP"
 # CONFIG_SYS_MALLOC_F is not set
diff --git a/configs/db-88f6720_defconfig b/configs/db-88f6720_defconfig
index 068f76b..e5a18d8 100644
--- a/configs/db-88f6720_defconfig
+++ b/configs/db-88f6720_defconfig
@@ -7,15 +7,16 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_DB_88F6720=y
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BASE=0xf1012000
 CONFIG_DEBUG_UART_CLOCK=250000000
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x40004030
+CONFIG_DEBUG_UART=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_BOOTDELAY=3
 CONFIG_USE_PREBOOT=y
@@ -23,7 +24,6 @@
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_CMD_I2C=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig
index e231ca4..146ea50 100644
--- a/configs/db-88f6820-amc_defconfig
+++ b/configs/db-88f6820-amc_defconfig
@@ -7,15 +7,16 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_DB_88F6820_AMC=y
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x24000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BASE=0xd0012000
 CONFIG_DEBUG_UART_CLOCK=200000000
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x40000030
+CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTDELAY=3
@@ -24,7 +25,6 @@
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x24000
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_I2C=y
 CONFIG_CMD_PCI=y
diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig
index c866131..20848ab 100644
--- a/configs/db-88f6820-gp_defconfig
+++ b/configs/db-88f6820-gp_defconfig
@@ -7,16 +7,17 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_DB_88F6820_GP=y
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x24000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BASE=0xd0012000
 CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
-CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_BOOTDELAY=3
 CONFIG_USE_PREBOOT=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
@@ -24,7 +25,6 @@
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
 CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x24000
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig
index 012149a..ab96622 100644
--- a/configs/db-mv784mp-gp_defconfig
+++ b/configs/db-mv784mp-gp_defconfig
@@ -7,15 +7,16 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_DB_MV784MP_GP=y
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BASE=0xd0012000
 CONFIG_DEBUG_UART_CLOCK=250000000
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x40004030
+CONFIG_DEBUG_UART=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_BOOTDELAY=3
 CONFIG_USE_PREBOOT=y
@@ -23,7 +24,6 @@
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_I2C=y
 CONFIG_CMD_PCI=y
diff --git a/configs/db-xc3-24g4xg_defconfig b/configs/db-xc3-24g4xg_defconfig
index 425d785..0d49d40 100644
--- a/configs/db-xc3-24g4xg_defconfig
+++ b/configs/db-xc3-24g4xg_defconfig
@@ -5,8 +5,8 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_DB_XC3_24G4XG=y
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_BUILD_TARGET="u-boot.kwb"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig
index 1b061cd..d8a81d7 100644
--- a/configs/devkit3250_defconfig
+++ b/configs/devkit3250_defconfig
@@ -48,6 +48,7 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_ADDR_ENABLE=y
 CONFIG_PHY_ADDR=31
+CONFIG_PHY_SMSC=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_USB=y
diff --git a/configs/dfi-bt700-q7x-151_defconfig b/configs/dfi-bt700-q7x-151_defconfig
index 71b1a2f..fdf686f 100644
--- a/configs/dfi-bt700-q7x-151_defconfig
+++ b/configs/dfi-bt700-q7x-151_defconfig
@@ -1,8 +1,8 @@
 CONFIG_X86=y
 CONFIG_SYS_TEXT_BASE=0xFFF00000
 CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x6EF000
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_VENDOR_DFI=y
 CONFIG_SMP=y
diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig
index 40de1d8..dcfbbb6 100644
--- a/configs/dh_imx6_defconfig
+++ b/configs/dh_imx6_defconfig
@@ -4,11 +4,12 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_MX6_DDRCAL=y
-CONFIG_TARGET_DHCOMIMX6=y
 CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
+CONFIG_MX6_DDRCAL=y
+CONFIG_TARGET_DHCOMIMX6=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
@@ -18,8 +19,8 @@
 CONFIG_ENV_OFFSET_REDUND=0x110000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 # CONFIG_SYS_MALLOC_F is not set
 CONFIG_FIT=y
@@ -30,7 +31,6 @@
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_UNZIP=y
diff --git a/configs/display5_defconfig b/configs/display5_defconfig
index 9026c17..4e10efd 100644
--- a/configs/display5_defconfig
+++ b/configs/display5_defconfig
@@ -5,14 +5,15 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x120000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_MX6_DDRCAL=y
 CONFIG_TARGET_DISPLAY5=y
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_ENV_OFFSET=0x120000
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
@@ -41,7 +42,6 @@
 CONFIG_SPL_FORCE_MMC_BOOT=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="display5 > "
diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig
index 710fef4..eb46e3b 100644
--- a/configs/display5_factory_defconfig
+++ b/configs/display5_factory_defconfig
@@ -5,14 +5,15 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x120000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_MX6_DDRCAL=y
 CONFIG_TARGET_DISPLAY5=y
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_ENV_OFFSET=0x120000
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
@@ -37,7 +38,6 @@
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_SPL_USB_HOST_SUPPORT=y
 CONFIG_SPL_USB_GADGET=y
 CONFIG_SPL_USB_SDP_SUPPORT=y
diff --git a/configs/dms-ba16-1g_defconfig b/configs/dms-ba16-1g_defconfig
index a23377f..0739527 100644
--- a/configs/dms-ba16-1g_defconfig
+++ b/configs/dms-ba16-1g_defconfig
@@ -1,11 +1,11 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_ADVANTECH_DMS_BA16=y
-CONFIG_SYS_DDR_1G=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_TARGET_ADVANTECH_DMS_BA16=y
+CONFIG_SYS_DDR_1G=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_BOOTDELAY=1
 # CONFIG_CONSOLE_MUX is not set
@@ -43,6 +43,7 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
 CONFIG_MII=y
 CONFIG_PWM_IMX=y
 CONFIG_SPI=y
diff --git a/configs/dms-ba16_defconfig b/configs/dms-ba16_defconfig
index 8ea6a70..03a2c59 100644
--- a/configs/dms-ba16_defconfig
+++ b/configs/dms-ba16_defconfig
@@ -1,10 +1,10 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_ADVANTECH_DMS_BA16=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_TARGET_ADVANTECH_DMS_BA16=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_BOOTDELAY=1
 # CONFIG_CONSOLE_MUX is not set
@@ -42,6 +42,7 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
 CONFIG_MII=y
 CONFIG_PWM_IMX=y
 CONFIG_SPI=y
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 4d765da..e4547d9 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -2,6 +2,7 @@
 CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_SYS_MALLOC_F_LEN=0x18000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_OMAP54XX=y
 CONFIG_TARGET_DRA7XX_EVM=y
@@ -11,8 +12,8 @@
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_ARMV7_LPAE=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x40300000
+CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_OF_BOARD_SETUP=y
@@ -29,7 +30,6 @@
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_SPL_USB_GADGET=y
 CONFIG_SPL_DFU=y
 CONFIG_CMD_SPL=y
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index c25d4ce..c08bcce 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -3,6 +3,7 @@
 CONFIG_TI_SECURE_DEVICE=y
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_SYS_MALLOC_F_LEN=0x18000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_OMAP54XX=y
 CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
@@ -34,7 +35,6 @@
 # CONFIG_SPL_NAND_SUPPORT is not set
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_SPL_USB_GADGET=y
 CONFIG_SPL_DFU=y
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig
index 8e74496..879c2b6 100644
--- a/configs/dra7xx_hs_evm_usb_defconfig
+++ b/configs/dra7xx_hs_evm_usb_defconfig
@@ -4,6 +4,7 @@
 CONFIG_ISW_ENTRY_ADDR=0x40306d50
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_SYS_MALLOC_F_LEN=0x18000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_OMAP54XX=y
 CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
@@ -16,8 +17,8 @@
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_ARMV7_LPAE=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x40306D50
+CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT_IMAGE_POST_PROCESS=y
 CONFIG_SPL_LOAD_FIT=y
@@ -36,7 +37,6 @@
 # CONFIG_SPL_NAND_SUPPORT is not set
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_SPL_USB_GADGET=y
 CONFIG_SPL_DFU=y
 CONFIG_SPL_YMODEM_SUPPORT=y
diff --git a/configs/draco_defconfig b/configs/draco_defconfig
index 1e1ea38..4c32621 100644
--- a/configs/draco_defconfig
+++ b/configs/draco_defconfig
@@ -6,6 +6,7 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_AM33XX=y
 CONFIG_SYS_MPUCLK=300
 CONFIG_TARGET_DRACO=y
@@ -27,7 +28,6 @@
 CONFIG_ARCH_MISC_INIT=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 # CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
@@ -73,6 +73,7 @@
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_MTD_UBI_FASTMAP=y
 CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
+CONFIG_PHY_SMSC=y
 CONFIG_DRIVER_TI_CPSW=y
 CONFIG_SPI=y
 CONFIG_OMAP3_SPI=y
diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig
index ebc3eb4..566aa0d 100644
--- a/configs/dreamplug_defconfig
+++ b/configs/dreamplug_defconfig
@@ -5,8 +5,8 @@
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_TARGET_DREAMPLUG=y
 CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_IDENT_STRING="\nMarvell-DreamPlug"
 # CONFIG_SYS_MALLOC_F is not set
diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig
index 0d7b895..3f7a661 100644
--- a/configs/ds109_defconfig
+++ b/configs/ds109_defconfig
@@ -5,8 +5,8 @@
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_TARGET_DS109=y
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x3D0000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_NR_DRAM_BANKS=2
 # CONFIG_SYS_MALLOC_F is not set
 CONFIG_USE_PREBOOT=y
diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig
index 01a3909..7d395d1 100644
--- a/configs/ds414_defconfig
+++ b/configs/ds414_defconfig
@@ -7,15 +7,16 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_DS414=y
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x7E0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x24000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BASE=0xd0012000
 CONFIG_DEBUG_UART_CLOCK=250000000
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x40004030
+CONFIG_DEBUG_UART=y
 CONFIG_BOOTDELAY=3
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200"
@@ -24,7 +25,6 @@
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x24000
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_I2C=y
 CONFIG_CMD_PCI=y
diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig
index 951ed1d..d9f110c 100644
--- a/configs/e2220-1170_defconfig
+++ b/configs/e2220-1170_defconfig
@@ -18,6 +18,7 @@
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_PREFER_SERVERIP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra210-e2220-1170"
@@ -43,4 +44,3 @@
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
-CONFIG_BOOTP_PREFER_SERVERIP=y
diff --git a/configs/elgin-rv1108_defconfig b/configs/elgin-rv1108_defconfig
index b668299..33da0f5 100644
--- a/configs/elgin-rv1108_defconfig
+++ b/configs/elgin-rv1108_defconfig
@@ -3,8 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0x60000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_ROCKCHIP_RV1108=y
-CONFIG_TARGET_ELGIN_RV1108=y
 CONFIG_ROCKCHIP_BOOT_MODE_REG=0
+CONFIG_TARGET_ELGIN_RV1108=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BASE=0x10210000
 CONFIG_DEBUG_UART_CLOCK=24000000
diff --git a/configs/emsdp_defconfig b/configs/emsdp_defconfig
index ea67e64..edf4453 100644
--- a/configs/emsdp_defconfig
+++ b/configs/emsdp_defconfig
@@ -19,7 +19,6 @@
 CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="emsdp"
 CONFIG_ENV_IS_IN_FAT=y
-CONFIG_ENV_FAT_INTERFACE="mmc"
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 # CONFIG_NET is not set
diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig
index 424dc94..16202c8 100644
--- a/configs/etamin_defconfig
+++ b/configs/etamin_defconfig
@@ -7,6 +7,7 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x980000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_AM33XX=y
 CONFIG_SYS_MPUCLK=300
 CONFIG_TARGET_ETAMIN=y
@@ -28,7 +29,6 @@
 CONFIG_ARCH_MISC_INIT=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 # CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
@@ -74,6 +74,7 @@
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_MTD_UBI_FASTMAP=y
 CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
+CONFIG_PHY_SMSC=y
 CONFIG_DRIVER_TI_CPSW=y
 CONFIG_SPI=y
 CONFIG_OMAP3_SPI=y
diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig
index e9ad7a8..3f90eae 100644
--- a/configs/ethernut5_defconfig
+++ b/configs/ethernut5_defconfig
@@ -5,8 +5,8 @@
 CONFIG_TARGET_ETHERNUT5=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x21000
-CONFIG_ENV_SECT_SIZE=0x21000
 CONFIG_ENV_OFFSET=0x3DE000
+CONFIG_ENV_SECT_SIZE=0x21000
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE"
diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig
index d2cf13e..b2fda44 100644
--- a/configs/evb-px30_defconfig
+++ b/configs/evb-px30_defconfig
@@ -12,8 +12,8 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BASE=0xFF160000
 CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x00000000
+CONFIG_DEBUG_UART=y
 CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 # CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_FIT=y
@@ -103,7 +103,6 @@
 CONFIG_LCD=y
 CONFIG_SPL_TINY_MEMSET=y
 CONFIG_TPL_TINY_MEMSET=y
-CONFIG_LZ4=y
 CONFIG_LZO=y
 CONFIG_ERRNO_STR=y
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index a106ae6..dddb9d2 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -10,8 +10,8 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BASE=0x20068000
 CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x10081000
+CONFIG_DEBUG_UART=y
 # CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_USE_PREBOOT=y
 CONFIG_DEFAULT_FDT_FILE="rk3036-evb.dtb"
diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
index f8e648b..4d7beca 100644
--- a/configs/evb-rk3229_defconfig
+++ b/configs/evb-rk3229_defconfig
@@ -10,8 +10,8 @@
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_DEBUG_UART_BASE=0x11030000
 CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x60000000
+CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig
index 1b25dc1..6456824 100644
--- a/configs/evb-rk3308_defconfig
+++ b/configs/evb-rk3308_defconfig
@@ -71,7 +71,6 @@
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_SPL_TINY_MEMSET=y
-CONFIG_LZ4=y
 CONFIG_LZO=y
 CONFIG_ERRNO_STR=y
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig
index dd7bd38..943e69a 100644
--- a/configs/ficus-rk3399_defconfig
+++ b/configs/ficus-rk3399_defconfig
@@ -7,8 +7,8 @@
 CONFIG_TARGET_ROCK960_RK3399=y
 CONFIG_DEBUG_UART_BASE=0xFF1A0000
 CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0xff8c2000
+CONFIG_DEBUG_UART=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_STACK_R=y
diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig
index 5ed6037..afd966d 100644
--- a/configs/firefly-px30_defconfig
+++ b/configs/firefly-px30_defconfig
@@ -13,8 +13,8 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BASE=0xFF160000
 CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x00000000
+CONFIG_DEBUG_UART=y
 CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 # CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_FIT=y
@@ -102,7 +102,6 @@
 CONFIG_LCD=y
 CONFIG_SPL_TINY_MEMSET=y
 CONFIG_TPL_TINY_MEMSET=y
-CONFIG_LZ4=y
 CONFIG_LZO=y
 CONFIG_ERRNO_STR=y
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index 09b49bd..4e2a23f 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -1,8 +1,8 @@
 CONFIG_X86=y
 CONFIG_SYS_TEXT_BASE=0xFFF10000
 CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x0
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_VENDOR_INTEL=y
 CONFIG_TARGET_GALILEO=y
diff --git a/configs/gardena-smart-gateway-at91sam_defconfig b/configs/gardena-smart-gateway-at91sam_defconfig
index 08a96be..79d1cb9 100644
--- a/configs/gardena-smart-gateway-at91sam_defconfig
+++ b/configs/gardena-smart-gateway-at91sam_defconfig
@@ -16,8 +16,8 @@
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
 CONFIG_DEBUG_UART_CLOCK=132000000
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x300000
+CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_NAND_BOOT=y
 CONFIG_BOOTDELAY=3
diff --git a/configs/gardena-smart-gateway-mt7688-ram_defconfig b/configs/gardena-smart-gateway-mt7688-ram_defconfig
deleted file mode 100644
index dbc94b4..0000000
--- a/configs/gardena-smart-gateway-mt7688-ram_defconfig
+++ /dev/null
@@ -1,74 +0,0 @@
-CONFIG_MIPS=y
-CONFIG_SYS_TEXT_BASE=0x80010000
-CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_ENV_OFFSET=0xA0000
-CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
-CONFIG_ENV_OFFSET_REDUND=0xB0000
-CONFIG_ARCH_MTMIPS=y
-# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
-CONFIG_MIPS_BOOT_FDT=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_FIT=y
-CONFIG_FIT_SIGNATURE=y
-CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="cp.b 83000000 84000000 10000 && dhcp uEnv.txt && env import -t ${fileaddr} ${filesize} && run do_u_boot_init; reset"
-CONFIG_USE_PREBOOT=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_LICENSE=y
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_MEMINFO=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_MTD=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_WDT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BOOTCOUNT=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_UUID=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="spi-nand0=spi0.1,nor0=spi0.0"
-CONFIG_MTDPARTS_DEFAULT="spi0.0:640k(uboot),64k(uboot_env0),64k(uboot_env1),64k(factory),-(unused);spi0.1:-(nand)"
-CONFIG_CMD_UBI=y
-CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-mt7688"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-# CONFIG_DM_DEVICE_REMOVE is not set
-CONFIG_HAVE_BLOCK_DEVICE=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_LED=y
-CONFIG_LED_BLINK=y
-CONFIG_LED_GPIO=y
-CONFIG_MTD=y
-CONFIG_DM_MTD=y
-CONFIG_MTD_SPI_NAND=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_SPI_FLASH_XMC=y
-CONFIG_SPI_FLASH_MTD=y
-CONFIG_MTD_UBI_BEB_LIMIT=22
-CONFIG_MT7628_ETH=y
-CONFIG_PHY=y
-CONFIG_SPI=y
-CONFIG_MT7621_SPI=y
-CONFIG_SYSRESET_SYSCON=y
-CONFIG_WDT=y
-CONFIG_WDT_MT7621=y
-CONFIG_LZMA=y
diff --git a/configs/gardena-smart-gateway-mt7688_defconfig b/configs/gardena-smart-gateway-mt7688_defconfig
index 23d8ddb..41496f7 100644
--- a/configs/gardena-smart-gateway-mt7688_defconfig
+++ b/configs/gardena-smart-gateway-mt7688_defconfig
@@ -1,16 +1,18 @@
 CONFIG_MIPS=y
-CONFIG_SYS_TEXT_BASE=0x9c000000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0xA0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
 CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
 CONFIG_ENV_OFFSET_REDUND=0xB0000
 CONFIG_ARCH_MTMIPS=y
-CONFIG_BOOT_ROM=y
-CONFIG_ONBOARD_DDR2_SIZE_1024MBIT=y
-CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT=y
+CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
@@ -24,6 +26,8 @@
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_VERSION_VARIABLE=y
 CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_NOR_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_LICENSE=y
 # CONFIG_CMD_ELF is not set
@@ -50,6 +54,7 @@
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_HAVE_BLOCK_DEVICE=y
 CONFIG_BOOTCOUNT_LIMIT=y
@@ -71,7 +76,7 @@
 CONFIG_PHY=y
 CONFIG_SPI=y
 CONFIG_MT7621_SPI=y
-CONFIG_SYSRESET_SYSCON=y
 CONFIG_WDT=y
 CONFIG_WDT_MT7621=y
 CONFIG_LZMA=y
+CONFIG_SPL_LZMA=y
diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig
index 44b4121..d125a6e 100644
--- a/configs/gazerbeam_defconfig
+++ b/configs/gazerbeam_defconfig
@@ -176,7 +176,16 @@
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHYLIB_10G=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_DM_ETH=y
 CONFIG_TSEC_ENET=y
 # CONFIG_PCI is not set
diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig
index a978d4e..f0893ce 100644
--- a/configs/ge_bx50v3_defconfig
+++ b/configs/ge_bx50v3_defconfig
@@ -2,10 +2,10 @@
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SYS_MALLOC_F_LEN=0x4000
-CONFIG_TARGET_GE_BX50V3=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_TARGET_GE_BX50V3=y
 CONFIG_DM_GPIO=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=10
 CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/gose_defconfig b/configs/gose_defconfig
index 3a2daac..8fc0df4 100644
--- a/configs/gose_defconfig
+++ b/configs/gose_defconfig
@@ -9,8 +9,9 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
 CONFIG_DM_GPIO=y
 CONFIG_ARCH_RMOBILE_BOARD_STRING="Gose"
 CONFIG_R8A7793=y
@@ -30,7 +31,6 @@
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
@@ -71,6 +71,7 @@
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_MTD=y
+CONFIG_BITBANGMII=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ8XXX=y
 CONFIG_DM_ETH=y
diff --git a/configs/grpeach_defconfig b/configs/grpeach_defconfig
index 99b656e..417938a 100644
--- a/configs/grpeach_defconfig
+++ b/configs/grpeach_defconfig
@@ -3,8 +3,8 @@
 CONFIG_ARCH_RMOBILE=y
 CONFIG_SYS_TEXT_BASE=0x18000000
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x80000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_RZA1=y
 CONFIG_NR_DRAM_BANKS=1
@@ -44,6 +44,7 @@
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_BITBANGMII=y
 CONFIG_DM_ETH=y
 CONFIG_SH_ETHER=y
 CONFIG_PINCTRL=y
diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig
index 3ec8485..639cb99 100644
--- a/configs/gwventana_emmc_defconfig
+++ b/configs/gwventana_emmc_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_GW_VENTANA=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0xB1400
+CONFIG_TARGET_GW_VENTANA=y
 CONFIG_CMD_EECONFIG=y
 CONFIG_CMD_GSC=y
 CONFIG_SPL_MMC_SUPPORT=y
diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig
index a3a432d..67ea57c 100644
--- a/configs/gwventana_gw5904_defconfig
+++ b/configs/gwventana_gw5904_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_GW_VENTANA=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0xB1400
+CONFIG_TARGET_GW_VENTANA=y
 CONFIG_CMD_EECONFIG=y
 CONFIG_CMD_GSC=y
 CONFIG_SPL_MMC_SUPPORT=y
diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig
index 9d147b0..f6e85b6 100644
--- a/configs/gwventana_nand_defconfig
+++ b/configs/gwventana_nand_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_GW_VENTANA=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x1000000
+CONFIG_TARGET_GW_VENTANA=y
 CONFIG_CMD_EECONFIG=y
 CONFIG_CMD_GSC=y
 CONFIG_SPL_MMC_SUPPORT=y
diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig
index 0fe8559..e15f10c 100644
--- a/configs/helios4_defconfig
+++ b/configs/helios4_defconfig
@@ -15,9 +15,9 @@
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BASE=0xd0012000
 CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
-CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=3
 CONFIG_USE_PREBOOT=y
@@ -54,6 +54,7 @@
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_SF_DEFAULT_SPEED=104000000
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_MVNETA=y
 CONFIG_MII=y
diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig
index dca5997..439231a 100644
--- a/configs/hrcon_defconfig
+++ b/configs/hrcon_defconfig
@@ -129,7 +129,16 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_BITBANGMII=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_CONS_INDEX=2
diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig
index 40de2f9..ef0ee4d 100644
--- a/configs/hrcon_dh_defconfig
+++ b/configs/hrcon_dh_defconfig
@@ -127,7 +127,16 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_BITBANGMII=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_CONS_INDEX=2
diff --git a/configs/hsdk_4xd_defconfig b/configs/hsdk_4xd_defconfig
new file mode 100644
index 0000000..64832ec
--- /dev/null
+++ b/configs/hsdk_4xd_defconfig
@@ -0,0 +1,67 @@
+CONFIG_ARC=y
+CONFIG_ISA_ARCV2=y
+CONFIG_TARGET_HSDK=y
+CONFIG_BOARD_HSDK_4XD=y
+CONFIG_SYS_TEXT_BASE=0x81000000
+CONFIG_DM_GPIO=y
+CONFIG_DEBUG_UART_BASE=0xf0005000
+CONFIG_DEBUG_UART_CLOCK=33333333
+CONFIG_SYS_CLK_FREQ=500000000
+CONFIG_DEBUG_UART=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200n8"
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="hsdk-4xd# "
+CONFIG_CMD_ENV_FLAGS=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="hsdk-4xd"
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_INTERFACE="mmc"
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_CLK_HSDK=y
+CONFIG_HSDK_CREG_GPIO=y
+CONFIG_MMC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_MII=y
+CONFIG_DM_RESET=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_PANIC_HANG=y
diff --git a/configs/hsdk_defconfig b/configs/hsdk_defconfig
index 84b22ed..4b76716 100644
--- a/configs/hsdk_defconfig
+++ b/configs/hsdk_defconfig
@@ -30,7 +30,6 @@
 CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="hsdk"
 CONFIG_ENV_IS_IN_FAT=y
-CONFIG_ENV_FAT_INTERFACE="mmc"
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig
index 8543780..555169d 100644
--- a/configs/i12-tvbox_defconfig
+++ b/configs/i12-tvbox_defconfig
@@ -8,6 +8,7 @@
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-i12-tvbox"
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
diff --git a/configs/icnova-a20-swac_defconfig b/configs/icnova-a20-swac_defconfig
index d6da5ac..063cdf7 100644
--- a/configs/icnova-a20-swac_defconfig
+++ b/configs/icnova-a20-swac_defconfig
@@ -15,6 +15,7 @@
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_CMD_UNZIP=y
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-icnova-swac"
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig
index 29f62e2..802b5a6 100644
--- a/configs/ids8313_defconfig
+++ b/configs/ids8313_defconfig
@@ -163,7 +163,15 @@
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 # CONFIG_PCI is not set
diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig
index 2d49b66..e23d77d 100644
--- a/configs/imx28_xea_defconfig
+++ b/configs/imx28_xea_defconfig
@@ -6,6 +6,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x800
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_TARGET_XEA=y
@@ -18,6 +19,7 @@
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_SPL_TEXT_BASE=0x1000
+CONFIG_SPL_PAYLOAD="u-boot.img"
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_BOARD_EARLY_INIT_F=y
@@ -31,9 +33,7 @@
 CONFIG_SPL_FORCE_MMC_BOOT=y
 CONFIG_SPL_MMC_TINY=y
 CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_PAYLOAD="u-boot.img"
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_SPL=y
 CONFIG_CMD_ASKENV=y
diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig
index 6d62022..fb18458 100644
--- a/configs/imx6dl_icore_nand_defconfig
+++ b/configs/imx6dl_icore_nand_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_MX6Q_ENGICAM=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x400000
+CONFIG_TARGET_MX6Q_ENGICAM=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig
index 37168d2..8f03f2f 100644
--- a/configs/imx6dl_mamoj_defconfig
+++ b/configs/imx6dl_mamoj_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_MX6DL_MAMOJ=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_TARGET_MX6DL_MAMOJ=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_IMX_HAB=y
 # CONFIG_CMD_BMODE is not set
diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig
index a0baab1..4f42f7a 100644
--- a/configs/imx6q_icore_nand_defconfig
+++ b/configs/imx6q_icore_nand_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_MX6Q_ENGICAM=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x400000
+CONFIG_TARGET_MX6Q_ENGICAM=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig
index f57e89d..f4ec96c 100644
--- a/configs/imx6q_logic_defconfig
+++ b/configs/imx6q_logic_defconfig
@@ -4,16 +4,17 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_MX6_OCRAM_256KB=y
-CONFIG_TARGET_MX6LOGICPD=y
 CONFIG_ENV_SIZE=0x100000
 CONFIG_ENV_OFFSET=0x400000
+CONFIG_MX6_OCRAM_256KB=y
+CONFIG_TARGET_MX6LOGICPD=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_PAYLOAD="u-boot.img"
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
 CONFIG_BOOTDELAY=3
@@ -28,7 +29,6 @@
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_PAYLOAD="u-boot.img"
 CONFIG_SPL_USB_HOST_SUPPORT=y
 CONFIG_SPL_USB_GADGET=y
 CONFIG_SPL_USB_SDP_SUPPORT=y
@@ -60,7 +60,6 @@
 CONFIG_DEFAULT_DEVICE_TREE="imx6q-logicpd"
 CONFIG_ENV_IS_IN_FAT=y
 CONFIG_ENV_IS_IN_NAND=y
-CONFIG_ENV_FAT_INTERFACE="mmc"
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
diff --git a/configs/imx6qdl_icore_mipi_defconfig b/configs/imx6qdl_icore_mipi_defconfig
index dbad2f3..fe37760 100644
--- a/configs/imx6qdl_icore_mipi_defconfig
+++ b/configs/imx6qdl_icore_mipi_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_MX6Q_ENGICAM=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_TARGET_MX6Q_ENGICAM=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
@@ -14,8 +14,8 @@
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SPL_LIBDISK_SUPPORT=y
 # CONFIG_CMD_BMODE is not set
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig
index e82a06e..486268c 100644
--- a/configs/imx6qdl_icore_mmc_defconfig
+++ b/configs/imx6qdl_icore_mmc_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_MX6Q_ENGICAM=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_TARGET_MX6Q_ENGICAM=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
 CONFIG_SYS_BOOTCOUNT_ADDR=0x020D8024
@@ -17,8 +17,8 @@
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SPL_LIBDISK_SUPPORT=y
 # CONFIG_CMD_BMODE is not set
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig
index a0baab1..4f42f7a 100644
--- a/configs/imx6qdl_icore_nand_defconfig
+++ b/configs/imx6qdl_icore_nand_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_MX6Q_ENGICAM=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x400000
+CONFIG_TARGET_MX6Q_ENGICAM=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
diff --git a/configs/imx6qdl_icore_rqs_defconfig b/configs/imx6qdl_icore_rqs_defconfig
index be9a027..f9a748d 100644
--- a/configs/imx6qdl_icore_rqs_defconfig
+++ b/configs/imx6qdl_icore_rqs_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_MX6Q_ENGICAM=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_TARGET_MX6Q_ENGICAM=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
diff --git a/configs/imx6ul_geam_mmc_defconfig b/configs/imx6ul_geam_mmc_defconfig
index d8076f8..8ae72e7 100644
--- a/configs/imx6ul_geam_mmc_defconfig
+++ b/configs/imx6ul_geam_mmc_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_MX6UL_ENGICAM=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_TARGET_MX6UL_ENGICAM=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
diff --git a/configs/imx6ul_geam_nand_defconfig b/configs/imx6ul_geam_nand_defconfig
index 9ac27f1..15201d2 100644
--- a/configs/imx6ul_geam_nand_defconfig
+++ b/configs/imx6ul_geam_nand_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_MX6UL_ENGICAM=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x400000
+CONFIG_TARGET_MX6UL_ENGICAM=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
diff --git a/configs/imx6ul_isiot_emmc_defconfig b/configs/imx6ul_isiot_emmc_defconfig
index 5347749..35c974e 100644
--- a/configs/imx6ul_isiot_emmc_defconfig
+++ b/configs/imx6ul_isiot_emmc_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_MX6UL_ENGICAM=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_TARGET_MX6UL_ENGICAM=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
diff --git a/configs/imx6ul_isiot_nand_defconfig b/configs/imx6ul_isiot_nand_defconfig
index 1dce463..bfa03a7 100644
--- a/configs/imx6ul_isiot_nand_defconfig
+++ b/configs/imx6ul_isiot_nand_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_MX6UL_ENGICAM=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x400000
+CONFIG_TARGET_MX6UL_ENGICAM=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig
index 1403067..d988507 100644
--- a/configs/imx8mm_evk_defconfig
+++ b/configs/imx8mm_evk_defconfig
@@ -7,11 +7,11 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_OFFSET=0x400000
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_IMX8MM_EVK=y
 CONFIG_SPL_MMC_SUPPORT=y
diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig
index e3f9989..f7485ab 100644
--- a/configs/imx8mn_ddr4_evk_defconfig
+++ b/configs/imx8mn_ddr4_evk_defconfig
@@ -7,11 +7,11 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_OFFSET=0x400000
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_IMX8MN_EVK=y
 CONFIG_SPL_MMC_SUPPORT=y
diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig
index b181543..ce6b342 100644
--- a/configs/imx8mp_evk_defconfig
+++ b/configs/imx8mp_evk_defconfig
@@ -7,11 +7,11 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_OFFSET=0x400000
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_IMX8MP_EVK=y
 CONFIG_SPL_MMC_SUPPORT=y
diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index a936f5b..23fdb3f 100644
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -37,6 +37,8 @@
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX8M=y
diff --git a/configs/imxrt1020-evk_defconfig b/configs/imxrt1020-evk_defconfig
index 2f35df1..ca5f83e 100644
--- a/configs/imxrt1020-evk_defconfig
+++ b/configs/imxrt1020-evk_defconfig
@@ -24,7 +24,6 @@
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
 # CONFIG_SPL_CRC32_SUPPORT is not set
-# CONFIG_SPL_DM_GPIO is not set
 # CONFIG_BOOTM_NETBSD is not set
 # CONFIG_BOOTM_PLAN9 is not set
 # CONFIG_BOOTM_RTEMS is not set
@@ -48,6 +47,7 @@
 CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_SPL_CLK_IMXRT1020=y
 CONFIG_CLK_IMXRT1020=y
+# CONFIG_SPL_DM_GPIO is not set
 CONFIG_MXC_GPIO=y
 # CONFIG_INPUT is not set
 CONFIG_DM_MMC=y
diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig
index 25d0ba1..0eafe26 100644
--- a/configs/imxrt1050-evk_defconfig
+++ b/configs/imxrt1050-evk_defconfig
@@ -27,7 +27,6 @@
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
 # CONFIG_SPL_CRC32_SUPPORT is not set
-# CONFIG_SPL_DM_GPIO is not set
 # CONFIG_BOOTM_NETBSD is not set
 # CONFIG_BOOTM_PLAN9 is not set
 # CONFIG_BOOTM_RTEMS is not set
@@ -51,6 +50,7 @@
 CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_SPL_CLK_IMXRT1050=y
 CONFIG_CLK_IMXRT1050=y
+# CONFIG_SPL_DM_GPIO is not set
 CONFIG_MXC_GPIO=y
 # CONFIG_INPUT is not set
 CONFIG_DM_MMC=y
diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig
index 5bae7a8..94c708e 100644
--- a/configs/inetspace_v2_defconfig
+++ b/configs/inetspace_v2_defconfig
@@ -5,8 +5,8 @@
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_TARGET_NETSPACE_V2=y
 CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x70000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_IDENT_STRING=" IS v2"
 CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2"
diff --git a/configs/iot_devkit_defconfig b/configs/iot_devkit_defconfig
index b354231..35039c4 100644
--- a/configs/iot_devkit_defconfig
+++ b/configs/iot_devkit_defconfig
@@ -23,7 +23,6 @@
 CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="iot_devkit"
 CONFIG_ENV_IS_IN_FAT=y
-CONFIG_ENV_FAT_INTERFACE="mmc"
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 # CONFIG_NET is not set
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index e9e82bb..4deb4e2 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -8,6 +8,7 @@
 CONFIG_TARGET_J721E_A72_EVM=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x680000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
@@ -43,7 +44,6 @@
 # CONFIG_SPL_SPI_FLASH_TINY is not set
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
 CONFIG_SPL_USB_GADGET=y
 CONFIG_SPL_DFU=y
 CONFIG_SPL_YMODEM_SUPPORT=y
@@ -120,7 +120,6 @@
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_HBMC_AM654=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_SPI_FLASH_MTD=y
diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index 917f82d..ee9217a 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -8,12 +8,12 @@
 CONFIG_K3_EARLY_CONS=y
 CONFIG_TARGET_J721E_R5_EVM=y
 CONFIG_ENV_SIZE=0x20000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_ENV_OFFSET_REDUND=0x700000
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -23,6 +23,7 @@
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_USE_BOOTCOMMAND=y
 # CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SPL_EARLY_BSS=y
@@ -42,7 +43,6 @@
 # CONFIG_SPL_SPI_FLASH_TINY is not set
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
 CONFIG_SPL_USB_GADGET=y
 CONFIG_SPL_DFU=y
 CONFIG_SPL_YMODEM_SUPPORT=y
@@ -78,9 +78,10 @@
 CONFIG_SYS_I2C_OMAP24XX=y
 CONFIG_DM_MAILBOX=y
 CONFIG_K3_SEC_PROXY=y
-CONFIG_MISC=y
 CONFIG_FS_LOADER=y
+CONFIG_ESM_K3=y
 CONFIG_K3_AVS0=y
+CONFIG_ESM_PMIC=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_MMC_SDHCI=y
@@ -132,6 +133,3 @@
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_FS_EXT4=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
-CONFIG_ESM_K3=y
-CONFIG_ESM_PMIC=y
-CONFIG_SPL_BOARD_INIT=y
diff --git a/configs/j721e_hs_evm_a72_defconfig b/configs/j721e_hs_evm_a72_defconfig
index a723e27..ae540a2 100644
--- a/configs/j721e_hs_evm_a72_defconfig
+++ b/configs/j721e_hs_evm_a72_defconfig
@@ -8,6 +8,7 @@
 CONFIG_TARGET_J721E_A72_EVM=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x680000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
@@ -39,7 +40,6 @@
 # CONFIG_SPL_SPI_FLASH_TINY is not set
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_DFU=y
@@ -110,7 +110,6 @@
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_HBMC_AM654=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_SPI_FLASH_MTD=y
diff --git a/configs/j721e_hs_evm_r5_defconfig b/configs/j721e_hs_evm_r5_defconfig
index 196625d..51d5a3b 100644
--- a/configs/j721e_hs_evm_r5_defconfig
+++ b/configs/j721e_hs_evm_r5_defconfig
@@ -9,6 +9,7 @@
 CONFIG_TARGET_J721E_R5_EVM=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x680000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
@@ -41,7 +42,6 @@
 # CONFIG_SPL_SPI_FLASH_TINY is not set
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_FLASH is not set
@@ -75,7 +75,6 @@
 CONFIG_SYS_I2C_OMAP24XX=y
 CONFIG_DM_MAILBOX=y
 CONFIG_K3_SEC_PROXY=y
-CONFIG_MISC=y
 CONFIG_FS_LOADER=y
 CONFIG_K3_AVS0=y
 CONFIG_DM_MMC=y
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index 5df19ef..644b6e5 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -10,6 +10,7 @@
 CONFIG_TARGET_K2E_EVM=y
 CONFIG_ENV_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
@@ -24,7 +25,6 @@
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
 CONFIG_CMD_MX_CYCLIC=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_GPIO is not set
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 5abf5fa..5bc7f7f 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -9,6 +9,7 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_TARGET_K2G_EVM=y
 CONFIG_ENV_SIZE=0x40000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
@@ -23,7 +24,6 @@
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
 CONFIG_CMD_MX_CYCLIC=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_GPIO is not set
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index 0635f4a..eb5916c 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -10,6 +10,7 @@
 CONFIG_TARGET_K2HK_EVM=y
 CONFIG_ENV_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
@@ -24,7 +25,6 @@
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
 CONFIG_CMD_MX_CYCLIC=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_GPIO is not set
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index 66f778f..71a35e3 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -10,6 +10,7 @@
 CONFIG_TARGET_K2L_EVM=y
 CONFIG_ENV_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
@@ -24,7 +25,6 @@
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
 CONFIG_CMD_MX_CYCLIC=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_GPIO is not set
diff --git a/configs/khadas-vim2_defconfig b/configs/khadas-vim2_defconfig
index a533566..5633f6d 100644
--- a/configs/khadas-vim2_defconfig
+++ b/configs/khadas-vim2_defconfig
@@ -19,6 +19,8 @@
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
@@ -30,7 +32,10 @@
 CONFIG_SARADC_MESON=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
 CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PHY_REALTEK=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
@@ -44,6 +49,9 @@
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MESON_SPIFC=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
diff --git a/configs/khadas-vim3_defconfig b/configs/khadas-vim3_defconfig
index 72987d9..692138e 100644
--- a/configs/khadas-vim3_defconfig
+++ b/configs/khadas-vim3_defconfig
@@ -18,6 +18,8 @@
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
@@ -28,6 +30,10 @@
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PHY_REALTEK=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
@@ -41,6 +47,9 @@
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MESON_SPIFC=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
diff --git a/configs/khadas-vim3l_defconfig b/configs/khadas-vim3l_defconfig
index 7e2ad41..28c20c0 100644
--- a/configs/khadas-vim3l_defconfig
+++ b/configs/khadas-vim3l_defconfig
@@ -18,6 +18,8 @@
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
@@ -28,6 +30,10 @@
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PHY_REALTEK=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
@@ -43,6 +49,9 @@
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MESON_SPIFC=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
diff --git a/configs/kmcoge4_defconfig b/configs/kmcoge4_defconfig
index 5537965..a0d2c1a 100644
--- a/configs/kmcoge4_defconfig
+++ b/configs/kmcoge4_defconfig
@@ -1,8 +1,8 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xfff40000
 CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
 CONFIG_SYS_BOOTCOUNT_ADDR=0xFB000020
 CONFIG_ENV_OFFSET_REDUND=0x110000
@@ -55,6 +55,7 @@
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
diff --git a/configs/kmcoge5un_defconfig b/configs/kmcoge5un_defconfig
index 1775273..b70bab6 100644
--- a/configs/kmcoge5un_defconfig
+++ b/configs/kmcoge5un_defconfig
@@ -8,8 +8,8 @@
 CONFIG_KM_ENV_IS_IN_SPI_NOR=y
 CONFIG_KM_PIGGY4_88E6352=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
 CONFIG_ENV_OFFSET_REDUND=0xD0000
 CONFIG_IDENT_STRING="\nKeymile COGE5UN"
diff --git a/configs/kmnusa_defconfig b/configs/kmnusa_defconfig
index 3cef72c..a4b301d 100644
--- a/configs/kmnusa_defconfig
+++ b/configs/kmnusa_defconfig
@@ -8,8 +8,8 @@
 CONFIG_KM_ENV_IS_IN_SPI_NOR=y
 CONFIG_KM_PIGGY4_88E6352=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
 CONFIG_ENV_OFFSET_REDUND=0xD0000
 CONFIG_IDENT_STRING="\nKeymile NUSA"
diff --git a/configs/kmsuse2_defconfig b/configs/kmsuse2_defconfig
index e81a8b0..119607a 100644
--- a/configs/kmsuse2_defconfig
+++ b/configs/kmsuse2_defconfig
@@ -9,8 +9,8 @@
 CONFIG_KM_FPGA_NO_RESET=y
 CONFIG_KM_ENV_IS_IN_SPI_NOR=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
 CONFIG_ENV_OFFSET_REDUND=0xD0000
 CONFIG_IDENT_STRING="\nABB SUSE2"
diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig
index edb7933..7d8ac65 100644
--- a/configs/koelsch_defconfig
+++ b/configs/koelsch_defconfig
@@ -9,8 +9,9 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
 CONFIG_DM_GPIO=y
 CONFIG_ARCH_RMOBILE_BOARD_STRING="Koelsch"
 CONFIG_R8A7791=y
@@ -30,7 +31,6 @@
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
@@ -71,6 +71,7 @@
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_MTD=y
+CONFIG_BITBANGMII=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ8XXX=y
 CONFIG_DM_ETH=y
diff --git a/configs/kp_imx53_defconfig b/configs/kp_imx53_defconfig
index 096ba53..936b51a 100644
--- a/configs/kp_imx53_defconfig
+++ b/configs/kp_imx53_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX5=y
 CONFIG_SYS_TEXT_BASE=0x77800000
-CONFIG_TARGET_KP_IMX53=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_TARGET_KP_IMX53=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_OFFSET_REDUND=0x102000
 # CONFIG_CMD_BMODE is not set
diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig
index 6bfe9af..2f46b23 100644
--- a/configs/kp_imx6q_tpc_defconfig
+++ b/configs/kp_imx6q_tpc_defconfig
@@ -5,18 +5,19 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x2200
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x100000
 CONFIG_MX6_DDRCAL=y
 CONFIG_TARGET_KP_IMX6Q_TPC=y
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 CONFIG_ENV_OFFSET_REDUND=0x102000
 CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_PAYLOAD="u-boot.img"
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
@@ -26,7 +27,6 @@
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_SPL_RAW_IMAGE_SUPPORT=y
-CONFIG_SPL_PAYLOAD="u-boot.img"
 CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_AUTOBOOT_KEYED=y
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index 51cd9b5..e59dc52 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -12,8 +12,8 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BASE=0x20068000
 CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x10081000
+CONFIG_DEBUG_UART=y
 # CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_USE_PREBOOT=y
 CONFIG_DEFAULT_FDT_FILE="rk3036-kylin.dtb"
diff --git a/configs/lager_defconfig b/configs/lager_defconfig
index 6e6ad00..918d9be 100644
--- a/configs/lager_defconfig
+++ b/configs/lager_defconfig
@@ -9,8 +9,9 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
 CONFIG_DM_GPIO=y
 CONFIG_ARCH_RMOBILE_BOARD_STRING="Lager"
 CONFIG_R8A7790=y
@@ -30,7 +31,6 @@
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
@@ -73,6 +73,7 @@
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_MTD=y
+CONFIG_BITBANGMII=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ8XXX=y
 CONFIG_DM_ETH=y
diff --git a/configs/libretech-ac_defconfig b/configs/libretech-ac_defconfig
index 7e48675..df0dbbd 100644
--- a/configs/libretech-ac_defconfig
+++ b/configs/libretech-ac_defconfig
@@ -3,8 +3,8 @@
 CONFIG_ARCH_MESON=y
 CONFIG_SYS_TEXT_BASE=0x01000000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0xFFFF0000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_MESON_GXL=y
 CONFIG_NR_DRAM_BANKS=1
@@ -69,8 +69,8 @@
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
 CONFIG_USB_DWC3=y
-CONFIG_USB_KEYBOARD=y
 # CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_KEYBOARD=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
 CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
diff --git a/configs/libretech-s905d-pc_defconfig b/configs/libretech-s905d-pc_defconfig
index 531d519..7210142 100644
--- a/configs/libretech-s905d-pc_defconfig
+++ b/configs/libretech-s905d-pc_defconfig
@@ -2,13 +2,14 @@
 CONFIG_SYS_BOARD="q200"
 CONFIG_ARCH_MESON=y
 CONFIG_SYS_TEXT_BASE=0x01000000
-CONFIG_MESON_GXL=y
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0xFFFF0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_MESON_GXL=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BASE=0xc81004c0
 CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_IDENT_STRING=" libretech-s905d-pc"
 CONFIG_DEBUG_UART=y
 CONFIG_OF_BOARD_SETUP=y
@@ -22,7 +23,6 @@
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
 CONFIG_CMD_SF_TEST=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
@@ -34,13 +34,11 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SARADC_MESON=y
-CONFIG_DM_GPIO=y
 CONFIG_DM_KEYBOARD=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_MESON_GX=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_PHY_REALTEK=y
 CONFIG_DM_ETH=y
@@ -67,12 +65,12 @@
 CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
 CONFIG_USB_DWC3=y
 # CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_KEYBOARD=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
 CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_KEYBOARD=y
 CONFIG_DM_VIDEO=y
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_MESON=y
diff --git a/configs/libretech-s912-pc_defconfig b/configs/libretech-s912-pc_defconfig
index 595ec21..4c255c1 100644
--- a/configs/libretech-s912-pc_defconfig
+++ b/configs/libretech-s912-pc_defconfig
@@ -1,14 +1,14 @@
 CONFIG_ARM=y
-CONFIG_SYS_BOARD="q200"
 CONFIG_ARCH_MESON=y
 CONFIG_SYS_TEXT_BASE=0x01000000
-CONFIG_MESON_GXM=y
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0xFFFF0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_MESON_GXM=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BASE=0xc81004c0
 CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_IDENT_STRING=" libretech-s912-pc"
 CONFIG_DEBUG_UART=y
 CONFIG_OF_BOARD_SETUP=y
@@ -22,7 +22,6 @@
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
 CONFIG_CMD_SF_TEST=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
@@ -34,13 +33,11 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SARADC_MESON=y
-CONFIG_DM_GPIO=y
 CONFIG_DM_KEYBOARD=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_MESON_GX=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_PHY_REALTEK=y
 CONFIG_DM_ETH=y
@@ -67,12 +64,12 @@
 CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
 CONFIG_USB_DWC3=y
 # CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_KEYBOARD=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
 CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_KEYBOARD=y
 CONFIG_DM_VIDEO=y
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_MESON=y
diff --git a/configs/linkit-smart-7688-ram_defconfig b/configs/linkit-smart-7688-ram_defconfig
deleted file mode 100644
index d1691ab..0000000
--- a/configs/linkit-smart-7688-ram_defconfig
+++ /dev/null
@@ -1,65 +0,0 @@
-CONFIG_MIPS=y
-CONFIG_SYS_TEXT_BASE=0x80010000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_ENV_OFFSET=0x80000
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ARCH_MTMIPS=y
-CONFIG_BOARD_LINKIT_SMART_7688=y
-# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
-CONFIG_MIPS_BOOT_FDT=y
-CONFIG_FIT=y
-CONFIG_FIT_SIGNATURE=y
-CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_LICENSE=y
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_MEMINFO=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_MTD=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_FS_GENERIC=y
-# CONFIG_DOS_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="linkit-smart-7688"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-# CONFIG_DM_DEVICE_REMOVE is not set
-CONFIG_BLK=y
-CONFIG_LED=y
-CONFIG_LED_BLINK=y
-CONFIG_LED_GPIO=y
-CONFIG_MTD=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_SPI_FLASH_MTD=y
-CONFIG_MT7628_ETH=y
-CONFIG_PHY=y
-CONFIG_MT76X8_USB_PHY=y
-CONFIG_SPI=y
-CONFIG_MT7621_SPI=y
-CONFIG_SYSRESET_SYSCON=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_STORAGE=y
-CONFIG_FS_EXT4=y
-CONFIG_FS_FAT=y
-CONFIG_LZMA=y
-CONFIG_LZO=y
diff --git a/configs/linkit-smart-7688_defconfig b/configs/linkit-smart-7688_defconfig
index a567c0c..8ec6693 100644
--- a/configs/linkit-smart-7688_defconfig
+++ b/configs/linkit-smart-7688_defconfig
@@ -1,14 +1,16 @@
 CONFIG_MIPS=y
-CONFIG_SYS_TEXT_BASE=0x9c000000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x80000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
 CONFIG_ARCH_MTMIPS=y
 CONFIG_BOARD_LINKIT_SMART_7688=y
-CONFIG_BOOT_ROM=y
-CONFIG_ONBOARD_DDR2_SIZE_1024MBIT=y
-CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT=y
+CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_FIT=y
@@ -17,6 +19,8 @@
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_NOR_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_LICENSE=y
 # CONFIG_CMD_ELF is not set
@@ -40,6 +44,7 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_BLK=y
 CONFIG_LED=y
@@ -57,7 +62,6 @@
 CONFIG_MT76X8_USB_PHY=y
 CONFIG_SPI=y
 CONFIG_MT7621_SPI=y
-CONFIG_SYSRESET_SYSCON=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_EHCI_HCD=y
@@ -67,3 +71,4 @@
 CONFIG_FS_FAT=y
 CONFIG_LZMA=y
 CONFIG_LZO=y
+CONFIG_SPL_LZMA=y
diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig
index e022b4c..b6504b7 100644
--- a/configs/lion-rk3368_defconfig
+++ b/configs/lion-rk3368_defconfig
@@ -14,9 +14,9 @@
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x00000000
 CONFIG_SMBIOS_PRODUCT_NAME="sheep_rk3368"
 CONFIG_DEBUG_UART=y
-CONFIG_SPL_TEXT_BASE=0x00000000
 CONFIG_ANDROID_BOOT_IMAGE=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
diff --git a/configs/liteboard_defconfig b/configs/liteboard_defconfig
index 665955c..7c94478 100644
--- a/configs/liteboard_defconfig
+++ b/configs/liteboard_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_LITEBOARD=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x80000
+CONFIG_TARGET_LITEBOARD=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
@@ -45,6 +45,7 @@
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_SMSC=y
 CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig
index b1cf8ef..9bf5b9c 100644
--- a/configs/ls1012a2g5rdb_qspi_defconfig
+++ b/configs/ls1012a2g5rdb_qspi_defconfig
@@ -2,8 +2,8 @@
 CONFIG_TARGET_LS1012A2G5RDB=y
 CONFIG_SYS_TEXT_BASE=0x40100000
 CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x300000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
diff --git a/configs/ls1012a2g5rdb_tfa_defconfig b/configs/ls1012a2g5rdb_tfa_defconfig
index a978580..d9d4f82 100644
--- a/configs/ls1012a2g5rdb_tfa_defconfig
+++ b/configs/ls1012a2g5rdb_tfa_defconfig
@@ -3,8 +3,8 @@
 CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x500000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_NR_DRAM_BANKS=2
diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
index 1e60148..02a80b1 100644
--- a/configs/ls1012afrdm_qspi_defconfig
+++ b/configs/ls1012afrdm_qspi_defconfig
@@ -2,10 +2,9 @@
 CONFIG_TARGET_LS1012AFRDM=y
 CONFIG_SYS_TEXT_BASE=0x40100000
 CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x300000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DM_GPIO=y
-CONFIG_BLK=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_NR_DRAM_BANKS=2
@@ -34,6 +33,7 @@
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
+CONFIG_BLK=y
 CONFIG_DM_I2C=y
 # CONFIG_MMC is not set
 CONFIG_MTD=y
diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig
index 420a2f4..ecc4c81 100644
--- a/configs/ls1012afrdm_tfa_defconfig
+++ b/configs/ls1012afrdm_tfa_defconfig
@@ -3,10 +3,9 @@
 CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x500000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DM_GPIO=y
-CONFIG_BLK=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
@@ -34,6 +33,7 @@
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
+CONFIG_BLK=y
 CONFIG_DM_I2C=y
 # CONFIG_MMC is not set
 CONFIG_MTD=y
diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
index cc5ee71..addb31c 100644
--- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
@@ -1,8 +1,8 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1012AFRWY=y
 CONFIG_SYS_TEXT_BASE=0x40100000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x10000
+CONFIG_NXP_ESBC=y
 CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_NR_DRAM_BANKS=2
diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig
index bee0936..2156f5e 100644
--- a/configs/ls1012afrwy_qspi_defconfig
+++ b/configs/ls1012afrwy_qspi_defconfig
@@ -2,8 +2,8 @@
 CONFIG_TARGET_LS1012AFRWY=y
 CONFIG_SYS_TEXT_BASE=0x40100000
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x1D0000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_NR_DRAM_BANKS=2
diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
index a983c30..a4fdd0c 100644
--- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
@@ -2,8 +2,8 @@
 CONFIG_TARGET_LS1012AFRWY=y
 CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x10000
+CONFIG_NXP_ESBC=y
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig
index f8ca448..280dbd3 100644
--- a/configs/ls1012afrwy_tfa_defconfig
+++ b/configs/ls1012afrwy_tfa_defconfig
@@ -3,8 +3,8 @@
 CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x1D0000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
index fd4fba5..7826661 100644
--- a/configs/ls1012aqds_qspi_defconfig
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -2,8 +2,8 @@
 CONFIG_TARGET_LS1012AQDS=y
 CONFIG_SYS_TEXT_BASE=0x40100000
 CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x300000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
index 23dea4c..8ab6cbc 100644
--- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
@@ -2,8 +2,8 @@
 CONFIG_TARGET_LS1012AQDS=y
 CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x40000
+CONFIG_NXP_ESBC=y
 CONFIG_DM_GPIO=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_NR_DRAM_BANKS=2
diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig
index 974cedc..1b783c5 100644
--- a/configs/ls1012aqds_tfa_defconfig
+++ b/configs/ls1012aqds_tfa_defconfig
@@ -3,8 +3,8 @@
 CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x500000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_NR_DRAM_BANKS=2
diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
index 5ad4e0d..4031b9b 100644
--- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
@@ -1,8 +1,8 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1012ARDB=y
 CONFIG_SYS_TEXT_BASE=0x40100000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x40000
+CONFIG_NXP_ESBC=y
 CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
index 98057a9..01770b8 100644
--- a/configs/ls1012ardb_qspi_defconfig
+++ b/configs/ls1012ardb_qspi_defconfig
@@ -2,8 +2,8 @@
 CONFIG_TARGET_LS1012ARDB=y
 CONFIG_SYS_TEXT_BASE=0x40100000
 CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x300000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
index 4e937e5..57e9dd9 100644
--- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
@@ -2,8 +2,8 @@
 CONFIG_TARGET_LS1012ARDB=y
 CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x40000
+CONFIG_NXP_ESBC=y
 CONFIG_DM_GPIO=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_NR_DRAM_BANKS=2
@@ -42,6 +42,8 @@
 CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_FSL_PFE=y
+CONFIG_DM_ETH=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
@@ -60,5 +62,3 @@
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_FSL_PFE=y
-CONFIG_DM_ETH=y
diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig
index fdf2324..06584ff 100644
--- a/configs/ls1012ardb_tfa_defconfig
+++ b/configs/ls1012ardb_tfa_defconfig
@@ -3,8 +3,8 @@
 CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x500000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_NR_DRAM_BANKS=2
diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig
index 512f775..dba33e2 100644
--- a/configs/ls1021aiot_qspi_defconfig
+++ b/configs/ls1021aiot_qspi_defconfig
@@ -2,8 +2,8 @@
 CONFIG_TARGET_LS1021AIOT=y
 CONFIG_SYS_TEXT_BASE=0x40010000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_AHCI=y
@@ -30,6 +30,7 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig
index 4cd4c31..fc6df70 100644
--- a/configs/ls1021aiot_sdcard_defconfig
+++ b/configs/ls1021aiot_sdcard_defconfig
@@ -7,8 +7,8 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x10000000
+CONFIG_AHCI=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT,SD_BOOT_QSPI"
 CONFIG_MISC_INIT_R=y
 CONFIG_BOARD_EARLY_INIT_F=y
@@ -36,6 +36,7 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig
index d29b6eb..203303b 100644
--- a/configs/ls1021aqds_ddr4_nor_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_defconfig
@@ -49,6 +49,7 @@
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_REALTEK=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
index 62c3bcc..f77b6db 100644
--- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
@@ -50,6 +50,7 @@
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_REALTEK=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index a940c74..dc45f8f 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -10,8 +10,8 @@
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x10000000
+CONFIG_AHCI=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -66,6 +66,7 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_REALTEK=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
index 73fd8c2..aaf0f13 100644
--- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
@@ -1,8 +1,8 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
 CONFIG_SYS_TEXT_BASE=0x60100000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_AHCI=y
@@ -48,6 +48,7 @@
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_REALTEK=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig
index b75b0c0..9211f97 100644
--- a/configs/ls1021aqds_nor_defconfig
+++ b/configs/ls1021aqds_nor_defconfig
@@ -50,6 +50,7 @@
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_REALTEK=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig
index 83daeb1..c27147e 100644
--- a/configs/ls1021aqds_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_nor_lpuart_defconfig
@@ -51,6 +51,7 @@
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_REALTEK=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
index 497ee52..c3b5627 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -2,8 +2,8 @@
 CONFIG_TARGET_LS1021AQDS=y
 CONFIG_SYS_TEXT_BASE=0x40100000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x300000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_AHCI=y
@@ -49,6 +49,7 @@
 CONFIG_MTD=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_REALTEK=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index 3d12ceb..e08f283 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -11,8 +11,8 @@
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x10000000
+CONFIG_AHCI=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT"
@@ -65,6 +65,7 @@
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_REALTEK=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index 22be8e6..605a378 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -11,8 +11,8 @@
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x10000000
+CONFIG_AHCI=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT,SD_BOOT_QSPI"
@@ -61,6 +61,7 @@
 CONFIG_MTD=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_REALTEK=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig
index b7e754c..a62e04e 100644
--- a/configs/ls1021atsn_qspi_defconfig
+++ b/configs/ls1021atsn_qspi_defconfig
@@ -2,8 +2,8 @@
 CONFIG_TARGET_LS1021ATSN=y
 CONFIG_SYS_TEXT_BASE=0x40100000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x300000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_AHCI=y
diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig
index 5245540..db4f0ab 100644
--- a/configs/ls1021atsn_sdcard_defconfig
+++ b/configs/ls1021atsn_sdcard_defconfig
@@ -10,8 +10,8 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x10000000
+CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
index 9af9912..af8b8ff 100644
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -1,8 +1,8 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021ATWR=y
 CONFIG_SYS_TEXT_BASE=0x60100000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x20000
+CONFIG_NXP_ESBC=y
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_AHCI=y
diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
index 0fcd675..504b2d9 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -2,8 +2,8 @@
 CONFIG_TARGET_LS1021ATWR=y
 CONFIG_SYS_TEXT_BASE=0x40100000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x300000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_AHCI=y
diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
index 2f2a9ff..82e6244 100644
--- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
@@ -3,8 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x20000
+CONFIG_NXP_ESBC=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index 7a98c26..ad05bc4 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -10,8 +10,8 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x10000000
+CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index 110631d..18fd5c3 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -10,8 +10,8 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x10000000
+CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
index c5f0bd8..c19c66f 100644
--- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
@@ -2,8 +2,8 @@
 CONFIG_TARGET_LS1028AQDS=y
 CONFIG_TFABOOT=y
 CONFIG_SYS_MALLOC_F_LEN=0x6000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_DM_GPIO=y
 CONFIG_FSPI_AHB_EN_4BYTE=y
 CONFIG_NR_DRAM_BANKS=2
@@ -28,7 +28,7 @@
 CONFIG_CMD_WDT=y
 CONFIG_CMD_CACHE=y
 CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-duart"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
 CONFIG_DM=y
@@ -79,3 +79,4 @@
 CONFIG_RSA=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig
index 7085be7..82b08a5 100644
--- a/configs/ls1028aqds_tfa_defconfig
+++ b/configs/ls1028aqds_tfa_defconfig
@@ -3,8 +3,8 @@
 CONFIG_TFABOOT=y
 CONFIG_SYS_MALLOC_F_LEN=0x6000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x500000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_FSPI_AHB_EN_4BYTE=y
 CONFIG_NR_DRAM_BANKS=2
@@ -30,7 +30,7 @@
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-duart"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_ADDR=0x20500000
@@ -84,3 +84,4 @@
 CONFIG_WDT_SP805=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
diff --git a/configs/ls1028aqds_tfa_lpuart_defconfig b/configs/ls1028aqds_tfa_lpuart_defconfig
new file mode 100644
index 0000000..417f292
--- /dev/null
+++ b/configs/ls1028aqds_tfa_lpuart_defconfig
@@ -0,0 +1,88 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1028AQDS=y
+CONFIG_TFABOOT=y
+CONFIG_SYS_MALLOC_F_LEN=0x6000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_ENV_OFFSET=0x500000
+CONFIG_DM_GPIO=y
+CONFIG_FSPI_AHB_EN_4BYTE=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
+CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_MISC_INIT_R=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-lpuart"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_ADDR=0x20500000
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
+CONFIG_FSL_CAAM=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_E1000=y
+CONFIG_FSL_ENETC=y
+CONFIG_MDIO_MUX_I2CREG=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_ECAM_GENERIC=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_PCF2127=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_WDT=y
+CONFIG_WDT_SP805=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
index 6fa14af..947c4b4 100644
--- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
@@ -2,8 +2,8 @@
 CONFIG_TARGET_LS1028ARDB=y
 CONFIG_TFABOOT=y
 CONFIG_SYS_MALLOC_F_LEN=0x6000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_DM_GPIO=y
 CONFIG_FSPI_AHB_EN_4BYTE=y
 CONFIG_NR_DRAM_BANKS=2
@@ -76,3 +76,4 @@
 CONFIG_RSA=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig
index 7ffd1c3..ad6de6c 100644
--- a/configs/ls1028ardb_tfa_defconfig
+++ b/configs/ls1028ardb_tfa_defconfig
@@ -3,8 +3,8 @@
 CONFIG_TFABOOT=y
 CONFIG_SYS_MALLOC_F_LEN=0x6000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x500000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_FSPI_AHB_EN_4BYTE=y
 CONFIG_NR_DRAM_BANKS=2
@@ -85,3 +85,4 @@
 CONFIG_WDT_SP805=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
index 93b86af..cd01a8d 100644
--- a/configs/ls1043aqds_defconfig
+++ b/configs/ls1043aqds_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_TEXT_BASE=0x60100000
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_AHCI=y
@@ -35,6 +36,7 @@
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
@@ -46,6 +48,9 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -62,5 +67,3 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig
index f89c2ee..1976e27 100644
--- a/configs/ls1043aqds_lpuart_defconfig
+++ b/configs/ls1043aqds_lpuart_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_TEXT_BASE=0x60100000
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_AHCI=y
@@ -36,6 +37,7 @@
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
@@ -47,6 +49,9 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -64,5 +69,3 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig
index a169bfe..1a1643e 100644
--- a/configs/ls1043aqds_nand_defconfig
+++ b/configs/ls1043aqds_nand_defconfig
@@ -5,13 +5,14 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x300000
+CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x10000000
+CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -52,6 +53,7 @@
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
@@ -62,6 +64,9 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -78,5 +83,3 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig
index 01d0af3..bd05cab 100644
--- a/configs/ls1043aqds_nor_ddr3_defconfig
+++ b/configs/ls1043aqds_nor_ddr3_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_TEXT_BASE=0x60100000
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_AHCI=y
@@ -36,6 +37,7 @@
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
 CONFIG_SYS_FSL_DDR3=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
@@ -47,6 +49,9 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -63,5 +68,3 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig
index 65eff7c..50af1a7 100644
--- a/configs/ls1043aqds_qspi_defconfig
+++ b/configs/ls1043aqds_qspi_defconfig
@@ -2,8 +2,9 @@
 CONFIG_TARGET_LS1043AQDS=y
 CONFIG_SYS_TEXT_BASE=0x40100000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x300000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_AHCI=y
@@ -36,11 +37,15 @@
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -58,5 +63,3 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig
index c5042a3..e5a91a3 100644
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ b/configs/ls1043aqds_sdcard_ifc_defconfig
@@ -5,14 +5,15 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x300000
+CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x10000000
+CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -52,6 +53,7 @@
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
@@ -63,6 +65,9 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -79,5 +84,3 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig
index 12706a4..42d0642 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -5,14 +5,15 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x300000
+CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x10000000
+CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -50,11 +51,15 @@
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -72,5 +77,3 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
index b7335bc..9dccd11 100644
--- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
@@ -2,8 +2,9 @@
 CONFIG_TARGET_LS1043AQDS=y
 CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
+CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
@@ -34,6 +35,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
@@ -45,6 +47,9 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -63,5 +68,3 @@
 CONFIG_SPL_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig
index 6e594ed..2be983f 100644
--- a/configs/ls1043aqds_tfa_defconfig
+++ b/configs/ls1043aqds_tfa_defconfig
@@ -3,8 +3,9 @@
 CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x500000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
@@ -43,6 +44,7 @@
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
@@ -55,6 +57,9 @@
 CONFIG_SF_DEFAULT_BUS=1
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -71,5 +76,3 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig
index 153a628..911bbef7 100644
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_SECURE_BOOT_defconfig
@@ -1,8 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1043ARDB=y
 CONFIG_SYS_TEXT_BASE=0x60100000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x20000
+CONFIG_NXP_ESBC=y
+CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_DISTRO_DEFAULTS=y
@@ -13,6 +14,7 @@
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
 CONFIG_MISC_INIT_R=y
 CONFIG_CMD_IMLS=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -25,6 +27,7 @@
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_DM=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
@@ -36,6 +39,10 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
@@ -55,5 +62,3 @@
 CONFIG_SPL_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index d1e5343..4a15992 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_TEXT_BASE=0x60100000
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_DISTRO_DEFAULTS=y
@@ -13,6 +14,7 @@
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
 CONFIG_MISC_INIT_R=y
 CONFIG_CMD_IMLS=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -28,6 +30,7 @@
 CONFIG_ENV_ADDR=0x60300000
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
@@ -40,6 +43,10 @@
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -55,5 +62,3 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
index 252c7c8..f399b1c 100644
--- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
@@ -3,8 +3,9 @@
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
+CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
@@ -31,6 +32,7 @@
 CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_CMD_IMLS=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -46,6 +48,7 @@
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
 CONFIG_SPL_DM=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
@@ -57,6 +60,10 @@
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -75,5 +82,3 @@
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index de18aaa..5f79460 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -5,6 +5,7 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x300000
+CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
@@ -31,6 +32,7 @@
 CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_CMD_IMLS=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -47,6 +49,7 @@
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
@@ -58,6 +61,10 @@
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -74,5 +81,3 @@
 CONFIG_USB_XHCI_DWC3=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
index 149b25f..2243218 100644
--- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
@@ -3,8 +3,9 @@
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
+CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
@@ -30,6 +31,7 @@
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_CMD_IMLS=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -45,6 +47,7 @@
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
 CONFIG_SPL_DM=y
+CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
@@ -55,6 +58,10 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
@@ -74,5 +81,3 @@
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index b386fc6..bf557d7 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -5,6 +5,7 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x300000
+CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
@@ -29,6 +30,7 @@
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_CMD_IMLS=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -45,6 +47,7 @@
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
@@ -57,6 +60,10 @@
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -73,5 +80,3 @@
 CONFIG_USB_XHCI_DWC3=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
index 36eb0fc..0f3f920 100644
--- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
@@ -2,8 +2,9 @@
 CONFIG_TARGET_LS1043ARDB=y
 CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
+CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
@@ -15,6 +16,7 @@
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
 CONFIG_MISC_INIT_R=y
 CONFIG_CMD_IMLS=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -27,6 +29,7 @@
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_DM=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
@@ -38,6 +41,10 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
@@ -56,5 +63,3 @@
 CONFIG_SPL_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig
index eaddbca..a62310c 100644
--- a/configs/ls1043ardb_tfa_defconfig
+++ b/configs/ls1043ardb_tfa_defconfig
@@ -3,8 +3,9 @@
 CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x500000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
@@ -16,6 +17,7 @@
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
 CONFIG_MISC_INIT_R=y
 CONFIG_CMD_IMLS=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -33,6 +35,7 @@
 CONFIG_ENV_ADDR=0x60500000
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
@@ -45,6 +48,10 @@
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -59,5 +66,3 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig
index 616984f..48dc7ac 100644
--- a/configs/ls1046afrwy_tfa_defconfig
+++ b/configs/ls1046afrwy_tfa_defconfig
@@ -3,8 +3,9 @@
 CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x500000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_DM_GPIO=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
@@ -34,6 +35,7 @@
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
@@ -62,5 +64,3 @@
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_ASIX88179=y
 CONFIG_USB_ETHER_RTL8152=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig
index ed25b7a..d3521c3 100644
--- a/configs/ls1046aqds_SECURE_BOOT_defconfig
+++ b/configs/ls1046aqds_SECURE_BOOT_defconfig
@@ -1,8 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1046AQDS=y
 CONFIG_SYS_TEXT_BASE=0x60100000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x20000
+CONFIG_NXP_ESBC=y
+CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_AHCI=y
@@ -32,6 +33,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
@@ -42,6 +44,9 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -60,5 +65,3 @@
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_RSA=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig
index 0a50bb1..cf92386 100644
--- a/configs/ls1046aqds_defconfig
+++ b/configs/ls1046aqds_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_TEXT_BASE=0x60100000
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_AHCI=y
@@ -35,6 +36,7 @@
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
@@ -45,6 +47,9 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -62,5 +67,3 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig
index 17d1685..a75a523 100644
--- a/configs/ls1046aqds_lpuart_defconfig
+++ b/configs/ls1046aqds_lpuart_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_TEXT_BASE=0x60100000
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_AHCI=y
@@ -36,6 +37,7 @@
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
@@ -46,6 +48,9 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -64,5 +69,3 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig
index 0bafcbe..8f92af5 100644
--- a/configs/ls1046aqds_nand_defconfig
+++ b/configs/ls1046aqds_nand_defconfig
@@ -3,12 +3,13 @@
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x300000
+CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x10000000
+CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -44,6 +45,7 @@
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
@@ -53,6 +55,9 @@
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -70,5 +75,3 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig
index ff0fd45..239483f 100644
--- a/configs/ls1046aqds_qspi_defconfig
+++ b/configs/ls1046aqds_qspi_defconfig
@@ -2,8 +2,9 @@
 CONFIG_TARGET_LS1046AQDS=y
 CONFIG_SYS_TEXT_BASE=0x40100000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x300000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_AHCI=y
@@ -35,11 +36,15 @@
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 # CONFIG_SPI_FLASH_BAR is not set
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -58,5 +63,3 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig
index 78edb45..c5ef64a 100644
--- a/configs/ls1046aqds_sdcard_ifc_defconfig
+++ b/configs/ls1046aqds_sdcard_ifc_defconfig
@@ -5,14 +5,15 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x300000
+CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x10000000
+CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -53,6 +54,7 @@
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
@@ -63,6 +65,9 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -80,5 +85,3 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig
index d085daf..a4d714f 100644
--- a/configs/ls1046aqds_sdcard_qspi_defconfig
+++ b/configs/ls1046aqds_sdcard_qspi_defconfig
@@ -5,14 +5,15 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x300000
+CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x10000000
+CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -51,11 +52,15 @@
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 # CONFIG_SPI_FLASH_BAR is not set
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -74,5 +79,3 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
index 6a93914..ece7c19 100644
--- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
@@ -2,8 +2,9 @@
 CONFIG_TARGET_LS1046AQDS=y
 CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
+CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
@@ -34,6 +35,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
@@ -44,6 +46,9 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -61,5 +66,3 @@
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_RSA=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig
index 04e6b23..f1693e1 100644
--- a/configs/ls1046aqds_tfa_defconfig
+++ b/configs/ls1046aqds_tfa_defconfig
@@ -3,8 +3,9 @@
 CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x500000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
@@ -43,6 +44,7 @@
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
@@ -54,6 +56,9 @@
 CONFIG_SF_DEFAULT_BUS=1
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -71,5 +76,3 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig
index bbb352d..def9140 100644
--- a/configs/ls1046ardb_emmc_defconfig
+++ b/configs/ls1046ardb_emmc_defconfig
@@ -5,14 +5,15 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x300000
+CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x10000000
+CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -31,6 +32,7 @@
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -48,6 +50,7 @@
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
@@ -56,6 +59,9 @@
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -73,5 +79,3 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
index b9c8a88..1f89222 100644
--- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
@@ -1,8 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1046ARDB=y
 CONFIG_SYS_TEXT_BASE=0x40100000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
+CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_NR_DRAM_BANKS=2
@@ -15,6 +16,7 @@
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 CONFIG_MISC_INIT_R=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -29,6 +31,7 @@
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
@@ -37,6 +40,9 @@
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -55,5 +61,3 @@
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_RSA=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig
index 51edada..8b1b695 100644
--- a/configs/ls1046ardb_qspi_defconfig
+++ b/configs/ls1046ardb_qspi_defconfig
@@ -2,8 +2,9 @@
 CONFIG_TARGET_LS1046ARDB=y
 CONFIG_SYS_TEXT_BASE=0x40100000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x300000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_NR_DRAM_BANKS=2
@@ -16,6 +17,7 @@
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 CONFIG_MISC_INIT_R=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -32,6 +34,7 @@
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
@@ -40,6 +43,9 @@
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -57,5 +63,3 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig
index 84e0596..cbc598d 100644
--- a/configs/ls1046ardb_qspi_spl_defconfig
+++ b/configs/ls1046ardb_qspi_spl_defconfig
@@ -4,8 +4,9 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x300000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_SPL_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
@@ -13,8 +14,8 @@
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x10000000
+CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
@@ -33,6 +34,7 @@
 CONFIG_SYS_OS_BASE=0x40980000
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_CMD_SPL=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -51,6 +53,7 @@
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
@@ -58,6 +61,9 @@
 # CONFIG_SPI_FLASH_BAR is not set
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
@@ -77,5 +83,3 @@
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_SPL_GZIP=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
index 9954e89..aeac0a2 100644
--- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
@@ -3,8 +3,9 @@
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
+CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
@@ -30,6 +31,7 @@
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -45,6 +47,7 @@
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
 CONFIG_SPL_DM=y
+CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
@@ -52,6 +55,9 @@
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -70,5 +76,3 @@
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig
index 3502809..878bdf0 100644
--- a/configs/ls1046ardb_sdcard_defconfig
+++ b/configs/ls1046ardb_sdcard_defconfig
@@ -5,14 +5,15 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x300000
+CONFIG_DM_GPIO=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x10000000
+CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -30,6 +31,7 @@
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -47,6 +49,7 @@
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
@@ -55,6 +58,9 @@
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -72,5 +78,3 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
index 9e3042b..140da79 100644
--- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
@@ -2,8 +2,9 @@
 CONFIG_TARGET_LS1046ARDB=y
 CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
+CONFIG_DM_GPIO=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
@@ -16,6 +17,7 @@
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 CONFIG_MISC_INIT_R=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -29,6 +31,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
@@ -37,6 +40,9 @@
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -54,5 +60,3 @@
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_RSA=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig
index 2f7686b..eab34cd 100644
--- a/configs/ls1046ardb_tfa_defconfig
+++ b/configs/ls1046ardb_tfa_defconfig
@@ -3,8 +3,9 @@
 CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x500000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_DM_GPIO=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
@@ -17,6 +18,7 @@
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 CONFIG_MISC_INIT_R=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -34,6 +36,7 @@
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
@@ -42,6 +45,9 @@
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
@@ -58,5 +64,3 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_DM_GPIO=y
diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig
index 7713e58..69e3a8f 100644
--- a/configs/ls1088aqds_defconfig
+++ b/configs/ls1088aqds_defconfig
@@ -42,6 +42,11 @@
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_DM_SPI_FLASH=y
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_PCI=y
@@ -59,3 +64,4 @@
 CONFIG_USB_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
+CONFIG_GIC_V3_ITS=y
diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
index 242c40b..3a36379 100644
--- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
@@ -1,8 +1,8 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1088AQDS=y
 CONFIG_SYS_TEXT_BASE=0x20100000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_NR_DRAM_BANKS=2
@@ -24,6 +24,7 @@
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MDIO is not set
 CONFIG_MP=y
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
@@ -39,6 +40,11 @@
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_PCI=y
@@ -60,3 +66,4 @@
 CONFIG_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig
index 3649b06..117fdd8 100644
--- a/configs/ls1088aqds_qspi_defconfig
+++ b/configs/ls1088aqds_qspi_defconfig
@@ -2,8 +2,8 @@
 CONFIG_TARGET_LS1088AQDS=y
 CONFIG_SYS_TEXT_BASE=0x20100000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x300000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_NR_DRAM_BANKS=2
@@ -25,6 +25,7 @@
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MDIO is not set
 CONFIG_MP=y
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
@@ -42,6 +43,11 @@
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_PCI=y
@@ -61,3 +67,4 @@
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig
index 815ea5c..eedee1e 100644
--- a/configs/ls1088aqds_sdcard_ifc_defconfig
+++ b/configs/ls1088aqds_sdcard_ifc_defconfig
@@ -11,8 +11,8 @@
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x1800a000
+CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_F is not set
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
@@ -52,6 +52,11 @@
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_PCI=y
@@ -67,3 +72,4 @@
 CONFIG_USB_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
+CONFIG_GIC_V3_ITS=y
diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig
index 275dbf9..621c411 100644
--- a/configs/ls1088aqds_sdcard_qspi_defconfig
+++ b/configs/ls1088aqds_sdcard_qspi_defconfig
@@ -11,8 +11,8 @@
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x1800a000
+CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 # CONFIG_SYS_MALLOC_F is not set
 CONFIG_FIT_VERBOSE=y
@@ -35,6 +35,7 @@
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MDIO is not set
 CONFIG_MP=y
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
@@ -52,6 +53,11 @@
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_PCI=y
@@ -70,3 +76,4 @@
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
+CONFIG_GIC_V3_ITS=y
diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig
index 1144cba..2bb84e1 100644
--- a/configs/ls1088aqds_tfa_defconfig
+++ b/configs/ls1088aqds_tfa_defconfig
@@ -4,8 +4,8 @@
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_SYS_MALLOC_F_LEN=0x6000
 CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x500000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_NR_DRAM_BANKS=2
@@ -28,6 +28,7 @@
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MDIO is not set
 CONFIG_MP=y
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
@@ -57,6 +58,11 @@
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_PCI=y
@@ -78,3 +84,4 @@
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
index 3f654e2..806d770 100644
--- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
@@ -1,8 +1,9 @@
 CONFIG_ARM=y
+CONFIG_GIC_V3_ITS=y
 CONFIG_TARGET_LS1088ARDB=y
 CONFIG_SYS_TEXT_BASE=0x20100000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_NR_DRAM_BANKS=2
@@ -21,10 +22,12 @@
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MDIO is not set
 CONFIG_MP=y
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
@@ -40,8 +43,13 @@
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig
index 935d76b..9b66fd9 100644
--- a/configs/ls1088ardb_qspi_defconfig
+++ b/configs/ls1088ardb_qspi_defconfig
@@ -1,9 +1,10 @@
 CONFIG_ARM=y
+CONFIG_GIC_V3_ITS=y
 CONFIG_TARGET_LS1088ARDB=y
 CONFIG_SYS_TEXT_BASE=0x20100000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x300000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_NR_DRAM_BANKS=2
@@ -22,10 +23,12 @@
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MDIO is not set
 CONFIG_MP=y
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
@@ -43,8 +46,13 @@
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
index 562cbdd..4a15f82 100644
--- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
@@ -1,10 +1,11 @@
 CONFIG_ARM=y
+CONFIG_GIC_V3_ITS=y
 CONFIG_TARGET_LS1088ARDB=y
 CONFIG_SYS_TEXT_BASE=0x80400000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
@@ -33,10 +34,12 @@
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MDIO is not set
 CONFIG_MP=y
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
@@ -52,8 +55,13 @@
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig
index 1e6fdce..1ab1fa3 100644
--- a/configs/ls1088ardb_sdcard_qspi_defconfig
+++ b/configs/ls1088ardb_sdcard_qspi_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_GIC_V3_ITS=y
 CONFIG_TARGET_LS1088ARDB=y
 CONFIG_SYS_TEXT_BASE=0x80400000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -11,8 +12,8 @@
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x1800a000
+CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 # CONFIG_SYS_MALLOC_F is not set
 CONFIG_FIT_VERBOSE=y
@@ -32,10 +33,12 @@
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MDIO is not set
 CONFIG_MP=y
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
@@ -53,8 +56,13 @@
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
index 0086039..4ad9a66 100644
--- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
@@ -1,10 +1,11 @@
 CONFIG_ARM=y
+CONFIG_GIC_V3_ITS=y
 CONFIG_TARGET_LS1088ARDB=y
 CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_SYS_MALLOC_F_LEN=0x6000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_DM_GPIO=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_NR_DRAM_BANKS=2
@@ -24,9 +25,11 @@
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
+# CONFIG_CMD_MDIO is not set
 CONFIG_MP=y
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
@@ -47,8 +50,13 @@
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig
index a7908e9..7690292 100644
--- a/configs/ls1088ardb_tfa_defconfig
+++ b/configs/ls1088ardb_tfa_defconfig
@@ -1,11 +1,12 @@
 CONFIG_ARM=y
+CONFIG_GIC_V3_ITS=y
 CONFIG_TARGET_LS1088ARDB=y
 CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_SYS_MALLOC_F_LEN=0x6000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x500000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_NR_DRAM_BANKS=2
@@ -25,10 +26,12 @@
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MDIO is not set
 CONFIG_MP=y
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
@@ -52,8 +55,13 @@
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig
index 8a792e4..4c85b11 100644
--- a/configs/ls2080aqds_SECURE_BOOT_defconfig
+++ b/configs/ls2080aqds_SECURE_BOOT_defconfig
@@ -1,8 +1,8 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS2080AQDS=y
 CONFIG_SYS_TEXT_BASE=0x30100000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_NR_DRAM_BANKS=3
 CONFIG_AHCI=y
@@ -43,6 +43,10 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
@@ -62,3 +66,4 @@
 CONFIG_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig
index bc4c218..0f8e22b 100644
--- a/configs/ls2080aqds_defconfig
+++ b/configs/ls2080aqds_defconfig
@@ -46,6 +46,10 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
@@ -63,3 +67,4 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index e840cbf..0441770 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -9,8 +9,8 @@
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=3
 CONFIG_SPL=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x1800a000
+CONFIG_AHCI=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -53,6 +53,10 @@
 CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
@@ -70,3 +74,4 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig
index 861e652..c159c15 100644
--- a/configs/ls2080aqds_qspi_defconfig
+++ b/configs/ls2080aqds_qspi_defconfig
@@ -2,8 +2,8 @@
 CONFIG_TARGET_LS2080AQDS=y
 CONFIG_SYS_TEXT_BASE=0x20100000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x300000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_NR_DRAM_BANKS=3
 CONFIG_AHCI=y
 CONFIG_FIT=y
@@ -45,6 +45,10 @@
 CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
@@ -62,3 +66,4 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig
index 864e70d..ac0b635 100644
--- a/configs/ls2080aqds_sdcard_defconfig
+++ b/configs/ls2080aqds_sdcard_defconfig
@@ -11,8 +11,8 @@
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=3
 CONFIG_SPL=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x1800a000
+CONFIG_AHCI=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -52,6 +52,10 @@
 CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
@@ -69,3 +73,4 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig
index 4abfc64..94087ce 100644
--- a/configs/ls2080ardb_SECURE_BOOT_defconfig
+++ b/configs/ls2080ardb_SECURE_BOOT_defconfig
@@ -1,8 +1,8 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS2080ARDB=y
 CONFIG_SYS_TEXT_BASE=0x30100000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_NR_DRAM_BANKS=3
 CONFIG_AHCI=y
@@ -64,3 +64,4 @@
 CONFIG_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig
index 0102e14..e9dfc36 100644
--- a/configs/ls2080ardb_defconfig
+++ b/configs/ls2080ardb_defconfig
@@ -65,3 +65,4 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index 448e0fe..d1086f9 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -9,8 +9,8 @@
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=3
 CONFIG_SPL=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x1800a000
+CONFIG_AHCI=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -70,3 +70,4 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig
index e446a11..032cb40 100644
--- a/configs/ls2081ardb_defconfig
+++ b/configs/ls2081ardb_defconfig
@@ -2,8 +2,8 @@
 CONFIG_TARGET_LS2081ARDB=y
 CONFIG_SYS_TEXT_BASE=0x20100000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x300000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_NR_DRAM_BANKS=3
@@ -62,3 +62,4 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig
index 9f49736..81bc489 100644
--- a/configs/ls2088aqds_tfa_defconfig
+++ b/configs/ls2088aqds_tfa_defconfig
@@ -3,8 +3,8 @@
 CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x500000
+CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=3
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
@@ -56,6 +56,10 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TERANETICS=y
+CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
@@ -74,3 +78,4 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
index ae4a682..2d71bae 100644
--- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
@@ -1,8 +1,8 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS2080ARDB=y
 CONFIG_SYS_TEXT_BASE=0x20100000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_NR_DRAM_BANKS=3
@@ -16,6 +16,7 @@
 # CONFIG_USE_BOOTCOMMAND is not set
 CONFIG_MISC_INIT_R=y
 CONFIG_CMD_GREPENV=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -39,8 +40,11 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
@@ -59,3 +63,4 @@
 CONFIG_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig
index 1ad5f3b..85b8dac 100644
--- a/configs/ls2088ardb_qspi_defconfig
+++ b/configs/ls2088ardb_qspi_defconfig
@@ -2,8 +2,8 @@
 CONFIG_TARGET_LS2080ARDB=y
 CONFIG_SYS_TEXT_BASE=0x20100000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x300000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_NR_DRAM_BANKS=3
@@ -19,6 +19,7 @@
 # CONFIG_USE_BOOTCOMMAND is not set
 CONFIG_MISC_INIT_R=y
 CONFIG_CMD_GREPENV=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -45,8 +46,11 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
@@ -63,3 +67,4 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
index c0d0a99..39a6973 100644
--- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
@@ -3,8 +3,8 @@
 CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_SYS_MALLOC_F_LEN=0x6000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_DM_GPIO=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_NR_DRAM_BANKS=3
@@ -22,6 +22,7 @@
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_EEPROM=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -31,7 +32,7 @@
 CONFIG_CMD_CACHE=y
 CONFIG_MP=y
 CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
@@ -54,8 +55,11 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
@@ -76,3 +80,4 @@
 CONFIG_SPL_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig
index ccbaaf7..34b9439 100644
--- a/configs/ls2088ardb_tfa_defconfig
+++ b/configs/ls2088ardb_tfa_defconfig
@@ -4,8 +4,8 @@
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_SYS_MALLOC_F_LEN=0x6000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x500000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_NR_DRAM_BANKS=3
@@ -23,6 +23,7 @@
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_EEPROM=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -62,8 +63,11 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
@@ -81,3 +85,4 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig
index 716aca3..2ce2346 100644
--- a/configs/lschlv2_defconfig
+++ b/configs/lschlv2_defconfig
@@ -5,8 +5,8 @@
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_TARGET_LSXL=y
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x70000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_IDENT_STRING=" LS-CHLv2"
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig
index 2e760e5..336fb34 100644
--- a/configs/lsxhl_defconfig
+++ b/configs/lsxhl_defconfig
@@ -5,8 +5,8 @@
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_TARGET_LSXL=y
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x70000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_IDENT_STRING=" LS-XHL"
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
index 319f710..cd7b413 100644
--- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
@@ -1,10 +1,11 @@
 CONFIG_ARM=y
+CONFIG_GIC_V3_ITS=y
 CONFIG_TARGET_LX2160AQDS=y
 CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_SYS_MALLOC_F_LEN=0x6000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_DM_GPIO=y
 CONFIG_FSPI_AHB_EN_4BYTE=y
 CONFIG_NR_DRAM_BANKS=3
@@ -74,4 +75,3 @@
 CONFIG_SPL_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_GIC_V3_ITS=y
diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig
index 0161dba..9b6ce38 100644
--- a/configs/lx2160aqds_tfa_defconfig
+++ b/configs/lx2160aqds_tfa_defconfig
@@ -1,11 +1,12 @@
 CONFIG_ARM=y
+CONFIG_GIC_V3_ITS=y
 CONFIG_TARGET_LX2160AQDS=y
 CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_SYS_MALLOC_F_LEN=0x6000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x500000
+CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DM_GPIO=y
 CONFIG_FSPI_AHB_EN_4BYTE=y
 CONFIG_NR_DRAM_BANKS=3
@@ -74,4 +75,3 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_GIC_V3_ITS=y
diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
index 10098ab..23f814f 100644
--- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
@@ -1,10 +1,11 @@
 CONFIG_ARM=y
+CONFIG_GIC_V3_ITS=y
 CONFIG_TARGET_LX2160ARDB=y
 CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_SYS_MALLOC_F_LEN=0x6000
-CONFIG_NXP_ESBC=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_NXP_ESBC=y
 CONFIG_DM_GPIO=y
 CONFIG_EMC2305=y
 CONFIG_FSPI_AHB_EN_4BYTE=y
@@ -21,6 +22,7 @@
 CONFIG_MISC_INIT_R=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_EEPROM=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -48,7 +50,10 @@
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_CORTINA=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
@@ -69,4 +74,3 @@
 CONFIG_SPL_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_GIC_V3_ITS=y
diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig
index c8582aa..bc654cf 100644
--- a/configs/lx2160ardb_tfa_defconfig
+++ b/configs/lx2160ardb_tfa_defconfig
@@ -1,11 +1,12 @@
 CONFIG_ARM=y
+CONFIG_GIC_V3_ITS=y
 CONFIG_TARGET_LX2160ARDB=y
 CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_SYS_MALLOC_F_LEN=0x6000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x500000
+CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DM_GPIO=y
 CONFIG_EMC2305=y
 CONFIG_FSPI_AHB_EN_4BYTE=y
@@ -23,6 +24,7 @@
 CONFIG_MISC_INIT_R=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_EEPROM=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -54,7 +56,10 @@
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_CORTINA=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
@@ -72,4 +77,3 @@
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_GIC_V3_ITS=y
diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig
index b7c1e6f..a65c21a 100644
--- a/configs/m53menlo_defconfig
+++ b/configs/m53menlo_defconfig
@@ -5,9 +5,9 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_TARGET_M53MENLO=y
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_TARGET_M53MENLO=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig
index 4e1dbf1..765a3ca 100644
--- a/configs/marsboard_defconfig
+++ b/configs/marsboard_defconfig
@@ -1,10 +1,10 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_EMBESTMX6BOARDS=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x2000
+CONFIG_TARGET_EMBESTMX6BOARDS=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024"
@@ -30,6 +30,7 @@
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
 CONFIG_MII=y
 CONFIG_SPI=y
 CONFIG_MXC_SPI=y
diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig
index 9cc9d66..1bdb151 100644
--- a/configs/maxbcm_defconfig
+++ b/configs/maxbcm_defconfig
@@ -7,22 +7,22 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_MAXBCM=y
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BASE=0xd0012000
 CONFIG_DEBUG_UART_CLOCK=250000000
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x40004030
+CONFIG_DEBUG_UART=y
 CONFIG_BOOTDELAY=3
 CONFIG_USE_PREBOOT=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_CMD_I2C=y
 CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig
index a49b638..2750747 100644
--- a/configs/mccmon6_nor_defconfig
+++ b/configs/mccmon6_nor_defconfig
@@ -3,11 +3,11 @@
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_TARGET_MCCMON6=y
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig
index c2e42c4..6c72a51 100644
--- a/configs/mccmon6_sd_defconfig
+++ b/configs/mccmon6_sd_defconfig
@@ -3,11 +3,11 @@
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_TARGET_MCCMON6=y
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/meesc_dataflash_defconfig b/configs/meesc_dataflash_defconfig
index 30700a4..63496d2 100644
--- a/configs/meesc_dataflash_defconfig
+++ b/configs/meesc_dataflash_defconfig
@@ -5,8 +5,8 @@
 CONFIG_TARGET_MEESC=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x4200
-CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_ENV_OFFSET=0x4200
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_FIT=y
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index 91ce67e..127fd5d 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -1,8 +1,8 @@
 CONFIG_X86=y
 CONFIG_SYS_TEXT_BASE=0xFFF00000
 CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x6EF000
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig
index e3e205f..5332abf 100644
--- a/configs/miqi-rk3288_defconfig
+++ b/configs/miqi-rk3288_defconfig
@@ -9,8 +9,8 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BASE=0xff690000
 CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0xff704000
+CONFIG_DEBUG_UART=y
 # CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_USE_PREBOOT=y
 CONFIG_SILENT_CONSOLE=y
@@ -70,12 +70,12 @@
 CONFIG_USB=y
 CONFIG_USB_DWC2=y
 CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_KEYBOARD=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_USB_KEYBOARD=y
 CONFIG_DM_VIDEO=y
 # CONFIG_VIDEO_BPP8 is not set
 CONFIG_DISPLAY=y
diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig
index 829491f..e4b3549 100644
--- a/configs/mixtile_loftq_defconfig
+++ b/configs/mixtile_loftq_defconfig
@@ -9,6 +9,7 @@
 CONFIG_USB2_VBUS_PIN=""
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mixtile-loftq"
+CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig
index 7dd8808..aa678d2 100644
--- a/configs/mpc8308_p1m_defconfig
+++ b/configs/mpc8308_p1m_defconfig
@@ -117,7 +117,15 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/mscc_jr2_defconfig b/configs/mscc_jr2_defconfig
index a27eb4b..c77b1c0 100644
--- a/configs/mscc_jr2_defconfig
+++ b/configs/mscc_jr2_defconfig
@@ -2,8 +2,8 @@
 CONFIG_SYS_TEXT_BASE=0x40000000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0x70100000
diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig
index cd3f1bb..b42b704 100644
--- a/configs/mscc_luton_defconfig
+++ b/configs/mscc_luton_defconfig
@@ -2,8 +2,8 @@
 CONFIG_SYS_TEXT_BASE=0x40000000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0x70100000
diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig
index 4aa0dd0..ecab4d0 100644
--- a/configs/mscc_ocelot_defconfig
+++ b/configs/mscc_ocelot_defconfig
@@ -2,8 +2,8 @@
 CONFIG_SYS_TEXT_BASE=0x40000000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0x70100000
diff --git a/configs/mscc_serval_defconfig b/configs/mscc_serval_defconfig
index 606ea5b..ee12e7c 100644
--- a/configs/mscc_serval_defconfig
+++ b/configs/mscc_serval_defconfig
@@ -2,8 +2,8 @@
 CONFIG_SYS_TEXT_BASE=0x40000000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_ENV_OFFSET_REDUND=0x140000
 CONFIG_ARCH_MSCC=y
diff --git a/configs/mscc_servalt_defconfig b/configs/mscc_servalt_defconfig
index c782992..5caef62 100644
--- a/configs/mscc_servalt_defconfig
+++ b/configs/mscc_servalt_defconfig
@@ -2,8 +2,8 @@
 CONFIG_SYS_TEXT_BASE=0x40000000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_ENV_OFFSET_REDUND=0x140000
 CONFIG_ARCH_MSCC=y
diff --git a/configs/mt7622_rfb_defconfig b/configs/mt7622_rfb_defconfig
index 1ce6ebd..1f3ccfe 100644
--- a/configs/mt7622_rfb_defconfig
+++ b/configs/mt7622_rfb_defconfig
@@ -51,6 +51,5 @@
 CONFIG_TIMER=y
 CONFIG_MTK_TIMER=y
 CONFIG_WDT_MTK=y
-CONFIG_LZ4=y
 CONFIG_LZO=y
 CONFIG_HEXDUMP=y
diff --git a/configs/mt7623n_bpir2_defconfig b/configs/mt7623n_bpir2_defconfig
index 07ddade..fe28f37 100644
--- a/configs/mt7623n_bpir2_defconfig
+++ b/configs/mt7623n_bpir2_defconfig
@@ -7,6 +7,7 @@
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_TARGET_MT7623=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTDELAY=3
@@ -56,4 +57,4 @@
 CONFIG_MTK_TIMER=y
 CONFIG_WDT_MTK=y
 CONFIG_LZMA=y
-# CONFIG_EFI_LOADER is not set
+CONFIG_EFI_LOADER=y
diff --git a/configs/mt7628_rfb_defconfig b/configs/mt7628_rfb_defconfig
new file mode 100644
index 0000000..f444cf9
--- /dev/null
+++ b/configs/mt7628_rfb_defconfig
@@ -0,0 +1,47 @@
+CONFIG_MIPS=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x30000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_ARCH_MTMIPS=y
+CONFIG_BOARD_MT7628_RFB=y
+CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_FIT=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_NOR_SUPPORT=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_DM is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_NFS is not set
+# CONFIG_PARTITIONS is not set
+CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7628-rfb"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+# CONFIG_INPUT is not set
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_MT7628_ETH=y
+# CONFIG_SPECIFY_CONSOLE_INDEX is not set
+CONFIG_SPI=y
+CONFIG_MT7621_SPI=y
+CONFIG_LZMA=y
+CONFIG_SPL_LZMA=y
diff --git a/configs/mt8512_bm1_emmc_defconfig b/configs/mt8512_bm1_emmc_defconfig
index a3dc962..e7659d7 100644
--- a/configs/mt8512_bm1_emmc_defconfig
+++ b/configs/mt8512_bm1_emmc_defconfig
@@ -31,5 +31,4 @@
 CONFIG_MTK_TIMER=y
 CONFIG_WDT=y
 CONFIG_WDT_MTK=y
-CONFIG_LZ4=y
 CONFIG_LZO=y
diff --git a/configs/mt8518_ap1_emmc_defconfig b/configs/mt8518_ap1_emmc_defconfig
index 943c1b2..a449804 100644
--- a/configs/mt8518_ap1_emmc_defconfig
+++ b/configs/mt8518_ap1_emmc_defconfig
@@ -45,5 +45,4 @@
 CONFIG_USB_GADGET_PRODUCT_NUM=0x0c01
 CONFIG_WDT=y
 CONFIG_WDT_MTK=y
-CONFIG_LZ4=y
 CONFIG_LZO=y
diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig
index e5284fa..144abb8 100644
--- a/configs/mvebu_db-88f3720_defconfig
+++ b/configs/mvebu_db-88f3720_defconfig
@@ -5,8 +5,8 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_MVEBU_ARMADA_37XX=y
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x180000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BASE=0xd0012000
diff --git a/configs/mvebu_db_armada8k_defconfig b/configs/mvebu_db_armada8k_defconfig
index 6fd2613..fb02f61 100644
--- a/configs/mvebu_db_armada8k_defconfig
+++ b/configs/mvebu_db_armada8k_defconfig
@@ -5,8 +5,8 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_MVEBU_ARMADA_8K=y
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x180000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_DEBUG_UART_BASE=0xf0512000
 CONFIG_DEBUG_UART_CLOCK=200000000
diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig
index 8e6c08b..01b6120 100644
--- a/configs/mvebu_espressobin-88f3720_defconfig
+++ b/configs/mvebu_espressobin-88f3720_defconfig
@@ -5,8 +5,8 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_MVEBU_ARMADA_37XX=y
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x180000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BASE=0xd0012000
diff --git a/configs/mvebu_mcbin-88f8040_defconfig b/configs/mvebu_mcbin-88f8040_defconfig
index 9b4cb14..0975ed3 100644
--- a/configs/mvebu_mcbin-88f8040_defconfig
+++ b/configs/mvebu_mcbin-88f8040_defconfig
@@ -5,8 +5,8 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_MVEBU_ARMADA_8K=y
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x180000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_DEBUG_UART_BASE=0xf0512000
diff --git a/configs/mx25pdk_defconfig b/configs/mx25pdk_defconfig
index f752b72..aa08e10 100644
--- a/configs/mx25pdk_defconfig
+++ b/configs/mx25pdk_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX25=y
 CONFIG_SYS_TEXT_BASE=0x81200000
-CONFIG_TARGET_MX25PDK=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x60000
+CONFIG_TARGET_MX25PDK=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg"
 CONFIG_DEFAULT_FDT_FILE="imx25-pdk.dtb"
diff --git a/configs/mx31pdk_defconfig b/configs/mx31pdk_defconfig
index 595a1be..c53c23a 100644
--- a/configs/mx31pdk_defconfig
+++ b/configs/mx31pdk_defconfig
@@ -5,9 +5,9 @@
 CONFIG_SPL_LDSCRIPT="arch/arm/cpu/u-boot-spl.lds"
 CONFIG_SYS_TEXT_BASE=0x87e00000
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_MX31PDK=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x40000
+CONFIG_TARGET_MX31PDK=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig
index a2af8ae..dbc4d85 100644
--- a/configs/mx51evk_defconfig
+++ b/configs/mx51evk_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX5=y
 CONFIG_SYS_TEXT_BASE=0x97800000
-CONFIG_TARGET_MX51EVK=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_TARGET_MX51EVK=y
 CONFIG_NR_DRAM_BANKS=1
 # CONFIG_CMD_BMODE is not set
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx51evk/imximage.cfg"
diff --git a/configs/mx53ard_defconfig b/configs/mx53ard_defconfig
index f0ecb4d..e021df2 100644
--- a/configs/mx53ard_defconfig
+++ b/configs/mx53ard_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX5=y
 CONFIG_SYS_TEXT_BASE=0x77800000
-CONFIG_TARGET_MX53ARD=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x60000
+CONFIG_TARGET_MX53ARD=y
 CONFIG_NR_DRAM_BANKS=2
 # CONFIG_CMD_BMODE is not set
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg"
diff --git a/configs/mx53cx9020_defconfig b/configs/mx53cx9020_defconfig
index 4e03532..5dc48c4 100644
--- a/configs/mx53cx9020_defconfig
+++ b/configs/mx53cx9020_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX5=y
 CONFIG_SYS_TEXT_BASE=0x77800000
-CONFIG_TARGET_MX53CX9020=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x60000
+CONFIG_TARGET_MX53CX9020=y
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=2
 # CONFIG_CMD_BMODE is not set
diff --git a/configs/mx53evk_defconfig b/configs/mx53evk_defconfig
index e520cba..9063f72 100644
--- a/configs/mx53evk_defconfig
+++ b/configs/mx53evk_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX5=y
 CONFIG_SYS_TEXT_BASE=0x77800000
-CONFIG_TARGET_MX53EVK=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x60000
+CONFIG_TARGET_MX53EVK=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53evk/imximage.cfg"
 CONFIG_HUSH_PARSER=y
diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig
index 277b528..e5d842a 100644
--- a/configs/mx53loco_defconfig
+++ b/configs/mx53loco_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX5=y
 CONFIG_SYS_TEXT_BASE=0x77800000
-CONFIG_TARGET_MX53LOCO=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_TARGET_MX53LOCO=y
 CONFIG_NR_DRAM_BANKS=2
 # CONFIG_CMD_BMODE is not set
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg"
diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig
index 29c9187..0b6564c 100644
--- a/configs/mx53ppd_defconfig
+++ b/configs/mx53ppd_defconfig
@@ -2,9 +2,9 @@
 CONFIG_ARCH_MX5=y
 CONFIG_SYS_TEXT_BASE=0x77800000
 CONFIG_SYS_MALLOC_F_LEN=0x4000
-CONFIG_TARGET_MX53PPD=y
 CONFIG_ENV_SIZE=0x2800
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_TARGET_MX53PPD=y
 CONFIG_DM_GPIO=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=10
 CONFIG_NR_DRAM_BANKS=2
diff --git a/configs/mx53smd_defconfig b/configs/mx53smd_defconfig
index 8cf6c80..fd13eea 100644
--- a/configs/mx53smd_defconfig
+++ b/configs/mx53smd_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX5=y
 CONFIG_SYS_TEXT_BASE=0x77800000
-CONFIG_TARGET_MX53SMD=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x60000
+CONFIG_TARGET_MX53SMD=y
 CONFIG_NR_DRAM_BANKS=2
 # CONFIG_CMD_BMODE is not set
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53smd/imximage.cfg"
diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig
index bee7d28..df7e461 100644
--- a/configs/mx6cuboxi_defconfig
+++ b/configs/mx6cuboxi_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_MX6CUBOXI=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFE000
+CONFIG_TARGET_MX6CUBOXI=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
@@ -15,8 +15,8 @@
 CONFIG_SPL_LIBDISK_SUPPORT=y
 # CONFIG_CMD_BMODE is not set
 CONFIG_CMD_HDMIDETECT=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
@@ -49,6 +49,7 @@
 CONFIG_DM_MMC=y
 CONFIG_FSL_USDHC=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
diff --git a/configs/mx6dlarm2_defconfig b/configs/mx6dlarm2_defconfig
index 4afd623..e826282 100644
--- a/configs/mx6dlarm2_defconfig
+++ b/configs/mx6dlarm2_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_MX6QARM2=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x60000
+CONFIG_TARGET_MX6QARM2=y
 CONFIG_NR_DRAM_BANKS=1
 # CONFIG_CMD_BMODE is not set
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,DDR_MB=2048"
diff --git a/configs/mx6dlarm2_lpddr2_defconfig b/configs/mx6dlarm2_lpddr2_defconfig
index bbb6948..fa87403 100644
--- a/configs/mx6dlarm2_lpddr2_defconfig
+++ b/configs/mx6dlarm2_lpddr2_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_MX6QARM2=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x60000
+CONFIG_TARGET_MX6QARM2=y
 CONFIG_NR_DRAM_BANKS=1
 # CONFIG_CMD_BMODE is not set
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,MX6DL_LPDDR2,DDR_MB=512"
diff --git a/configs/mx6memcal_defconfig b/configs/mx6memcal_defconfig
index 1b0158b..5063049 100644
--- a/configs/mx6memcal_defconfig
+++ b/configs/mx6memcal_defconfig
@@ -3,9 +3,9 @@
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
 CONFIG_MX6_DDRCAL=y
 CONFIG_TARGET_MX6MEMCAL=y
-CONFIG_ENV_SIZE=0x2000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
diff --git a/configs/mx6qarm2_defconfig b/configs/mx6qarm2_defconfig
index a26a8b0..93cf05b 100644
--- a/configs/mx6qarm2_defconfig
+++ b/configs/mx6qarm2_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_MX6QARM2=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x60000
+CONFIG_TARGET_MX6QARM2=y
 CONFIG_NR_DRAM_BANKS=1
 # CONFIG_CMD_BMODE is not set
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,DDR_MB=2048"
diff --git a/configs/mx6qarm2_lpddr2_defconfig b/configs/mx6qarm2_lpddr2_defconfig
index 169f19b..86f1224 100644
--- a/configs/mx6qarm2_lpddr2_defconfig
+++ b/configs/mx6qarm2_lpddr2_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_MX6QARM2=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x60000
+CONFIG_TARGET_MX6QARM2=y
 CONFIG_NR_DRAM_BANKS=1
 # CONFIG_CMD_BMODE is not set
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,MX6DQ_LPDDR2,DDR_MB=512"
diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig
index a85bfe0..510b8d7 100644
--- a/configs/mx6qsabrelite_defconfig
+++ b/configs/mx6qsabrelite_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_NITROGEN6X=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x60000
+CONFIG_TARGET_NITROGEN6X=y
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_CMD_HDMIDETECT=y
diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index 06835f2..5304050 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig
@@ -5,9 +5,9 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x4000
-CONFIG_TARGET_MX6SABREAUTO=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_TARGET_MX6SABREAUTO=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
@@ -74,6 +74,11 @@
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
@@ -97,8 +102,3 @@
 # CONFIG_VIDEO_BPP32 is not set
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_IPUV3=y
-CONFIG_FEC_MXC=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_DM_ETH=y
-CONFIG_DM_MDIO=y
-CONFIG_RGMII=y
diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index f218408..2a517cc 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -5,9 +5,9 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x4000
-CONFIG_TARGET_MX6SABRESD=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_TARGET_MX6SABRESD=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig
index 163cb1a..3436076 100644
--- a/configs/mx6slevk_defconfig
+++ b/configs/mx6slevk_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
-CONFIG_TARGET_MX6SLEVK=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x80000
+CONFIG_TARGET_MX6SLEVK=y
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 # CONFIG_CMD_BMODE is not set
@@ -43,6 +43,9 @@
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_SMSC=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
@@ -61,6 +64,3 @@
 CONFIG_USB_STORAGE=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
-CONFIG_DM_ETH=y
-CONFIG_FEC_MXC=y
-CONFIG_PHY_SMSC=y
diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig
index 7d46eec..4d348df 100644
--- a/configs/mx6slevk_spinor_defconfig
+++ b/configs/mx6slevk_spinor_defconfig
@@ -1,10 +1,10 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
-CONFIG_TARGET_MX6SLEVK=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_TARGET_MX6SLEVK=y
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 # CONFIG_CMD_BMODE is not set
diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig
index c5be957..3a0ae92 100644
--- a/configs/mx6slevk_spl_defconfig
+++ b/configs/mx6slevk_spl_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_MX6SLEVK=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x80000
+CONFIG_TARGET_MX6SLEVK=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
diff --git a/configs/mx6sllevk_defconfig b/configs/mx6sllevk_defconfig
index 537dd3d..064684a 100644
--- a/configs/mx6sllevk_defconfig
+++ b/configs/mx6sllevk_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
-CONFIG_TARGET_MX6SLLEVK=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_TARGET_MX6SLLEVK=y
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 # CONFIG_CMD_BMODE is not set
diff --git a/configs/mx6sllevk_plugin_defconfig b/configs/mx6sllevk_plugin_defconfig
index 36f73f7..ae06ad4 100644
--- a/configs/mx6sllevk_plugin_defconfig
+++ b/configs/mx6sllevk_plugin_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
-CONFIG_TARGET_MX6SLLEVK=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_TARGET_MX6SLLEVK=y
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_USE_IMXIMG_PLUGIN=y
diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig
index 2c5f519..be20be2 100644
--- a/configs/mx6sxsabreauto_defconfig
+++ b/configs/mx6sxsabreauto_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
-CONFIG_TARGET_MX6SXSABREAUTO=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x80000
+CONFIG_TARGET_MX6SXSABREAUTO=y
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 # CONFIG_CMD_BMODE is not set
@@ -45,6 +45,7 @@
 CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig
index 7cf6729..745a8be 100644
--- a/configs/mx6sxsabresd_defconfig
+++ b/configs/mx6sxsabresd_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
-CONFIG_TARGET_MX6SXSABRESD=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xE0000
+CONFIG_TARGET_MX6SXSABRESD=y
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 # CONFIG_CMD_BMODE is not set
@@ -49,6 +49,7 @@
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
 CONFIG_MII=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
index 2a7f5fd..6498f02 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_MX6UL_14X14_EVK=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x80000
+CONFIG_TARGET_MX6UL_14X14_EVK=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
@@ -56,8 +56,8 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ8XXX=y
-CONFIG_FEC_MXC=y
 CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig
index c02f71f..ce87cc1 100644
--- a/configs/mx6ul_9x9_evk_defconfig
+++ b/configs/mx6ul_9x9_evk_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_MX6UL_9X9_EVK=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x80000
+CONFIG_TARGET_MX6UL_9X9_EVK=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig
index c16ecfa..357932a 100644
--- a/configs/mx6ull_14x14_evk_defconfig
+++ b/configs/mx6ull_14x14_evk_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
-CONFIG_TARGET_MX6ULL_14X14_EVK=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_TARGET_MX6ULL_14X14_EVK=y
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg"
@@ -41,8 +41,8 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ8XXX=y
-CONFIG_FEC_MXC=y
 CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig
index ddfc476..a5451fc 100644
--- a/configs/mx6ull_14x14_evk_plugin_defconfig
+++ b/configs/mx6ull_14x14_evk_plugin_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
-CONFIG_TARGET_MX6ULL_14X14_EVK=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_TARGET_MX6ULL_14X14_EVK=y
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_USE_IMXIMG_PLUGIN=y
diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig
index 92d73a8..ae81e10 100644
--- a/configs/mx6ulz_14x14_evk_defconfig
+++ b/configs/mx6ulz_14x14_evk_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
-CONFIG_TARGET_MX6ULL_14X14_EVK=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_TARGET_MX6ULL_14X14_EVK=y
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg"
@@ -16,8 +16,6 @@
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig
index 607a00d..ae86590 100644
--- a/configs/nanopc-t4-rk3399_defconfig
+++ b/configs/nanopc-t4-rk3399_defconfig
@@ -46,18 +46,16 @@
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_KEYBOARD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_ASIX88179=y
 CONFIG_USB_ETHER_MCS7830=y
 CONFIG_USB_ETHER_RTL8152=y
 CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_SPL_TINY_MEMSET=y
-CONFIG_ERRNO_STR=y
 CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_BPP16=y
-CONFIG_VIDEO_BPP32=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
 CONFIG_DISPLAY_ROCKCHIP_HDMI=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig
index 3fcb7ac..ab7c2d1 100644
--- a/configs/nanopi-m4-rk3399_defconfig
+++ b/configs/nanopi-m4-rk3399_defconfig
@@ -46,18 +46,16 @@
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_KEYBOARD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_ASIX88179=y
 CONFIG_USB_ETHER_MCS7830=y
 CONFIG_USB_ETHER_RTL8152=y
 CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_SPL_TINY_MEMSET=y
-CONFIG_ERRNO_STR=y
 CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_BPP16=y
-CONFIG_VIDEO_BPP32=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
 CONFIG_DISPLAY_ROCKCHIP_HDMI=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig
index b9ea535..45cd56f 100644
--- a/configs/nanopi-neo4-rk3399_defconfig
+++ b/configs/nanopi-neo4-rk3399_defconfig
@@ -46,18 +46,16 @@
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_KEYBOARD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_ASIX88179=y
 CONFIG_USB_ETHER_MCS7830=y
 CONFIG_USB_ETHER_RTL8152=y
 CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_SPL_TINY_MEMSET=y
-CONFIG_ERRNO_STR=y
 CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_BPP16=y
-CONFIG_VIDEO_BPP32=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
 CONFIG_DISPLAY_ROCKCHIP_HDMI=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig
index d334db0..b7565e5 100644
--- a/configs/net2big_v2_defconfig
+++ b/configs/net2big_v2_defconfig
@@ -5,8 +5,8 @@
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_TARGET_NET2BIG_V2=y
 CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x70000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_IDENT_STRING=" 2Big v2"
 CONFIG_SYS_EXTRA_OPTIONS="NET2BIG_V2"
diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig
index cb00d48..3f95f38 100644
--- a/configs/netspace_lite_v2_defconfig
+++ b/configs/netspace_lite_v2_defconfig
@@ -5,8 +5,8 @@
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_TARGET_NETSPACE_V2=y
 CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x70000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_IDENT_STRING=" NS v2 Lite"
 CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2"
diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig
index 0317cb9..1d71039 100644
--- a/configs/netspace_max_v2_defconfig
+++ b/configs/netspace_max_v2_defconfig
@@ -5,8 +5,8 @@
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_TARGET_NETSPACE_V2=y
 CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x70000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_IDENT_STRING=" NS Max v2"
 CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2"
diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig
index a87aadd..abf8011 100644
--- a/configs/netspace_mini_v2_defconfig
+++ b/configs/netspace_mini_v2_defconfig
@@ -5,8 +5,8 @@
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_TARGET_NETSPACE_V2=y
 CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x70000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_IDENT_STRING=" NS v2 Mini"
 CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2"
diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig
index e4e08a2..052049a 100644
--- a/configs/netspace_v2_defconfig
+++ b/configs/netspace_v2_defconfig
@@ -5,8 +5,8 @@
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_TARGET_NETSPACE_V2=y
 CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x70000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_IDENT_STRING=" NS v2"
 CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2"
diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig
index d101625..57d7ca9 100644
--- a/configs/nitrogen6dl2g_defconfig
+++ b/configs/nitrogen6dl2g_defconfig
@@ -1,10 +1,10 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_NITROGEN6X=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x2000
+CONFIG_TARGET_NITROGEN6X=y
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_CMD_HDMIDETECT=y
diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig
index dd07ce0..b0f28c5 100644
--- a/configs/nitrogen6dl_defconfig
+++ b/configs/nitrogen6dl_defconfig
@@ -1,10 +1,10 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_NITROGEN6X=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x2000
+CONFIG_TARGET_NITROGEN6X=y
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_CMD_HDMIDETECT=y
diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig
index 91b85ea..02632dc 100644
--- a/configs/nitrogen6q2g_defconfig
+++ b/configs/nitrogen6q2g_defconfig
@@ -1,10 +1,10 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_NITROGEN6X=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x2000
+CONFIG_TARGET_NITROGEN6X=y
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_CMD_HDMIDETECT=y
diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig
index 009382f..8e04199 100644
--- a/configs/nitrogen6q_defconfig
+++ b/configs/nitrogen6q_defconfig
@@ -1,10 +1,10 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_NITROGEN6X=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x2000
+CONFIG_TARGET_NITROGEN6X=y
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_CMD_HDMIDETECT=y
diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig
index c0f4261..592fb4a 100644
--- a/configs/nitrogen6s1g_defconfig
+++ b/configs/nitrogen6s1g_defconfig
@@ -1,10 +1,10 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_NITROGEN6X=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x2000
+CONFIG_TARGET_NITROGEN6X=y
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_CMD_HDMIDETECT=y
diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig
index 1dc9d53..3a4572a 100644
--- a/configs/nitrogen6s_defconfig
+++ b/configs/nitrogen6s_defconfig
@@ -1,10 +1,10 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_NITROGEN6X=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x2000
+CONFIG_TARGET_NITROGEN6X=y
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_CMD_HDMIDETECT=y
diff --git a/configs/novena_defconfig b/configs/novena_defconfig
index 87adc1e..27bc0fa 100644
--- a/configs/novena_defconfig
+++ b/configs/novena_defconfig
@@ -4,10 +4,10 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_MX6_DDRCAL=y
-CONFIG_TARGET_KOSAGI_NOVENA=y
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x80000
+CONFIG_MX6_DDRCAL=y
+CONFIG_TARGET_KOSAGI_NOVENA=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
@@ -16,8 +16,8 @@
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_CMD_HDMIDETECT=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index 8c08ee6..2b1bcb8 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -9,8 +9,8 @@
 CONFIG_DEBUG_UART_CLOCK=408000000
 CONFIG_TEGRA124=y
 CONFIG_TARGET_NYAN_BIG=y
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x80108000
+CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_BEST_MATCH=y
 CONFIG_OF_SYSTEM_SETUP=y
diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig
index cb4e847..3ac6319 100644
--- a/configs/omap4_panda_defconfig
+++ b/configs/omap4_panda_defconfig
@@ -24,7 +24,6 @@
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_ENV_IS_IN_FAT=y
-CONFIG_ENV_FAT_INTERFACE="mmc"
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig
index 8dee24c..632ca1c 100644
--- a/configs/opos6uldev_defconfig
+++ b/configs/opos6uldev_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_OPOS6ULDEV=y
 CONFIG_ENV_SIZE=0x2800
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_TARGET_OPOS6ULDEV=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/ot1200_defconfig b/configs/ot1200_defconfig
index 2b4ecb6..45b9f2d 100644
--- a/configs/ot1200_defconfig
+++ b/configs/ot1200_defconfig
@@ -1,10 +1,10 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_OT1200=y
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_TARGET_OT1200=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/bachmann/ot1200/mx6q_4x_mt41j128.cfg,MX6Q"
 CONFIG_BOOTDELAY=3
@@ -45,6 +45,7 @@
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_SMSC=y
 CONFIG_MII=y
 CONFIG_SPI=y
 CONFIG_MXC_SPI=y
diff --git a/configs/ot1200_spl_defconfig b/configs/ot1200_spl_defconfig
index 0c4d9d9..9472d29 100644
--- a/configs/ot1200_spl_defconfig
+++ b/configs/ot1200_spl_defconfig
@@ -4,10 +4,11 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_OT1200=y
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
+CONFIG_TARGET_OT1200=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
@@ -23,7 +24,6 @@
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
@@ -56,6 +56,7 @@
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_SMSC=y
 CONFIG_MII=y
 CONFIG_SPI=y
 CONFIG_MXC_SPI=y
diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig
index 7081719..3c183df 100644
--- a/configs/p2371-0000_defconfig
+++ b/configs/p2371-0000_defconfig
@@ -19,6 +19,7 @@
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_PREFER_SERVERIP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2371-0000"
@@ -44,4 +45,3 @@
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
-CONFIG_BOOTP_PREFER_SERVERIP=y
diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig
index c70217c..3aa6f57 100644
--- a/configs/p2371-2180_defconfig
+++ b/configs/p2371-2180_defconfig
@@ -21,6 +21,7 @@
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_PREFER_SERVERIP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_OF_LIVE=y
@@ -52,4 +53,3 @@
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
-CONFIG_BOOTP_PREFER_SERVERIP=y
diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig
index 43c24b8..37685ea 100644
--- a/configs/p2571_defconfig
+++ b/configs/p2571_defconfig
@@ -19,6 +19,7 @@
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_PREFER_SERVERIP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2571"
@@ -44,4 +45,3 @@
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
-CONFIG_BOOTP_PREFER_SERVERIP=y
diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig
index 8bf8419..e3d42a2 100644
--- a/configs/p2771-0000-000_defconfig
+++ b/configs/p2771-0000-000_defconfig
@@ -18,6 +18,7 @@
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_PREFER_SERVERIP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000-000"
@@ -36,5 +37,3 @@
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
-CONFIG_POSITION_INDEPENDENT=y
-CONFIG_BOOTP_PREFER_SERVERIP=y
diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig
index 1f40333..51715d0 100644
--- a/configs/p2771-0000-500_defconfig
+++ b/configs/p2771-0000-500_defconfig
@@ -18,6 +18,7 @@
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_PREFER_SERVERIP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000-500"
@@ -36,5 +37,3 @@
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
-CONFIG_POSITION_INDEPENDENT=y
-CONFIG_BOOTP_PREFER_SERVERIP=y
diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig
index f78e1d3..c12d58a 100644
--- a/configs/p3450-0000_defconfig
+++ b/configs/p3450-0000_defconfig
@@ -1,39 +1,41 @@
 CONFIG_ARM=y
 CONFIG_TEGRA=y
 CONFIG_SYS_TEXT_BASE=0x80080000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xFFFFE000
+CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_NR_DRAM_BANKS=2
 CONFIG_TEGRA210=y
 CONFIG_TARGET_P3450_0000=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_CONSOLE_MUX=y
 CONFIG_SYS_STDIO_DEREGISTER=y
 CONFIG_SYS_PROMPT="Tegra210 (P3450-0000) # "
 # CONFIG_CMD_IMI is not set
 CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_PREFER_SERVERIP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_OF_LIVE=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra210-p3450-0000"
+# CONFIG_ENV_IS_IN_MMC is not set
+CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_DFU_SF=y
 CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_USE_4K_SECTORS=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=24000000
+CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_RTL8169=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
@@ -54,11 +56,3 @@
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
-# CONFIG_ENV_IS_IN_MMC is not set
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x1000
-CONFIG_ENV_OFFSET=0xFFFFE000
-CONFIG_BOOTP_PREFER_SERVERIP=y
-CONFIG_POSITION_INDEPENDENT=y
-CONFIG_DISABLE_SDMMC1_EARLY=y
diff --git a/configs/parrot_r16_defconfig b/configs/parrot_r16_defconfig
index 2c2edbc..4c9b248 100644
--- a/configs/parrot_r16_defconfig
+++ b/configs/parrot_r16_defconfig
@@ -11,7 +11,6 @@
 CONFIG_USB1_VBUS_PIN="PD12"
 CONFIG_AXP_GPIO=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-# CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-parrot"
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_CONS_INDEX=5
diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig
index cbe6594..ea7a076 100644
--- a/configs/pcm051_rev1_defconfig
+++ b/configs/pcm051_rev1_defconfig
@@ -45,6 +45,7 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_SMSC=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
 CONFIG_SPI=y
diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig
index 744c582..43e6463 100644
--- a/configs/pcm051_rev3_defconfig
+++ b/configs/pcm051_rev3_defconfig
@@ -45,6 +45,7 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_SMSC=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
 CONFIG_SPI=y
diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig
index 87cac5c..0dfbc17 100644
--- a/configs/pcm058_defconfig
+++ b/configs/pcm058_defconfig
@@ -4,10 +4,11 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_PCM058=y
 CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
+CONFIG_TARGET_PCM058=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
@@ -30,7 +31,6 @@
 CONFIG_SPL_FS_EXT4=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig
index 6efca9b..b0128a6 100644
--- a/configs/peach-pi_defconfig
+++ b/configs/peach-pi_defconfig
@@ -5,8 +5,8 @@
 CONFIG_ARCH_EXYNOS5=y
 CONFIG_TARGET_PEACH_PI=y
 CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_SECT_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x3FC000
+CONFIG_ENV_SECT_SIZE=0x4000
 CONFIG_NR_DRAM_BANKS=7
 CONFIG_SPL=y
 CONFIG_IDENT_STRING=" for Peach-Pi"
diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig
index 216ec90..ea4155d 100644
--- a/configs/peach-pit_defconfig
+++ b/configs/peach-pit_defconfig
@@ -5,8 +5,8 @@
 CONFIG_ARCH_EXYNOS5=y
 CONFIG_TARGET_PEACH_PIT=y
 CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_SECT_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x3FC000
+CONFIG_ENV_SECT_SIZE=0x4000
 CONFIG_SPL=y
 CONFIG_IDENT_STRING=" for Peach-Pit"
 CONFIG_SPL_TEXT_BASE=0x02024410
diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig
index eadab3e..3d0fcf3 100644
--- a/configs/pengwyn_defconfig
+++ b/configs/pengwyn_defconfig
@@ -52,6 +52,8 @@
 CONFIG_MMC_OMAP_HS=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
 CONFIG_SPI=y
diff --git a/configs/pfla02_defconfig b/configs/pfla02_defconfig
index 50fcbb3..5e5bbb0 100644
--- a/configs/pfla02_defconfig
+++ b/configs/pfla02_defconfig
@@ -4,10 +4,11 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_PFLA02=y
 CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
+CONFIG_TARGET_PFLA02=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
@@ -30,7 +31,6 @@
 CONFIG_SPL_FS_EXT4=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/phycore-am335x-r2-wega_defconfig b/configs/phycore-am335x-r2-wega_defconfig
index ef19bb6..864e2ff 100644
--- a/configs/phycore-am335x-r2-wega_defconfig
+++ b/configs/phycore-am335x-r2-wega_defconfig
@@ -13,6 +13,7 @@
 CONFIG_SPL=y
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_PAYLOAD="u-boot.img"
 # CONFIG_FIT is not set
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
@@ -22,7 +23,6 @@
 CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_PAYLOAD="u-boot.img"
 CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
@@ -49,7 +49,6 @@
 CONFIG_DEFAULT_DEVICE_TREE="am335x-wega-rdk"
 CONFIG_ENV_IS_IN_FAT=y
 CONFIG_ENV_IS_IN_NAND=y
-CONFIG_ENV_FAT_INTERFACE="mmc"
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig
index 8c1bd20..51b3e41 100644
--- a/configs/phycore-rk3288_defconfig
+++ b/configs/phycore-rk3288_defconfig
@@ -9,8 +9,8 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BASE=0xff690000
 CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0xff704000
+CONFIG_DEBUG_UART=y
 # CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_USE_PREBOOT=y
 CONFIG_SILENT_CONSOLE=y
diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig
index 8d7d4b9..760f62a 100644
--- a/configs/phycore_pcl063_defconfig
+++ b/configs/phycore_pcl063_defconfig
@@ -3,8 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_PCL063=y
 CONFIG_ENV_SIZE=0x4000
+CONFIG_TARGET_PCL063=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=8
diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig
index 8b50d26..cb9e4e3 100644
--- a/configs/phycore_pcl063_ull_defconfig
+++ b/configs/phycore_pcl063_ull_defconfig
@@ -3,8 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_PCL063_ULL=y
 CONFIG_ENV_SIZE=0x4000
+CONFIG_TARGET_PCL063_ULL=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=8
diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
index f98e6a2..bb09a9a 100644
--- a/configs/pic32mzdask_defconfig
+++ b/configs/pic32mzdask_defconfig
@@ -31,6 +31,7 @@
 CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PIC32=y
+CONFIG_PHY_SMSC=y
 CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_PIC32_ETH=y
diff --git a/configs/pico-dwarf-imx6ul_defconfig b/configs/pico-dwarf-imx6ul_defconfig
index f914418..bb02813 100644
--- a/configs/pico-dwarf-imx6ul_defconfig
+++ b/configs/pico-dwarf-imx6ul_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_PICO_IMX6UL=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_TARGET_PICO_IMX6UL=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
diff --git a/configs/pico-hobbit-imx6ul_defconfig b/configs/pico-hobbit-imx6ul_defconfig
index d18341f..ffa5cc8 100644
--- a/configs/pico-hobbit-imx6ul_defconfig
+++ b/configs/pico-hobbit-imx6ul_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_PICO_IMX6UL=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_TARGET_PICO_IMX6UL=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
diff --git a/configs/pico-imx6_defconfig b/configs/pico-imx6_defconfig
index fe73ac5..0bc7e4f 100644
--- a/configs/pico-imx6_defconfig
+++ b/configs/pico-imx6_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_PICO_IMX6=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_TARGET_PICO_IMX6=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
@@ -39,6 +39,7 @@
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_SDP=y
 CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_MDIO is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_SPL_DOS_PARTITION is not set
@@ -61,6 +62,8 @@
 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
 CONFIG_DM_MMC=y
 CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_USB=y
diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig
index 3fd1012..24948ddd 100644
--- a/configs/pico-imx6ul_defconfig
+++ b/configs/pico-imx6ul_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_PICO_IMX6UL=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_TARGET_PICO_IMX6UL=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
diff --git a/configs/pico-pi-imx6ul_defconfig b/configs/pico-pi-imx6ul_defconfig
index 951d9d3..5eb6fe2 100644
--- a/configs/pico-pi-imx6ul_defconfig
+++ b/configs/pico-pi-imx6ul_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_PICO_IMX6UL=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_TARGET_PICO_IMX6UL=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig
index cb5e624..8937c51 100644
--- a/configs/pine_h64_defconfig
+++ b/configs/pine_h64_defconfig
@@ -6,9 +6,9 @@
 CONFIG_MMC0_CD_PIN="PF6"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 CONFIG_USB3_VBUS_PIN="PL5"
+CONFIG_SPL_SPI_SUNXI=y
 # CONFIG_PSCI_RESET is not set
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-pine-h64"
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
-CONFIG_SPL_SPI_SUNXI=y
diff --git a/configs/platinum_picon_defconfig b/configs/platinum_picon_defconfig
index 216dad8..1164669 100644
--- a/configs/platinum_picon_defconfig
+++ b/configs/platinum_picon_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_PLATINUM_PICON=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x1000000
+CONFIG_TARGET_PLATINUM_PICON=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/platinum_titanium_defconfig b/configs/platinum_titanium_defconfig
index a01641f..cecfa89 100644
--- a/configs/platinum_titanium_defconfig
+++ b/configs/platinum_titanium_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_PLATINUM_TITANIUM=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x1000000
+CONFIG_TARGET_PLATINUM_TITANIUM=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig
index 01d3603..36d767d 100644
--- a/configs/popmetal-rk3288_defconfig
+++ b/configs/popmetal-rk3288_defconfig
@@ -9,8 +9,8 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BASE=0xff690000
 CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0xff704000
+CONFIG_DEBUG_UART=y
 # CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_USE_PREBOOT=y
 CONFIG_SILENT_CONSOLE=y
diff --git a/configs/porter_defconfig b/configs/porter_defconfig
index 1bb11c9..0cb9036 100644
--- a/configs/porter_defconfig
+++ b/configs/porter_defconfig
@@ -9,8 +9,9 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
 CONFIG_DM_GPIO=y
 CONFIG_ARCH_RMOBILE_BOARD_STRING="Porter"
 CONFIG_R8A7791=y
@@ -30,7 +31,6 @@
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
@@ -71,6 +71,7 @@
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_MTD=y
+CONFIG_BITBANGMII=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ8XXX=y
 CONFIG_DM_ETH=y
diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig
index d4cf845..a148832 100644
--- a/configs/puma-rk3399_defconfig
+++ b/configs/puma-rk3399_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_TEXT_BASE=0x00200000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_ROCKCHIP_RK3399=y
 CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0
 CONFIG_TARGET_PUMA_RK3399=y
@@ -11,8 +12,8 @@
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0xff8c2000
+CONFIG_DEBUG_UART=y
 CONFIG_SPL_FIT_GENERATOR="board/theobroma-systems/puma_rk3399/fit_spl_atf.sh"
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb"
 CONFIG_MISC_INIT_R=y
@@ -24,7 +25,6 @@
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index 7253341..67de086 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -6,6 +6,7 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_AM33XX=y
 CONFIG_SYS_MPUCLK=720
 CONFIG_TARGET_PXM2=y
@@ -28,7 +29,6 @@
 CONFIG_ARCH_MISC_INIT=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
@@ -73,6 +73,7 @@
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_MTD_UBI_FASTMAP=y
 CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
+CONFIG_PHY_ATHEROS=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
 CONFIG_SPI=y
diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig
index a37ec4d..0cb123e 100644
--- a/configs/qemu-x86_64_defconfig
+++ b/configs/qemu-x86_64_defconfig
@@ -1,11 +1,12 @@
 CONFIG_X86=y
 CONFIG_SYS_TEXT_BASE=0x1110000
 CONFIG_SYS_MALLOC_F_LEN=0x1000
-CONFIG_MAX_CPUS=2
 CONFIG_ENV_SIZE=0x40000
+CONFIG_MAX_CPUS=2
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_SPL_TEXT_BASE=0xfffd0000
 CONFIG_X86_RUN_64BIT=y
 CONFIG_TARGET_QEMU_X86_64=y
 CONFIG_DEBUG_UART=y
@@ -14,7 +15,6 @@
 CONFIG_GENERATE_MP_TABLE=y
 CONFIG_GENERATE_ACPI_TABLE=y
 CONFIG_X86_OFFSET_U_BOOT=0xfff00000
-CONFIG_SPL_TEXT_BASE=0xfffd0000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BUILD_ROM=y
 CONFIG_FIT=y
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index 4a4792d..a562f21 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -1,7 +1,7 @@
 CONFIG_X86=y
 CONFIG_SYS_TEXT_BASE=0xFFF00000
-CONFIG_MAX_CPUS=2
 CONFIG_ENV_SIZE=0x40000
+CONFIG_MAX_CPUS=2
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_SMP=y
 CONFIG_GENERATE_PIRQ_TABLE=y
diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig
index 084b4c1..80e0ad5 100644
--- a/configs/qemu_arm64_defconfig
+++ b/configs/qemu_arm64_defconfig
@@ -2,7 +2,6 @@
 CONFIG_ARCH_QEMU=y
 CONFIG_ENV_SIZE=0x40000
 CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_TARGET_QEMU_ARM_64BIT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/r8a7795_ulcb_defconfig b/configs/r8a7795_ulcb_defconfig
deleted file mode 100644
index c1979f4..0000000
--- a/configs/r8a7795_ulcb_defconfig
+++ /dev/null
@@ -1,68 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_ARCH_RMOBILE=y
-CONFIG_SYS_TEXT_BASE=0x50000000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0xFFFE0000
-CONFIG_DM_GPIO=y
-CONFIG_RCAR_GEN3=y
-CONFIG_TARGET_ULCB=y
-CONFIG_SMBIOS_PRODUCT_NAME=""
-CONFIG_SPL_TEXT_BASE=0xe6338000
-CONFIG_FIT=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_DEFAULT_FDT_FILE="r8a7795-h3ulcb.dtb"
-CONFIG_VERSION_VARIABLE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="r8a7795-h3ulcb-u-boot"
-CONFIG_OF_LIST="r8a7795-h3ulcb-u-boot r8a7796-m3ulcb-u-boot r8a77965-m3nulcb-u-boot"
-CONFIG_MULTI_DTB_FIT_LZO=y
-CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_CLK=y
-CONFIG_CLK_RENESAS=y
-CONFIG_RCAR_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_RCAR_IIC=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_RENESAS_SDHI=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_DM_ETH=y
-CONFIG_RENESAS_RAVB=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SYSRESET=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_SMBIOS_MANUFACTURER=""
diff --git a/configs/r8a77965_salvator-x_defconfig b/configs/r8a77965_salvator-x_defconfig
deleted file mode 100644
index 8da542c..0000000
--- a/configs/r8a77965_salvator-x_defconfig
+++ /dev/null
@@ -1,71 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_ARCH_RMOBILE=y
-CONFIG_SYS_TEXT_BASE=0x50000000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0xFFFE0000
-CONFIG_DM_GPIO=y
-CONFIG_RCAR_GEN3=y
-CONFIG_TARGET_SALVATOR_X=y
-CONFIG_SMBIOS_PRODUCT_NAME=""
-CONFIG_SPL_TEXT_BASE=0xe6338000
-CONFIG_FIT=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_DEFAULT_FDT_FILE="r8a77965-salvator-x.dtb"
-CONFIG_VERSION_VARIABLE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="r8a77965-salvator-x-u-boot"
-CONFIG_OF_LIST="r8a7795-salvator-x-u-boot r8a7796-salvator-x-u-boot r8a77965-salvator-x-u-boot"
-CONFIG_MULTI_DTB_FIT_LZO=y
-CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_CLK=y
-CONFIG_CLK_RENESAS=y
-CONFIG_RCAR_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_RCAR_IIC=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_RENESAS_SDHI=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_DM_ETH=y
-CONFIG_RENESAS_RAVB=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_PCI_RCAR_GEN3=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_SMBIOS_MANUFACTURER=""
diff --git a/configs/r8a77965_ulcb_defconfig b/configs/r8a77965_ulcb_defconfig
deleted file mode 100644
index 117939b..0000000
--- a/configs/r8a77965_ulcb_defconfig
+++ /dev/null
@@ -1,68 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_ARCH_RMOBILE=y
-CONFIG_SYS_TEXT_BASE=0x50000000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0xFFFE0000
-CONFIG_DM_GPIO=y
-CONFIG_RCAR_GEN3=y
-CONFIG_TARGET_ULCB=y
-CONFIG_SMBIOS_PRODUCT_NAME=""
-CONFIG_SPL_TEXT_BASE=0xe6338000
-CONFIG_FIT=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_DEFAULT_FDT_FILE="r8a77965-m3nulcb.dtb"
-CONFIG_VERSION_VARIABLE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="r8a77965-m3nulcb-u-boot"
-CONFIG_OF_LIST="r8a7795-h3ulcb-u-boot r8a7796-m3ulcb-u-boot r8a77965-m3nulcb-u-boot"
-CONFIG_MULTI_DTB_FIT_LZO=y
-CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_CLK=y
-CONFIG_CLK_RENESAS=y
-CONFIG_RCAR_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_RCAR_IIC=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_RENESAS_SDHI=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_DM_ETH=y
-CONFIG_RENESAS_RAVB=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SYSRESET=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_SMBIOS_MANUFACTURER=""
diff --git a/configs/r8a7796_salvator-x_defconfig b/configs/r8a7796_salvator-x_defconfig
deleted file mode 100644
index 86d666f..0000000
--- a/configs/r8a7796_salvator-x_defconfig
+++ /dev/null
@@ -1,71 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_ARCH_RMOBILE=y
-CONFIG_SYS_TEXT_BASE=0x50000000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0xFFFE0000
-CONFIG_DM_GPIO=y
-CONFIG_RCAR_GEN3=y
-CONFIG_TARGET_SALVATOR_X=y
-CONFIG_SMBIOS_PRODUCT_NAME=""
-CONFIG_SPL_TEXT_BASE=0xe6338000
-CONFIG_FIT=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_DEFAULT_FDT_FILE="r8a7796-salvator-x.dtb"
-CONFIG_VERSION_VARIABLE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="r8a7796-salvator-x-u-boot"
-CONFIG_OF_LIST="r8a7795-salvator-x-u-boot r8a7796-salvator-x-u-boot r8a77965-salvator-x-u-boot"
-CONFIG_MULTI_DTB_FIT_LZO=y
-CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_CLK=y
-CONFIG_CLK_RENESAS=y
-CONFIG_RCAR_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_RCAR_IIC=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_RENESAS_SDHI=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_DM_ETH=y
-CONFIG_RENESAS_RAVB=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_PCI_RCAR_GEN3=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_SMBIOS_MANUFACTURER=""
diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig
index 2658ae8..78bfb9a 100644
--- a/configs/r8a77970_eagle_defconfig
+++ b/configs/r8a77970_eagle_defconfig
@@ -4,13 +4,13 @@
 CONFIG_SYS_TEXT_BASE=0x50000000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x700000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_RCAR_GEN3=y
 CONFIG_TARGET_EAGLE=y
-CONFIG_SMBIOS_PRODUCT_NAME=""
 CONFIG_SPL_TEXT_BASE=0xe6318000
+CONFIG_SMBIOS_PRODUCT_NAME=""
 CONFIG_FIT=y
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
@@ -48,6 +48,7 @@
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_BITBANGMII=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
diff --git a/configs/r8a77980_condor_defconfig b/configs/r8a77980_condor_defconfig
index bf2e65a..83d6a75 100644
--- a/configs/r8a77980_condor_defconfig
+++ b/configs/r8a77980_condor_defconfig
@@ -4,13 +4,13 @@
 CONFIG_SYS_TEXT_BASE=0x50000000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x700000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_RCAR_GEN3=y
 CONFIG_TARGET_CONDOR=y
-CONFIG_SMBIOS_PRODUCT_NAME=""
 CONFIG_SPL_TEXT_BASE=0xe6318000
+CONFIG_SMBIOS_PRODUCT_NAME=""
 CONFIG_FIT=y
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
@@ -52,6 +52,7 @@
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_BITBANGMII=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig
index 621849f..cc9257b 100644
--- a/configs/r8a77990_ebisu_defconfig
+++ b/configs/r8a77990_ebisu_defconfig
@@ -8,8 +8,8 @@
 CONFIG_DM_GPIO=y
 CONFIG_RCAR_GEN3=y
 CONFIG_TARGET_EBISU=y
-CONFIG_SMBIOS_PRODUCT_NAME=""
 CONFIG_SPL_TEXT_BASE=0xe6318000
+CONFIG_SMBIOS_PRODUCT_NAME=""
 CONFIG_FIT=y
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
@@ -46,6 +46,7 @@
 CONFIG_MMC_UHS_SUPPORT=y
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_RENESAS_SDHI=y
+CONFIG_BITBANGMII=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig
index fbbef30..89b0f15 100644
--- a/configs/r8a77995_draak_defconfig
+++ b/configs/r8a77995_draak_defconfig
@@ -8,8 +8,8 @@
 CONFIG_DM_GPIO=y
 CONFIG_RCAR_GEN3=y
 CONFIG_TARGET_DRAAK=y
-CONFIG_SMBIOS_PRODUCT_NAME=""
 CONFIG_SPL_TEXT_BASE=0xe6318000
+CONFIG_SMBIOS_PRODUCT_NAME=""
 CONFIG_FIT=y
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
@@ -54,6 +54,7 @@
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_RENESAS_RPC_HF=y
+CONFIG_BITBANGMII=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig
index 905e53b..c4a4e13 100644
--- a/configs/rastaban_defconfig
+++ b/configs/rastaban_defconfig
@@ -6,6 +6,7 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_AM33XX=y
 CONFIG_SYS_MPUCLK=300
 CONFIG_TARGET_RASTABAN=y
@@ -27,7 +28,6 @@
 CONFIG_ARCH_MISC_INIT=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 # CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
@@ -73,6 +73,7 @@
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_MTD_UBI_FASTMAP=y
 CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
+CONFIG_PHY_SMSC=y
 CONFIG_DRIVER_TI_CPSW=y
 CONFIG_SPI=y
 CONFIG_OMAP3_SPI=y
diff --git a/configs/r8a7795_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig
similarity index 87%
rename from configs/r8a7795_salvator-x_defconfig
rename to configs/rcar3_salvator-x_defconfig
index 328d8b1..3031fdd 100644
--- a/configs/r8a7795_salvator-x_defconfig
+++ b/configs/rcar3_salvator-x_defconfig
@@ -7,13 +7,13 @@
 CONFIG_DM_GPIO=y
 CONFIG_RCAR_GEN3=y
 CONFIG_TARGET_SALVATOR_X=y
-CONFIG_SMBIOS_PRODUCT_NAME=""
 CONFIG_SPL_TEXT_BASE=0xe6338000
+CONFIG_SMBIOS_PRODUCT_NAME=""
 CONFIG_FIT=y
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
 CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_DEFAULT_FDT_FILE="r8a7795-salvator-x.dtb"
+CONFIG_DEFAULT_FDT_FILE="r8a77950-salvator-x.dtb"
 CONFIG_VERSION_VARIABLE=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
@@ -31,8 +31,8 @@
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="r8a7795-salvator-x-u-boot"
-CONFIG_OF_LIST="r8a7795-salvator-x-u-boot r8a7796-salvator-x-u-boot r8a77965-salvator-x-u-boot"
+CONFIG_DEFAULT_DEVICE_TREE="r8a77950-salvator-x-u-boot"
+CONFIG_OF_LIST="r8a77950-salvator-x-u-boot r8a77960-salvator-x-u-boot r8a77965-salvator-x-u-boot"
 CONFIG_MULTI_DTB_FIT_LZO=y
 CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
 CONFIG_ENV_IS_IN_MMC=y
@@ -49,6 +49,7 @@
 CONFIG_MMC_UHS_SUPPORT=y
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_RENESAS_SDHI=y
+CONFIG_BITBANGMII=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
diff --git a/configs/r8a7796_ulcb_defconfig b/configs/rcar3_ulcb_defconfig
similarity index 88%
rename from configs/r8a7796_ulcb_defconfig
rename to configs/rcar3_ulcb_defconfig
index ce4d5ac..53ea938 100644
--- a/configs/r8a7796_ulcb_defconfig
+++ b/configs/rcar3_ulcb_defconfig
@@ -8,13 +8,13 @@
 CONFIG_DM_GPIO=y
 CONFIG_RCAR_GEN3=y
 CONFIG_TARGET_ULCB=y
-CONFIG_SMBIOS_PRODUCT_NAME=""
 CONFIG_SPL_TEXT_BASE=0xe6338000
+CONFIG_SMBIOS_PRODUCT_NAME=""
 CONFIG_FIT=y
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
 CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_DEFAULT_FDT_FILE="r8a7796-m3ulcb.dtb"
+CONFIG_DEFAULT_FDT_FILE="r8a77950-ulcb.dtb"
 CONFIG_VERSION_VARIABLE=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
@@ -31,8 +31,8 @@
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="r8a7796-m3ulcb-u-boot"
-CONFIG_OF_LIST="r8a7795-h3ulcb-u-boot r8a7796-m3ulcb-u-boot r8a77965-m3nulcb-u-boot"
+CONFIG_DEFAULT_DEVICE_TREE="r8a77950-ulcb-u-boot"
+CONFIG_OF_LIST="r8a77950-ulcb-u-boot r8a77960-ulcb-u-boot r8a77965-ulcb-u-boot"
 CONFIG_MULTI_DTB_FIT_LZO=y
 CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
 CONFIG_ENV_IS_IN_MMC=y
@@ -49,6 +49,7 @@
 CONFIG_MMC_UHS_SUPPORT=y
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_RENESAS_SDHI=y
+CONFIG_BITBANGMII=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig
index 0e60c47..7365601 100644
--- a/configs/riotboard_defconfig
+++ b/configs/riotboard_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_EMBESTMX6BOARDS=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x60000
+CONFIG_TARGET_EMBESTMX6BOARDS=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024"
@@ -30,6 +30,7 @@
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
 CONFIG_MII=y
 CONFIG_SPI=y
 CONFIG_MXC_SPI=y
diff --git a/configs/riotboard_spl_defconfig b/configs/riotboard_spl_defconfig
index 61fe41d6..5ff8da0 100644
--- a/configs/riotboard_spl_defconfig
+++ b/configs/riotboard_spl_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_EMBESTMX6BOARDS=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x60000
+CONFIG_TARGET_EMBESTMX6BOARDS=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
@@ -40,6 +40,7 @@
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
 CONFIG_MII=y
 CONFIG_SPI=y
 CONFIG_MXC_SPI=y
diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig
index 569166b..9e59ca4 100644
--- a/configs/roc-cc-rk3308_defconfig
+++ b/configs/roc-cc-rk3308_defconfig
@@ -71,7 +71,6 @@
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_SPL_TINY_MEMSET=y
-CONFIG_LZ4=y
 CONFIG_LZO=y
 CONFIG_ERRNO_STR=y
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig
index be76524..aff690f 100644
--- a/configs/roc-pc-rk3399_defconfig
+++ b/configs/roc-pc-rk3399_defconfig
@@ -50,18 +50,16 @@
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_KEYBOARD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_ASIX88179=y
 CONFIG_USB_ETHER_MCS7830=y
 CONFIG_USB_ETHER_RTL8152=y
 CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_SPL_TINY_MEMSET=y
-CONFIG_ERRNO_STR=y
 CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_BPP16=y
-CONFIG_VIDEO_BPP32=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
 CONFIG_DISPLAY_ROCKCHIP_HDMI=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index cf71c85..2118402 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -9,8 +9,8 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BASE=0xff690000
 CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0xff704000
+CONFIG_DEBUG_UART=y
 # CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_USE_PREBOOT=y
 CONFIG_SILENT_CONSOLE=y
@@ -72,9 +72,9 @@
 CONFIG_USB=y
 CONFIG_USB_DWC2=y
 CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_KEYBOARD=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_KEYBOARD=y
 CONFIG_DM_VIDEO=y
 # CONFIG_VIDEO_BPP8 is not set
 CONFIG_DISPLAY=y
diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig
index c4e9547..045d989 100644
--- a/configs/rock960-rk3399_defconfig
+++ b/configs/rock960-rk3399_defconfig
@@ -51,6 +51,7 @@
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_DWC3=y
 CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_KEYBOARD=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
@@ -58,12 +59,9 @@
 CONFIG_USB_ETHER_MCS7830=y
 CONFIG_USB_ETHER_RTL8152=y
 CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_SPL_TINY_MEMSET=y
-CONFIG_ERRNO_STR=y
 CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_BPP16=y
-CONFIG_VIDEO_BPP32=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
 CONFIG_DISPLAY_ROCKCHIP_HDMI=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/rock_defconfig b/configs/rock_defconfig
index 78cd548..4e804e9 100644
--- a/configs/rock_defconfig
+++ b/configs/rock_defconfig
@@ -11,8 +11,8 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BASE=0x20064000
 CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x10080800
+CONFIG_DEBUG_UART=y
 CONFIG_USE_PREBOOT=y
 CONFIG_DEFAULT_FDT_FILE="rk3188-radxarock.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig
index cecc16c..5053a38 100644
--- a/configs/rpi_0_w_defconfig
+++ b/configs/rpi_0_w_defconfig
@@ -19,7 +19,6 @@
 CONFIG_CMD_FS_UUID=y
 CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-zero-w"
-CONFIG_ENV_FAT_INTERFACE="mmc"
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig
index 762a72a..0000a75 100644
--- a/configs/rpi_2_defconfig
+++ b/configs/rpi_2_defconfig
@@ -19,7 +19,6 @@
 CONFIG_CMD_FS_UUID=y
 CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="bcm2836-rpi-2-b"
-CONFIG_ENV_FAT_INTERFACE="mmc"
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig
index 5ca3164..a714f9e 100644
--- a/configs/rpi_3_32b_defconfig
+++ b/configs/rpi_3_32b_defconfig
@@ -20,7 +20,6 @@
 CONFIG_CMD_FS_UUID=y
 CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b"
-CONFIG_ENV_FAT_INTERFACE="mmc"
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
diff --git a/configs/rpi_3_b_plus_defconfig b/configs/rpi_3_b_plus_defconfig
index 4f03320..c9efa06 100644
--- a/configs/rpi_3_b_plus_defconfig
+++ b/configs/rpi_3_b_plus_defconfig
@@ -20,7 +20,6 @@
 CONFIG_CMD_FS_UUID=y
 CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b-plus"
-CONFIG_ENV_FAT_INTERFACE="mmc"
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig
index 51d5a71..244d9b3 100644
--- a/configs/rpi_3_defconfig
+++ b/configs/rpi_3_defconfig
@@ -20,7 +20,6 @@
 CONFIG_CMD_FS_UUID=y
 CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b"
-CONFIG_ENV_FAT_INTERFACE="mmc"
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
index 72cda5d..8d262d8 100644
--- a/configs/rpi_4_32b_defconfig
+++ b/configs/rpi_4_32b_defconfig
@@ -17,7 +17,6 @@
 CONFIG_CMD_MMC=y
 CONFIG_CMD_FS_UUID=y
 CONFIG_OF_BOARD=y
-CONFIG_ENV_FAT_INTERFACE="mmc"
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig
index 6d148da..2a0cea4 100644
--- a/configs/rpi_4_defconfig
+++ b/configs/rpi_4_defconfig
@@ -17,7 +17,6 @@
 CONFIG_CMD_MMC=y
 CONFIG_CMD_FS_UUID=y
 CONFIG_OF_BOARD=y
-CONFIG_ENV_FAT_INTERFACE="mmc"
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig
index fea86be..d2406ca 100644
--- a/configs/rpi_arm64_defconfig
+++ b/configs/rpi_arm64_defconfig
@@ -17,7 +17,6 @@
 CONFIG_CMD_USB=y
 CONFIG_CMD_FS_UUID=y
 CONFIG_OF_BOARD=y
-CONFIG_ENV_FAT_INTERFACE="mmc"
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM_KEYBOARD=y
diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig
index dbbc818..64bb184 100644
--- a/configs/rpi_defconfig
+++ b/configs/rpi_defconfig
@@ -19,7 +19,6 @@
 CONFIG_CMD_FS_UUID=y
 CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-b"
-CONFIG_ENV_FAT_INTERFACE="mmc"
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index 22572ef..40c9de2 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -6,6 +6,7 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_AM33XX=y
 CONFIG_SYS_MPUCLK=600
 CONFIG_TARGET_RUT=y
@@ -29,7 +30,6 @@
 CONFIG_ARCH_MISC_INIT=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
@@ -74,6 +74,7 @@
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_MTD_UBI_FASTMAP=y
 CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
+CONFIG_PHY_NATSEMI=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
 CONFIG_SPI=y
diff --git a/configs/sama5d27_som1_ek_mmc1_defconfig b/configs/sama5d27_som1_ek_mmc1_defconfig
index b640648..a750ec9 100644
--- a/configs/sama5d27_som1_ek_mmc1_defconfig
+++ b/configs/sama5d27_som1_ek_mmc1_defconfig
@@ -18,8 +18,8 @@
 CONFIG_DEBUG_UART_CLOCK=82000000
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_DEBUG_UART=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig
index dfd8047..3f22fde 100644
--- a/configs/sama5d27_som1_ek_mmc_defconfig
+++ b/configs/sama5d27_som1_ek_mmc_defconfig
@@ -19,8 +19,8 @@
 CONFIG_DEBUG_UART_CLOCK=82000000
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_DEBUG_UART=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
diff --git a/configs/sama5d27_som1_ek_qspiflash_defconfig b/configs/sama5d27_som1_ek_qspiflash_defconfig
index 6c23363..2c8ae8d 100644
--- a/configs/sama5d27_som1_ek_qspiflash_defconfig
+++ b/configs/sama5d27_som1_ek_qspiflash_defconfig
@@ -19,8 +19,8 @@
 CONFIG_DEBUG_UART_CLOCK=82000000
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_DEBUG_UART=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig
index a22dcf1..a5fb4f5 100644
--- a/configs/sama5d27_wlsom1_ek_mmc_defconfig
+++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig
@@ -17,8 +17,8 @@
 CONFIG_DEBUG_UART_CLOCK=82000000
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_DEBUG_UART=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
diff --git a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
index 31a7edf..92decb4 100644
--- a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
+++ b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
@@ -7,6 +7,7 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
@@ -16,8 +17,8 @@
 CONFIG_DEBUG_UART_CLOCK=82000000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_DEBUG_UART=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
@@ -32,7 +33,6 @@
 CONFIG_SPL_DISPLAY_PRINT=y
 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_SPL_AT91_MCK_BYPASS=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/sama5d2_xplained_emmc_defconfig b/configs/sama5d2_xplained_emmc_defconfig
index 64b23db..75d68a7 100644
--- a/configs/sama5d2_xplained_emmc_defconfig
+++ b/configs/sama5d2_xplained_emmc_defconfig
@@ -18,8 +18,8 @@
 CONFIG_DEBUG_UART_CLOCK=83000000
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_DEBUG_UART=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC"
diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig
index 12571ff..779e91a 100644
--- a/configs/sama5d2_xplained_mmc_defconfig
+++ b/configs/sama5d2_xplained_mmc_defconfig
@@ -19,8 +19,8 @@
 CONFIG_DEBUG_UART_CLOCK=83000000
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_DEBUG_UART=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC"
diff --git a/configs/sama5d2_xplained_qspiflash_defconfig b/configs/sama5d2_xplained_qspiflash_defconfig
index e64f1b6..9b56456 100644
--- a/configs/sama5d2_xplained_qspiflash_defconfig
+++ b/configs/sama5d2_xplained_qspiflash_defconfig
@@ -19,8 +19,8 @@
 CONFIG_DEBUG_UART_CLOCK=83000000
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_DEBUG_UART=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC"
diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig
index 6da9bd3..43d493b 100644
--- a/configs/sama5d2_xplained_spiflash_defconfig
+++ b/configs/sama5d2_xplained_spiflash_defconfig
@@ -8,8 +8,9 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x6000
+CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
@@ -20,8 +21,8 @@
 CONFIG_DEBUG_UART_CLOCK=83000000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_DEBUG_UART=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y
 CONFIG_SPI_BOOT=y
@@ -31,7 +32,6 @@
 CONFIG_MISC_INIT_R=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig b/configs/sama5d36ek_cmp_spiflash_defconfig
index 024ac65..440f3cb 100644
--- a/configs/sama5d36ek_cmp_spiflash_defconfig
+++ b/configs/sama5d36ek_cmp_spiflash_defconfig
@@ -5,8 +5,8 @@
 CONFIG_TARGET_SAMA5D3XEK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x6000
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig
index fa85fab..76e981d 100644
--- a/configs/sama5d3_xplained_mmc_defconfig
+++ b/configs/sama5d3_xplained_mmc_defconfig
@@ -19,8 +19,8 @@
 CONFIG_DEBUG_UART_CLOCK=132000000
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x300000
+CONFIG_DEBUG_UART=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y
 CONFIG_SD_BOOT=y
diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig
index 83ff270..44c6184 100644
--- a/configs/sama5d3_xplained_nandflash_defconfig
+++ b/configs/sama5d3_xplained_nandflash_defconfig
@@ -16,8 +16,8 @@
 CONFIG_DEBUG_UART_BASE=0xffffee00
 CONFIG_DEBUG_UART_CLOCK=132000000
 CONFIG_ENV_OFFSET_REDUND=0x100000
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x300000
+CONFIG_DEBUG_UART=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y
 CONFIG_NAND_BOOT=y
diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig
index a5fc191..d7f2ebe 100644
--- a/configs/sama5d3xek_mmc_defconfig
+++ b/configs/sama5d3xek_mmc_defconfig
@@ -19,8 +19,8 @@
 CONFIG_DEBUG_UART_CLOCK=132000000
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x300000
+CONFIG_DEBUG_UART=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y
 CONFIG_SD_BOOT=y
diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig
index e39bd49..5ad8542 100644
--- a/configs/sama5d3xek_nandflash_defconfig
+++ b/configs/sama5d3xek_nandflash_defconfig
@@ -16,8 +16,8 @@
 CONFIG_DEBUG_UART_BASE=0xffffee00
 CONFIG_DEBUG_UART_CLOCK=132000000
 CONFIG_ENV_OFFSET_REDUND=0x100000
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x300000
+CONFIG_DEBUG_UART=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y
 CONFIG_NAND_BOOT=y
diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig
index 6c7cc2e..6a76d7c 100644
--- a/configs/sama5d3xek_spiflash_defconfig
+++ b/configs/sama5d3xek_spiflash_defconfig
@@ -8,8 +8,9 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x6000
+CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
@@ -20,8 +21,8 @@
 CONFIG_DEBUG_UART_CLOCK=132000000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x300000
+CONFIG_DEBUG_UART=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y
 CONFIG_SPI_BOOT=y
@@ -30,7 +31,6 @@
 CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig
index bca732c..eaee73e 100644
--- a/configs/sama5d4_xplained_mmc_defconfig
+++ b/configs/sama5d4_xplained_mmc_defconfig
@@ -19,8 +19,8 @@
 CONFIG_DEBUG_UART_CLOCK=100000000
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_DEBUG_UART=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y
 CONFIG_SD_BOOT=y
diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig
index 58f314b..a277be1 100644
--- a/configs/sama5d4_xplained_nandflash_defconfig
+++ b/configs/sama5d4_xplained_nandflash_defconfig
@@ -16,8 +16,8 @@
 CONFIG_DEBUG_UART_BASE=0xfc00c000
 CONFIG_DEBUG_UART_CLOCK=100000000
 CONFIG_ENV_OFFSET_REDUND=0x100000
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_DEBUG_UART=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y
 CONFIG_NAND_BOOT=y
diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig
index d833962..3be18e6 100644
--- a/configs/sama5d4_xplained_spiflash_defconfig
+++ b/configs/sama5d4_xplained_spiflash_defconfig
@@ -8,8 +8,9 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x6000
+CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
@@ -20,8 +21,8 @@
 CONFIG_DEBUG_UART_CLOCK=100000000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_DEBUG_UART=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y
 CONFIG_SPI_BOOT=y
@@ -31,7 +32,6 @@
 CONFIG_MISC_INIT_R=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig
index b0486ed..c1c64dd 100644
--- a/configs/sama5d4ek_mmc_defconfig
+++ b/configs/sama5d4ek_mmc_defconfig
@@ -19,8 +19,8 @@
 CONFIG_DEBUG_UART_CLOCK=88000000
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_DEBUG_UART=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y
 CONFIG_SD_BOOT=y
diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig
index 9fdc36a..935945c 100644
--- a/configs/sama5d4ek_nandflash_defconfig
+++ b/configs/sama5d4ek_nandflash_defconfig
@@ -16,8 +16,8 @@
 CONFIG_DEBUG_UART_BASE=0xfc00c000
 CONFIG_DEBUG_UART_CLOCK=88000000
 CONFIG_ENV_OFFSET_REDUND=0x100000
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_DEBUG_UART=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y
 CONFIG_NAND_BOOT=y
diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig
index 13243a7..a7541a2 100644
--- a/configs/sama5d4ek_spiflash_defconfig
+++ b/configs/sama5d4ek_spiflash_defconfig
@@ -8,8 +8,9 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x6000
+CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
@@ -20,8 +21,8 @@
 CONFIG_DEBUG_UART_CLOCK=88000000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_DEBUG_UART=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y
 CONFIG_SPI_BOOT=y
@@ -30,7 +31,6 @@
 CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index 9d09233..d69b185 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -203,7 +203,6 @@
 CONFIG_FS_CBFS=y
 CONFIG_FS_CRAMFS=y
 CONFIG_CMD_DHRYSTONE=y
-CONFIG_RSA_VERIFY_WITH_PKEY=y
 CONFIG_TPM=y
 CONFIG_LZ4=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index cc38315..7812387 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -229,7 +229,6 @@
 CONFIG_FS_CBFS=y
 CONFIG_FS_CRAMFS=y
 CONFIG_CMD_DHRYSTONE=y
-CONFIG_RSA_VERIFY_WITH_PKEY=y
 CONFIG_TPM=y
 CONFIG_LZ4=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig
index a042b1e..52afd44 100644
--- a/configs/sbc8349_PCI_33_defconfig
+++ b/configs/sbc8349_PCI_33_defconfig
@@ -108,7 +108,15 @@
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig
index 6d09d61..c50a76b 100644
--- a/configs/sbc8349_PCI_66_defconfig
+++ b/configs/sbc8349_PCI_66_defconfig
@@ -108,7 +108,15 @@
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig
index efcaae9..2b06272 100644
--- a/configs/sbc8349_defconfig
+++ b/configs/sbc8349_defconfig
@@ -85,7 +85,15 @@
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_TSEC_ENET=y
 # CONFIG_PCI is not set
 CONFIG_SYS_NS16550=y
diff --git a/configs/sbc8548_PCI_33_PCIE_defconfig b/configs/sbc8548_PCI_33_PCIE_defconfig
index e3eca06..1c480b6 100644
--- a/configs/sbc8548_PCI_33_PCIE_defconfig
+++ b/configs/sbc8548_PCI_33_PCIE_defconfig
@@ -26,7 +26,15 @@
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/sbc8548_PCI_33_defconfig b/configs/sbc8548_PCI_33_defconfig
index 9583402..9b5a369 100644
--- a/configs/sbc8548_PCI_33_defconfig
+++ b/configs/sbc8548_PCI_33_defconfig
@@ -26,7 +26,15 @@
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/sbc8548_PCI_66_PCIE_defconfig b/configs/sbc8548_PCI_66_PCIE_defconfig
index 3d8033f..97474a2 100644
--- a/configs/sbc8548_PCI_66_PCIE_defconfig
+++ b/configs/sbc8548_PCI_66_PCIE_defconfig
@@ -26,7 +26,15 @@
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/sbc8548_PCI_66_defconfig b/configs/sbc8548_PCI_66_defconfig
index 0eb0cc5..843c9d1 100644
--- a/configs/sbc8548_PCI_66_defconfig
+++ b/configs/sbc8548_PCI_66_defconfig
@@ -26,7 +26,15 @@
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/sbc8548_defconfig b/configs/sbc8548_defconfig
index 4e09077..0b693f5 100644
--- a/configs/sbc8548_defconfig
+++ b/configs/sbc8548_defconfig
@@ -24,7 +24,15 @@
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 # CONFIG_PCI is not set
diff --git a/configs/sbc8641d_defconfig b/configs/sbc8641d_defconfig
index 767428a..67fbb1c 100644
--- a/configs/sbc8641d_defconfig
+++ b/configs/sbc8641d_defconfig
@@ -24,7 +24,15 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sc_sps_1_defconfig b/configs/sc_sps_1_defconfig
index b525d6a..a56c425 100644
--- a/configs/sc_sps_1_defconfig
+++ b/configs/sc_sps_1_defconfig
@@ -34,6 +34,7 @@
 CONFIG_MXS_GPIO=y
 CONFIG_MMC_MXS=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_SMSC=y
 CONFIG_MII=y
 CONFIG_CONS_INDEX=0
 CONFIG_USB=y
diff --git a/configs/secomx6quq7_defconfig b/configs/secomx6quq7_defconfig
index 2f679fc..3383517 100644
--- a/configs/secomx6quq7_defconfig
+++ b/configs/secomx6quq7_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_SECOMX6=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_TARGET_SECOMX6=y
 CONFIG_SECOMX6_UQ7=y
 CONFIG_SECOMX6Q=y
 CONFIG_SECOMX6_2GB=y
diff --git a/configs/sei510_defconfig b/configs/sei510_defconfig
index 79777e3..c3fe419 100644
--- a/configs/sei510_defconfig
+++ b/configs/sei510_defconfig
@@ -77,5 +77,4 @@
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_MESON=y
 CONFIG_VIDEO_DT_SIMPLEFB=y
-CONFIG_LZ4=y
 CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sei610_defconfig b/configs/sei610_defconfig
index bfcba34..f147235 100644
--- a/configs/sei610_defconfig
+++ b/configs/sei610_defconfig
@@ -77,5 +77,4 @@
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_MESON=y
 CONFIG_VIDEO_DT_SIMPLEFB=y
-CONFIG_LZ4=y
 CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sh7752evb_defconfig b/configs/sh7752evb_defconfig
index b49734a..1d0c558 100644
--- a/configs/sh7752evb_defconfig
+++ b/configs/sh7752evb_defconfig
@@ -30,6 +30,8 @@
 CONFIG_DOS_PARTITION=y
 CONFIG_MMC=y
 CONFIG_SH_MMCIF=y
+CONFIG_BITBANGMII=y
+CONFIG_PHY_VITESSE=y
 CONFIG_SH_ETHER=y
 CONFIG_SCIF_CONSOLE=y
 CONFIG_SPI=y
diff --git a/configs/sh7753evb_defconfig b/configs/sh7753evb_defconfig
index 396d6e3..b1563ed 100644
--- a/configs/sh7753evb_defconfig
+++ b/configs/sh7753evb_defconfig
@@ -29,6 +29,8 @@
 CONFIG_DOS_PARTITION=y
 CONFIG_MMC=y
 CONFIG_SH_MMCIF=y
+CONFIG_BITBANGMII=y
+CONFIG_PHY_VITESSE=y
 CONFIG_SH_ETHER=y
 CONFIG_SCIF_CONSOLE=y
 CONFIG_SPI=y
diff --git a/configs/sh7757lcr_defconfig b/configs/sh7757lcr_defconfig
index a7e7c2d..4f5808a 100644
--- a/configs/sh7757lcr_defconfig
+++ b/configs/sh7757lcr_defconfig
@@ -32,6 +32,7 @@
 CONFIG_DOS_PARTITION=y
 CONFIG_MMC=y
 CONFIG_SH_MMCIF=y
+CONFIG_BITBANGMII=y
 CONFIG_SH_ETHER=y
 CONFIG_SCIF_CONSOLE=y
 CONFIG_SPI=y
diff --git a/configs/sh7763rdp_defconfig b/configs/sh7763rdp_defconfig
index 2ec6939..9c5acf4 100644
--- a/configs/sh7763rdp_defconfig
+++ b/configs/sh7763rdp_defconfig
@@ -35,6 +35,7 @@
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_BITBANGMII=y
 CONFIG_SH_ETHER=y
 CONFIG_SCIF_CONSOLE=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/silk_defconfig b/configs/silk_defconfig
index 89ef1d4..59503bc 100644
--- a/configs/silk_defconfig
+++ b/configs/silk_defconfig
@@ -9,8 +9,9 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
 CONFIG_DM_GPIO=y
 CONFIG_ARCH_RMOBILE_BOARD_STRING="Silk"
 CONFIG_R8A7794=y
@@ -30,7 +31,6 @@
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
@@ -73,6 +73,7 @@
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_MTD=y
+CONFIG_BITBANGMII=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ8XXX=y
 CONFIG_DM_ETH=y
diff --git a/configs/sksimx6_defconfig b/configs/sksimx6_defconfig
index 601a29e..5a8469b 100644
--- a/configs/sksimx6_defconfig
+++ b/configs/sksimx6_defconfig
@@ -4,10 +4,10 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_MX6_DDRCAL=y
-CONFIG_TARGET_SKSIMX6=y
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x60000
+CONFIG_MX6_DDRCAL=y
+CONFIG_TARGET_SKSIMX6=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig
index 722bac1..cf67164 100644
--- a/configs/smdk5250_defconfig
+++ b/configs/smdk5250_defconfig
@@ -7,8 +7,8 @@
 CONFIG_ARCH_EXYNOS5=y
 CONFIG_TARGET_SMDK5250=y
 CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_SECT_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x3FC000
+CONFIG_ENV_SECT_SIZE=0x4000
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_SPL=y
 CONFIG_IDENT_STRING=" for SMDK5250"
diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig
index 6ec0beb..9af878d 100644
--- a/configs/smdk5420_defconfig
+++ b/configs/smdk5420_defconfig
@@ -5,8 +5,8 @@
 CONFIG_ARCH_EXYNOS5=y
 CONFIG_TARGET_SMDK5420=y
 CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_SECT_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x3FC000
+CONFIG_ENV_SECT_SIZE=0x4000
 CONFIG_NR_DRAM_BANKS=7
 CONFIG_SPL=y
 CONFIG_IDENT_STRING=" for SMDK5420"
diff --git a/configs/snow_defconfig b/configs/snow_defconfig
index 81dc729..d408e00 100644
--- a/configs/snow_defconfig
+++ b/configs/snow_defconfig
@@ -7,15 +7,15 @@
 CONFIG_ARCH_EXYNOS5=y
 CONFIG_TARGET_SNOW=y
 CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_SECT_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x3FC000
+CONFIG_ENV_SECT_SIZE=0x4000
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BASE=0x12c30000
 CONFIG_DEBUG_UART_CLOCK=100000000
 CONFIG_IDENT_STRING=" for snow"
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x02023400
+CONFIG_DEBUG_UART=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_BEST_MATCH=y
diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig
index 4fd84ad..4bca53a 100644
--- a/configs/socfpga_agilex_defconfig
+++ b/configs/socfpga_agilex_defconfig
@@ -4,6 +4,7 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x200
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c00000
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
@@ -13,7 +14,6 @@
 CONFIG_BOOTDELAY=5
 CONFIG_SPL_CACHE=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c00000
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # "
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
index ca34457..35ae18f 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -27,6 +27,7 @@
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
@@ -49,4 +50,7 @@
 CONFIG_TIMER=y
 CONFIG_SPL_TIMER=y
 CONFIG_DESIGNWARE_APB_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
 # CONFIG_SPL_WDT is not set
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index 0478a72..ce23011 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -2,6 +2,7 @@
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x4400
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y
 CONFIG_SPL_TEXT_BASE=0xFFFF0000
@@ -16,7 +17,6 @@
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_DFU=y
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index b6220e4..1633ca1 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -2,6 +2,7 @@
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x4400
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
 CONFIG_SPL_TEXT_BASE=0xFFFF0000
@@ -16,7 +17,6 @@
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_DFU=y
diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig
index 878b409..3e1a06d 100644
--- a/configs/socfpga_dbm_soc1_defconfig
+++ b/configs/socfpga_dbm_soc1_defconfig
@@ -2,6 +2,7 @@
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x4400
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1=y
 CONFIG_SPL_TEXT_BASE=0xFFFF0000
@@ -17,7 +18,6 @@
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_ASKENV=y
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index 349be72..dafb5e8 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -2,6 +2,7 @@
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x4400
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y
 CONFIG_SPL_TEXT_BASE=0xFFFF0000
@@ -17,7 +18,6 @@
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_DFU=y
diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig
index ed34223..64ee602 100644
--- a/configs/socfpga_de10_nano_defconfig
+++ b/configs/socfpga_de10_nano_defconfig
@@ -2,6 +2,7 @@
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x4400
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_TERASIC_DE10_NANO=y
 CONFIG_SPL_TEXT_BASE=0xFFFF0000
@@ -16,7 +17,6 @@
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_DFU=y
diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig
index ec1abbc..a60df9b 100644
--- a/configs/socfpga_is1_defconfig
+++ b/configs/socfpga_is1_defconfig
@@ -1,8 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
 CONFIG_TARGET_SOCFPGA_IS1=y
@@ -19,7 +20,6 @@
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index a517969..157efea 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -2,6 +2,7 @@
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x4400
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_ARIES_MCVEVK=y
 CONFIG_SPL_TEXT_BASE=0xFFFF0000
@@ -17,7 +18,6 @@
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_DFU=y
diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig
index fcb38f1..2ded297 100644
--- a/configs/socfpga_secu1_defconfig
+++ b/configs/socfpga_secu1_defconfig
@@ -11,8 +11,8 @@
 # CONFIG_SPL_LIBDISK_SUPPORT is not set
 # CONFIG_SPL_SPI_SUPPORT is not set
 CONFIG_SPL_TEXT_BASE=0xFFFF0000
-CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BUILD_TARGET="u-boot-with-nand-spl.sfp"
+CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 # CONFIG_USE_BOOTCOMMAND is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index 255b0d6..247f3ab 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -2,6 +2,7 @@
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x4400
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y
 CONFIG_SPL_TEXT_BASE=0xFFFF0000
@@ -16,7 +17,6 @@
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_DFU=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index 68d57a1..a9ec97f 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -2,6 +2,7 @@
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x4400
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y
 CONFIG_SPL_TEXT_BASE=0xFFFF0000
@@ -16,7 +17,6 @@
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_DFU=y
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index af7c7bc..099ed7e 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -1,8 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0xE0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
 CONFIG_TARGET_SOCFPGA_SR1500=y
@@ -21,7 +22,6 @@
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
index 26db40f..155de1a 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -4,6 +4,7 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x200
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x3C00000
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
@@ -12,7 +13,6 @@
 CONFIG_SPL_TEXT_BASE=0xFFE00000
 CONFIG_BOOTDELAY=5
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x3C00000
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
index 47fb5a8..61b569e 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -1,8 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_SOFTING_VINING_FPGA=y
 CONFIG_ENV_OFFSET_REDUND=0x110000
@@ -23,7 +24,6 @@
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_EEPROM=y
diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig
index 244822f..5b2d025 100644
--- a/configs/socrates_defconfig
+++ b/configs/socrates_defconfig
@@ -51,7 +51,15 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_DM_PCI=y
diff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig
index a206fe6..4d7accc 100644
--- a/configs/som-db5800-som-6867_defconfig
+++ b/configs/som-db5800-som-6867_defconfig
@@ -1,8 +1,8 @@
 CONFIG_X86=y
 CONFIG_SYS_TEXT_BASE=0xFFF00000
 CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x6EF000
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
diff --git a/configs/somlabs_visionsom_6ull_defconfig b/configs/somlabs_visionsom_6ull_defconfig
index e39c035..03e37af 100644
--- a/configs/somlabs_visionsom_6ull_defconfig
+++ b/configs/somlabs_visionsom_6ull_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
-CONFIG_TARGET_SOMLABS_VISIONSOM_6ULL=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_TARGET_SOMLABS_VISIONSOM_6ULL=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/somlabs/visionsom-6ull/imximage.cfg"
diff --git a/configs/spear600_defconfig b/configs/spear600_defconfig
index 70086c2..40d4aac 100644
--- a/configs/spear600_defconfig
+++ b/configs/spear600_defconfig
@@ -31,6 +31,7 @@
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_NATSEMI=y
 CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
diff --git a/configs/spear600_nand_defconfig b/configs/spear600_nand_defconfig
index c7bfcad..e22bd33 100644
--- a/configs/spear600_nand_defconfig
+++ b/configs/spear600_nand_defconfig
@@ -28,6 +28,7 @@
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_NATSEMI=y
 CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
diff --git a/configs/spear600_usbtty_defconfig b/configs/spear600_usbtty_defconfig
index 854b97a..3c26fbe 100644
--- a/configs/spear600_usbtty_defconfig
+++ b/configs/spear600_usbtty_defconfig
@@ -28,6 +28,7 @@
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_NATSEMI=y
 CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
diff --git a/configs/spear600_usbtty_nand_defconfig b/configs/spear600_usbtty_nand_defconfig
index ae87614..cee2305 100644
--- a/configs/spear600_usbtty_nand_defconfig
+++ b/configs/spear600_usbtty_nand_defconfig
@@ -28,6 +28,7 @@
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_NATSEMI=y
 CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
diff --git a/configs/spring_defconfig b/configs/spring_defconfig
index ceddbf8..ee9cbb7 100644
--- a/configs/spring_defconfig
+++ b/configs/spring_defconfig
@@ -7,15 +7,15 @@
 CONFIG_ARCH_EXYNOS5=y
 CONFIG_TARGET_SPRING=y
 CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_SECT_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x3FC000
+CONFIG_ENV_SECT_SIZE=0x4000
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BASE=0x12c30000
 CONFIG_DEBUG_UART_CLOCK=100000000
 CONFIG_IDENT_STRING=" for spring"
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x02023400
+CONFIG_DEBUG_UART=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_BEST_MATCH=y
diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
index c9e2256..cdfa8bb 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -46,6 +46,7 @@
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_SMSC=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig
index 19a7493..c40730e 100644
--- a/configs/stm32f769-disco_defconfig
+++ b/configs/stm32f769-disco_defconfig
@@ -46,6 +46,7 @@
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_SMSC=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
index c8f1780..100f174 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -1,8 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_STM32MP=y
 CONFIG_SYS_MALLOC_F_LEN=0x3000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x280000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_TARGET_ST_STM32MP15x=y
@@ -19,7 +20,6 @@
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_MTD_SUPPORT=y
 CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
 CONFIG_SYS_PROMPT="STM32MP> "
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_EXPORTENV is not set
diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig
index f830feb..5f3813e 100644
--- a/configs/stm32mp15_dhcom_basic_defconfig
+++ b/configs/stm32mp15_dhcom_basic_defconfig
@@ -2,6 +2,7 @@
 CONFIG_ARCH_STM32MP=y
 CONFIG_SYS_MALLOC_F_LEN=0x3000
 CONFIG_ENV_SIZE=0x4000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_TARGET_DH_STM32MP1_PDK2=y
@@ -17,7 +18,6 @@
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_MTD_SUPPORT=y
 CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
 CONFIG_SYS_PROMPT="STM32MP> "
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_EXPORTENV is not set
@@ -90,7 +90,6 @@
 CONFIG_SPL_SPI_FLASH_MTD=y
 CONFIG_DM_ETH=y
 CONFIG_DWC_ETH_QOS=y
-CONFIG_KS8851_MLL=y
 CONFIG_PHY=y
 CONFIG_PHY_STM32_USBPHYC=y
 CONFIG_PINCONF=y
diff --git a/configs/stm32mp15_optee_defconfig b/configs/stm32mp15_optee_defconfig
index 6c17bd9..596fe19 100644
--- a/configs/stm32mp15_optee_defconfig
+++ b/configs/stm32mp15_optee_defconfig
@@ -2,8 +2,8 @@
 CONFIG_ARCH_STM32MP=y
 CONFIG_TFABOOT=y
 CONFIG_SYS_MALLOC_F_LEN=0x3000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x280000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_TARGET_ST_STM32MP15x=y
 CONFIG_STM32MP1_OPTEE=y
 CONFIG_ENV_OFFSET_REDUND=0x2C0000
diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig
index d22605f..f9df13a 100644
--- a/configs/stm32mp15_trusted_defconfig
+++ b/configs/stm32mp15_trusted_defconfig
@@ -2,8 +2,8 @@
 CONFIG_ARCH_STM32MP=y
 CONFIG_TFABOOT=y
 CONFIG_SYS_MALLOC_F_LEN=0x3000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x280000
+CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_TARGET_ST_STM32MP15x=y
 CONFIG_ENV_OFFSET_REDUND=0x2C0000
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/stmark2_defconfig b/configs/stmark2_defconfig
index 82c6c13..036ff70 100644
--- a/configs/stmark2_defconfig
+++ b/configs/stmark2_defconfig
@@ -1,8 +1,8 @@
 CONFIG_M68K=y
 CONFIG_SYS_TEXT_BASE=0x47E00000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x40000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_TARGET_STMARK2=y
 CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=30000000"
 # CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/stout_defconfig b/configs/stout_defconfig
index 286d30f..cc4a519 100644
--- a/configs/stout_defconfig
+++ b/configs/stout_defconfig
@@ -9,8 +9,9 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
 CONFIG_DM_GPIO=y
 CONFIG_ARCH_RMOBILE_BOARD_STRING="Stout"
 CONFIG_R8A7790=y
@@ -30,7 +31,6 @@
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
@@ -71,6 +71,7 @@
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_MTD=y
+CONFIG_BITBANGMII=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ8XXX=y
 CONFIG_DM_ETH=y
diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig
index 1c3146e..0790c76 100644
--- a/configs/strider_con_defconfig
+++ b/configs/strider_con_defconfig
@@ -126,7 +126,16 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_BITBANGMII=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_CONS_INDEX=2
diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig
index 0cea69d..f203f40 100644
--- a/configs/strider_con_dp_defconfig
+++ b/configs/strider_con_dp_defconfig
@@ -126,7 +126,16 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_BITBANGMII=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_CONS_INDEX=2
diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig
index 3a5db81..c2875c5 100644
--- a/configs/strider_cpu_defconfig
+++ b/configs/strider_cpu_defconfig
@@ -126,7 +126,16 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_BITBANGMII=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_CONS_INDEX=2
diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig
index 3897d86..7647fd8 100644
--- a/configs/strider_cpu_dp_defconfig
+++ b/configs/strider_cpu_dp_defconfig
@@ -126,7 +126,16 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_BITBANGMII=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_CONS_INDEX=2
diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig
index 016be7a..0b52b00 100644
--- a/configs/stv0991_defconfig
+++ b/configs/stv0991_defconfig
@@ -4,8 +4,8 @@
 CONFIG_SYS_TEXT_BASE=0x00010000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x30000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_EXTRA_OPTIONS="STV0991"
 CONFIG_BOOTDELAY=3
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index 61d4c74..f4fdd38 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_TBS2910=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x60000
+CONFIG_TARGET_TBS2910=y
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_PRE_CON_BUF_ADDR=0x7c000000
diff --git a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig
index 5710ad5..7a8feee 100644
--- a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig
+++ b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig
@@ -1,8 +1,8 @@
 CONFIG_X86=y
 CONFIG_SYS_TEXT_BASE=0xFFF00000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x6EC000
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_ENV_OFFSET_REDUND=0x6EE000
 CONFIG_VENDOR_CONGATEC=y
diff --git a/configs/theadorable-x86-conga-qa3-e3845_defconfig b/configs/theadorable-x86-conga-qa3-e3845_defconfig
index a69b907..dbbac6b 100644
--- a/configs/theadorable-x86-conga-qa3-e3845_defconfig
+++ b/configs/theadorable-x86-conga-qa3-e3845_defconfig
@@ -1,8 +1,8 @@
 CONFIG_X86=y
 CONFIG_SYS_TEXT_BASE=0xFFF00000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x6EC000
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_ENV_OFFSET_REDUND=0x6EE000
 CONFIG_VENDOR_CONGATEC=y
diff --git a/configs/theadorable-x86-dfi-bt700_defconfig b/configs/theadorable-x86-dfi-bt700_defconfig
index 3f63bde..de9701a 100644
--- a/configs/theadorable-x86-dfi-bt700_defconfig
+++ b/configs/theadorable-x86-dfi-bt700_defconfig
@@ -1,8 +1,8 @@
 CONFIG_X86=y
 CONFIG_SYS_TEXT_BASE=0xFFF00000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x6EC000
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_ENV_OFFSET_REDUND=0x6EE000
 CONFIG_VENDOR_DFI=y
diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig
index 616c07a..ab4a460 100644
--- a/configs/theadorable_debug_defconfig
+++ b/configs/theadorable_debug_defconfig
@@ -7,16 +7,17 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_THEADORABLE=y
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x1a000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BASE=0xd0012000
 CONFIG_DEBUG_UART_CLOCK=250000000
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x40004030
+CONFIG_DEBUG_UART=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_FIT=y
 CONFIG_BOOTDELAY=3
@@ -26,7 +27,6 @@
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x1a000
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPIO=y
diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig
index 447491f..d81981a 100644
--- a/configs/thuban_defconfig
+++ b/configs/thuban_defconfig
@@ -6,6 +6,7 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_AM33XX=y
 CONFIG_SYS_MPUCLK=300
 CONFIG_TARGET_THUBAN=y
@@ -27,7 +28,6 @@
 CONFIG_ARCH_MISC_INIT=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 # CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
@@ -73,6 +73,7 @@
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_MTD_UBI_FASTMAP=y
 CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
+CONFIG_PHY_SMSC=y
 CONFIG_DRIVER_TI_CPSW=y
 CONFIG_SPI=y
 CONFIG_OMAP3_SPI=y
diff --git a/configs/ti814x_evm_defconfig b/configs/ti814x_evm_defconfig
index b705019..71c9119 100644
--- a/configs/ti814x_evm_defconfig
+++ b/configs/ti814x_evm_defconfig
@@ -38,6 +38,7 @@
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_MMC_OMAP_HS=y
+CONFIG_PHY_ET1011C=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
index 034d28e..9e6bcac 100644
--- a/configs/tinker-rk3288_defconfig
+++ b/configs/tinker-rk3288_defconfig
@@ -75,12 +75,12 @@
 CONFIG_USB=y
 CONFIG_USB_DWC2=y
 CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_KEYBOARD=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_USB_KEYBOARD=y
 CONFIG_DM_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig
index 06c5d9b..daae189 100644
--- a/configs/tinker-s-rk3288_defconfig
+++ b/configs/tinker-s-rk3288_defconfig
@@ -75,12 +75,12 @@
 CONFIG_USB=y
 CONFIG_USB_DWC2=y
 CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_KEYBOARD=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_USB_KEYBOARD=y
 CONFIG_DM_VIDEO=y
 # CONFIG_VIDEO_BPP8 is not set
 CONFIG_DISPLAY=y
diff --git a/configs/titanium_defconfig b/configs/titanium_defconfig
index d123544..f8ba766 100644
--- a/configs/titanium_defconfig
+++ b/configs/titanium_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_TITANIUM=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x1000000
+CONFIG_TARGET_TITANIUM=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_OFFSET_REDUND=0x1080000
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/barco/titanium/imximage.cfg"
diff --git a/configs/tools-only_defconfig b/configs/tools-only_defconfig
index 2811b2c..70e62bf 100644
--- a/configs/tools-only_defconfig
+++ b/configs/tools-only_defconfig
@@ -12,6 +12,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sandbox"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_IP_DEFRAG=y
+# CONFIG_ACPIGEN is not set
 CONFIG_AXI=y
 CONFIG_AXI_SANDBOX=y
 # CONFIG_UDP_FUNCTION_FASTBOOT is not set
@@ -26,4 +27,3 @@
 # CONFIG_VIRTIO_PCI is not set
 # CONFIG_VIRTIO_SANDBOX is not set
 # CONFIG_EFI_LOADER is not set
-# CONFIG_ACPIGEN is not set
diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig
index b989b7f..5c244b4 100644
--- a/configs/topic_miami_defconfig
+++ b/configs/topic_miami_defconfig
@@ -5,6 +5,7 @@
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_ENV_SIZE=0x8000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_SPL=y
@@ -19,7 +20,6 @@
 CONFIG_USE_PREBOOT=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_SYS_PROMPT="zynq-uboot> "
 CONFIG_CMD_THOR_DOWNLOAD=y
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig
index 9000d32..068b5bc 100644
--- a/configs/topic_miamilite_defconfig
+++ b/configs/topic_miamilite_defconfig
@@ -5,6 +5,7 @@
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_ENV_SIZE=0x8000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_SPL=y
@@ -19,7 +20,6 @@
 CONFIG_USE_PREBOOT=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_SYS_PROMPT="zynq-uboot> "
 CONFIG_CMD_THOR_DOWNLOAD=y
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig
index 30ccf40..8698077 100644
--- a/configs/topic_miamiplus_defconfig
+++ b/configs/topic_miamiplus_defconfig
@@ -5,6 +5,7 @@
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_ENV_SIZE=0x8000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_SPL=y
@@ -19,7 +20,6 @@
 CONFIG_USE_PREBOOT=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_SYS_PROMPT="zynq-uboot> "
 CONFIG_CMD_THOR_DOWNLOAD=y
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/tqma6dl_mba6_mmc_defconfig b/configs/tqma6dl_mba6_mmc_defconfig
index d0021872..4e1645d 100644
--- a/configs/tqma6dl_mba6_mmc_defconfig
+++ b/configs/tqma6dl_mba6_mmc_defconfig
@@ -1,8 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
-CONFIG_TARGET_TQMA6=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_TARGET_TQMA6=y
 CONFIG_TQMA6DL=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_FIT=y
diff --git a/configs/tqma6dl_mba6_spi_defconfig b/configs/tqma6dl_mba6_spi_defconfig
index 7554c3d..b0596c2 100644
--- a/configs/tqma6dl_mba6_spi_defconfig
+++ b/configs/tqma6dl_mba6_spi_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
-CONFIG_TARGET_TQMA6=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x80000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_TARGET_TQMA6=y
 CONFIG_TQMA6DL=y
 CONFIG_TQMA6X_SPI_BOOT=y
 CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/tqma6q_mba6_mmc_defconfig b/configs/tqma6q_mba6_mmc_defconfig
index 5c61b75..bee5e9e 100644
--- a/configs/tqma6q_mba6_mmc_defconfig
+++ b/configs/tqma6q_mba6_mmc_defconfig
@@ -1,8 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
-CONFIG_TARGET_TQMA6=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_TARGET_TQMA6=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
diff --git a/configs/tqma6q_mba6_spi_defconfig b/configs/tqma6q_mba6_spi_defconfig
index 745bf17..f1325a6 100644
--- a/configs/tqma6q_mba6_spi_defconfig
+++ b/configs/tqma6q_mba6_spi_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
-CONFIG_TARGET_TQMA6=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x80000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_TARGET_TQMA6=y
 CONFIG_TQMA6X_SPI_BOOT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_OFFSET_REDUND=0x90000
diff --git a/configs/tqma6s_mba6_mmc_defconfig b/configs/tqma6s_mba6_mmc_defconfig
index fc60e9a..9d5f451 100644
--- a/configs/tqma6s_mba6_mmc_defconfig
+++ b/configs/tqma6s_mba6_mmc_defconfig
@@ -1,8 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
-CONFIG_TARGET_TQMA6=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_TARGET_TQMA6=y
 CONFIG_TQMA6S=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_FIT=y
diff --git a/configs/tqma6s_mba6_spi_defconfig b/configs/tqma6s_mba6_spi_defconfig
index 23e3f1a..f28548b 100644
--- a/configs/tqma6s_mba6_spi_defconfig
+++ b/configs/tqma6s_mba6_spi_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
-CONFIG_TARGET_TQMA6=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x80000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_TARGET_TQMA6=y
 CONFIG_TQMA6S=y
 CONFIG_TQMA6X_SPI_BOOT=y
 CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/tqma6s_wru4_mmc_defconfig b/configs/tqma6s_wru4_mmc_defconfig
index 49dcdec..73ca9ab 100644
--- a/configs/tqma6s_wru4_mmc_defconfig
+++ b/configs/tqma6s_wru4_mmc_defconfig
@@ -1,11 +1,11 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x100000
 CONFIG_TARGET_TQMA6=y
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
 CONFIG_TQMA6S=y
 CONFIG_WRU4=y
 CONFIG_SYS_BOOTCOUNT_ADDR=0x00900000
@@ -68,6 +68,7 @@
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_SMSC=y
 CONFIG_MII=y
 # CONFIG_SPECIFY_CONSOLE_INDEX is not set
 CONFIG_MXC_UART=y
diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig
index 6613701..fb9be30 100644
--- a/configs/trimslice_defconfig
+++ b/configs/trimslice_defconfig
@@ -2,8 +2,8 @@
 CONFIG_TEGRA=y
 CONFIG_SYS_TEXT_BASE=0x00110000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFE000
+CONFIG_ENV_SECT_SIZE=0x2000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_TEGRA20=y
 CONFIG_TARGET_TRIMSLICE=y
diff --git a/configs/ts4800_defconfig b/configs/ts4800_defconfig
index 5701bfa..810f0d8 100644
--- a/configs/ts4800_defconfig
+++ b/configs/ts4800_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX5=y
 CONFIG_SYS_TEXT_BASE=0x90008000
-CONFIG_TARGET_TS4800=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x60000
+CONFIG_TARGET_TS4800=y
 CONFIG_NR_DRAM_BANKS=1
 # CONFIG_CMD_BMODE is not set
 CONFIG_BOOTDELAY=1
@@ -21,6 +21,7 @@
 CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MTD=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_SMSC=y
 CONFIG_MII=y
 CONFIG_SPI=y
 CONFIG_MXC_SPI=y
diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig
index d786255..66d475d 100644
--- a/configs/turris_mox_defconfig
+++ b/configs/turris_mox_defconfig
@@ -5,8 +5,8 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_TURRIS_MOX=y
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x180000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_DEBUG_UART_BASE=0xd0012000
@@ -14,6 +14,7 @@
 CONFIG_DEBUG_UART=y
 CONFIG_DISTRO_DEFAULTS=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_USE_PREBOOT=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_MISC_INIT_R=y
@@ -37,7 +38,6 @@
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_MAC_PARTITION=y
 CONFIG_OF_BOARD_FIXUP=y
-CONFIG_OF_BOARD_SETUP=y
 CONFIG_DEFAULT_DEVICE_TREE="armada-3720-turris-mox"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
@@ -57,6 +57,7 @@
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_MVNETA=y
 CONFIG_PCI=y
diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig
index 29c4968..07d8612 100644
--- a/configs/turris_omnia_defconfig
+++ b/configs/turris_omnia_defconfig
@@ -9,17 +9,18 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_TURRIS_OMNIA=y
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0xF0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x24000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BASE=0xd0012000
 CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
-CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -30,7 +31,6 @@
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x24000
 CONFIG_CMD_MEMTEST=y
 CONFIG_SYS_ALT_MEMTEST=y
 CONFIG_CMD_SHA1SUM=y
diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig
index 1878182..ee5bf0b 100644
--- a/configs/uDPU_defconfig
+++ b/configs/uDPU_defconfig
@@ -5,8 +5,8 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_MVEBU_ARMADA_37XX=y
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x180000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_DEBUG_UART_BASE=0xd0012000
 CONFIG_DEBUG_UART_CLOCK=25804800
diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig
index 9f87c72..5581196 100644
--- a/configs/udoo_defconfig
+++ b/configs/udoo_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_UDOO=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x60000
+CONFIG_TARGET_UDOO=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig
index a2355af..b2333a5 100644
--- a/configs/udoo_neo_defconfig
+++ b/configs/udoo_neo_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_UDOO_NEO=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x80000
+CONFIG_TARGET_UDOO_NEO=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/usb_a9263_dataflash_defconfig b/configs/usb_a9263_dataflash_defconfig
index 0c57b7a..65a6047 100644
--- a/configs/usb_a9263_dataflash_defconfig
+++ b/configs/usb_a9263_dataflash_defconfig
@@ -5,8 +5,8 @@
 CONFIG_TARGET_USB_A9263=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x2000
+CONFIG_ENV_SECT_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig
index a0cb3e9..da14fb0 100644
--- a/configs/usbarmory_defconfig
+++ b/configs/usbarmory_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX5=y
 CONFIG_SYS_TEXT_BASE=0x77800000
-CONFIG_TARGET_USBARMORY=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x60000
+CONFIG_TARGET_USBARMORY=y
 CONFIG_NR_DRAM_BANKS=1
 # CONFIG_CMD_BMODE is not set
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/variscite_dart6ul_defconfig b/configs/variscite_dart6ul_defconfig
index 0380295..b674d5a 100644
--- a/configs/variscite_dart6ul_defconfig
+++ b/configs/variscite_dart6ul_defconfig
@@ -4,8 +4,8 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x4000
-CONFIG_TARGET_DART_6UL=y
 CONFIG_ENV_SIZE=0x2000
+CONFIG_TARGET_DART_6UL=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=8
diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig
index 60d06cf..ed98cd1 100644
--- a/configs/ve8313_defconfig
+++ b/configs/ve8313_defconfig
@@ -146,7 +146,15 @@
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig
index a964e3c..590750e 100644
--- a/configs/verdin-imx8mm_defconfig
+++ b/configs/verdin-imx8mm_defconfig
@@ -7,11 +7,11 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xFFFFDE00
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xFFFFDE00
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_VERDIN_IMX8MM=y
 CONFIG_SPL_MMC_SUPPORT=y
diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig
index b52c761..c909326 100644
--- a/configs/vexpress_aemv8a_semi_defconfig
+++ b/configs/vexpress_aemv8a_semi_defconfig
@@ -7,6 +7,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_IDENT_STRING=" vexpress_aemv8a"
 CONFIG_DISTRO_DEFAULTS=y
+CONFIG_ANDROID_BOOT_IMAGE=y
 CONFIG_BOOTDELAY=1
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyAMA0 earlycon=pl011,0x1c090000 debug user_debug=31 loglevel=9"
@@ -14,9 +15,8 @@
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SYS_PROMPT="VExpress64# "
-CONFIG_ANDROID_BOOT_IMAGE=y
-CONFIG_CMD_ABOOTIMG=y
 # CONFIG_CMD_CONSOLE is not set
+CONFIG_CMD_ABOOTIMG=y
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_EDITENV is not set
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig
index 6bd1f25..8234b5d 100644
--- a/configs/vexpress_ca9x4_defconfig
+++ b/configs/vexpress_ca9x4_defconfig
@@ -6,6 +6,7 @@
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTCOMMAND="run distro_bootcmd; run bootflash"
+CONFIG_DEFAULT_FDT_FILE="vexpress-v2p-ca9.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 # CONFIG_CMD_CONSOLE is not set
@@ -34,4 +35,3 @@
 CONFIG_BAUDRATE=38400
 CONFIG_CONS_INDEX=0
 CONFIG_OF_LIBFDT=y
-CONFIG_DEFAULT_FDT_FILE="vexpress-v2p-ca9.dtb"
diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig
index d8daadc..2684324 100644
--- a/configs/vinco_defconfig
+++ b/configs/vinco_defconfig
@@ -4,8 +4,8 @@
 CONFIG_SYS_TEXT_BASE=0x20f00000
 CONFIG_TARGET_VINCO=y
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x10000
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_SPI_BOOT=y
@@ -35,6 +35,7 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_PHY_SMSC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig
index bcab7fb..a645667 100644
--- a/configs/vining_2000_defconfig
+++ b/configs/vining_2000_defconfig
@@ -5,10 +5,10 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x4000
-CONFIG_MX6_DDRCAL=y
-CONFIG_TARGET_SOFTING_VINING_2000=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x80000
+CONFIG_MX6_DDRCAL=y
+CONFIG_TARGET_SOFTING_VINING_2000=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
@@ -63,6 +63,7 @@
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_FSL_USDHC=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_SMSC=y
 CONFIG_DM_ETH=y
 CONFIG_FEC_MXC=y
diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig
index 536c2d1..66c3c96 100644
--- a/configs/vme8349_defconfig
+++ b/configs/vme8349_defconfig
@@ -117,7 +117,15 @@
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_TSEC_ENET=y
 CONFIG_RTC_RX8025=y
 CONFIG_BAUDRATE=9600
diff --git a/configs/vocore2_defconfig b/configs/vocore2_defconfig
new file mode 100644
index 0000000..6cacec0
--- /dev/null
+++ b/configs/vocore2_defconfig
@@ -0,0 +1,101 @@
+CONFIG_MIPS=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x04e000
+CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x20000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_ARCH_MTMIPS=y
+CONFIG_BOARD_VOCORE2=y
+CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_BOOT_GET_CMDLINE=y
+CONFIG_SYS_BOOT_GET_KBD=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_LOGLEVEL=8
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_LICENSE=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BOOTCOUNT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=spi0.0"
+CONFIG_MTDPARTS_DEFAULT="spi0.0:312k(u-boot),4k(env),4k(factory),2368k(kernel),-(filesystem)"
+CONFIG_DEFAULT_DEVICE_TREE="vocore_vocore2"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_MMC=y
+CONFIG_DM_MMC=y
+# CONFIG_MMC_HW_PARTITIONING is not set
+CONFIG_MMC_MTK=y
+CONFIG_MTD=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_MT7628_ETH=y
+CONFIG_PHY=y
+CONFIG_MT76X8_USB_PHY=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=3
+CONFIG_SPI=y
+CONFIG_MT7621_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_WDT=y
+CONFIG_WDT_MT7621=y
+CONFIG_FS_EXT4=y
+CONFIG_FAT_WRITE=y
+CONFIG_LZMA=y
+CONFIG_LZO=y
+CONFIG_SPL_LZMA=y
diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
index f9a5fe4..733b4e8 100644
--- a/configs/wandboard_defconfig
+++ b/configs/wandboard_defconfig
@@ -4,12 +4,12 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xC0000
 CONFIG_TARGET_WANDBOARD=y
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xC0000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
@@ -17,8 +17,8 @@
 CONFIG_SPL=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_CMD_HDMIDETECT=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_SPL_FIT_PRINT=y
diff --git a/configs/warp_defconfig b/configs/warp_defconfig
index 69957c9..e981f51 100644
--- a/configs/warp_defconfig
+++ b/configs/warp_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
-CONFIG_TARGET_WARP=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x60000
+CONFIG_TARGET_WARP=y
 CONFIG_NR_DRAM_BANKS=1
 # CONFIG_CMD_BMODE is not set
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp/imximage.cfg"
diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig
index 3de8ebb..547f531 100644
--- a/configs/work_92105_defconfig
+++ b/configs/work_92105_defconfig
@@ -45,5 +45,6 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_SMSC=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/x530_defconfig b/configs/x530_defconfig
index c49211d..67c8fbf 100644
--- a/configs/x530_defconfig
+++ b/configs/x530_defconfig
@@ -7,16 +7,17 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_X530=y
 CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x24000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BASE=0xd0012000
 CONFIG_DEBUG_UART_CLOCK=250000000
-CONFIG_DEBUG_UART=y
 CONFIG_SPL_TEXT_BASE=0x40000030
+CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SILENT_CONSOLE=y
@@ -24,7 +25,6 @@
 CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC=y
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_BOARD_INIT=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x24000
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_CMD_MEMINFO=y
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig
index 7493972..0743592 100644
--- a/configs/xilinx_versal_mini_defconfig
+++ b/configs/xilinx_versal_mini_defconfig
@@ -3,8 +3,8 @@
 CONFIG_SYS_ICACHE_OFF=y
 CONFIG_ARCH_VERSAL=y
 CONFIG_SYS_TEXT_BASE=0xFFFC0000
-CONFIG_SYS_MALLOC_LEN=0x2000
 CONFIG_ENV_SIZE=0x80
+CONFIG_SYS_MALLOC_LEN=0x2000
 CONFIG_NR_DRAM_BANKS=3
 CONFIG_SYS_MEM_RSVD_FOR_MMU=y
 CONFIG_COUNTER_FREQUENCY=2720000
diff --git a/configs/xilinx_versal_mini_emmc0_defconfig b/configs/xilinx_versal_mini_emmc0_defconfig
index a0a737d..e25077b 100644
--- a/configs/xilinx_versal_mini_emmc0_defconfig
+++ b/configs/xilinx_versal_mini_emmc0_defconfig
@@ -3,8 +3,8 @@
 CONFIG_SYS_ICACHE_OFF=y
 CONFIG_ARCH_VERSAL=y
 CONFIG_SYS_TEXT_BASE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x80000
 CONFIG_ENV_SIZE=0x80
+CONFIG_SYS_MALLOC_LEN=0x80000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_COUNTER_FREQUENCY=2720000
 # CONFIG_PSCI_RESET is not set
diff --git a/configs/xilinx_versal_mini_emmc1_defconfig b/configs/xilinx_versal_mini_emmc1_defconfig
index 3a9834f..3b477ad 100644
--- a/configs/xilinx_versal_mini_emmc1_defconfig
+++ b/configs/xilinx_versal_mini_emmc1_defconfig
@@ -3,8 +3,8 @@
 CONFIG_SYS_ICACHE_OFF=y
 CONFIG_ARCH_VERSAL=y
 CONFIG_SYS_TEXT_BASE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x80000
 CONFIG_ENV_SIZE=0x80
+CONFIG_SYS_MALLOC_LEN=0x80000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_COUNTER_FREQUENCY=2720000
 # CONFIG_PSCI_RESET is not set
diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig
index 54cbd3e..7441e10 100644
--- a/configs/xilinx_zynq_virt_defconfig
+++ b/configs/xilinx_zynq_virt_defconfig
@@ -2,6 +2,7 @@
 CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_SPL=y
@@ -19,7 +20,6 @@
 CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
 # CONFIG_BOOTM_NETBSD is not set
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_THOR_DOWNLOAD=y
@@ -32,12 +32,17 @@
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
 CONFIG_CMD_NAND_LOCK_UNLOCK=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_MTDPARTS_SPREAD=y
+CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
+CONFIG_CMD_UBI=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706"
 CONFIG_OF_LIST="zynq-zc702 zynq-zc706 zynq-zc770-xm010 zynq-zc770-xm011 zynq-zc770-xm011-x16 zynq-zc770-xm012 zynq-zc770-xm013 zynq-cc108 zynq-microzed zynq-minized zynq-picozed zynq-zed zynq-zturn zynq-zybo zynq-zybo-z7 zynq-dlc20-rev1.0"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index 7b09edd..73e8d84 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -35,6 +35,7 @@
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
 CONFIG_CMD_NAND_LOCK_UNLOCK=y
 CONFIG_CMD_POWEROFF=y
 CONFIG_CMD_SDRAM=y
@@ -45,6 +46,10 @@
 CONFIG_CMD_TIME=y
 CONFIG_CMD_TIMER=y
 CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_MTDPARTS_SPREAD=y
+CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
+CONFIG_CMD_UBI=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revC"
 CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA"
diff --git a/configs/xpedite517x_defconfig b/configs/xpedite517x_defconfig
index 2d975fb..caf9545 100644
--- a/configs/xpedite517x_defconfig
+++ b/configs/xpedite517x_defconfig
@@ -38,7 +38,15 @@
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/xpedite520x_defconfig b/configs/xpedite520x_defconfig
index c4ca18c..8803317 100644
--- a/configs/xpedite520x_defconfig
+++ b/configs/xpedite520x_defconfig
@@ -38,7 +38,15 @@
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/xpedite537x_defconfig b/configs/xpedite537x_defconfig
index a0b87bd..88378d6 100644
--- a/configs/xpedite537x_defconfig
+++ b/configs/xpedite537x_defconfig
@@ -41,7 +41,15 @@
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/xpedite550x_defconfig b/configs/xpedite550x_defconfig
index c685632..ff46e25 100644
--- a/configs/xpedite550x_defconfig
+++ b/configs/xpedite550x_defconfig
@@ -39,7 +39,15 @@
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/xpress_defconfig b/configs/xpress_defconfig
index 124abf1..3c18dea 100644
--- a/configs/xpress_defconfig
+++ b/configs/xpress_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
-CONFIG_TARGET_XPRESS=y
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x80000
+CONFIG_TARGET_XPRESS=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ccv/xpress/imximage.cfg"
 CONFIG_BOOTDELAY=3
@@ -32,6 +32,7 @@
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_SMSC=y
 CONFIG_MII=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/xpress_spl_defconfig b/configs/xpress_spl_defconfig
index 3df0021..aae7f6d 100644
--- a/configs/xpress_spl_defconfig
+++ b/configs/xpress_spl_defconfig
@@ -4,9 +4,9 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_XPRESS=y
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x80000
+CONFIG_TARGET_XPRESS=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
@@ -43,6 +43,7 @@
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_SMSC=y
 CONFIG_MII=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/zc5202_defconfig b/configs/zc5202_defconfig
index 4c6a765..ce40145 100644
--- a/configs/zc5202_defconfig
+++ b/configs/zc5202_defconfig
@@ -4,9 +4,10 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_ZC5202=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
+CONFIG_TARGET_ZC5202=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
@@ -25,7 +26,6 @@
 CONFIG_SPL_FS_EXT4=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_GPIO=y
@@ -46,6 +46,7 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_MV88E6352_SWITCH=y
 CONFIG_MII=y
 CONFIG_PCI=y
 CONFIG_SPI=y
diff --git a/configs/zc5601_defconfig b/configs/zc5601_defconfig
index faa4c5e..c1b7fb1 100644
--- a/configs/zc5601_defconfig
+++ b/configs/zc5601_defconfig
@@ -4,9 +4,10 @@
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_ZC5601=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
+CONFIG_TARGET_ZC5601=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
@@ -25,7 +26,6 @@
 CONFIG_SPL_FS_EXT4=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_GPIO=y
diff --git a/configs/zmx25_defconfig b/configs/zmx25_defconfig
index adb80e5..24eb20b 100644
--- a/configs/zmx25_defconfig
+++ b/configs/zmx25_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX25=y
 CONFIG_SYS_TEXT_BASE=0xA0000000
-CONFIG_TARGET_ZMX25=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_TARGET_ZMX25=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_BOOTDELAY=5
 CONFIG_USE_PREBOOT=y
diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig
index 2b58c46..6a01da2 100644
--- a/configs/zynq_cse_nand_defconfig
+++ b/configs/zynq_cse_nand_defconfig
@@ -4,8 +4,8 @@
 CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x100000
-CONFIG_SYS_MALLOC_LEN=0x1000
 CONFIG_ENV_SIZE=0x190
+CONFIG_SYS_MALLOC_LEN=0x8000
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_SPL=y
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig
index 3b4e2f9..7b18ba3 100644
--- a/configs/zynq_cse_nor_defconfig
+++ b/configs/zynq_cse_nor_defconfig
@@ -4,8 +4,8 @@
 CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0xFFFC0000
-CONFIG_SYS_MALLOC_LEN=0x1000
 CONFIG_ENV_SIZE=0x190
+CONFIG_SYS_MALLOC_LEN=0x1000
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_SPL=y
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig
index 073e2ce..15d8473 100644
--- a/configs/zynq_cse_qspi_defconfig
+++ b/configs/zynq_cse_qspi_defconfig
@@ -4,8 +4,9 @@
 CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0xFFFC0000
-CONFIG_SYS_MALLOC_LEN=0x1000
 CONFIG_ENV_SIZE=0x190
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
+CONFIG_SYS_MALLOC_LEN=0x1000
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BASE=0x0
@@ -22,7 +23,6 @@
 # CONFIG_ARCH_EARLY_INIT_R is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
 # CONFIG_CMDLINE_EDITING is not set
 # CONFIG_AUTO_COMPLETE is not set
 # CONFIG_SYS_LONGHELP is not set
diff --git a/disk/part_dos.c b/disk/part_dos.c
index 83ff40d..813379f 100644
--- a/disk/part_dos.c
+++ b/disk/part_dos.c
@@ -45,9 +45,15 @@
 	    part_type == 0x85);
 }
 
-static inline int is_bootable(dos_partition_t *p)
+static int get_bootable(dos_partition_t *p)
 {
-	return (p->sys_ind == 0xef) || (p->boot_ind == 0x80);
+	int ret = 0;
+
+	if (p->sys_ind == 0xef)
+		ret |= PART_EFI_SYSTEM_PARTITION;
+	if (p->boot_ind == 0x80)
+		ret |= PART_BOOTABLE;
+	return ret;
 }
 
 static void print_one_part(dos_partition_t *p, lbaint_t ext_part_sector,
@@ -60,7 +66,7 @@
 		"u\t%08x-%02x\t%02x%s%s\n",
 		part_num, lba_start, lba_size, disksig, part_num, p->sys_ind,
 		(is_extended(p->sys_ind) ? " Extd" : ""),
-		(is_bootable(p) ? " Boot" : ""));
+		(get_bootable(p) ? " Boot" : ""));
 }
 
 static int test_block_type(unsigned char *buffer)
@@ -258,7 +264,7 @@
 					      (char *)info->name);
 			/* sprintf(info->type, "%d, pt->sys_ind); */
 			strcpy((char *)info->type, "U-Boot");
-			info->bootable = is_bootable(pt);
+			info->bootable = get_bootable(pt);
 #if CONFIG_IS_ENABLED(PARTITION_UUIDS)
 			sprintf(info->uuid, "%08x-%02x", disksig, part_num);
 #endif
diff --git a/disk/part_efi.c b/disk/part_efi.c
index b2e157d..83876a7 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -71,11 +71,15 @@
 
 static const efi_guid_t system_guid = PARTITION_SYSTEM_GUID;
 
-static inline int is_bootable(gpt_entry *p)
+static int get_bootable(gpt_entry *p)
 {
-	return p->attributes.fields.legacy_bios_bootable ||
-		!memcmp(&(p->partition_type_guid), &system_guid,
-			sizeof(efi_guid_t));
+	int ret = 0;
+
+	if (!memcmp(&p->partition_type_guid, &system_guid, sizeof(efi_guid_t)))
+		ret |=  PART_EFI_SYSTEM_PARTITION;
+	if (p->attributes.fields.legacy_bios_bootable)
+		ret |=  PART_BOOTABLE;
+	return ret;
 }
 
 static int validate_gpt_header(gpt_header *gpt_h, lbaint_t lba,
@@ -286,7 +290,7 @@
 	snprintf((char *)info->name, sizeof(info->name), "%s",
 		 print_efiname(&gpt_pte[part - 1]));
 	strcpy((char *)info->type, "U-Boot");
-	info->bootable = is_bootable(&gpt_pte[part - 1]);
+	info->bootable = get_bootable(&gpt_pte[part - 1]);
 #if CONFIG_IS_ENABLED(PARTITION_UUIDS)
 	uuid_bin_to_str(gpt_pte[part - 1].unique_partition_guid.b, info->uuid,
 			UUID_STR_FORMAT_GUID);
@@ -501,7 +505,7 @@
 		memset(&gpt_e[i].attributes, 0,
 		       sizeof(gpt_entry_attributes));
 
-		if (partitions[i].bootable)
+		if (partitions[i].bootable & PART_BOOTABLE)
 			gpt_e[i].attributes.fields.legacy_bios_bootable = 1;
 
 		/* partition name */
diff --git a/doc/arch/x86.rst b/doc/arch/x86.rst
index a441738..c6b70ce 100644
--- a/doc/arch/x86.rst
+++ b/doc/arch/x86.rst
@@ -712,6 +712,34 @@
 See :doc:`../uefi/u-boot_on_efi` and :doc:`../uefi/uefi` for details of
 EFI support in U-Boot.
 
+Chain-loading
+-------------
+U-Boot can be chain-loaded from another bootloader, such as coreboot or
+Slim Bootloader. Typically this is done by building for targets 'coreboot' or
+'slimbootloader'.
+
+For example, at present we have a 'coreboot' target but this runs very
+different code from the bare-metal targets, such as coral. There is very little
+in common between them.
+
+It is useful to be able to boot the same U-Boot on a device, with or without a
+first-stage bootloader. For example, with chromebook_coral, it is helpful for
+testing to be able to boot the same U-Boot (complete with FSP) on bare metal
+and from coreboot. It allows checking of things like CPU speed, comparing
+registers, ACPI tables and the like.
+
+To do this you can use ll_boot_init() in appropriate places to skip init that
+has already been done by the previous stage. This works by setting a
+GD_FLG_NO_LL_INIT flag when U-Boot detects that it is running from another
+bootloader.
+
+With this feature, you can build a bare-metal target and boot it from
+coreboot, for example.
+
+Note that this is a development feature only. It is not intended for use in
+production environments. Also it is not currently part of the automated tests
+so may break in the future.
+
 TODO List
 ---------
 - Audio
diff --git a/doc/conf.py b/doc/conf.py
index 8bb27ad..93250a6 100644
--- a/doc/conf.py
+++ b/doc/conf.py
@@ -31,6 +31,8 @@
 # If your documentation needs a minimal Sphinx version, state it here.
 needs_sphinx = '1.3'
 
+latex_engine = 'xelatex'
+
 # Add any Sphinx extension module names here, as strings. They can be
 # extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
 # ones.
diff --git a/doc/develop/crash_dumps.rst b/doc/develop/crash_dumps.rst
new file mode 100644
index 0000000..1869637
--- /dev/null
+++ b/doc/develop/crash_dumps.rst
@@ -0,0 +1,122 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (c) 2020 Heinrich Schuchardt
+
+Analyzing crash dumps
+=====================
+
+When the CPU detects an instruction that it cannot execute it raises an
+interrupt. U-Boot than writes a crash dump. This chapter describes how such
+dump can be analyzed.
+
+Creating a crash dump voluntarily
+---------------------------------
+
+For describing the analysis of a crash dump we need an example. U-Boot comes
+with a command 'exception' that comes in handy here. The command is enabled
+by::
+
+    CONFIG_CMD_EXCEPTION=y
+
+The example output below was recorded when running qemu\_arm64\_defconfig on
+QEMU::
+
+    => exception undefined
+    "Synchronous Abort" handler, esr 0x02000000
+    elr: 00000000000101fc lr : 00000000000214ec (reloc)
+    elr: 000000007ff291fc lr : 000000007ff3a4ec
+    x0 : 000000007ffbd7f8 x1 : 0000000000000000
+    x2 : 0000000000000001 x3 : 000000007eedce18
+    x4 : 000000007ff291fc x5 : 000000007eedce50
+    x6 : 0000000000000064 x7 : 000000007eedce10
+    x8 : 0000000000000000 x9 : 0000000000000004
+    x10: 6db6db6db6db6db7 x11: 000000000000000d
+    x12: 0000000000000006 x13: 000000000001869f
+    x14: 000000007edd7dc0 x15: 0000000000000002
+    x16: 000000007ff291fc x17: 0000000000000000
+    x18: 000000007eed8dc0 x19: 0000000000000000
+    x20: 000000007ffbd7f8 x21: 0000000000000000
+    x22: 000000007eedce10 x23: 0000000000000002
+    x24: 000000007ffd4c80 x25: 0000000000000000
+    x26: 0000000000000000 x27: 0000000000000000
+    x28: 000000007eedce70 x29: 000000007edd7b40
+
+    Code: b00003c0 912ad000 940029d6 17ffff52 (e7f7defb)
+    Resetting CPU ...
+
+    resetting ...
+
+The first line provides us with the type of interrupt that occurred.
+(On ARMv8 a synchronous abort is an exception where the return address stored
+in the ESR register indicates the instruction that caused the exception.)
+
+The second line provides the contents of the elr and the lr register after
+subtracting the relocation offset. - U-Boot relocates itself after being
+loaded. - The relocation offset can also be displayed using the bdinfo command.
+
+After the contents of the registers we get a line indicating the machine
+code of the instructions preceding the crash and in parentheses the instruction
+leading to the dump.
+
+Analyzing the code location
+---------------------------
+
+We can convert the instructions in the line starting with 'Code:' into mnemonics
+using the objdump command. To make things easier scripts/decodecode is
+supplied::
+
+    $echo 'Code: b00003c0 912ad000 940029d6 17ffff52 (e7f7defb)' | \
+      CROSS_COMPILE=aarch64-linux-gnu- ARCH=arm64 scripts/decodecode
+    Code: b00003c0 912ad000 940029d6 17ffff52 (e7f7defb)
+    All code
+    ========
+       0:   b00003c0     adrp   x0, 0x79000
+       4:   912ad000     add    x0, x0, #0xab4
+       8:   940029d6     bl     0xa760
+       c:   17ffff52     b      0xfffffffffffffd54
+      10:*  e7f7defb     .inst  0xe7f7defb ; undefined <-- trapping instruction
+
+    Code starting with the faulting instruction
+    ===========================================
+       0:   e7f7defb     .inst  0xe7f7defb ; undefined
+
+Now lets use the locations provided by the elr and lr registers after
+subtracting the relocation offset to find out where in the code the crash
+occurred and from where it was invoked.
+
+File u-boot.map contains the memory layout of the U-Boot binary. Here we find
+these lines::
+
+   .text.do_undefined
+                  0x00000000000101fc        0xc cmd/built-in.o
+   .text.exception_complete
+                  0x0000000000010208       0x90 cmd/built-in.o
+   ...
+   .text.cmd_process
+                  0x00000000000213b8      0x164 common/built-in.o
+                  0x00000000000213b8                cmd_process
+   .text.cmd_process_error
+                  0x000000000002151c       0x40 common/built-in.o
+                  0x000000000002151c                cmd_process_error
+
+So the error occurred at the start of function do\_undefined() and this
+function was invoked from somewhere inside function cmd\_process().
+
+If we want to dive deeper, we can disassemble the U-Boot binary::
+
+    $ aarch64-linux-gnu-objdump -S -D u-boot | less
+
+    00000000000101fc <do_undefined>:
+    {
+            /*
+             * 0xe7f...f.   is undefined in ARM mode
+             * 0xde..       is undefined in Thumb mode
+            */
+            asm volatile (".word 0xe7f7defb\n");
+       101fc:       e7f7defb        .inst   0xe7f7defb ; undefined
+            return CMD_RET_FAILURE;
+    }
+    10200:       52800020        mov     w0, #0x1        // #1
+    10204:       d65f03c0        ret
+
+This example is based on the ARMv8 architecture but the same procedures can be
+used on other architectures as well.
diff --git a/doc/develop/index.rst b/doc/develop/index.rst
new file mode 100644
index 0000000..072db63
--- /dev/null
+++ b/doc/develop/index.rst
@@ -0,0 +1,10 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Develop U-Boot
+==============
+
+
+.. toctree::
+   :maxdepth: 2
+
+   crash_dumps
diff --git a/doc/device-tree-bindings/device.txt b/doc/device-tree-bindings/device.txt
new file mode 100644
index 0000000..27bd397
--- /dev/null
+++ b/doc/device-tree-bindings/device.txt
@@ -0,0 +1,36 @@
+Devices
+=======
+
+Device bindings are described by their own individual binding files.
+
+U-Boot provides for some optional properties which are documented here. See
+also hid-over-i2c.txt which describes HID devices. See also
+Documentation/firmware-guide/acpi/enumeration.rst in the Linux kernel for
+the acpi,compatible property.
+
+ - acpi,has-power-resource : (boolean) true if this device has a power resource.
+    This causes an ACPI PowerResource to be written containing the properties
+    provided by this binding, to describe how to handle powering the device up
+    and down using GPIOs
+ - acpi,compatible : compatible string to report
+ - acpi,ddn : Contains the string to use as the _DDN (DOS (Disk Operating
+    System) Device Name)
+ - acpi,hid : Contains the string to use as the HID (Hardware ID)
+    identifier _HID
+ - acpi,uid : _UID value for device
+ - linux,probed : Tells U-Boot to add 'linux,probed' to the ACPI tables so that
+    Linux will only load the driver if the device can be detected (e.g. on I2C
+    bus). Note that this is an out-of-tree Linux feature.
+
+
+Example
+-------
+
+elan_touchscreen: elan-touchscreen@10 {
+	compatible = "i2c-chip";
+	reg = <0x10>;
+	acpi,hid = "ELAN0001";
+	acpi,ddn = "ELAN Touchscreen";
+	interrupts-extended = <&acpi_gpe GPIO_21_IRQ IRQ_TYPE_EDGE_FALLING>;
+	linux,probed;
+};
diff --git a/doc/index.rst b/doc/index.rst
index cd98be6..fd9f10f 100644
--- a/doc/index.rst
+++ b/doc/index.rst
@@ -26,6 +26,17 @@
 
    build/index
 
+Developer-oriented documentation
+--------------------------------
+
+The following manuals are written for *developers* of the U-Boot - those who
+want to contribute to U-Boot.
+
+.. toctree::
+   :maxdepth: 2
+
+   develop/index
+
 Unified Extensible Firmware (UEFI)
 ----------------------------------
 
diff --git a/doc/sphinx/parse-headers.pl b/doc/sphinx/parse-headers.pl
index d4f3826..c518050 100755
--- a/doc/sphinx/parse-headers.pl
+++ b/doc/sphinx/parse-headers.pl
@@ -344,7 +344,7 @@
 
 B<parse_headers.pl> [<options>] <C_FILE> <OUT_FILE> [<EXCEPTIONS_FILE>]
 
-Where <options> can be: --debug, --help or --man.
+Where <options> can be: --debug, --help or --usage.
 
 =head1 OPTIONS
 
@@ -382,7 +382,7 @@
 The EXCEPTIONS_FILE contain two rules to allow ignoring a symbol or
 to replace the default references by a custom one.
 
-Please read doc/doc-guide/parse-headers.rst at the Kernel's
+Please read Documentation/doc-guide/parse-headers.rst at the Kernel's
 tree for more details.
 
 =head1 BUGS
diff --git a/doc/uefi/uefi.rst b/doc/uefi/uefi.rst
index a35fbd3..4fda00d 100644
--- a/doc/uefi/uefi.rst
+++ b/doc/uefi/uefi.rst
@@ -100,79 +100,93 @@
 Configuring UEFI secure boot
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-UEFI specification[1] defines a secure way of executing UEFI images
+The UEFI specification[1] defines a secure way of executing UEFI images
 by verifying a signature (or message digest) of image with certificates.
 This feature on U-Boot is enabled with::
 
     CONFIG_UEFI_SECURE_BOOT=y
 
 To make the boot sequence safe, you need to establish a chain of trust;
-In UEFI secure boot, you can make it with the UEFI variables, "PK"
-(Platform Key), "KEK" (Key Exchange Keys), "db" (white list database)
-and "dbx" (black list database).
+In UEFI secure boot the chain trust is defined by the following UEFI variables
 
-There are many online documents that describe what UEFI secure boot is
-and how it works. Please consult some of them for details.
+* PK - Platform Key
+* KEK - Key Exchange Keys
+* db - white list database
+* dbx - black list database
 
-Here is a simple example that you can follow for your initial attempt
-(Please note that the actual steps would absolutely depend on your system
-and environment.):
+An in depth description of UEFI secure boot is beyond the scope of this
+document. Please, refer to the UEFI specification and available online
+documentation. Here is a simple example that you can follow for your initial
+attempt (Please note that the actual steps will depend on your system and
+environment.):
 
-1. Install utility commands on your host
-    * openssl
-    * efitools
-    * sbsigntool
+Install the required tools on your host
 
-2. Create signing keys and key database files on your host
-    for PK::
+* openssl
+* efitools
+* sbsigntool
 
-        $ openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=TEST_PK/ \
-                -keyout PK.key -out PK.crt -nodes -days 365
-        $ cert-to-efi-sig-list -g 11111111-2222-3333-4444-123456789abc \
-                PK.crt PK.esl;
-        $ sign-efi-sig-list -c PK.crt -k PK.key PK PK.esl PK.auth
+Create signing keys and the key database on your host:
 
-    for KEK::
+The platform key
 
-        $ openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=TEST_KEK/ \
-                -keyout KEK.key -out KEK.crt -nodes -days 365
-        $ cert-to-efi-sig-list -g 11111111-2222-3333-4444-123456789abc \
-                KEK.crt KEK.esl
-        $ sign-efi-sig-list -c PK.crt -k PK.key KEK KEK.esl KEK.auth
+.. code-block:: bash
 
-    for db::
+    openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=TEST_PK/ \
+            -keyout PK.key -out PK.crt -nodes -days 365
+    cert-to-efi-sig-list -g 11111111-2222-3333-4444-123456789abc \
+            PK.crt PK.esl;
+    sign-efi-sig-list -c PK.crt -k PK.key PK PK.esl PK.auth
 
-        $ openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=TEST_db/ \
-                -keyout db.key -out db.crt -nodes -days 365
-        $ cert-to-efi-sig-list -g 11111111-2222-3333-4444-123456789abc \
-                db.crt db.esl
-        $ sign-efi-sig-list -c KEK.crt -k KEK.key db db.esl db.auth
+The key exchange keys
 
-    Copy \*.auth to media, say mmc, that is accessible from U-Boot.
+.. code-block:: bash
 
-3. Sign an image with one key in "db" on your host::
+    openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=TEST_KEK/ \
+            -keyout KEK.key -out KEK.crt -nodes -days 365
+    cert-to-efi-sig-list -g 11111111-2222-3333-4444-123456789abc \
+            KEK.crt KEK.esl
+    sign-efi-sig-list -c PK.crt -k PK.key KEK KEK.esl KEK.auth
 
-    $ sbsign --key db.key --cert db.crt helloworld.efi
+The whitelist database
 
-4. Install keys on your board::
+.. code-block:: bash
 
-    ==> fatload mmc 0:1 <tmpaddr> PK.auth
-    ==> setenv -e -nv -bs -rt -at -i <tmpaddr>,$filesize PK
-    ==> fatload mmc 0:1 <tmpaddr> KEK.auth
-    ==> setenv -e -nv -bs -rt -at -i <tmpaddr>,$filesize KEK
-    ==> fatload mmc 0:1 <tmpaddr> db.auth
-    ==> setenv -e -nv -bs -rt -at -i <tmpaddr>,$filesize db
+    $ openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=TEST_db/ \
+            -keyout db.key -out db.crt -nodes -days 365
+    $ cert-to-efi-sig-list -g 11111111-2222-3333-4444-123456789abc \
+            db.crt db.esl
+    $ sign-efi-sig-list -c KEK.crt -k KEK.key db db.esl db.auth
 
-5. Set up boot parameters on your board::
+Copy the \*.auth files to media, say mmc, that is accessible from U-Boot.
 
-    ==> efidebug boot add 1 HELLO mmc 0:1 /helloworld.efi.signed ""
+Sign an image with one of the keys in "db" on your host
 
-Then your board runs that image from Boot manager (See below).
+.. code-block:: bash
+
+    sbsign --key db.key --cert db.crt helloworld.efi
+
+Now in U-Boot install the keys on your board::
+
+    fatload mmc 0:1 <tmpaddr> PK.auth
+    setenv -e -nv -bs -rt -at -i <tmpaddr>,$filesize PK
+    fatload mmc 0:1 <tmpaddr> KEK.auth
+    setenv -e -nv -bs -rt -at -i <tmpaddr>,$filesize KEK
+    fatload mmc 0:1 <tmpaddr> db.auth
+    setenv -e -nv -bs -rt -at -i <tmpaddr>,$filesize db
+
+Set up boot parameters on your board::
+
+    efidebug boot add 1 HELLO mmc 0:1 /helloworld.efi.signed ""
+
+Now your board can run the signed image via the boot manager (see below).
 You can also try this sequence by running Pytest, test_efi_secboot,
-on sandbox::
+on the sandbox
+
+.. code-block:: bash
 
-    $ cd <U-Boot source directory>
-    $ pytest.py test/py/tests/test_efi_secboot/test_signed.py --bd sandbox
+    cd <U-Boot source directory>
+    pytest.py test/py/tests/test_efi_secboot/test_signed.py --bd sandbox
 
 Executing the boot manager
 ~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c
index 6eaafde..3035c5f 100644
--- a/drivers/clk/clk-hsdk-cgu.c
+++ b/drivers/clk/clk-hsdk-cgu.c
@@ -67,6 +67,7 @@
 #define CGU_TUN_IDIV_TUN	0x380
 #define CGU_TUN_IDIV_ROM	0x390
 #define CGU_TUN_IDIV_PWM	0x3A0
+#define CGU_TUN_IDIV_TIMER	0x3B0
 #define CGU_HDMI_IDIV_APB	0x480
 #define CGU_SYS_IDIV_APB	0x180
 #define CGU_SYS_IDIV_AXI	0x190
@@ -123,12 +124,12 @@
 #define MIN_PLL_RATE			100000000 /* 100 MHz */
 #define PARENT_RATE_33			33333333 /* fixed clock - xtal */
 #define PARENT_RATE_27			27000000 /* fixed clock - xtal */
-#define CGU_MAX_CLOCKS			26
+#define CGU_MAX_CLOCKS			27
 
 #define CGU_SYS_CLOCKS			16
 #define MAX_AXI_CLOCKS			4
 
-#define CGU_TUN_CLOCKS			3
+#define CGU_TUN_CLOCKS			4
 #define MAX_TUN_CLOCKS			6
 
 struct hsdk_tun_idiv_cfg {
@@ -147,7 +148,8 @@
 	{ 600000000, 600000000, 600000000, 600000000, 750000000, 600000000 }, {
 	{ CGU_TUN_IDIV_TUN,	{ 24,	12,	8,	6,	6,	4 } },
 	{ CGU_TUN_IDIV_ROM,	{ 4,	4,	4,	4,	5,	4 } },
-	{ CGU_TUN_IDIV_PWM,	{ 8,	8,	8,	8,	10,	8 } }
+	{ CGU_TUN_IDIV_PWM,	{ 8,	8,	8,	8,	10,	8 } },
+	{ CGU_TUN_IDIV_TIMER,	{ 12,	12,	12,	12,	15,	12 } }
 	}
 };
 
@@ -316,6 +318,7 @@
 	{ CGU_TUN_PLL, 0, CGU_TUN_IDIV_TUN, &sdt_pll_dat, idiv_get, tun_clk_set, idiv_off },
 	{ CGU_TUN_PLL, 0, CGU_TUN_IDIV_ROM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
 	{ CGU_TUN_PLL, 0, CGU_TUN_IDIV_PWM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+	{ CGU_TUN_PLL, 0, CGU_TUN_IDIV_TIMER, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
 	{ CGU_HDMI_PLL, 0, 0, &hdmi_pll_dat, pll_get, pll_set, NULL },
 	{ CGU_HDMI_PLL, 0, CGU_HDMI_IDIV_APB, &hdmi_pll_dat, idiv_get, idiv_set, idiv_off }
 };
diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
index d3673a5..075a083 100644
--- a/drivers/clk/clk_versal.c
+++ b/drivers/clk/clk_versal.c
@@ -503,6 +503,9 @@
 	     NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF)
 		return versal_clock_ref(clk_id);
 
+	if (!parent_id)
+		return 0;
+
 	clk_rate = versal_clock_calc(parent_id);
 
 	if (versal_clock_div(clk_id)) {
@@ -526,7 +529,7 @@
 	     NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_OUT &&
 	    ((clk_id >> NODE_CLASS_SHIFT) &
 	     NODE_CLASS_MASK) == NODE_CLASS_CLOCK) {
-		if (!versal_clock_gate(clk_id))
+		if (!versal_clock_gate(clk_id) && !versal_clock_mux(clk_id))
 			return -EINVAL;
 		*clk_rate = versal_clock_calc(clk_id);
 		return 0;
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index c1976aa..6089f84 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -112,6 +112,7 @@
 	MESON_GATE(CLKID_I2C, HHI_GCLK_MPEG0, 9),
 	MESON_GATE(CLKID_UART0, HHI_GCLK_MPEG0, 13),
 	MESON_GATE(CLKID_SPICC1, HHI_GCLK_MPEG0, 14),
+	MESON_GATE(CLKID_SD_EMMC_A, HHI_GCLK_MPEG0, 4),
 	MESON_GATE(CLKID_SD_EMMC_B, HHI_GCLK_MPEG0, 25),
 	MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26),
 	MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3),
@@ -127,6 +128,7 @@
 	MESON_GATE(CLKID_FCLK_DIV4, HHI_FIX_PLL_CNTL1, 21),
 	MESON_GATE(CLKID_FCLK_DIV5, HHI_FIX_PLL_CNTL1, 22),
 	MESON_GATE(CLKID_FCLK_DIV7, HHI_FIX_PLL_CNTL1, 23),
+	MESON_GATE(CLKID_SD_EMMC_A_CLK0, HHI_SD_EMMC_CLK_CNTL, 7),
 	MESON_GATE(CLKID_SD_EMMC_B_CLK0, HHI_SD_EMMC_CLK_CNTL, 23),
 	MESON_GATE(CLKID_SD_EMMC_C_CLK0, HHI_NAND_CLK_CNTL, 7),
 	MESON_GATE(CLKID_VPU_0, HHI_VPU_CLK_CNTL, 8),
diff --git a/drivers/core/acpi.c b/drivers/core/acpi.c
index ba50d68..e09905c 100644
--- a/drivers/core/acpi.c
+++ b/drivers/core/acpi.c
@@ -11,8 +11,17 @@
 #include <common.h>
 #include <dm.h>
 #include <dm/acpi.h>
+#include <dm/device-internal.h>
 #include <dm/root.h>
 
+/* Type of method to call */
+enum method_t {
+	METHOD_WRITE_TABLES,
+};
+
+/* Prototype for all methods */
+typedef int (*acpi_method)(const struct udevice *dev, struct acpi_ctx *ctx);
+
 int acpi_copy_name(char *out_name, const char *name)
 {
 	strncpy(out_name, name, ACPI_NAME_LEN);
@@ -31,3 +40,56 @@
 
 	return -ENOSYS;
 }
+
+acpi_method acpi_get_method(struct udevice *dev, enum method_t method)
+{
+	struct acpi_ops *aops;
+
+	aops = device_get_acpi_ops(dev);
+	if (aops) {
+		switch (method) {
+		case METHOD_WRITE_TABLES:
+			return aops->write_tables;
+		}
+	}
+
+	return NULL;
+}
+
+int acpi_recurse_method(struct acpi_ctx *ctx, struct udevice *parent,
+			enum method_t method)
+{
+	struct udevice *dev;
+	acpi_method func;
+	int ret;
+
+	func = acpi_get_method(parent, method);
+	if (func) {
+		log_debug("\n");
+		log_debug("- %s %p\n", parent->name, func);
+		ret = device_ofdata_to_platdata(parent);
+		if (ret)
+			return log_msg_ret("ofdata", ret);
+		ret = func(parent, ctx);
+		if (ret)
+			return log_msg_ret("func", ret);
+	}
+	device_foreach_child(dev, parent) {
+		ret = acpi_recurse_method(ctx, dev, method);
+		if (ret)
+			return log_msg_ret("recurse", ret);
+	}
+
+	return 0;
+}
+
+int acpi_write_dev_tables(struct acpi_ctx *ctx)
+{
+	int ret;
+
+	log_debug("Writing device tables\n");
+	ret = acpi_recurse_method(ctx, dm_root(), METHOD_WRITE_TABLES);
+	log_debug("Writing finished, err=%d\n", ret);
+
+	return ret;
+}
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 520c9f9..372dc0a 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -839,8 +839,7 @@
 		cfg->host_caps &= ~MMC_MODE_HS_52MHz;
 	}
 
-	if (!(cfg->voltages & MMC_VDD_165_195) ||
-	    (host->quirks & SDHCI_QUIRK_NO_1_8_V))
+	if (!(cfg->voltages & MMC_VDD_165_195))
 		caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 			    SDHCI_SUPPORT_DDR50);
 
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index da3ff53..18925d0 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -22,14 +22,12 @@
 struct arasan_sdhci_plat {
 	struct mmc_config cfg;
 	struct mmc mmc;
-	unsigned int f_max;
 };
 
 struct arasan_sdhci_priv {
 	struct sdhci_host *host;
 	u8 deviceid;
 	u8 bank;
-	u8 no_1p8;
 };
 
 #if defined(CONFIG_ARCH_ZYNQMP)
@@ -238,8 +236,11 @@
 	host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
 #endif
 
-	if (priv->no_1p8)
-		host->quirks |= SDHCI_QUIRK_NO_1_8_V;
+	plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ;
+
+	ret = mmc_of_parse(dev, &plat->cfg);
+	if (ret)
+		return ret;
 
 	host->max_clk = clock;
 
@@ -247,7 +248,7 @@
 	host->mmc->dev = dev;
 	host->mmc->priv = host;
 
-	ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
+	ret = sdhci_setup_cfg(&plat->cfg, host, plat->cfg.f_max,
 			      CONFIG_ZYNQ_SDHCI_MIN_FREQ);
 	if (ret)
 		return ret;
@@ -258,7 +259,6 @@
 
 static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
 {
-	struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
 	struct arasan_sdhci_priv *priv = dev_get_priv(dev);
 
 	priv->host = calloc(1, sizeof(struct sdhci_host));
@@ -277,10 +277,7 @@
 
 	priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
 	priv->bank = dev_read_u32_default(dev, "xlnx,mio_bank", -1);
-	priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
 
-	plat->f_max = dev_read_u32_default(dev, "max-frequency",
-					   CONFIG_ZYNQ_SDHCI_MAX_FREQ);
 	return 0;
 }
 
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index 5232328..7bdebf5 100644
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
@@ -2714,6 +2714,14 @@
 	}
 #endif /* __UBOOT__ */
 
+	/* No chip-selects could initialize properly */
+	if (list_empty(&ctrl->host_list)) {
+		ret = -ENODEV;
+		goto err;
+	}
+
+	return 0;
+
 err:
 #ifndef __UBOOT__
 	clk_disable_unprepare(ctrl->clk);
@@ -2722,7 +2730,6 @@
 		clk_disable(ctrl->clk);
 #endif /* __UBOOT__ */
 	return ret;
-
 }
 EXPORT_SYMBOL_GPL(brcmnand_probe);
 
diff --git a/drivers/mtd/nand/raw/zynq_nand.c b/drivers/mtd/nand/raw/zynq_nand.c
index 0aea83d..3941297 100644
--- a/drivers/mtd/nand/raw/zynq_nand.c
+++ b/drivers/mtd/nand/raw/zynq_nand.c
@@ -845,7 +845,7 @@
 	if (curr_cmd->end_cmd_valid == ZYNQ_NAND_CMD_PHASE)
 		end_cmd_valid = 1;
 
-	if (curr_cmd->end_cmd == NAND_CMD_NONE)
+	if (curr_cmd->end_cmd == (u8)NAND_CMD_NONE)
 		end_cmd = 0x0;
 	else
 		end_cmd = curr_cmd->end_cmd;
diff --git a/drivers/mtd/nand/spi/Makefile b/drivers/mtd/nand/spi/Makefile
index dd6baca..6c65b18 100644
--- a/drivers/mtd/nand/spi/Makefile
+++ b/drivers/mtd/nand/spi/Makefile
@@ -1,4 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0
 
-spinand-objs := core.o gigadevice.o macronix.o micron.o winbond.o
+spinand-objs := core.o gigadevice.o macronix.o micron.o toshiba.o winbond.o
 obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index cd624ec..397dfa4 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -835,6 +835,7 @@
 	&gigadevice_spinand_manufacturer,
 	&macronix_spinand_manufacturer,
 	&micron_spinand_manufacturer,
+	&toshiba_spinand_manufacturer,
 	&winbond_spinand_manufacturer,
 };
 
diff --git a/drivers/mtd/nand/spi/toshiba.c b/drivers/mtd/nand/spi/toshiba.c
new file mode 100644
index 0000000..77c2539
--- /dev/null
+++ b/drivers/mtd/nand/spi/toshiba.c
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 exceet electronics GmbH
+ * Copyright (c) 2018 Kontron Electronics GmbH
+ *
+ * Author: Frieder Schrempf <frieder.schrempf@kontron.de>
+ */
+
+#ifndef __UBOOT__
+#include <malloc.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#endif
+#include <linux/mtd/spinand.h>
+
+#define SPINAND_MFR_TOSHIBA		0x98
+#define TOSH_STATUS_ECC_HAS_BITFLIPS_T	(3 << 4)
+
+static SPINAND_OP_VARIANTS(read_cache_variants,
+		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(write_cache_variants,
+		SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_variants,
+		SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
+static int tc58cxgxsx_ooblayout_ecc(struct mtd_info *mtd, int section,
+				     struct mtd_oob_region *region)
+{
+	if (section > 0)
+		return -ERANGE;
+
+	region->offset = mtd->oobsize / 2;
+	region->length = mtd->oobsize / 2;
+
+	return 0;
+}
+
+static int tc58cxgxsx_ooblayout_free(struct mtd_info *mtd, int section,
+				      struct mtd_oob_region *region)
+{
+	if (section > 0)
+		return -ERANGE;
+
+	/* 2 bytes reserved for BBM */
+	region->offset = 2;
+	region->length = (mtd->oobsize / 2) - 2;
+
+	return 0;
+}
+
+static const struct mtd_ooblayout_ops tc58cxgxsx_ooblayout = {
+	.ecc = tc58cxgxsx_ooblayout_ecc,
+	.rfree = tc58cxgxsx_ooblayout_free,
+};
+
+static int tc58cxgxsx_ecc_get_status(struct spinand_device *spinand,
+				      u8 status)
+{
+	struct nand_device *nand = spinand_to_nand(spinand);
+	u8 mbf = 0;
+	struct spi_mem_op op = SPINAND_GET_FEATURE_OP(0x30, &mbf);
+
+	switch (status & STATUS_ECC_MASK) {
+	case STATUS_ECC_NO_BITFLIPS:
+		return 0;
+
+	case STATUS_ECC_UNCOR_ERROR:
+		return -EBADMSG;
+
+	case STATUS_ECC_HAS_BITFLIPS:
+	case TOSH_STATUS_ECC_HAS_BITFLIPS_T:
+		/*
+		 * Let's try to retrieve the real maximum number of bitflips
+		 * in order to avoid forcing the wear-leveling layer to move
+		 * data around if it's not necessary.
+		 */
+		if (spi_mem_exec_op(spinand->slave, &op))
+			return nand->eccreq.strength;
+
+		mbf >>= 4;
+
+		if (WARN_ON(mbf > nand->eccreq.strength || !mbf))
+			return nand->eccreq.strength;
+
+		return mbf;
+
+	default:
+		break;
+	}
+
+	return -EINVAL;
+}
+
+static const struct spinand_info toshiba_spinand_table[] = {
+	/* 3.3V 1Gb */
+	SPINAND_INFO("TC58CVG0S3", 0xC2,
+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
+				     tc58cxgxsx_ecc_get_status)),
+	/* 3.3V 2Gb */
+	SPINAND_INFO("TC58CVG1S3", 0xCB,
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
+				     tc58cxgxsx_ecc_get_status)),
+	/* 3.3V 4Gb */
+	SPINAND_INFO("TC58CVG2S0", 0xCD,
+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
+				     tc58cxgxsx_ecc_get_status)),
+	/* 3.3V 4Gb */
+	SPINAND_INFO("TC58CVG2S0", 0xED,
+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
+				     tc58cxgxsx_ecc_get_status)),
+	/* 1.8V 1Gb */
+	SPINAND_INFO("TC58CYG0S3", 0xB2,
+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
+				     tc58cxgxsx_ecc_get_status)),
+	/* 1.8V 2Gb */
+	SPINAND_INFO("TC58CYG1S3", 0xBB,
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
+				     tc58cxgxsx_ecc_get_status)),
+	/* 1.8V 4Gb */
+	SPINAND_INFO("TC58CYG2S0", 0xBD,
+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
+				     tc58cxgxsx_ecc_get_status)),
+};
+
+static int toshiba_spinand_detect(struct spinand_device *spinand)
+{
+	u8 *id = spinand->id.data;
+	int ret;
+
+	/*
+	 * Toshiba SPI NAND read ID needs a dummy byte,
+	 * so the first byte in id is garbage.
+	 */
+	if (id[1] != SPINAND_MFR_TOSHIBA)
+		return 0;
+
+	ret = spinand_match_and_init(spinand, toshiba_spinand_table,
+				     ARRAY_SIZE(toshiba_spinand_table),
+				     id[2]);
+	if (ret)
+		return ret;
+
+	return 1;
+}
+
+static const struct spinand_manufacturer_ops toshiba_spinand_manuf_ops = {
+	.detect = toshiba_spinand_detect,
+};
+
+const struct spinand_manufacturer toshiba_spinand_manufacturer = {
+	.id = SPINAND_MFR_TOSHIBA,
+	.name = "Toshiba",
+	.ops = &toshiba_spinand_manuf_ops,
+};
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 7b6ad49..e840c60 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -325,6 +325,7 @@
 	case SNOR_MFR_MICRON:
 		/* Some Micron need WREN command; all will accept it */
 		need_wren = true;
+	case SNOR_MFR_ISSI:
 	case SNOR_MFR_MACRONIX:
 	case SNOR_MFR_WINBOND:
 		if (need_wren)
@@ -1246,11 +1247,8 @@
 		 * If page_size is a power of two, the offset can be quickly
 		 * calculated with an AND operation. On the other cases we
 		 * need to do a modulus operation (more expensive).
-		 * Power of two numbers have only one bit set and we can use
-		 * the instruction hweight32 to detect if we need to do a
-		 * modulus (do_div()) or not.
 		 */
-		if (hweight32(nor->page_size) == 1) {
+		if (is_power_of_2(nor->page_size)) {
 			page_offset = addr & (nor->page_size - 1);
 		} else {
 			u64 aux = addr;
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index abdf560..e5e7102 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -135,7 +135,8 @@
 	{ INFO("is25wp128",  0x9d7018, 0, 64 * 1024, 256,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("is25wp256",  0x9d7019, 0, 64 * 1024, 512,
-			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+			SPI_NOR_4B_OPCODES) },
 #endif
 #ifdef CONFIG_SPI_FLASH_MACRONIX	/* MACRONIX */
 	/* Macronix */
@@ -183,8 +184,8 @@
 	{ INFO("n25q00",      0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 	{ INFO("n25q00a",     0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 	{ INFO("mt25qu02g",   0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
-	{ INFO("mt35xu512aba", 0x2c5b1a, 0,  128 * 1024,  512, USE_FSR | SPI_NOR_4B_OPCODES) },
-	{ INFO("mt35xu02g",  0x2c5b1c, 0, 128 * 1024,  2048, USE_FSR | SPI_NOR_4B_OPCODES) },
+	{ INFO("mt35xu512aba", 0x2c5b1a, 0,  128 * 1024,  512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mt35xu02g",  0x2c5b1c, 0, 128 * 1024,  2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
 #endif
 #ifdef CONFIG_SPI_FLASH_SPANSION	/* SPANSION */
 	/* Spansion/Cypress -- single (large) sector size only, at least
@@ -192,9 +193,10 @@
 	 */
 	{ INFO("s25sl032p",  0x010215, 0x4d00,  64 * 1024,  64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("s25sl064p",  0x010216, 0x4d00,  64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
-	{ INFO("s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
+	{ INFO("s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
 	{ INFO("s25fl256s1", 0x010219, 0x4d01,  64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
-	{ INFO6("s25fl512s",  0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
+	{ INFO6("s25fl512s",  0x010220, 0x4d0080, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
+	{ INFO6("s25fs512s",  0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
 	{ INFO("s25fl512s_256k",  0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
 	{ INFO("s25fl512s_64k",  0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
 	{ INFO("s25fl512s_512k", 0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 4d1013c..a2587a2 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -388,11 +388,13 @@
 
 if SMC911X
 
+if !DM_ETH
 config SMC911X_BASE
 	hex "SMC911X Base Address"
 	help
 	  Define this to hold the physical address
 	  of the device (I/O space)
+endif #DM_ETH
 
 choice
 	prompt "SMC911X bus width"
@@ -640,4 +642,11 @@
 
 	  This driver is used by the MVPP2 and MVNETA drivers.
 
+config FSL_LS_MDIO
+	bool "NXP Layerscape MDIO interface support"
+	depends on DM_MDIO
+	help
+	  This driver supports the MDIO bus found on the Fman 10G Ethernet MACs and
+	  on the mEMAC (which supports both Clauses 22 and 45).
+
 endif # NETDEVICES
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 6e0a688..6d9b877 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -83,3 +83,4 @@
 obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o
 obj-$(CONFIG_MDIO_SANDBOX) += mdio_sandbox.o
 obj-$(CONFIG_FSL_ENETC) += fsl_enetc.o fsl_enetc_mdio.o
+obj-$(CONFIG_FSL_LS_MDIO) += fsl_ls_mdio.o
diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c
index 43c2253..d008696 100644
--- a/drivers/net/dc2114x.c
+++ b/drivers/net/dc2114x.c
@@ -7,24 +7,21 @@
 #include <netdev.h>
 #include <pci.h>
 
-#undef DEBUG_SROM
-#undef DEBUG_SROM2
+#define SROM_DLEVEL	0
 
 #undef UPDATE_SROM
 
-/* PCI Registers.
- */
-#define PCI_CFDA_PSM		0x43
+/* PCI Registers. */
+#define PCI_CFDA_PSM	0x43
 
 #define CFRV_RN		0x000000f0	/* Revision Number */
 
 #define WAKEUP		0x00		/* Power Saving Wakeup */
 #define SLEEP		0x80		/* Power Saving Sleep Mode */
 
-#define DC2114x_BRK	0x0020		/* CFRV break between DC21142 & DC21143 */
+#define DC2114x_BRK	0x0020	/* CFRV break between DC21142 & DC21143 */
 
-/* Ethernet chip registers.
- */
+/* Ethernet chip registers. */
 #define DE4X5_BMR	0x000		/* Bus Mode Register */
 #define DE4X5_TPD	0x008		/* Transmit Poll Demand Reg */
 #define DE4X5_RRBA	0x018		/* RX Ring Base Address Reg */
@@ -34,8 +31,7 @@
 #define DE4X5_SICR	0x068		/* SIA Connectivity Register */
 #define DE4X5_APROM	0x048		/* Ethernet Address PROM */
 
-/* Register bits.
- */
+/* Register bits. */
 #define BMR_SWR		0x00000001	/* Software Reset */
 #define STS_TS		0x00700000	/* Transmit Process State */
 #define STS_RS		0x000e0000	/* Receive Process State */
@@ -45,8 +41,7 @@
 #define OMR_SDP		0x02000000	/* SD Polarity - MUST BE ASSERTED */
 #define OMR_PM		0x00000080	/* Pass All Multicast */
 
-/* Descriptor bits.
- */
+/* Descriptor bits. */
 #define R_OWN		0x80000000	/* Own Bit */
 #define RD_RER		0x02000000	/* Receive End Of Ring */
 #define RD_LS		0x00000100	/* Last Descriptor */
@@ -63,12 +58,12 @@
 #define SROM_READ_CMD	6
 #define SROM_ERASE_CMD	7
 
-#define SROM_HWADD	    0x0014	/* Hardware Address offset in SROM */
+#define SROM_HWADD	0x0014		/* Hardware Address offset in SROM */
 #define SROM_RD		0x00004000	/* Read from Boot ROM */
-#define EE_DATA_WRITE	      0x04	/* EEPROM chip data in. */
-#define EE_WRITE_0	    0x4801
-#define EE_WRITE_1	    0x4805
-#define EE_DATA_READ	      0x08	/* EEPROM chip data out. */
+#define EE_DATA_WRITE	0x04		/* EEPROM chip data in. */
+#define EE_WRITE_0	0x4801
+#define EE_WRITE_1	0x4805
+#define EE_DATA_READ	0x08		/* EEPROM chip data out. */
 #define SROM_SR		0x00000800	/* Select Serial ROM when set */
 
 #define DT_IN		0x00000004	/* Serial Data In */
@@ -77,48 +72,14 @@
 
 #define POLL_DEMAND	1
 
-#ifdef CONFIG_TULIP_FIX_DAVICOM
-#define RESET_DM9102(dev) {\
-    unsigned long i;\
-    i=INL(dev, 0x0);\
-    udelay(1000);\
-    OUTL(dev, i | BMR_SWR, DE4X5_BMR);\
-    udelay(1000);\
-}
+#if defined(CONFIG_E500)
+#define phys_to_bus(a) (a)
 #else
-#define RESET_DE4X5(dev) {\
-    int i;\
-    i=INL(dev, DE4X5_BMR);\
-    udelay(1000);\
-    OUTL(dev, i | BMR_SWR, DE4X5_BMR);\
-    udelay(1000);\
-    OUTL(dev, i, DE4X5_BMR);\
-    udelay(1000);\
-    for (i=0;i<5;i++) {INL(dev, DE4X5_BMR); udelay(10000);}\
-    udelay(1000);\
-}
+#define phys_to_bus(a)	pci_phys_to_mem((pci_dev_t)dev->priv, a)
 #endif
 
-#define START_DE4X5(dev) {\
-    s32 omr; \
-    omr = INL(dev, DE4X5_OMR);\
-    omr |= OMR_ST | OMR_SR;\
-    OUTL(dev, omr, DE4X5_OMR);		/* Enable the TX and/or RX */\
-}
-
-#define STOP_DE4X5(dev) {\
-    s32 omr; \
-    omr = INL(dev, DE4X5_OMR);\
-    omr &= ~(OMR_ST|OMR_SR);\
-    OUTL(dev, omr, DE4X5_OMR);		/* Disable the TX and/or RX */ \
-}
-
 #define NUM_RX_DESC PKTBUFSRX
-#ifndef CONFIG_TULIP_FIX_DAVICOM
-	#define NUM_TX_DESC 1			/* Number of TX descriptors   */
-#else
-	#define NUM_TX_DESC 4
-#endif
+#define NUM_TX_DESC 1			/* Number of TX descriptors   */
 #define RX_BUFF_SZ  PKTSIZE_ALIGN
 
 #define TOUT_LOOP   1000000
@@ -132,455 +93,117 @@
 	u32 next;
 };
 
-static struct de4x5_desc rx_ring[NUM_RX_DESC] __attribute__ ((aligned(32))); /* RX descriptor ring         */
-static struct de4x5_desc tx_ring[NUM_TX_DESC] __attribute__ ((aligned(32))); /* TX descriptor ring         */
-static int rx_new;                             /* RX descriptor ring pointer */
-static int tx_new;                             /* TX descriptor ring pointer */
-
-static char rxRingSize;
-static char txRingSize;
-
-#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM)
-static void  sendto_srom(struct eth_device* dev, u_int command, u_long addr);
-static int   getfrom_srom(struct eth_device* dev, u_long addr);
-static int   do_eeprom_cmd(struct eth_device *dev, u_long ioaddr,int cmd,int cmd_len);
-static int   do_read_eeprom(struct eth_device *dev,u_long ioaddr,int location,int addr_len);
-#endif	/* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */
-#ifdef UPDATE_SROM
-static int   write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value);
-static void  update_srom(struct eth_device *dev, bd_t *bis);
-#endif
-#ifndef CONFIG_TULIP_FIX_DAVICOM
-static int   read_srom(struct eth_device *dev, u_long ioaddr, int index);
-static void  read_hw_addr(struct eth_device* dev, bd_t * bis);
-#endif	/* CONFIG_TULIP_FIX_DAVICOM */
-static void  send_setup_frame(struct eth_device* dev, bd_t * bis);
-
-static int   dc21x4x_init(struct eth_device* dev, bd_t* bis);
-static int   dc21x4x_send(struct eth_device *dev, void *packet, int length);
-static int   dc21x4x_recv(struct eth_device* dev);
-static void  dc21x4x_halt(struct eth_device* dev);
-#ifdef CONFIG_TULIP_SELECT_MEDIA
-extern void  dc21x4x_select_media(struct eth_device* dev);
-#endif
-
-#if defined(CONFIG_E500)
-#define phys_to_bus(a) (a)
-#else
-#define phys_to_bus(a)	pci_phys_to_mem((pci_dev_t)dev->priv, a)
-#endif
-
-static int INL(struct eth_device* dev, u_long addr)
-{
-	return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase));
-}
-
-static void OUTL(struct eth_device* dev, int command, u_long addr)
-{
-	*(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command);
-}
-
-static struct pci_device_id supported[] = {
-	{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST },
-	{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 },
-#ifdef CONFIG_TULIP_FIX_DAVICOM
-	{ PCI_VENDOR_ID_DAVICOM, PCI_DEVICE_ID_DAVICOM_DM9102A },
-#endif
-	{ }
-};
-
-int dc21x4x_initialize(bd_t *bis)
-{
-	int			idx=0;
-	int			card_number = 0;
-	unsigned int		cfrv;
-	unsigned char		timer;
-	pci_dev_t		devbusfn;
-	unsigned int		iobase;
-	unsigned short		status;
-	struct eth_device*	dev;
-
-	while(1) {
-		devbusfn =  pci_find_devices(supported, idx++);
-		if (devbusfn == -1) {
-			break;
-		}
-
-		/* Get the chip configuration revision register. */
-		pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv);
-
-#ifndef CONFIG_TULIP_FIX_DAVICOM
-		if ((cfrv & CFRV_RN) < DC2114x_BRK ) {
-			printf("Error: The chip is not DC21143.\n");
-			continue;
-		}
-#endif
-
-		pci_read_config_word(devbusfn, PCI_COMMAND, &status);
-		status |=
-#ifdef CONFIG_TULIP_USE_IO
-		  PCI_COMMAND_IO |
-#else
-		  PCI_COMMAND_MEMORY |
-#endif
-		  PCI_COMMAND_MASTER;
-		pci_write_config_word(devbusfn, PCI_COMMAND, status);
-
-		pci_read_config_word(devbusfn, PCI_COMMAND, &status);
-#ifdef CONFIG_TULIP_USE_IO
-		if (!(status & PCI_COMMAND_IO)) {
-			printf("Error: Can not enable I/O access.\n");
-			continue;
-		}
-#else
-		if (!(status & PCI_COMMAND_MEMORY)) {
-			printf("Error: Can not enable MEMORY access.\n");
-			continue;
-		}
-#endif
-
-		if (!(status & PCI_COMMAND_MASTER)) {
-			printf("Error: Can not enable Bus Mastering.\n");
-			continue;
-		}
-
-		/* Check the latency timer for values >= 0x60. */
-		pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer);
+/* RX and TX descriptor ring */
+static struct de4x5_desc rx_ring[NUM_RX_DESC] __aligned(32);
+static struct de4x5_desc tx_ring[NUM_TX_DESC] __aligned(32);
+static int rx_new;	/* RX descriptor ring pointer */
+static int tx_new;	/* TX descriptor ring pointer */
 
-		if (timer < 0x60) {
-			pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x60);
-		}
+static char rx_ring_size;
+static char tx_ring_size;
 
-#ifdef CONFIG_TULIP_USE_IO
-		/* read BAR for memory space access */
-		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
-		iobase &= PCI_BASE_ADDRESS_IO_MASK;
-#else
-		/* read BAR for memory space access */
-		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
-		iobase &= PCI_BASE_ADDRESS_MEM_MASK;
-#endif
-		debug ("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
-
-		dev = (struct eth_device*) malloc(sizeof *dev);
-
-		if (!dev) {
-			printf("Can not allocalte memory of dc21x4x\n");
-			break;
-		}
-		memset(dev, 0, sizeof(*dev));
-
-#ifdef CONFIG_TULIP_FIX_DAVICOM
-		sprintf(dev->name, "Davicom#%d", card_number);
-#else
-		sprintf(dev->name, "dc21x4x#%d", card_number);
-#endif
-
-#ifdef CONFIG_TULIP_USE_IO
-		dev->iobase = pci_io_to_phys(devbusfn, iobase);
-#else
-		dev->iobase = pci_mem_to_phys(devbusfn, iobase);
-#endif
-		dev->priv   = (void*) devbusfn;
-		dev->init   = dc21x4x_init;
-		dev->halt   = dc21x4x_halt;
-		dev->send   = dc21x4x_send;
-		dev->recv   = dc21x4x_recv;
-
-		/* Ensure we're not sleeping. */
-		pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
-
-		udelay(10 * 1000);
-
-#ifndef CONFIG_TULIP_FIX_DAVICOM
-		read_hw_addr(dev, bis);
-#endif
-		eth_register(dev);
-
-		card_number++;
-	}
-
-	return card_number;
-}
-
-static int dc21x4x_init(struct eth_device* dev, bd_t* bis)
+static u32 dc2114x_inl(struct eth_device *dev, u32 addr)
 {
-	int		i;
-	int		devbusfn = (int) dev->priv;
-
-	/* Ensure we're not sleeping. */
-	pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
-
-#ifdef CONFIG_TULIP_FIX_DAVICOM
-	RESET_DM9102(dev);
-#else
-	RESET_DE4X5(dev);
-#endif
-
-	if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
-		printf("Error: Cannot reset ethernet controller.\n");
-		return -1;
-	}
-
-#ifdef CONFIG_TULIP_SELECT_MEDIA
-	dc21x4x_select_media(dev);
-#else
-	OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
-#endif
-
-	for (i = 0; i < NUM_RX_DESC; i++) {
-		rx_ring[i].status = cpu_to_le32(R_OWN);
-		rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
-		rx_ring[i].buf = cpu_to_le32(
-			phys_to_bus((u32)net_rx_packets[i]));
-#ifdef CONFIG_TULIP_FIX_DAVICOM
-		rx_ring[i].next = cpu_to_le32(
-			phys_to_bus((u32)&rx_ring[(i + 1) % NUM_RX_DESC]));
-#else
-		rx_ring[i].next = 0;
-#endif
-	}
-
-	for (i=0; i < NUM_TX_DESC; i++) {
-		tx_ring[i].status = 0;
-		tx_ring[i].des1 = 0;
-		tx_ring[i].buf = 0;
-
-#ifdef CONFIG_TULIP_FIX_DAVICOM
-	tx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &tx_ring[(i+1) % NUM_TX_DESC]));
-#else
-		tx_ring[i].next = 0;
-#endif
-	}
-
-	rxRingSize = NUM_RX_DESC;
-	txRingSize = NUM_TX_DESC;
-
-	/* Write the end of list marker to the descriptor lists. */
-	rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
-	tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
-
-	/* Tell the adapter where the TX/RX rings are located. */
-	OUTL(dev, phys_to_bus((u32) &rx_ring), DE4X5_RRBA);
-	OUTL(dev, phys_to_bus((u32) &tx_ring), DE4X5_TRBA);
-
-	START_DE4X5(dev);
-
-	tx_new = 0;
-	rx_new = 0;
-
-	send_setup_frame(dev, bis);
-
-	return 0;
+	return le32_to_cpu(*(volatile u32 *)(addr + dev->iobase));
 }
 
-static int dc21x4x_send(struct eth_device *dev, void *packet, int length)
+static void dc2114x_outl(struct eth_device *dev, u32 command, u32 addr)
 {
-	int		status = -1;
-	int		i;
-
-	if (length <= 0) {
-		printf("%s: bad packet size: %d\n", dev->name, length);
-		goto Done;
-	}
-
-	for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
-		if (i >= TOUT_LOOP) {
-			printf("%s: tx error buffer not ready\n", dev->name);
-			goto Done;
-		}
-	}
-
-	tx_ring[tx_new].buf    = cpu_to_le32(phys_to_bus((u32) packet));
-	tx_ring[tx_new].des1   = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
-	tx_ring[tx_new].status = cpu_to_le32(T_OWN);
-
-	OUTL(dev, POLL_DEMAND, DE4X5_TPD);
-
-	for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
-		if (i >= TOUT_LOOP) {
-			printf(".%s: tx buffer not ready\n", dev->name);
-			goto Done;
-		}
-	}
-
-	if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) {
-#if 0 /* test-only */
-		printf("TX error status = 0x%08X\n",
-			le32_to_cpu(tx_ring[tx_new].status));
-#endif
-		tx_ring[tx_new].status = 0x0;
-		goto Done;
-	}
-
-	status = length;
-
- Done:
-    tx_new = (tx_new+1) % NUM_TX_DESC;
-	return status;
+	*(volatile u32 *)(addr + dev->iobase) = cpu_to_le32(command);
 }
 
-static int dc21x4x_recv(struct eth_device* dev)
+static void reset_de4x5(struct eth_device *dev)
 {
-	s32		status;
-	int		length    = 0;
-
-	for ( ; ; ) {
-		status = (s32)le32_to_cpu(rx_ring[rx_new].status);
-
-		if (status & R_OWN) {
-			break;
-		}
-
-		if (status & RD_LS) {
-			/* Valid frame status.
-			 */
-			if (status & RD_ES) {
-
-				/* There was an error.
-				 */
-				printf("RX error status = 0x%08X\n", status);
-			} else {
-				/* A valid frame received.
-				 */
-				length = (le32_to_cpu(rx_ring[rx_new].status) >> 16);
-
-				/* Pass the packet up to the protocol
-				 * layers.
-				 */
-				net_process_received_packet(
-					net_rx_packets[rx_new], length - 4);
-			}
+	u32 i;
 
-			/* Change buffer ownership for this frame, back
-			 * to the adapter.
-			 */
-			rx_ring[rx_new].status = cpu_to_le32(R_OWN);
-		}
+	i = dc2114x_inl(dev, DE4X5_BMR);
+	mdelay(1);
+	dc2114x_outl(dev, i | BMR_SWR, DE4X5_BMR);
+	mdelay(1);
+	dc2114x_outl(dev, i, DE4X5_BMR);
+	mdelay(1);
 
-		/* Update entry information.
-		 */
-		rx_new = (rx_new + 1) % rxRingSize;
+	for (i = 0; i < 5; i++) {
+		dc2114x_inl(dev, DE4X5_BMR);
+		mdelay(10);
 	}
 
-	return length;
+	mdelay(1);
 }
 
-static void dc21x4x_halt(struct eth_device* dev)
+static void start_de4x5(struct eth_device *dev)
 {
-	int		devbusfn = (int) dev->priv;
+	u32 omr;
 
-	STOP_DE4X5(dev);
-	OUTL(dev, 0, DE4X5_SICR);
-
-	pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP);
+	omr = dc2114x_inl(dev, DE4X5_OMR);
+	omr |= OMR_ST | OMR_SR;
+	dc2114x_outl(dev, omr, DE4X5_OMR);	/* Enable the TX and/or RX */
 }
 
-static void send_setup_frame(struct eth_device* dev, bd_t *bis)
+static void stop_de4x5(struct eth_device *dev)
 {
-	int		i;
-	char	setup_frame[SETUP_FRAME_LEN];
-	char	*pa = &setup_frame[0];
-
-	memset(pa, 0xff, SETUP_FRAME_LEN);
+	u32 omr;
 
-	for (i = 0; i < ETH_ALEN; i++) {
-		*(pa + (i & 1)) = dev->enetaddr[i];
-		if (i & 0x01) {
-			pa += 4;
-		}
-	}
-
-	for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
-		if (i >= TOUT_LOOP) {
-			printf("%s: tx error buffer not ready\n", dev->name);
-			goto Done;
-		}
-	}
-
-	tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) &setup_frame[0]));
-	tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN);
-	tx_ring[tx_new].status = cpu_to_le32(T_OWN);
-
-	OUTL(dev, POLL_DEMAND, DE4X5_TPD);
-
-	for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
-		if (i >= TOUT_LOOP) {
-			printf("%s: tx buffer not ready\n", dev->name);
-			goto Done;
-		}
-	}
-
-	if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) {
-		printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[tx_new].status));
-	}
-	tx_new = (tx_new+1) % NUM_TX_DESC;
-
-Done:
-	return;
+	omr = dc2114x_inl(dev, DE4X5_OMR);
+	omr &= ~(OMR_ST | OMR_SR);
+	dc2114x_outl(dev, omr, DE4X5_OMR);	/* Disable the TX and/or RX */
 }
 
-#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM)
-/* SROM Read and write routines.
- */
-static void
-sendto_srom(struct eth_device* dev, u_int command, u_long addr)
+/* SROM Read and write routines. */
+static void sendto_srom(struct eth_device *dev, u_int command, u_long addr)
 {
-	OUTL(dev, command, addr);
+	dc2114x_outl(dev, command, addr);
 	udelay(1);
 }
 
-static int
-getfrom_srom(struct eth_device* dev, u_long addr)
+static int getfrom_srom(struct eth_device *dev, u_long addr)
 {
-	s32 tmp;
+	u32 tmp = dc2114x_inl(dev, addr);
 
-	tmp = INL(dev, addr);
 	udelay(1);
-
 	return tmp;
 }
 
 /* Note: this routine returns extra data bits for size detection. */
-static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len)
+static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location,
+			  int addr_len)
 {
-	int i;
-	unsigned retval = 0;
 	int read_cmd = location | (SROM_READ_CMD << addr_len);
+	unsigned int retval = 0;
+	int i;
 
 	sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
 	sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
 
-#ifdef DEBUG_SROM
-	printf(" EEPROM read at %d ", location);
-#endif
+	debug_cond(SROM_DLEVEL >= 1, " EEPROM read at %d ", location);
 
 	/* Shift the read command bits out. */
 	for (i = 4 + addr_len; i >= 0; i--) {
 		short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
-		sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval, ioaddr);
+
+		sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval,
+			    ioaddr);
 		udelay(10);
-		sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK, ioaddr);
+		sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK,
+			    ioaddr);
 		udelay(10);
-#ifdef DEBUG_SROM2
-		printf("%X", getfrom_srom(dev, ioaddr) & 15);
-#endif
-		retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
+		debug_cond(SROM_DLEVEL >= 2, "%X",
+			   getfrom_srom(dev, ioaddr) & 15);
+		retval = (retval << 1) |
+			 !!(getfrom_srom(dev, ioaddr) & EE_DATA_READ);
 	}
 
 	sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
 
-#ifdef DEBUG_SROM2
-	printf(" :%X:", getfrom_srom(dev, ioaddr) & 15);
-#endif
+	debug_cond(SROM_DLEVEL >= 2, " :%X:", getfrom_srom(dev, ioaddr) & 15);
 
 	for (i = 16; i > 0; i--) {
 		sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
 		udelay(10);
-#ifdef DEBUG_SROM2
-		printf("%X", getfrom_srom(dev, ioaddr) & 15);
-#endif
-		retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
+		debug_cond(SROM_DLEVEL >= 2, "%X",
+			   getfrom_srom(dev, ioaddr) & 15);
+		retval = (retval << 1) |
+			 !!(getfrom_srom(dev, ioaddr) & EE_DATA_READ);
 		sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
 		udelay(10);
 	}
@@ -588,145 +211,115 @@
 	/* Terminate the EEPROM access. */
 	sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
 
-#ifdef DEBUG_SROM2
-	printf(" EEPROM value at %d is %5.5x.\n", location, retval);
-#endif
+	debug_cond(SROM_DLEVEL >= 2, " EEPROM value at %d is %5.5x.\n",
+		   location, retval);
 
 	return retval;
 }
-#endif	/* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */
 
-/* This executes a generic EEPROM command, typically a write or write
+/*
+ * This executes a generic EEPROM command, typically a write or write
  * enable. It returns the data output from the EEPROM, and thus may
  * also be used for reads.
  */
-#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM)
-static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len)
+static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd,
+			 int cmd_len)
 {
-	unsigned retval = 0;
+	unsigned int retval = 0;
 
-#ifdef DEBUG_SROM
-	printf(" EEPROM op 0x%x: ", cmd);
-#endif
+	debug_cond(SROM_DLEVEL >= 1, " EEPROM op 0x%x: ", cmd);
 
-	sendto_srom(dev,SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
+	sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
 
 	/* Shift the command bits out. */
 	do {
-		short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
-		sendto_srom(dev,dataval, ioaddr);
+		short dataval = (cmd & BIT(cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
+
+		sendto_srom(dev, dataval, ioaddr);
 		udelay(10);
 
-#ifdef DEBUG_SROM2
-		printf("%X", getfrom_srom(dev,ioaddr) & 15);
-#endif
+		debug_cond(SROM_DLEVEL >= 2, "%X",
+			   getfrom_srom(dev, ioaddr) & 15);
 
-		sendto_srom(dev,dataval | DT_CLK, ioaddr);
+		sendto_srom(dev, dataval | DT_CLK, ioaddr);
 		udelay(10);
-		retval = (retval << 1) | ((getfrom_srom(dev,ioaddr) & EE_DATA_READ) ? 1 : 0);
+		retval = (retval << 1) |
+			 !!(getfrom_srom(dev, ioaddr) & EE_DATA_READ);
 	} while (--cmd_len >= 0);
-	sendto_srom(dev,SROM_RD | SROM_SR | DT_CS, ioaddr);
+
+	sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
 
 	/* Terminate the EEPROM access. */
-	sendto_srom(dev,SROM_RD | SROM_SR, ioaddr);
+	sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
 
-#ifdef DEBUG_SROM
-	printf(" EEPROM result is 0x%5.5x.\n", retval);
-#endif
+	debug_cond(SROM_DLEVEL >= 1, " EEPROM result is 0x%5.5x.\n", retval);
 
 	return retval;
 }
-#endif	/* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */
 
-#ifndef CONFIG_TULIP_FIX_DAVICOM
 static int read_srom(struct eth_device *dev, u_long ioaddr, int index)
 {
-	int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
+	int ee_addr_size;
 
-	return do_eeprom_cmd(dev, ioaddr,
-			     (((SROM_READ_CMD << ee_addr_size) | index) << 16)
-			     | 0xffff, 3 + ee_addr_size + 16);
+	ee_addr_size = (do_read_eeprom(dev, ioaddr, 0xff, 8) & BIT(18)) ? 8 : 6;
+
+	return do_eeprom_cmd(dev, ioaddr, 0xffff |
+			     (((SROM_READ_CMD << ee_addr_size) | index) << 16),
+			     3 + ee_addr_size + 16);
 }
-#endif	/* CONFIG_TULIP_FIX_DAVICOM */
 
 #ifdef UPDATE_SROM
-static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value)
+static int write_srom(struct eth_device *dev, u_long ioaddr, int index,
+		      int new_value)
 {
-	int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
-	int i;
 	unsigned short newval;
+	int ee_addr_size;
+	int i;
 
-	udelay(10*1000); /* test-only */
+	ee_addr_size = (do_read_eeprom(dev, ioaddr, 0xff, 8) & BIT(18)) ? 8 : 6;
 
-#ifdef DEBUG_SROM
-	printf("ee_addr_size=%d.\n", ee_addr_size);
-	printf("Writing new entry 0x%4.4x to offset %d.\n", new_value, index);
-#endif
+	udelay(10 * 1000); /* test-only */
+
+	debug_cond(SROM_DLEVEL >= 1, "ee_addr_size=%d.\n", ee_addr_size);
+	debug_cond(SROM_DLEVEL >= 1,
+		   "Writing new entry 0x%4.4x to offset %d.\n",
+		   new_value, index);
 
 	/* Enable programming modes. */
-	do_eeprom_cmd(dev, ioaddr, (0x4f << (ee_addr_size-4)), 3+ee_addr_size);
+	do_eeprom_cmd(dev, ioaddr, 0x4f << (ee_addr_size - 4),
+		      3 + ee_addr_size);
 
 	/* Do the actual write. */
-	do_eeprom_cmd(dev, ioaddr,
-		      (((SROM_WRITE_CMD<<ee_addr_size)|index) << 16) | new_value,
+	do_eeprom_cmd(dev, ioaddr, new_value |
+		      (((SROM_WRITE_CMD << ee_addr_size) | index) << 16),
 		      3 + ee_addr_size + 16);
 
 	/* Poll for write finished. */
 	sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
-	for (i = 0; i < 10000; i++)			/* Typical 2000 ticks */
+	for (i = 0; i < 10000; i++) {	/* Typical 2000 ticks */
 		if (getfrom_srom(dev, ioaddr) & EE_DATA_READ)
 			break;
+	}
 
-#ifdef DEBUG_SROM
-	printf(" Write finished after %d ticks.\n", i);
-#endif
+	debug_cond(SROM_DLEVEL >= 1, " Write finished after %d ticks.\n", i);
 
 	/* Disable programming. */
-	do_eeprom_cmd(dev, ioaddr, (0x40 << (ee_addr_size-4)), 3 + ee_addr_size);
+	do_eeprom_cmd(dev, ioaddr, (0x40 << (ee_addr_size - 4)),
+		      3 + ee_addr_size);
 
 	/* And read the result. */
 	newval = do_eeprom_cmd(dev, ioaddr,
-			       (((SROM_READ_CMD<<ee_addr_size)|index) << 16)
+			       (((SROM_READ_CMD << ee_addr_size) | index) << 16)
 			       | 0xffff, 3 + ee_addr_size + 16);
-#ifdef DEBUG_SROM
-	printf("  New value at offset %d is %4.4x.\n", index, newval);
-#endif
-	return 1;
-}
-#endif
-
-#ifndef CONFIG_TULIP_FIX_DAVICOM
-static void read_hw_addr(struct eth_device *dev, bd_t *bis)
-{
-	u_short tmp, *p = (u_short *)(&dev->enetaddr[0]);
-	int i, j = 0;
 
-	for (i = 0; i < (ETH_ALEN >> 1); i++) {
-		tmp = read_srom(dev, DE4X5_APROM, ((SROM_HWADD >> 1) + i));
-		*p = le16_to_cpu(tmp);
-		j += *p++;
-	}
+	debug_cond(SROM_DLEVEL >= 1, "  New value at offset %d is %4.4x.\n",
+		   index, newval);
 
-	if ((j == 0) || (j == 0x2fffd)) {
-		memset (dev->enetaddr, 0, ETH_ALEN);
-		debug ("Warning: can't read HW address from SROM.\n");
-		goto Done;
-	}
-
-	return;
-
-Done:
-#ifdef UPDATE_SROM
-	update_srom(dev, bis);
-#endif
-	return;
+	return 1;
 }
-#endif	/* CONFIG_TULIP_FIX_DAVICOM */
 
-#ifdef UPDATE_SROM
 static void update_srom(struct eth_device *dev, bd_t *bis)
 {
-	int i;
 	static unsigned short eeprom[0x40] = {
 		0x140b, 0x6610, 0x0000, 0x0000,	/* 00 */
 		0x0000, 0x0000, 0x0000, 0x0000,	/* 04 */
@@ -746,16 +339,318 @@
 		0x0000, 0x0000, 0x0000, 0x4e07,	/* 3c */
 	};
 	uchar enetaddr[6];
+	int i;
 
 	/* Ethernet Addr... */
 	if (!eth_env_get_enetaddr("ethaddr", enetaddr))
 		return;
+
 	eeprom[0x0a] = (enetaddr[1] << 8) | enetaddr[0];
 	eeprom[0x0b] = (enetaddr[3] << 8) | enetaddr[2];
 	eeprom[0x0c] = (enetaddr[5] << 8) | enetaddr[4];
 
-	for (i=0; i<0x40; i++) {
+	for (i = 0; i < 0x40; i++)
 		write_srom(dev, DE4X5_APROM, i, eeprom[i]);
+}
+#endif /* UPDATE_SROM */
+
+static void send_setup_frame(struct eth_device *dev, bd_t *bis)
+{
+	char setup_frame[SETUP_FRAME_LEN];
+	char *pa = &setup_frame[0];
+	int i;
+
+	memset(pa, 0xff, SETUP_FRAME_LEN);
+
+	for (i = 0; i < ETH_ALEN; i++) {
+		*(pa + (i & 1)) = dev->enetaddr[i];
+		if (i & 0x01)
+			pa += 4;
+	}
+
+	for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
+		if (i < TOUT_LOOP)
+			continue;
+
+		printf("%s: tx error buffer not ready\n", dev->name);
+		return;
+	}
+
+	tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32)&setup_frame[0]));
+	tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET | SETUP_FRAME_LEN);
+	tx_ring[tx_new].status = cpu_to_le32(T_OWN);
+
+	dc2114x_outl(dev, POLL_DEMAND, DE4X5_TPD);
+
+	for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
+		if (i < TOUT_LOOP)
+			continue;
+
+		printf("%s: tx buffer not ready\n", dev->name);
+		return;
+	}
+
+	if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) {
+		printf("TX error status2 = 0x%08X\n",
+		       le32_to_cpu(tx_ring[tx_new].status));
+	}
+
+	tx_new = (tx_new + 1) % NUM_TX_DESC;
+}
+
+static int dc21x4x_send(struct eth_device *dev, void *packet, int length)
+{
+	int status = -1;
+	int i;
+
+	if (length <= 0) {
+		printf("%s: bad packet size: %d\n", dev->name, length);
+		goto done;
+	}
+
+	for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
+		if (i < TOUT_LOOP)
+			continue;
+
+		printf("%s: tx error buffer not ready\n", dev->name);
+		goto done;
+	}
+
+	tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32)packet));
+	tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
+	tx_ring[tx_new].status = cpu_to_le32(T_OWN);
+
+	dc2114x_outl(dev, POLL_DEMAND, DE4X5_TPD);
+
+	for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
+		if (i < TOUT_LOOP)
+			continue;
+
+		printf(".%s: tx buffer not ready\n", dev->name);
+		goto done;
 	}
+
+	if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) {
+		tx_ring[tx_new].status = 0x0;
+		goto done;
+	}
+
+	status = length;
+
+done:
+	tx_new = (tx_new + 1) % NUM_TX_DESC;
+	return status;
+}
+
+static int dc21x4x_recv(struct eth_device *dev)
+{
+	int length = 0;
+	u32 status;
+
+	while (true) {
+		status = le32_to_cpu(rx_ring[rx_new].status);
+
+		if (status & R_OWN)
+			break;
+
+		if (status & RD_LS) {
+			/* Valid frame status. */
+			if (status & RD_ES) {
+				/* There was an error. */
+				printf("RX error status = 0x%08X\n", status);
+			} else {
+				/* A valid frame received. */
+				length = (le32_to_cpu(rx_ring[rx_new].status)
+					  >> 16);
+
+				/* Pass the packet up to the protocol layers */
+				net_process_received_packet
+					(net_rx_packets[rx_new], length - 4);
+			}
+
+			/*
+			 * Change buffer ownership for this frame,
+			 * back to the adapter.
+			 */
+			rx_ring[rx_new].status = cpu_to_le32(R_OWN);
+		}
+
+		/* Update entry information. */
+		rx_new = (rx_new + 1) % rx_ring_size;
+	}
+
+	return length;
+}
+
+static int dc21x4x_init(struct eth_device *dev, bd_t *bis)
+{
+	int i;
+	int devbusfn = (int)dev->priv;
+
+	/* Ensure we're not sleeping. */
+	pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
+
+	reset_de4x5(dev);
+
+	if (dc2114x_inl(dev, DE4X5_STS) & (STS_TS | STS_RS)) {
+		printf("Error: Cannot reset ethernet controller.\n");
+		return -1;
+	}
+
+	dc2114x_outl(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
+
+	for (i = 0; i < NUM_RX_DESC; i++) {
+		rx_ring[i].status = cpu_to_le32(R_OWN);
+		rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
+		rx_ring[i].buf =
+			cpu_to_le32(phys_to_bus((u32)net_rx_packets[i]));
+		rx_ring[i].next = 0;
+	}
+
+	for (i = 0; i < NUM_TX_DESC; i++) {
+		tx_ring[i].status = 0;
+		tx_ring[i].des1 = 0;
+		tx_ring[i].buf = 0;
+		tx_ring[i].next = 0;
+	}
+
+	rx_ring_size = NUM_RX_DESC;
+	tx_ring_size = NUM_TX_DESC;
+
+	/* Write the end of list marker to the descriptor lists. */
+	rx_ring[rx_ring_size - 1].des1 |= cpu_to_le32(RD_RER);
+	tx_ring[tx_ring_size - 1].des1 |= cpu_to_le32(TD_TER);
+
+	/* Tell the adapter where the TX/RX rings are located. */
+	dc2114x_outl(dev, phys_to_bus((u32)&rx_ring), DE4X5_RRBA);
+	dc2114x_outl(dev, phys_to_bus((u32)&tx_ring), DE4X5_TRBA);
+
+	start_de4x5(dev);
+
+	tx_new = 0;
+	rx_new = 0;
+
+	send_setup_frame(dev, bis);
+
+	return 0;
+}
+
+static void dc21x4x_halt(struct eth_device *dev)
+{
+	int devbusfn = (int)dev->priv;
+
+	stop_de4x5(dev);
+	dc2114x_outl(dev, 0, DE4X5_SICR);
+
+	pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP);
+}
+
+static void read_hw_addr(struct eth_device *dev, bd_t *bis)
+{
+	u_short tmp, *p = (u_short *)(&dev->enetaddr[0]);
+	int i, j = 0;
+
+	for (i = 0; i < (ETH_ALEN >> 1); i++) {
+		tmp = read_srom(dev, DE4X5_APROM, (SROM_HWADD >> 1) + i);
+		*p = le16_to_cpu(tmp);
+		j += *p++;
+	}
+
+	if (!j || j == 0x2fffd) {
+		memset(dev->enetaddr, 0, ETH_ALEN);
+		debug("Warning: can't read HW address from SROM.\n");
+#ifdef UPDATE_SROM
+		update_srom(dev, bis);
+#endif
+	}
+}
+
+static struct pci_device_id supported[] = {
+	{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST },
+	{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 },
+	{ }
+};
+
+int dc21x4x_initialize(bd_t *bis)
+{
+	struct eth_device *dev;
+	unsigned short status;
+	unsigned char timer;
+	unsigned int iobase;
+	int card_number = 0;
+	pci_dev_t devbusfn;
+	unsigned int cfrv;
+	int idx = 0;
+
+	while (1) {
+		devbusfn = pci_find_devices(supported, idx++);
+		if (devbusfn == -1)
+			break;
+
+		/* Get the chip configuration revision register. */
+		pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv);
+
+		if ((cfrv & CFRV_RN) < DC2114x_BRK) {
+			printf("Error: The chip is not DC21143.\n");
+			continue;
+		}
+
+		pci_read_config_word(devbusfn, PCI_COMMAND, &status);
+		status |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+		pci_write_config_word(devbusfn, PCI_COMMAND, status);
+
+		pci_read_config_word(devbusfn, PCI_COMMAND, &status);
+		if (!(status & PCI_COMMAND_MEMORY)) {
+			printf("Error: Can not enable MEMORY access.\n");
+			continue;
+		}
+
+		if (!(status & PCI_COMMAND_MASTER)) {
+			printf("Error: Can not enable Bus Mastering.\n");
+			continue;
+		}
+
+		/* Check the latency timer for values >= 0x60. */
+		pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer);
+
+		if (timer < 0x60) {
+			pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER,
+					      0x60);
+		}
+
+		/* read BAR for memory space access */
+		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
+		iobase &= PCI_BASE_ADDRESS_MEM_MASK;
+		debug("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
+
+		dev = (struct eth_device *)malloc(sizeof(*dev));
+		if (!dev) {
+			printf("Can not allocalte memory of dc21x4x\n");
+			break;
+		}
+
+		memset(dev, 0, sizeof(*dev));
+
+		sprintf(dev->name, "dc21x4x#%d", card_number);
+
+		dev->iobase = pci_mem_to_phys(devbusfn, iobase);
+		dev->priv = (void *)devbusfn;
+		dev->init = dc21x4x_init;
+		dev->halt = dc21x4x_halt;
+		dev->send = dc21x4x_send;
+		dev->recv = dc21x4x_recv;
+
+		/* Ensure we're not sleeping. */
+		pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
+
+		udelay(10 * 1000);
+
+		read_hw_addr(dev, bis);
+
+		eth_register(dev);
+
+		card_number++;
+	}
+
+	return card_number;
 }
-#endif	/* UPDATE_SROM */
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 63f2086..60dfd17 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1288,9 +1288,9 @@
 		struct eqos_desc *rx_desc = &(eqos->rx_descs[i]);
 		rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
 					     (i * EQOS_MAX_PACKET_SIZE));
-		rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
+		rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
+		eqos->config->ops->eqos_flush_desc(rx_desc);
 	}
-	eqos->config->ops->eqos_flush_desc(eqos->descs);
 
 	writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress);
 	writel((ulong)eqos->tx_descs, &eqos->dma_regs->ch0_txdesc_list_address);
@@ -1419,7 +1419,8 @@
 	tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | length;
 	eqos->config->ops->eqos_flush_desc(tx_desc);
 
-	writel((ulong)(tx_desc + 1), &eqos->dma_regs->ch0_txdesc_tail_pointer);
+	writel((ulong)(&(eqos->tx_descs[eqos->tx_desc_idx])),
+		&eqos->dma_regs->ch0_txdesc_tail_pointer);
 
 	for (i = 0; i < 1000000; i++) {
 		eqos->config->ops->eqos_inval_desc(tx_desc);
@@ -1442,6 +1443,7 @@
 	debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags);
 
 	rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
+	eqos->config->ops->eqos_inval_desc(rx_desc);
 	if (rx_desc->des3 & EQOS_DESC3_OWN) {
 		debug("%s: RX packet not available\n", __func__);
 		return -EAGAIN;
@@ -1474,6 +1476,11 @@
 	}
 
 	rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
+
+	rx_desc->des0 = 0;
+	mb();
+	eqos->config->ops->eqos_flush_desc(rx_desc);
+	eqos->config->ops->eqos_inval_buffer(packet, length);
 	rx_desc->des0 = (u32)(ulong)packet;
 	rx_desc->des1 = 0;
 	rx_desc->des2 = 0;
@@ -1482,7 +1489,7 @@
 	 * writes to the rest of the descriptor too.
 	 */
 	mb();
-	rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
+	rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
 	eqos->config->ops->eqos_flush_desc(rx_desc);
 
 	writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
@@ -1536,6 +1543,9 @@
 	}
 	debug("%s: rx_pkt=%p\n", __func__, eqos->rx_pkt);
 
+	eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf,
+			EQOS_MAX_PACKET_SIZE * EQOS_DESCRIPTORS_RX);
+
 	debug("%s: OK\n", __func__);
 	return 0;
 
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 88019c9..5f1a023 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -1,10 +1,17 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2009-2012 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  *	Dave Liu <daveliu@freescale.com>
  */
 #include <common.h>
 #include <asm/io.h>
+#ifdef CONFIG_DM_ETH
+#include <dm.h>
+#include <dm/ofnode.h>
+#include <linux/compat.h>
+#include <phy_interface.h>
+#endif
 #include <malloc.h>
 #include <net.h>
 #include <hwconfig.h>
@@ -18,8 +25,10 @@
 
 #include "fm.h"
 
+#ifndef CONFIG_DM_ETH
 static struct eth_device *devlist[NUM_FM_PORTS];
 static int num_controllers;
+#endif
 
 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
 
@@ -37,10 +46,18 @@
 #ifdef CONFIG_SYS_FMAN_V3
 	u32 value;
 	struct mii_dev bus;
-	bus.priv = priv->mac->phyregs;
 	bool sgmii_2500 = (priv->enet_if ==
 			PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
-	int i = 0;
+	int i = 0, j;
+
+#ifndef CONFIG_DM_ETH
+	bus.priv = priv->mac->phyregs;
+#else
+	bus.priv = priv->pcs_mdio;
+#endif
+	bus.read = memac_mdio_read;
+	bus.write = memac_mdio_write;
+	bus.reset = memac_mdio_reset;
 
 qsgmii_loop:
 	/* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
@@ -51,6 +68,10 @@
 	else
 		value = PHY_SGMII_IF_MODE_SGMII | PHY_SGMII_IF_MODE_AN;
 
+	for (j = 0; j <= 3; j++)
+		debug("dump PCS reg %#x: %#x\n", j,
+		      memac_mdio_read(&bus, i, MDIO_DEVAD_NONE, j));
+
 	memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x14, value);
 
 	/* Dev ability according to SGMII specification */
@@ -98,9 +119,8 @@
 #endif
 }
 
-static void dtsec_init_phy(struct eth_device *dev)
+static void dtsec_init_phy(struct fm_eth *fm_eth)
 {
-	struct fm_eth *fm_eth = dev->priv;
 #ifndef CONFIG_SYS_FMAN_V3
 	struct dtsec *regs = (struct dtsec *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
 
@@ -114,10 +134,10 @@
 		dtsec_configure_serdes(fm_eth);
 }
 
+#ifndef CONFIG_DM_ETH
 #ifdef CONFIG_PHYLIB
-static int tgec_is_fibre(struct eth_device *dev)
+static int tgec_is_fibre(struct fm_eth *fm)
 {
-	struct fm_eth *fm = dev->priv;
 	char phyopt[20];
 
 	sprintf(phyopt, "fsl_fm%d_xaui_phy", fm->fm_index + 1);
@@ -125,6 +145,7 @@
 	return hwconfig_arg_cmp(phyopt, "xfi");
 }
 #endif
+#endif /* CONFIG_DM_ETH */
 #endif
 
 static u16 muram_readw(u16 *addr)
@@ -168,6 +189,8 @@
 	/* wait until the rx port is not busy */
 	while ((in_be32(&rx_port->fmbm_rst) & FMBM_RST_BSY) && timeout--)
 		;
+	if (!timeout)
+		printf("%s - timeout\n", __func__);
 }
 
 static void bmi_rx_port_init(struct fm_bmi_rx_port *rx_port)
@@ -196,6 +219,8 @@
 	/* wait until the tx port is not busy */
 	while ((in_be32(&tx_port->fmbm_tst) & FMBM_TST_BSY) && timeout--)
 		;
+	if (!timeout)
+		printf("%s - timeout\n", __func__);
 }
 
 static void bmi_tx_port_init(struct fm_bmi_tx_port *tx_port)
@@ -435,23 +460,39 @@
 	sync();
 }
 
+#ifndef CONFIG_DM_ETH
 static int fm_eth_open(struct eth_device *dev, bd_t *bd)
+#else
+static int fm_eth_open(struct udevice *dev)
+#endif
 {
-	struct fm_eth *fm_eth;
+#ifndef CONFIG_DM_ETH
+	struct fm_eth *fm_eth = dev->priv;
+#else
+	struct eth_pdata *pdata = dev_get_platdata(dev);
+	struct fm_eth *fm_eth = dev_get_priv(dev);
+#endif
+	unsigned char *enetaddr;
 	struct fsl_enet_mac *mac;
 #ifdef CONFIG_PHYLIB
 	int ret;
 #endif
 
-	fm_eth = (struct fm_eth *)dev->priv;
 	mac = fm_eth->mac;
 
+#ifndef CONFIG_DM_ETH
+	enetaddr = &dev->enetaddr[0];
+#else
+	enetaddr = pdata->enetaddr;
+#endif
+
 	/* setup the MAC address */
-	if (dev->enetaddr[0] & 0x01) {
-		printf("%s: MacAddress is multcast address\n",	__func__);
-		return 1;
+	if (enetaddr[0] & 0x01) {
+		printf("%s: MacAddress is multicast address\n",	__func__);
+		enetaddr[0] = 0;
+		enetaddr[5] = fm_eth->num;
 	}
-	mac->set_mac_addr(mac, dev->enetaddr);
+	mac->set_mac_addr(mac, enetaddr);
 
 	/* enable bmi Rx port */
 	setbits_be32(&fm_eth->rx_port->fmbm_rcfg, FMBM_RCFG_EN);
@@ -466,8 +507,12 @@
 	if (fm_eth->phydev) {
 		ret = phy_startup(fm_eth->phydev);
 		if (ret) {
+#ifndef CONFIG_DM_ETH
 			printf("%s: Could not initialize\n",
 			       fm_eth->phydev->dev->name);
+#else
+			printf("%s: Could not initialize\n", dev->name);
+#endif
 			return ret;
 		}
 	} else {
@@ -481,6 +526,8 @@
 
 	/* set the MAC-PHY mode */
 	mac->set_if_mode(mac, fm_eth->enet_if, fm_eth->phydev->speed);
+	debug("MAC IF mode %d, speed %d, link %d\n", fm_eth->enet_if,
+	      fm_eth->phydev->speed, fm_eth->phydev->link);
 
 	if (!fm_eth->phydev->link)
 		printf("%s: No link.\n", fm_eth->phydev->dev->name);
@@ -488,7 +535,11 @@
 	return fm_eth->phydev->link ? 0 : -1;
 }
 
+#ifndef CONFIG_DM_ETH
 static void fm_eth_halt(struct eth_device *dev)
+#else
+static void fm_eth_halt(struct udevice *dev)
+#endif
 {
 	struct fm_eth *fm_eth;
 	struct fsl_enet_mac *mac;
@@ -511,7 +562,11 @@
 #endif
 }
 
+#ifndef CONFIG_DM_ETH
 static int fm_eth_send(struct eth_device *dev, void *buf, int len)
+#else
+static int fm_eth_send(struct udevice *dev, void *buf, int len)
+#endif
 {
 	struct fm_eth *fm_eth;
 	struct fm_port_global_pram *pram;
@@ -569,20 +624,50 @@
 	return 1;
 }
 
-static int fm_eth_recv(struct eth_device *dev)
+static struct fm_port_bd *fm_eth_free_one(struct fm_eth *fm_eth,
+					  struct fm_port_bd *rxbd)
 {
-	struct fm_eth *fm_eth;
 	struct fm_port_global_pram *pram;
-	struct fm_port_bd *rxbd, *rxbd_base;
-	u16 status, len;
-	u32 buf_lo, buf_hi;
-	u8 *data;
+	struct fm_port_bd *rxbd_base;
 	u16 offset_out;
-	int ret = 1;
 
-	fm_eth = (struct fm_eth *)dev->priv;
 	pram = fm_eth->rx_pram;
-	rxbd = fm_eth->cur_rxbd;
+
+	/* clear the RxBDs */
+	muram_writew(&rxbd->status, RxBD_EMPTY);
+	muram_writew(&rxbd->len, 0);
+	sync();
+
+	/* advance RxBD */
+	rxbd++;
+	rxbd_base = (struct fm_port_bd *)fm_eth->rx_bd_ring;
+	if (rxbd >= (rxbd_base + RX_BD_RING_SIZE))
+		rxbd = rxbd_base;
+
+	/* update RxQD */
+	offset_out = muram_readw(&pram->rxqd.offset_out);
+	offset_out += sizeof(struct fm_port_bd);
+	if (offset_out >= muram_readw(&pram->rxqd.bd_ring_size))
+		offset_out = 0;
+	muram_writew(&pram->rxqd.offset_out, offset_out);
+	sync();
+
+	return rxbd;
+}
+
+#ifndef CONFIG_DM_ETH
+static int fm_eth_recv(struct eth_device *dev)
+#else
+static int fm_eth_recv(struct udevice *dev, int flags, uchar **packetp)
+#endif
+{
+	struct fm_eth *fm_eth = (struct fm_eth *)dev->priv;
+	struct fm_port_bd *rxbd = fm_eth->cur_rxbd;
+	u32 buf_lo, buf_hi;
+	u16 status, len;
+	int ret = -1;
+	u8 *data;
+
 	status = muram_readw(&rxbd->status);
 
 	while (!(status & RxBD_EMPTY)) {
@@ -591,38 +676,40 @@
 			buf_lo = in_be32(&rxbd->buf_ptr_lo);
 			data = (u8 *)((ulong)(buf_hi << 16) << 16 | buf_lo);
 			len = muram_readw(&rxbd->len);
+#ifndef CONFIG_DM_ETH
 			net_process_received_packet(data, len);
+#else
+			*packetp = data;
+			return len;
+#endif
 		} else {
 			printf("%s: Rx error\n", dev->name);
 			ret = 0;
 		}
 
-		/* clear the RxBDs */
-		muram_writew(&rxbd->status, RxBD_EMPTY);
-		muram_writew(&rxbd->len, 0);
-		sync();
+		/* free current bd, advance to next one */
+		rxbd = fm_eth_free_one(fm_eth, rxbd);
 
-		/* advance RxBD */
-		rxbd++;
-		rxbd_base = (struct fm_port_bd *)fm_eth->rx_bd_ring;
-		if (rxbd >= (rxbd_base + RX_BD_RING_SIZE))
-			rxbd = rxbd_base;
 		/* read next status */
 		status = muram_readw(&rxbd->status);
-
-		/* update RxQD */
-		offset_out = muram_readw(&pram->rxqd.offset_out);
-		offset_out += sizeof(struct fm_port_bd);
-		if (offset_out >= muram_readw(&pram->rxqd.bd_ring_size))
-			offset_out = 0;
-		muram_writew(&pram->rxqd.offset_out, offset_out);
-		sync();
 	}
 	fm_eth->cur_rxbd = (void *)rxbd;
 
 	return ret;
 }
+
+#ifdef CONFIG_DM_ETH
+static int fm_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+	struct fm_eth *fm_eth = (struct fm_eth *)dev->priv;
+
+	fm_eth->cur_rxbd = fm_eth_free_one(fm_eth, fm_eth->cur_rxbd);
+
+	return 0;
+}
+#endif /* CONFIG_DM_ETH */
 
+#ifndef CONFIG_DM_ETH
 static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
 {
 	struct fsl_enet_mac *mac;
@@ -678,22 +765,75 @@
 
 	return 0;
 }
+#else /* CONFIG_DM_ETH */
+static int fm_eth_init_mac(struct fm_eth *fm_eth, void *reg)
+{
+#ifndef CONFIG_SYS_FMAN_V3
+	void *mdio;
+#endif
+
+	fm_eth->mac = kzalloc(sizeof(*fm_eth->mac), GFP_KERNEL);
+	if (!fm_eth->mac)
+		return -ENOMEM;
+
+#ifndef CONFIG_SYS_FMAN_V3
+	mdio = fman_mdio(fm_eth->dev->parent, fm_eth->mac_type, fm_eth->num);
+	debug("MDIO %d @ %p\n", fm_eth->num, mdio);
+#endif
 
-static int init_phy(struct eth_device *dev)
+	switch (fm_eth->mac_type) {
+#ifdef CONFIG_SYS_FMAN_V3
+	case FM_MEMAC:
+		init_memac(fm_eth->mac, reg, NULL, MAX_RXBUF_LEN);
+		break;
+#else
+	case FM_DTSEC:
+		init_dtsec(fm_eth->mac, reg, mdio, MAX_RXBUF_LEN);
+		break;
+	case FM_TGEC:
+		init_tgec(fm_eth->mac, reg, mdio, MAX_RXBUF_LEN);
+		break;
+#endif
+	}
+
+	return 0;
+}
+#endif /* CONFIG_DM_ETH */
+
+static int init_phy(struct fm_eth *fm_eth)
 {
-	struct fm_eth *fm_eth = dev->priv;
 #ifdef CONFIG_PHYLIB
+	u32 supported = PHY_GBIT_FEATURES;
+#ifndef CONFIG_DM_ETH
 	struct phy_device *phydev = NULL;
-	u32 supported;
+#endif
+
+	if (fm_eth->type == FM_ETH_10G_E)
+		supported = PHY_10G_FEATURES;
+	if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
+		supported |= SUPPORTED_2500baseX_Full;
 #endif
 
 	if (fm_eth->type == FM_ETH_1G_E)
-		dtsec_init_phy(dev);
+		dtsec_init_phy(fm_eth);
 
+#ifdef CONFIG_DM_ETH
+#ifdef CONFIG_PHYLIB
+#ifdef CONFIG_DM_MDIO
+	fm_eth->phydev = dm_eth_phy_connect(fm_eth->dev);
+	if (!fm_eth->phydev)
+		return -ENODEV;
+#endif
+	fm_eth->phydev->advertising &= supported;
+	fm_eth->phydev->supported &= supported;
+
+	phy_config(fm_eth->phydev);
+#endif
+#else /* CONFIG_DM_ETH */
 #ifdef CONFIG_PHYLIB
 	if (fm_eth->bus) {
-		phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, dev,
-					fm_eth->enet_if);
+		phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, fm_eth->dev,
+				     fm_eth->enet_if);
 		if (!phydev) {
 			printf("Failed to connect\n");
 			return -1;
@@ -711,7 +851,7 @@
 	} else {
 		supported = SUPPORTED_10000baseT_Full;
 
-		if (tgec_is_fibre(dev))
+		if (tgec_is_fibre(fm_eth))
 			phydev->port = PORT_FIBRE;
 	}
 
@@ -722,10 +862,11 @@
 
 	phy_config(phydev);
 #endif
-
+#endif /* CONFIG_DM_ETH */
 	return 0;
 }
 
+#ifndef CONFIG_DM_ETH
 int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
 {
 	struct eth_device *dev;
@@ -784,12 +925,210 @@
 	if (ret)
 		return ret;
 
-	init_phy(dev);
+	init_phy(fm_eth);
 
 	/* clear the ethernet address */
 	for (i = 0; i < 6; i++)
 		dev->enetaddr[i] = 0;
 	eth_register(dev);
 
+	return 0;
+}
+#else /* CONFIG_DM_ETH */
+#ifdef CONFIG_PHYLIB
+phy_interface_t fman_read_sys_if(struct udevice *dev)
+{
+	const char *if_str;
+
+	if_str = ofnode_read_string(dev->node, "phy-connection-type");
+	debug("MAC system interface mode %s\n", if_str);
+
+	return phy_get_interface_by_name(if_str);
+}
+#endif
+
+static int fm_eth_bind(struct udevice *dev)
+{
+	char mac_name[11];
+	u32 fm, num;
+
+	if (ofnode_read_u32(ofnode_get_parent(dev->node), "cell-index", &fm)) {
+		printf("FMan node property cell-index missing\n");
+		return -EINVAL;
+	}
+
+	if (dev && dev_read_u32(dev, "cell-index", &num)) {
+		printf("FMan MAC node property cell-index missing\n");
+		return -EINVAL;
+	}
+
+	sprintf(mac_name, "fm%d-mac%d", fm + 1, num + 1);
+	device_set_name(dev, mac_name);
+
+	debug("%s - binding %s\n", __func__, mac_name);
+
+	return 0;
+}
+
+static struct udevice *fm_get_internal_mdio(struct udevice *dev)
+{
+	struct ofnode_phandle_args phandle = {.node = ofnode_null()};
+	struct udevice *mdiodev;
+
+	if (dev_read_phandle_with_args(dev, "pcsphy-handle", NULL,
+				       0, 0, &phandle) ||
+	    !ofnode_valid(phandle.node)) {
+		if (dev_read_phandle_with_args(dev, "tbi-handle", NULL,
+					       0, 0, &phandle) ||
+		    !ofnode_valid(phandle.node)) {
+			printf("Issue reading pcsphy-handle/tbi-handle for MAC %s\n",
+			       dev->name);
+			return NULL;
+		}
+	}
+
+	if (uclass_get_device_by_ofnode(UCLASS_MDIO,
+					ofnode_get_parent(phandle.node),
+					&mdiodev)) {
+		printf("can't find MDIO bus for node %s\n",
+		       ofnode_get_name(ofnode_get_parent(phandle.node)));
+		return NULL;
+	}
+	debug("Found internal MDIO bus %p\n", mdiodev);
+
+	return mdiodev;
+}
+
+static int fm_eth_probe(struct udevice *dev)
+{
+	struct fm_eth *fm_eth = (struct fm_eth *)dev->priv;
+	struct ofnode_phandle_args args;
+	void *reg;
+	int ret, index;
+
+	debug("%s enter for dev %p fm_eth %p - %s\n", __func__, dev, fm_eth,
+	      (dev) ? dev->name : "-");
+
+	if (fm_eth->dev) {
+		printf("%s already probed, exit\n", (dev) ? dev->name : "-");
+		return 0;
+	}
+
+	fm_eth->dev = dev;
+	fm_eth->fm_index = fman_id(dev->parent);
+	reg = (void *)(uintptr_t)dev_read_addr(dev);
+	fm_eth->mac_type = dev_get_driver_data(dev);
+#ifdef CONFIG_PHYLIB
+	fm_eth->enet_if = fman_read_sys_if(dev);
+#else
+	fm_eth->enet_if = PHY_INTERFACE_MODE_SGMII;
+	printf("%s: warning - unable to determine interface type\n", __func__);
+#endif
+	switch (fm_eth->mac_type) {
+#ifndef CONFIG_SYS_FMAN_V3
+	case FM_TGEC:
+		fm_eth->type = FM_ETH_10G_E;
+		break;
+	case FM_DTSEC:
+#else
+	case FM_MEMAC:
+		/* default to 1G, 10G is indicated by port property in dts */
+#endif
+		fm_eth->type = FM_ETH_1G_E;
+		break;
+	}
+
+	if (dev_read_u32(dev, "cell-index", &fm_eth->num)) {
+		printf("FMan MAC node property cell-index missing\n");
+		return -EINVAL;
+	}
+
+	if (dev_read_phandle_with_args(dev, "fsl,fman-ports", NULL,
+				       0, 0, &args))
+		goto ports_ref_failure;
+	index = ofnode_read_u32_default(args.node, "cell-index", 0);
+	if (index <= 0)
+		goto ports_ref_failure;
+	fm_eth->rx_port = fman_port(dev->parent, index);
+
+	if (ofnode_read_bool(args.node, "fsl,fman-10g-port"))
+		fm_eth->type = FM_ETH_10G_E;
+
+	if (dev_read_phandle_with_args(dev, "fsl,fman-ports", NULL,
+				       0, 1, &args))
+		goto ports_ref_failure;
+	index = ofnode_read_u32_default(args.node, "cell-index", 0);
+	if (index <= 0)
+		goto ports_ref_failure;
+	fm_eth->tx_port = fman_port(dev->parent, index);
+
+	/* set the ethernet max receive length */
+	fm_eth->max_rx_len = MAX_RXBUF_LEN;
+
+	switch (fm_eth->enet_if) {
+	case PHY_INTERFACE_MODE_QSGMII:
+		/* all PCS blocks are accessed on one controller */
+		if (fm_eth->num != 0)
+			break;
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_SGMII_2500:
+		fm_eth->pcs_mdio = fm_get_internal_mdio(dev);
+		break;
+	default:
+		break;
+	}
+
+	/* init global mac structure */
+	ret = fm_eth_init_mac(fm_eth, reg);
+	if (ret)
+		return ret;
+
+	/* startup the FM im */
+	ret = fm_eth_startup(fm_eth);
+
+	if (!ret)
+		ret = init_phy(fm_eth);
+
+	return ret;
+
+ports_ref_failure:
+	printf("Issue reading fsl,fman-ports for MAC %s\n", dev->name);
+	return -ENOENT;
+}
+
+static int fm_eth_remove(struct udevice *dev)
+{
 	return 0;
 }
+
+static const struct eth_ops fm_eth_ops = {
+	.start = fm_eth_open,
+	.send = fm_eth_send,
+	.recv = fm_eth_recv,
+	.free_pkt = fm_eth_free_pkt,
+	.stop = fm_eth_halt,
+};
+
+static const struct udevice_id fm_eth_ids[] = {
+#ifdef CONFIG_SYS_FMAN_V3
+	{ .compatible = "fsl,fman-memac", .data = FM_MEMAC },
+#else
+	{ .compatible = "fsl,fman-dtsec", .data = FM_DTSEC },
+	{ .compatible = "fsl,fman-xgec", .data = FM_TGEC },
+#endif
+	{}
+};
+
+U_BOOT_DRIVER(eth_fman) = {
+	.name = "eth_fman",
+	.id = UCLASS_ETH,
+	.of_match = fm_eth_ids,
+	.bind = fm_eth_bind,
+	.probe = fm_eth_probe,
+	.remove = fm_eth_remove,
+	.ops = &fm_eth_ops,
+	.priv_auto_alloc_size = sizeof(struct fm_eth),
+	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
+	.flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+#endif /* CONFIG_DM_ETH */
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index 7a081b9..8ab1816 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -9,6 +9,9 @@
 #include <asm/io.h>
 #include <linux/errno.h>
 #include <u-boot/crc.h>
+#ifdef CONFIG_DM_ETH
+#include <dm.h>
+#endif
 
 #include "fm.h"
 #include <fsl_qe.h>		/* For struct qe_firmware */
@@ -529,3 +532,80 @@
 	return fm_init_bmi(index, &reg->fm_bmi_common);
 }
 #endif
+
+#ifdef CONFIG_DM_ETH
+struct fman_priv {
+	struct ccsr_fman *reg;
+	unsigned int fman_id;
+};
+
+static const struct udevice_id fman_ids[] = {
+	{ .compatible = "fsl,fman" },
+	{}
+};
+
+static int fman_probe(struct udevice *dev)
+{
+	struct fman_priv *priv = dev_get_priv(dev);
+
+	priv->reg = (struct ccsr_fman *)(uintptr_t)dev_read_addr(dev);
+
+	if (dev_read_u32(dev, "cell-index", &priv->fman_id)) {
+		printf("FMan node property cell-index missing\n");
+		return -EINVAL;
+	}
+
+	return fm_init_common(priv->fman_id, priv->reg);
+}
+
+static int fman_remove(struct udevice *dev)
+{
+	return 0;
+}
+
+int fman_id(struct udevice *dev)
+{
+	struct fman_priv *priv = dev_get_priv(dev);
+
+	return priv->fman_id;
+}
+
+void *fman_port(struct udevice *dev, int num)
+{
+	struct fman_priv *priv = dev_get_priv(dev);
+
+	return &priv->reg->port[num - 1].fm_bmi;
+}
+
+void *fman_mdio(struct udevice *dev, enum fm_mac_type type, int num)
+{
+	struct fman_priv *priv = dev_get_priv(dev);
+	void *res = NULL;
+
+	switch (type) {
+#ifdef CONFIG_SYS_FMAN_V3
+	case FM_MEMAC:
+		res = &priv->reg->memac[num].fm_memac_mdio;
+		break;
+#else
+	case FM_DTSEC:
+		res = &priv->reg->mac_1g[num].fm_mdio.miimcfg;
+		break;
+	case FM_TGEC:
+		res = &priv->reg->mac_10g[num].fm_10gec_mdio;
+		break;
+#endif
+	}
+	return res;
+}
+
+U_BOOT_DRIVER(fman) = {
+	.name = "fman",
+	.id = UCLASS_SIMPLE_BUS,
+	.of_match = fman_ids,
+	.probe = fman_probe,
+	.remove = fman_remove,
+	.priv_auto_alloc_size = sizeof(struct fman_priv),
+	.flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+#endif /* CONFIG_DM_ETH */
diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h
index e5deaf52..2379b3a 100644
--- a/drivers/net/fm/fm.h
+++ b/drivers/net/fm/fm.h
@@ -57,6 +57,18 @@
 #define TxBD_READY		0x8000
 #define TxBD_LAST		BD_LAST
 
+#ifdef CONFIG_DM_ETH
+enum fm_mac_type {
+#ifdef CONFIG_SYS_FMAN_V3
+	FM_MEMAC,
+#else
+	FM_DTSEC,
+	FM_TGEC,
+#endif
+};
+#endif
+
+/* Fman ethernet private struct */
 /* Rx/Tx queue descriptor */
 struct fm_port_qd {
 	u16 gen;
@@ -101,6 +113,11 @@
 phy_interface_t fman_port_enet_if(enum fm_port port);
 void fman_disable_port(enum fm_port port);
 void fman_enable_port(enum fm_port port);
+int fman_id(struct udevice *dev);
+void *fman_port(struct udevice *dev, int num);
+#ifdef CONFIG_DM_ETH
+void *fman_mdio(struct udevice *dev, enum fm_mac_type type, int num);
+#endif
 
 struct fsl_enet_mac {
 	void *base; /* MAC controller registers base address */
@@ -126,7 +143,13 @@
 	struct mii_dev *bus;
 	struct phy_device *phydev;
 	int phyaddr;
+#ifndef CONFIG_DM_ETH
 	struct eth_device *dev;
+#else
+	enum fm_mac_type mac_type;
+	struct udevice *dev;
+	struct udevice *pcs_mdio;
+#endif
 	int max_rx_len;
 	struct fm_port_global_pram *rx_pram; /* Rx parameter table */
 	struct fm_port_global_pram *tx_pram; /* Tx parameter table */
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index f896e80..8669d21 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -15,6 +15,7 @@
 
 #include "fm.h"
 
+#ifndef CONFIG_DM_ETH
 struct fm_eth_info fm_info[] = {
 #if (CONFIG_SYS_NUM_FM1_DTSEC >= 1)
 	FM_DTSEC_INFO_INITIALIZER(1, 1),
@@ -380,3 +381,4 @@
 
 	return 0;
 }
+#endif /* CONFIG_DM_ETH */
diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c
index bed8f14..77ea083 100644
--- a/drivers/net/fm/memac.c
+++ b/drivers/net/fm/memac.c
@@ -137,6 +137,7 @@
 void init_memac(struct fsl_enet_mac *mac, void *base,
 		void *phyregs, int max_rx_len)
 {
+	debug("%s: @ %p, mdio @ %p\n", __func__, base, phyregs);
 	mac->base = base;
 	mac->phyregs = phyregs;
 	mac->max_rx_len = max_rx_len;
diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c
index c2ef1b4..4cbfbc7 100644
--- a/drivers/net/fm/memac_phy.c
+++ b/drivers/net/fm/memac_phy.c
@@ -22,6 +22,12 @@
 #define memac_setbits_32(a, v)	setbits_be32(a, v)
 #endif
 
+#ifdef CONFIG_DM_ETH
+struct fm_mdio_priv {
+	struct memac_mdio_controller *regs;
+};
+#endif
+
 static u32 memac_in_32(u32 *reg)
 {
 #ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
@@ -39,10 +45,23 @@
 int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
 			int regnum, u16 value)
 {
+	struct memac_mdio_controller *regs;
 	u32 mdio_ctl;
-	struct memac_mdio_controller *regs = bus->priv;
 	u32 c45 = 1; /* Default to 10G interface */
 
+#ifndef CONFIG_DM_ETH
+	regs = bus->priv;
+#else
+	struct fm_mdio_priv *priv;
+
+	if (!bus->priv)
+		return -EINVAL;
+	priv = dev_get_priv(bus->priv);
+	regs = priv->regs;
+	debug("memac_mdio_write(regs %p, port %d, dev %d, reg %d, val %#x)\n",
+	      regs, port_addr, dev_addr, regnum, value);
+#endif
+
 	if (dev_addr == MDIO_DEVAD_NONE) {
 		c45 = 0; /* clause 22 */
 		dev_addr = regnum & 0x1f;
@@ -84,13 +103,26 @@
 int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
 			int regnum)
 {
+	struct memac_mdio_controller *regs;
 	u32 mdio_ctl;
-	struct memac_mdio_controller *regs = bus->priv;
 	u32 c45 = 1;
 
+#ifndef CONFIG_DM_ETH
+	regs = bus->priv;
+#else
+	struct fm_mdio_priv *priv;
+
+	if (!bus->priv)
+		return -EINVAL;
+	priv = dev_get_priv(bus->priv);
+	regs = priv->regs;
+#endif
+
 	if (dev_addr == MDIO_DEVAD_NONE) {
+#ifndef CONFIG_DM_ETH
 		if (!strcmp(bus->name, DEFAULT_FM_TGEC_MDIO_NAME))
 			return 0xffff;
+#endif
 		c45 = 0; /* clause 22 */
 		dev_addr = regnum & 0x1f;
 		memac_clrbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
@@ -133,6 +165,7 @@
 	return 0;
 }
 
+#ifndef CONFIG_DM_ETH
 int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info)
 {
 	struct mii_dev *bus = mdio_alloc();
@@ -167,3 +200,105 @@
 
 	return mdio_register(bus);
 }
+
+#else /* CONFIG_DM_ETH */
+#if defined(CONFIG_PHYLIB) && defined(CONFIG_DM_MDIO)
+static int fm_mdio_read(struct udevice *dev, int addr, int devad, int reg)
+{
+	struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
+						 NULL;
+
+	if (pdata && pdata->mii_bus)
+		return memac_mdio_read(pdata->mii_bus, addr, devad, reg);
+
+	return -1;
+}
+
+static int fm_mdio_write(struct udevice *dev, int addr, int devad, int reg,
+			 u16 val)
+{
+	struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
+						 NULL;
+
+	if (pdata && pdata->mii_bus)
+		return memac_mdio_write(pdata->mii_bus, addr, devad, reg, val);
+
+	return -1;
+}
+
+static int fm_mdio_reset(struct udevice *dev)
+{
+	struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
+						 NULL;
+
+	if (pdata && pdata->mii_bus)
+		return memac_mdio_reset(pdata->mii_bus);
+
+	return -1;
+}
+
+static const struct mdio_ops fm_mdio_ops = {
+	.read = fm_mdio_read,
+	.write = fm_mdio_write,
+	.reset = fm_mdio_reset,
+};
+
+static const struct udevice_id fm_mdio_ids[] = {
+	{ .compatible = "fsl,fman-memac-mdio" },
+	{}
+};
+
+static int fm_mdio_probe(struct udevice *dev)
+{
+	struct fm_mdio_priv *priv = (dev) ? dev_get_priv(dev) : NULL;
+	struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
+						 NULL;
+
+	if (!dev) {
+		printf("%s dev = NULL\n", __func__);
+		return -1;
+	}
+	if (!priv) {
+		printf("dev_get_priv(dev %p) = NULL\n", dev);
+		return -1;
+	}
+	priv->regs = (void *)(uintptr_t)dev_read_addr(dev);
+	debug("%s priv %p @ regs %p, pdata %p\n", __func__,
+	      priv, priv->regs, pdata);
+
+	/*
+	 * On some platforms like B4860, default value of MDIO_CLK_DIV bits
+	 * in mdio_stat(mdio_cfg) register generates MDIO clock too high
+	 * (much higher than 2.5MHz), violating the IEEE specs.
+	 * On other platforms like T1040, default value of MDIO_CLK_DIV bits
+	 * is zero, so MDIO clock is disabled.
+	 * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to
+	 * be properly initialized.
+	 * The default NEG bit should be '1' as per FMANv3 RM, but on platforms
+	 * like T2080QDS, this bit default is '0', which leads to MDIO failure
+	 * on XAUI PHY, so set this bit definitely.
+	 */
+	if (priv && priv->regs && priv->regs->mdio_stat)
+		memac_setbits_32(&priv->regs->mdio_stat,
+				 MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG);
+
+	return 0;
+}
+
+static int fm_mdio_remove(struct udevice *dev)
+{
+	return 0;
+}
+
+U_BOOT_DRIVER(fman_mdio) = {
+	.name = "fman_mdio",
+	.id = UCLASS_MDIO,
+	.of_match = fm_mdio_ids,
+	.probe = fm_mdio_probe,
+	.remove = fm_mdio_remove,
+	.ops = &fm_mdio_ops,
+	.priv_auto_alloc_size = sizeof(struct fm_mdio_priv),
+	.platdata_auto_alloc_size = sizeof(struct mdio_perdev_priv),
+};
+#endif /* CONFIG_PHYLIB && CONFIG_DM_MDIO */
+#endif /* CONFIG_DM_ETH */
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 07bbcc9..fee3729 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -174,9 +174,21 @@
 };
 
 static int mc_fixup_mac_addr(void *blob, int nodeoffset,
+#ifdef CONFIG_DM_ETH
+			     const char *propname, struct udevice *eth_dev,
+#else
 			     const char *propname, struct eth_device *eth_dev,
+#endif
 			     enum mc_fixup_type type)
 {
+#ifdef CONFIG_DM_ETH
+	struct eth_pdata *plat = dev_get_platdata(eth_dev);
+	unsigned char *enetaddr = plat->enetaddr;
+	int eth_index = eth_dev->seq;
+#else
+	unsigned char *enetaddr = eth_dev->enetaddr;
+	int eth_index = eth_dev->index;
+#endif
 	int err = 0, len = 0, size, i;
 	unsigned char env_enetaddr[ARP_HLEN];
 	unsigned int enetaddr_32[ARP_HLEN];
@@ -184,23 +196,22 @@
 
 	switch (type) {
 	case MC_FIXUP_DPL:
-	/* DPL likes its addresses on 32 * ARP_HLEN bits */
-	for (i = 0; i < ARP_HLEN; i++)
-		enetaddr_32[i] = cpu_to_fdt32(eth_dev->enetaddr[i]);
-	val = enetaddr_32;
-	len = sizeof(enetaddr_32);
-	break;
-
+		/* DPL likes its addresses on 32 * ARP_HLEN bits */
+		for (i = 0; i < ARP_HLEN; i++)
+			enetaddr_32[i] = cpu_to_fdt32(enetaddr[i]);
+		val = enetaddr_32;
+		len = sizeof(enetaddr_32);
+		break;
 	case MC_FIXUP_DPC:
-	val = eth_dev->enetaddr;
-	len = ARP_HLEN;
-	break;
+		val = enetaddr;
+		len = ARP_HLEN;
+		break;
 	}
 
 	/* MAC address property present */
 	if (fdt_get_property(blob, nodeoffset, propname, NULL)) {
 		/* u-boot MAC addr randomly assigned - leave the present one */
-		if (!eth_env_get_enetaddr_by_index("eth", eth_dev->index,
+		if (!eth_env_get_enetaddr_by_index("eth", eth_index,
 						   env_enetaddr))
 			return err;
 	} else {
@@ -250,7 +261,11 @@
 }
 
 static int mc_fixup_dpl_mac_addr(void *blob, int dpmac_id,
+#ifdef CONFIG_DM_ETH
+				 struct udevice *eth_dev)
+#else
 				 struct eth_device *eth_dev)
+#endif
 {
 	int objoff = fdt_path_offset(blob, "/objects");
 	int dpmacoff = -1, dpnioff = -1;
@@ -334,7 +349,11 @@
 }
 
 static int mc_fixup_dpc_mac_addr(void *blob, int dpmac_id,
+#ifdef CONFIG_DM_ETH
+				 struct udevice *eth_dev)
+#else
 				 struct eth_device *eth_dev)
+#endif
 {
 	int nodeoffset = fdt_path_offset(blob, "/board_info/ports"), noff;
 	int err = 0;
@@ -377,8 +396,13 @@
 static int mc_fixup_mac_addrs(void *blob, enum mc_fixup_type type)
 {
 	int i, err = 0, ret = 0;
-	char ethname[ETH_NAME_LEN];
+#ifdef CONFIG_DM_ETH
+#define ETH_NAME_LEN 20
+	struct udevice *eth_dev;
+#else
 	struct eth_device *eth_dev;
+#endif
+	char ethname[ETH_NAME_LEN];
 
 	for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
 		/* port not enabled */
diff --git a/drivers/net/fsl_ls_mdio.c b/drivers/net/fsl_ls_mdio.c
new file mode 100644
index 0000000..6d8332d
--- /dev/null
+++ b/drivers/net/fsl_ls_mdio.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <fsl_memac.h>
+
+#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+#define memac_out_32(a, v)	out_le32(a, v)
+#define memac_clrbits_32(a, v)	clrbits_le32(a, v)
+#define memac_setbits_32(a, v)	setbits_le32(a, v)
+#else
+#define memac_out_32(a, v)	out_be32(a, v)
+#define memac_clrbits_32(a, v)	clrbits_be32(a, v)
+#define memac_setbits_32(a, v)	setbits_be32(a, v)
+#endif
+
+static u32 memac_in_32(u32 *reg)
+{
+#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+	return in_le32(reg);
+#else
+	return in_be32(reg);
+#endif
+}
+
+struct fsl_ls_mdio_priv {
+	void *regs_base;
+};
+
+static u32 fsl_ls_mdio_setup_operation(struct udevice *dev, int addr, int devad,
+				       int reg)
+{
+	struct fsl_ls_mdio_priv *priv = dev_get_priv(dev);
+	struct memac_mdio_controller *regs;
+	u32 mdio_ctl;
+	u32 c45 = 1;
+
+	regs = (struct memac_mdio_controller *)(priv->regs_base);
+	if (devad == MDIO_DEVAD_NONE) {
+		c45 = 0; /* clause 22 */
+		devad = reg & 0x1f;
+		memac_clrbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
+	} else {
+		memac_setbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
+	}
+
+	/* Wait till the bus is free */
+	while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
+		;
+
+	/* Set the Port and Device Addrs */
+	mdio_ctl = MDIO_CTL_PORT_ADDR(addr) | MDIO_CTL_DEV_ADDR(devad);
+	memac_out_32(&regs->mdio_ctl, mdio_ctl);
+
+	/* Set the register address */
+	if (c45)
+		memac_out_32(&regs->mdio_addr, reg & 0xffff);
+
+	/* Wait till the bus is free */
+	while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
+		;
+
+	return mdio_ctl;
+}
+
+static int dm_fsl_ls_mdio_read(struct udevice *dev, int addr,
+			       int devad, int reg)
+{
+	struct fsl_ls_mdio_priv *priv = dev_get_priv(dev);
+	struct memac_mdio_controller *regs;
+	u32 mdio_ctl;
+
+	regs = (struct memac_mdio_controller *)(priv->regs_base);
+	mdio_ctl = fsl_ls_mdio_setup_operation(dev, addr, devad, reg);
+
+	/* Initiate the read */
+	mdio_ctl |= MDIO_CTL_READ;
+	memac_out_32(&regs->mdio_ctl, mdio_ctl);
+
+	/* Wait till the MDIO write is complete */
+	while ((memac_in_32(&regs->mdio_data)) & MDIO_DATA_BSY)
+		;
+
+	/* Return all Fs if nothing was there */
+	if (memac_in_32(&regs->mdio_stat) & MDIO_STAT_RD_ER)
+		return 0xffff;
+
+	return memac_in_32(&regs->mdio_data) & 0xffff;
+}
+
+static int dm_fsl_ls_mdio_write(struct udevice *dev, int addr, int devad,
+				int reg, u16 val)
+{
+	struct fsl_ls_mdio_priv *priv = dev_get_priv(dev);
+	struct memac_mdio_controller *regs;
+
+	regs = (struct memac_mdio_controller *)(priv->regs_base);
+	fsl_ls_mdio_setup_operation(dev, addr, devad, reg);
+
+	/* Write the value to the register */
+	memac_out_32(&regs->mdio_data, MDIO_DATA(val));
+
+	/* Wait till the MDIO write is complete */
+	while ((memac_in_32(&regs->mdio_data)) & MDIO_DATA_BSY)
+		;
+
+	return 0;
+}
+
+static const struct mdio_ops fsl_ls_mdio_ops = {
+	.read = dm_fsl_ls_mdio_read,
+	.write = dm_fsl_ls_mdio_write,
+};
+
+static int fsl_ls_mdio_probe(struct udevice *dev)
+{
+	struct fsl_ls_mdio_priv *priv = dev_get_priv(dev);
+	struct memac_mdio_controller *regs;
+
+	priv->regs_base = dev_read_addr_ptr(dev);
+	regs = (struct memac_mdio_controller *)(priv->regs_base);
+
+	memac_setbits_32(&regs->mdio_stat,
+			 MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG);
+
+	return 0;
+}
+
+static const struct udevice_id fsl_ls_mdio_of_ids[] = {
+	{ .compatible = "fsl,ls-mdio" },
+};
+
+U_BOOT_DRIVER(fsl_ls_mdio) = {
+	.name = "fsl_ls_mdio",
+	.id = UCLASS_MDIO,
+	.of_match = fsl_ls_mdio_of_ids,
+	.probe = fsl_ls_mdio_probe,
+	.ops = &fsl_ls_mdio_ops,
+	.priv_auto_alloc_size = sizeof(struct fsl_ls_mdio_priv),
+};
diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c
index a3b9c15..48343dc 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.c
+++ b/drivers/net/ldpaa_eth/ldpaa_eth.c
@@ -12,6 +12,7 @@
 #include <net.h>
 #include <hwconfig.h>
 #include <phy.h>
+#include <miiphy.h>
 #include <linux/compat.h>
 #include <fsl-mc/fsl_dpmac.h>
 
@@ -19,6 +20,19 @@
 #include "ldpaa_eth.h"
 
 #ifdef CONFIG_PHYLIB
+#ifdef CONFIG_DM_ETH
+static void init_phy(struct udevice *dev)
+{
+	struct ldpaa_eth_priv *priv = dev_get_priv(dev);
+
+	priv->phy = dm_eth_phy_connect(dev);
+
+	if (!priv->phy)
+		return;
+
+	phy_config(priv->phy);
+}
+#else
 static int init_phy(struct eth_device *dev)
 {
 	struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)dev->priv;
@@ -63,6 +77,7 @@
 	return ret;
 }
 #endif
+#endif
 
 #ifdef DEBUG
 
@@ -128,9 +143,15 @@
 	}
 }
 
+#ifdef CONFIG_DM_ETH
+static void ldpaa_eth_get_dpmac_counter(struct udevice *dev)
+{
+	struct ldpaa_eth_priv *priv = dev_get_priv(dev);
+#else
 static void ldpaa_eth_get_dpmac_counter(struct eth_device *net_dev)
 {
 	struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
+#endif
 	int err = 0;
 	u64 value;
 
@@ -263,9 +284,16 @@
 	return;
 }
 
+#ifdef CONFIG_DM_ETH
+static int ldpaa_eth_pull_dequeue_rx(struct udevice *dev,
+				     int flags, uchar **packetp)
+{
+	struct ldpaa_eth_priv *priv = dev_get_priv(dev);
+#else
 static int ldpaa_eth_pull_dequeue_rx(struct eth_device *dev)
 {
 	struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)dev->priv;
+#endif
 	const struct ldpaa_dq *dq;
 	const struct dpaa_fd *fd;
 	int i = 5, err = 0, status;
@@ -322,9 +350,15 @@
 	return err;
 }
 
+#ifdef CONFIG_DM_ETH
+static int ldpaa_eth_tx(struct udevice *dev, void *buf, int len)
+{
+	struct ldpaa_eth_priv *priv = dev_get_priv(dev);
+#else
 static int ldpaa_eth_tx(struct eth_device *net_dev, void *buf, int len)
 {
 	struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
+#endif
 	struct dpaa_fd fd;
 	u64 buffer_start;
 	int data_offset, err;
@@ -400,15 +434,33 @@
 	return err;
 }
 
+static struct phy_device *ldpaa_get_phydev(struct ldpaa_eth_priv *priv)
+{
+#ifdef CONFIG_DM_ETH
+	return priv->phy;
+#else
+#ifdef CONFIG_PHYLIB
+	struct phy_device *phydev = NULL;
+	int phy_num;
+
+	/* start the phy devices one by one and update the dpmac state */
+	for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
+		phydev = wriop_get_phy_dev(priv->dpmac_id, phy_num);
+		if (phydev)
+			return phydev;
+	}
+	return NULL;
+#endif
+	return NULL;
+#endif
+}
+
 static int ldpaa_get_dpmac_state(struct ldpaa_eth_priv *priv,
 				 struct dpmac_link_state *state)
 {
 	phy_interface_t enet_if;
-	int phys_detected;
-#ifdef CONFIG_PHYLIB
 	struct phy_device *phydev = NULL;
-	int err, phy_num;
-#endif
+	int err;
 
 	/* let's start off with maximum capabilities */
 	enet_if = wriop_get_enet_if(priv->dpmac_id);
@@ -420,39 +472,28 @@
 		state->rate = SPEED_1000;
 		break;
 	}
-	state->up = 1;
 
-	phys_detected = 0;
-#ifdef CONFIG_PHYLIB
+	state->up = 1;
 	state->options |= DPMAC_LINK_OPT_AUTONEG;
-
-	/* start the phy devices one by one and update the dpmac state */
-	for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
-		phydev = wriop_get_phy_dev(priv->dpmac_id, phy_num);
-		if (!phydev)
-			continue;
+	phydev = ldpaa_get_phydev(priv);
 
-		phys_detected++;
+	if (phydev) {
 		err = phy_startup(phydev);
 		if (err) {
 			printf("%s: Could not initialize\n", phydev->dev->name);
 			state->up = 0;
-			break;
-		}
-		if (phydev->link) {
+		} else if (phydev->link) {
 			state->rate = min(state->rate, (uint32_t)phydev->speed);
 			if (!phydev->duplex)
 				state->options |= DPMAC_LINK_OPT_HALF_DUPLEX;
 			if (!phydev->autoneg)
 				state->options &= ~DPMAC_LINK_OPT_AUTONEG;
 		} else {
-			/* break out of loop even if one phy is down */
 			state->up = 0;
-			break;
 		}
 	}
-#endif
-	if (!phys_detected)
+
+	if (!phydev)
 		state->options &= ~DPMAC_LINK_OPT_AUTONEG;
 
 	if (!state->up) {
@@ -464,9 +505,16 @@
 	return 0;
 }
 
+#ifdef CONFIG_DM_ETH
+static int ldpaa_eth_open(struct udevice *dev)
+{
+	struct eth_pdata *plat = dev_get_platdata(dev);
+	struct ldpaa_eth_priv *priv = dev_get_priv(dev);
+#else
 static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd)
 {
 	struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
+#endif
 	struct dpmac_link_state	dpmac_link_state = { 0 };
 #ifdef DEBUG
 	struct dpni_link_state link_state;
@@ -474,8 +522,13 @@
 	int err = 0;
 	struct dpni_queue d_queue;
 
+#ifdef CONFIG_DM_ETH
+	if (eth_is_active(dev))
+		return 0;
+#else
 	if (net_dev->state == ETH_STATE_ACTIVE)
 		return 0;
+#endif
 
 	if (get_mc_boot_status() != 0) {
 		printf("ERROR (MC is not booted)\n");
@@ -515,8 +568,13 @@
 	if (err)
 		goto err_dpni_bind;
 
+#ifdef CONFIG_DM_ETH
+	err = dpni_add_mac_addr(dflt_mc_io, MC_CMD_NO_FLAGS,
+				dflt_dpni->dpni_handle, plat->enetaddr);
+#else
 	err = dpni_add_mac_addr(dflt_mc_io, MC_CMD_NO_FLAGS,
 				dflt_dpni->dpni_handle, net_dev->enetaddr);
+#endif
 	if (err) {
 		printf("dpni_add_mac_addr() failed\n");
 		return err;
@@ -589,23 +647,35 @@
 	return err;
 }
 
+#ifdef CONFIG_DM_ETH
+static void ldpaa_eth_stop(struct udevice *dev)
+{
+	struct ldpaa_eth_priv *priv = dev_get_priv(dev);
+#else
 static void ldpaa_eth_stop(struct eth_device *net_dev)
 {
 	struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
-	int err = 0;
-#ifdef CONFIG_PHYLIB
-	struct phy_device *phydev = NULL;
-	int phy_num;
 #endif
+	struct phy_device *phydev = NULL;
+	int err = 0;
 
+#ifdef CONFIG_DM_ETH
+	if (!eth_is_active(dev))
+		return;
+#else
 	if ((net_dev->state == ETH_STATE_PASSIVE) ||
 	    (net_dev->state == ETH_STATE_INIT))
 		return;
+#endif
 
 #ifdef DEBUG
 	ldpaa_eth_get_dpni_counter();
+#ifdef CONFIG_DM_ETH
+	ldpaa_eth_get_dpmac_counter(dev);
+#else
 	ldpaa_eth_get_dpmac_counter(net_dev);
 #endif
+#endif
 
 	err = dprc_disconnect(dflt_mc_io, MC_CMD_NO_FLAGS,
 			      dflt_dprc_handle, &dpmac_endpoint);
@@ -628,13 +698,9 @@
 	if (err < 0)
 		printf("dpni_disable() failed\n");
 
-#ifdef CONFIG_PHYLIB
-	for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
-		phydev = wriop_get_phy_dev(priv->dpmac_id, phy_num);
-		if (phydev)
-			phy_shutdown(phydev);
-	}
-#endif
+	phydev = ldpaa_get_phydev(priv);
+	if (phydev)
+		phy_shutdown(phydev);
 
 	/* Free DPBP handle and reset. */
 	ldpaa_dpbp_free();
@@ -1027,6 +1093,107 @@
 	return 0;
 }
 
+#ifdef CONFIG_DM_ETH
+static int ldpaa_eth_probe(struct udevice *dev)
+{
+	struct ofnode_phandle_args phandle;
+
+	/* Nothing to do if there is no "phy-handle" in the DTS node */
+	if (dev_read_phandle_with_args(dev, "phy-handle", NULL,
+				       0, 0, &phandle)) {
+		return 0;
+	}
+
+	init_phy(dev);
+
+	return 0;
+}
+
+static uint32_t ldpaa_eth_get_dpmac_id(struct udevice *dev)
+{
+	int port_node = dev_of_offset(dev);
+
+	return fdtdec_get_uint(gd->fdt_blob, port_node, "reg", -1);
+}
+
+static const char *ldpaa_eth_get_phy_mode_str(struct udevice *dev)
+{
+	int port_node = dev_of_offset(dev);
+	const char *phy_mode_str;
+
+	phy_mode_str = fdt_getprop(gd->fdt_blob, port_node,
+				   "phy-connection-type", NULL);
+	if (phy_mode_str)
+		return phy_mode_str;
+
+	phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode", NULL);
+	return phy_mode_str;
+}
+
+static int ldpaa_eth_bind(struct udevice *dev)
+{
+	const char *phy_mode_str = NULL;
+	uint32_t dpmac_id;
+	char eth_name[16];
+	int phy_mode = -1;
+
+	phy_mode_str = ldpaa_eth_get_phy_mode_str(dev);
+	if (phy_mode_str)
+		phy_mode = phy_get_interface_by_name(phy_mode_str);
+	if (phy_mode == -1) {
+		dev_err(dev, "incorrect phy mode\n");
+		return -EINVAL;
+	}
+
+	dpmac_id = ldpaa_eth_get_dpmac_id(dev);
+	if (dpmac_id == -1) {
+		dev_err(dev, "missing reg field from the dpmac node\n");
+		return -EINVAL;
+	}
+
+	sprintf(eth_name, "DPMAC%d@%s", dpmac_id, phy_mode_str);
+	device_set_name(dev, eth_name);
+
+	return 0;
+}
+
+static int ldpaa_eth_ofdata_to_platdata(struct udevice *dev)
+{
+	struct ldpaa_eth_priv *priv = dev_get_priv(dev);
+	const char *phy_mode_str;
+
+	priv->dpmac_id = ldpaa_eth_get_dpmac_id(dev);
+	phy_mode_str = ldpaa_eth_get_phy_mode_str(dev);
+	priv->phy_mode = phy_get_interface_by_name(phy_mode_str);
+
+	return 0;
+}
+
+static const struct eth_ops ldpaa_eth_ops = {
+	.start	= ldpaa_eth_open,
+	.send	= ldpaa_eth_tx,
+	.recv	= ldpaa_eth_pull_dequeue_rx,
+	.stop	= ldpaa_eth_stop,
+};
+
+static const struct udevice_id ldpaa_eth_of_ids[] = {
+	{ .compatible = "fsl,qoriq-mc-dpmac" },
+};
+
+U_BOOT_DRIVER(ldpaa_eth) = {
+	.name = "ldpaa_eth",
+	.id = UCLASS_ETH,
+	.of_match = ldpaa_eth_of_ids,
+	.ofdata_to_platdata = ldpaa_eth_ofdata_to_platdata,
+	.bind = ldpaa_eth_bind,
+	.probe = ldpaa_eth_probe,
+	.ops = &ldpaa_eth_ops,
+	.priv_auto_alloc_size = sizeof(struct ldpaa_eth_priv),
+	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
+
+#else
+
 static int ldpaa_eth_netdev_init(struct eth_device *net_dev,
 				 phy_interface_t enet_if)
 {
@@ -1099,3 +1266,4 @@
 
 	return err;
 }
+#endif
diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.h b/drivers/net/ldpaa_eth/ldpaa_eth.h
index 3f9154b..e90513e 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.h
+++ b/drivers/net/ldpaa_eth/ldpaa_eth.h
@@ -116,7 +116,13 @@
 					 LDPAA_ETH_FAS_TIDE)
 
 struct ldpaa_eth_priv {
+#ifdef CONFIG_DM_ETH
+	struct phy_device *phy;
+	int phy_mode;
+	bool started;
+#else
 	struct eth_device *net_dev;
+#endif
 	uint32_t dpmac_id;
 	uint16_t dpmac_handle;
 
diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c
index b4ad11d..34a5a16 100644
--- a/drivers/net/pcnet.c
+++ b/drivers/net/pcnet.c
@@ -21,10 +21,6 @@
 #define PCNET_DEBUG2(fmt,args...)	\
 	debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args)
 
-#if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975)
-#error "Macro for PCnet chip version is not defined!"
-#endif
-
 /*
  * Set the number of Tx and Rx buffers, using Log_2(# buffers).
  * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
@@ -183,14 +179,14 @@
 		/*
 		 * Setup the PCI device.
 		 */
-		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &bar);
-		dev->iobase = pci_io_to_phys(devbusfn, bar);
+		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &bar);
+		dev->iobase = pci_mem_to_phys(devbusfn, bar);
 		dev->iobase &= ~0xf;
 
 		PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ",
 			     dev->name, devbusfn, (unsigned long)dev->iobase);
 
-		command = PCI_COMMAND_IO | PCI_COMMAND_MASTER;
+		command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 		pci_write_config_word(devbusfn, PCI_COMMAND, command);
 		pci_read_config_word(devbusfn, PCI_COMMAND, &status);
 		if ((status & command) != command) {
@@ -254,16 +250,12 @@
 	case 0x2621:
 		chipname = "PCnet/PCI II 79C970A";	/* PCI */
 		break;
-#ifdef CONFIG_PCNET_79C973
 	case 0x2625:
 		chipname = "PCnet/FAST III 79C973";	/* PCI */
 		break;
-#endif
-#ifdef CONFIG_PCNET_79C975
 	case 0x2627:
 		chipname = "PCnet/FAST III 79C975";	/* PCI */
 		break;
-#endif
 	default:
 		printf("%s: PCnet version %#x not supported\n",
 		       dev->name, chip_version);
@@ -340,7 +332,9 @@
 		addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
 					       sizeof(*lp->uc));
 		flush_dcache_range(addr, addr + sizeof(*lp->uc));
-		addr = UNCACHED_SDRAM(addr);
+		addr = (unsigned long)map_physmem(addr,
+				roundup(sizeof(*lp->uc), ARCH_DMA_MINALIGN),
+				MAP_NOCACHE);
 		lp->uc = (struct pcnet_uncached_priv *)addr;
 
 		addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c
index bb59629..1f08397 100644
--- a/drivers/net/rtl8139.c
+++ b/drivers/net/rtl8139.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * rtl8139.c : U-Boot driver for the RealTek RTL8139
  *
@@ -8,71 +9,68 @@
  */
 
 /* rtl8139.c - etherboot driver for the Realtek 8139 chipset
-
-  ported from the linux driver written by Donald Becker
-  by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999
-
-  This software may be used and distributed according to the terms
-  of the GNU Public License, incorporated herein by reference.
-
-  changes to the original driver:
-  - removed support for interrupts, switching to polling mode (yuck!)
-  - removed support for the 8129 chip (external MII)
-
-*/
+ *
+ * ported from the linux driver written by Donald Becker
+ * by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999
+ *
+ * changes to the original driver:
+ * - removed support for interrupts, switching to polling mode (yuck!)
+ * - removed support for the 8129 chip (external MII)
+ */
 
 /*********************************************************************/
 /* Revision History						     */
 /*********************************************************************/
 
 /*
-  28 Dec 2002	ken_yap@users.sourceforge.net (Ken Yap)
-     Put in virt_to_bus calls to allow Etherboot relocation.
-
-  06 Apr 2001	ken_yap@users.sourceforge.net (Ken Yap)
-     Following email from Hyun-Joon Cha, added a disable routine, otherwise
-     NIC remains live and can crash the kernel later.
-
-  4 Feb 2000	espenlaub@informatik.uni-ulm.de (Klaus Espenlaub)
-     Shuffled things around, removed the leftovers from the 8129 support
-     that was in the Linux driver and added a bit more 8139 definitions.
-     Moved the 8K receive buffer to a fixed, available address outside the
-     0x98000-0x9ffff range.  This is a bit of a hack, but currently the only
-     way to make room for the Etherboot features that need substantial amounts
-     of code like the ANSI console support.  Currently the buffer is just below
-     0x10000, so this even conforms to the tagged boot image specification,
-     which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000.  My
-     interpretation of this "reserved" is that Etherboot may do whatever it
-     likes, as long as its environment is kept intact (like the BIOS
-     variables).  Hopefully fixed rtl_poll() once and for all.	The symptoms
-     were that if Etherboot was left at the boot menu for several minutes, the
-     first eth_poll failed.  Seems like I am the only person who does this.
-     First of all I fixed the debugging code and then set out for a long bug
-     hunting session.  It took me about a week full time work - poking around
-     various places in the driver, reading Don Becker's and Jeff Garzik's Linux
-     driver and even the FreeBSD driver (what a piece of crap!) - and
-     eventually spotted the nasty thing: the transmit routine was acknowledging
-     each and every interrupt pending, including the RxOverrun and RxFIFIOver
-     interrupts.  This confused the RTL8139 thoroughly.	 It destroyed the
-     Rx ring contents by dumping the 2K FIFO contents right where we wanted to
-     get the next packet.  Oh well, what fun.
-
-  18 Jan 2000	mdc@thinguin.org (Marty Connor)
-     Drastically simplified error handling.  Basically, if any error
-     in transmission or reception occurs, the card is reset.
-     Also, pointed all transmit descriptors to the same buffer to
-     save buffer space.	 This should decrease driver size and avoid
-     corruption because of exceeding 32K during runtime.
-
-  28 Jul 1999	(Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de)
-     rtl_poll was quite broken: it used the RxOK interrupt flag instead
-     of the RxBufferEmpty flag which often resulted in very bad
-     transmission performace - below 1kBytes/s.
-
-*/
+ * 28 Dec 2002 ken_yap@users.sourceforge.net (Ken Yap)
+ *    Put in virt_to_bus calls to allow Etherboot relocation.
+ *
+ * 06 Apr 2001 ken_yap@users.sourceforge.net (Ken Yap)
+ *    Following email from Hyun-Joon Cha, added a disable routine, otherwise
+ *    NIC remains live and can crash the kernel later.
+ *
+ * 4 Feb 2000 espenlaub@informatik.uni-ulm.de (Klaus Espenlaub)
+ *    Shuffled things around, removed the leftovers from the 8129 support
+ *    that was in the Linux driver and added a bit more 8139 definitions.
+ *    Moved the 8K receive buffer to a fixed, available address outside the
+ *    0x98000-0x9ffff range. This is a bit of a hack, but currently the only
+ *    way to make room for the Etherboot features that need substantial amounts
+ *    of code like the ANSI console support. Currently the buffer is just below
+ *    0x10000, so this even conforms to the tagged boot image specification,
+ *    which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My
+ *    interpretation of this "reserved" is that Etherboot may do whatever it
+ *    likes, as long as its environment is kept intact (like the BIOS
+ *    variables). Hopefully fixed rtl8139_recv() once and for all. The symptoms
+ *    were that if Etherboot was left at the boot menu for several minutes, the
+ *    first eth_poll failed. Seems like I am the only person who does this.
+ *    First of all I fixed the debugging code and then set out for a long bug
+ *    hunting session. It took me about a week full time work - poking around
+ *    various places in the driver, reading Don Becker's and Jeff Garzik's Linux
+ *    driver and even the FreeBSD driver (what a piece of crap!) - and
+ *    eventually spotted the nasty thing: the transmit routine was acknowledging
+ *    each and every interrupt pending, including the RxOverrun and RxFIFIOver
+ *    interrupts. This confused the RTL8139 thoroughly. It destroyed the
+ *    Rx ring contents by dumping the 2K FIFO contents right where we wanted to
+ *    get the next packet. Oh well, what fun.
+ *
+ * 18 Jan 2000 mdc@thinguin.org (Marty Connor)
+ *    Drastically simplified error handling. Basically, if any error
+ *    in transmission or reception occurs, the card is reset.
+ *    Also, pointed all transmit descriptors to the same buffer to
+ *    save buffer space. This should decrease driver size and avoid
+ *    corruption because of exceeding 32K during runtime.
+ *
+ * 28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de)
+ *    rtl8139_recv was quite broken: it used the RxOK interrupt flag instead
+ *    of the RxBufferEmpty flag which often resulted in very bad
+ *    transmission performace - below 1kBytes/s.
+ *
+ */
 
 #include <common.h>
 #include <cpu_func.h>
+#include <linux/types.h>
 #include <malloc.h>
 #include <net.h>
 #include <netdev.h>
@@ -81,8 +79,8 @@
 
 #define RTL_TIMEOUT	100000
 
-/* PCI Tuning Parameters
-   Threshold is bytes transferred to chip before transmission starts. */
+/* PCI Tuning Parameters */
+/* Threshold is bytes transferred to chip before transmission starts. */
 #define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */
 #define RX_FIFO_THRESH	4	/* Rx buffer level before first PCI xfer.  */
 #define RX_DMA_BURST	4	/* Maximum PCI burst, '4' is 256 bytes */
@@ -99,173 +97,103 @@
 #define phys_to_bus(a)	pci_phys_to_mem((pci_dev_t)dev->priv, a)
 
 /* Symbolic offsets to registers. */
-enum RTL8139_registers {
-	MAC0=0,			/* Ethernet hardware address. */
-	MAR0=8,			/* Multicast filter. */
-	TxStatus0=0x10,		/* Transmit status (four 32bit registers). */
-	TxAddr0=0x20,		/* Tx descriptors (also four 32bit). */
-	RxBuf=0x30, RxEarlyCnt=0x34, RxEarlyStatus=0x36,
-	ChipCmd=0x37, RxBufPtr=0x38, RxBufAddr=0x3A,
-	IntrMask=0x3C, IntrStatus=0x3E,
-	TxConfig=0x40, RxConfig=0x44,
-	Timer=0x48,		/* general-purpose counter. */
-	RxMissed=0x4C,		/* 24 bits valid, write clears. */
-	Cfg9346=0x50, Config0=0x51, Config1=0x52,
-	TimerIntrReg=0x54,	/* intr if gp counter reaches this value */
-	MediaStatus=0x58,
-	Config3=0x59,
-	MultiIntr=0x5C,
-	RevisionID=0x5E,	/* revision of the RTL8139 chip */
-	TxSummary=0x60,
-	MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68,
-	NWayExpansion=0x6A,
-	DisconnectCnt=0x6C, FalseCarrierCnt=0x6E,
-	NWayTestReg=0x70,
-	RxCnt=0x72,		/* packet received counter */
-	CSCR=0x74,		/* chip status and configuration register */
-	PhyParm1=0x78,TwisterParm=0x7c,PhyParm2=0x80,	/* undocumented */
-	/* from 0x84 onwards are a number of power management/wakeup frame
-	 * definitions we will probably never need to know about.  */
-};
-
-enum ChipCmdBits {
-	CmdReset=0x10, CmdRxEnb=0x08, CmdTxEnb=0x04, RxBufEmpty=0x01, };
-
-/* Interrupt register bits, using my own meaningful names. */
-enum IntrStatusBits {
-	PCIErr=0x8000, PCSTimeout=0x4000, CableLenChange= 0x2000,
-	RxFIFOOver=0x40, RxUnderrun=0x20, RxOverflow=0x10,
-	TxErr=0x08, TxOK=0x04, RxErr=0x02, RxOK=0x01,
-};
-enum TxStatusBits {
-	TxHostOwns=0x2000, TxUnderrun=0x4000, TxStatOK=0x8000,
-	TxOutOfWindow=0x20000000, TxAborted=0x40000000,
-	TxCarrierLost=0x80000000,
-};
-enum RxStatusBits {
-	RxMulticast=0x8000, RxPhysical=0x4000, RxBroadcast=0x2000,
-	RxBadSymbol=0x0020, RxRunt=0x0010, RxTooLong=0x0008, RxCRCErr=0x0004,
-	RxBadAlign=0x0002, RxStatusOK=0x0001,
-};
-
-enum MediaStatusBits {
-	MSRTxFlowEnable=0x80, MSRRxFlowEnable=0x40, MSRSpeed10=0x08,
-	MSRLinkFail=0x04, MSRRxPauseFlag=0x02, MSRTxPauseFlag=0x01,
-};
-
-enum MIIBMCRBits {
-	BMCRReset=0x8000, BMCRSpeed100=0x2000, BMCRNWayEnable=0x1000,
-	BMCRRestartNWay=0x0200, BMCRDuplex=0x0100,
-};
-
-enum CSCRBits {
-	CSCR_LinkOKBit=0x0400, CSCR_LinkChangeBit=0x0800,
-	CSCR_LinkStatusBits=0x0f000, CSCR_LinkDownOffCmd=0x003c0,
-	CSCR_LinkDownCmd=0x0f3c0,
-};
+/* Ethernet hardware address. */
+#define RTL_REG_MAC0				0x00
+/* Multicast filter. */
+#define RTL_REG_MAR0				0x08
+/* Transmit status (four 32bit registers). */
+#define RTL_REG_TXSTATUS0			0x10
+/* Tx descriptors (also four 32bit). */
+#define RTL_REG_TXADDR0				0x20
+#define RTL_REG_RXBUF				0x30
+#define RTL_REG_RXEARLYCNT			0x34
+#define RTL_REG_RXEARLYSTATUS			0x36
+#define RTL_REG_CHIPCMD				0x37
+#define RTL_REG_CHIPCMD_CMDRESET		BIT(4)
+#define RTL_REG_CHIPCMD_CMDRXENB		BIT(3)
+#define RTL_REG_CHIPCMD_CMDTXENB		BIT(2)
+#define RTL_REG_CHIPCMD_RXBUFEMPTY		BIT(0)
+#define RTL_REG_RXBUFPTR			0x38
+#define RTL_REG_RXBUFADDR			0x3A
+#define RTL_REG_INTRMASK			0x3C
+#define RTL_REG_INTRSTATUS			0x3E
+#define RTL_REG_INTRSTATUS_PCIERR		BIT(15)
+#define RTL_REG_INTRSTATUS_PCSTIMEOUT		BIT(14)
+#define RTL_REG_INTRSTATUS_CABLELENCHANGE	BIT(13)
+#define RTL_REG_INTRSTATUS_RXFIFOOVER		BIT(6)
+#define RTL_REG_INTRSTATUS_RXUNDERRUN		BIT(5)
+#define RTL_REG_INTRSTATUS_RXOVERFLOW		BIT(4)
+#define RTL_REG_INTRSTATUS_TXERR		BIT(3)
+#define RTL_REG_INTRSTATUS_TXOK			BIT(2)
+#define RTL_REG_INTRSTATUS_RXERR		BIT(1)
+#define RTL_REG_INTRSTATUS_RXOK			BIT(0)
+#define RTL_REG_TXCONFIG			0x40
+#define RTL_REG_RXCONFIG			0x44
+#define RTL_REG_RXCONFIG_RXCFGWRAP		BIT(7)
+#define RTL_REG_RXCONFIG_ACCEPTERR		BIT(5)
+#define RTL_REG_RXCONFIG_ACCEPTRUNT		BIT(4)
+#define RTL_REG_RXCONFIG_ACCEPTBROADCAST	BIT(3)
+#define RTL_REG_RXCONFIG_ACCEPTMULTICAST	BIT(2)
+#define RTL_REG_RXCONFIG_ACCEPTMYPHYS		BIT(1)
+#define RTL_REG_RXCONFIG_ACCEPTALLPHYS		BIT(0)
+/* general-purpose counter. */
+#define RTL_REG_TIMER				0x48
+/* 24 bits valid, write clears. */
+#define RTL_REG_RXMISSED			0x4C
+#define RTL_REG_CFG9346				0x50
+#define RTL_REG_CONFIG0				0x51
+#define RTL_REG_CONFIG1				0x52
+/* intr if gp counter reaches this value */
+#define RTL_REG_TIMERINTRREG			0x54
+#define RTL_REG_MEDIASTATUS			0x58
+#define RTL_REG_MEDIASTATUS_MSRTXFLOWENABLE	BIT(7)
+#define RTL_REG_MEDIASTATUS_MSRRXFLOWENABLE	BIT(6)
+#define RTL_REG_MEDIASTATUS_MSRSPEED10		BIT(3)
+#define RTL_REG_MEDIASTATUS_MSRLINKFAIL		BIT(2)
+#define RTL_REG_MEDIASTATUS_MSRRXPAUSEFLAG	BIT(1)
+#define RTL_REG_MEDIASTATUS_MSRTXPAUSEFLAG	BIT(0)
+#define RTL_REG_CONFIG3				0x59
+#define RTL_REG_MULTIINTR			0x5C
+/* revision of the RTL8139 chip */
+#define RTL_REG_REVISIONID			0x5E
+#define RTL_REG_TXSUMMARY			0x60
+#define RTL_REG_MII_BMCR			0x62
+#define RTL_REG_MII_BMSR			0x64
+#define RTL_REG_NWAYADVERT			0x66
+#define RTL_REG_NWAYLPAR			0x68
+#define RTL_REG_NWAYEXPANSION			0x6A
+#define RTL_REG_DISCONNECTCNT			0x6C
+#define RTL_REG_FALSECARRIERCNT			0x6E
+#define RTL_REG_NWAYTESTREG			0x70
+/* packet received counter */
+#define RTL_REG_RXCNT				0x72
+/* chip status and configuration register */
+#define RTL_REG_CSCR				0x74
+#define RTL_REG_PHYPARM1			0x78
+#define RTL_REG_TWISTERPARM			0x7c
+/* undocumented */
+#define RTL_REG_PHYPARM2			0x80
+/*
+ * from 0x84 onwards are a number of power management/wakeup frame
+ * definitions we will probably never need to know about.
+ */
 
-/* Bits in RxConfig. */
-enum rx_mode_bits {
-	RxCfgWrap=0x80,
-	AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0x08,
-	AcceptMulticast=0x04, AcceptMyPhys=0x02, AcceptAllPhys=0x01,
-};
+#define RTL_STS_RXMULTICAST			BIT(15)
+#define RTL_STS_RXPHYSICAL			BIT(14)
+#define RTL_STS_RXBROADCAST			BIT(13)
+#define RTL_STS_RXBADSYMBOL			BIT(5)
+#define RTL_STS_RXRUNT				BIT(4)
+#define RTL_STS_RXTOOLONG			BIT(3)
+#define RTL_STS_RXCRCERR			BIT(2)
+#define RTL_STS_RXBADALIGN			BIT(1)
+#define RTL_STS_RXSTATUSOK			BIT(0)
 
+static unsigned int cur_rx, cur_tx;
 static int ioaddr;
-static unsigned int cur_rx,cur_tx;
 
 /* The RTL8139 can only transmit from a contiguous, aligned memory block.  */
-static unsigned char tx_buffer[TX_BUF_SIZE] __attribute__((aligned(4)));
-static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4)));
-
-static int rtl8139_probe(struct eth_device *dev, bd_t *bis);
-static int read_eeprom(int location, int addr_len);
-static void rtl_reset(struct eth_device *dev);
-static int rtl_transmit(struct eth_device *dev, void *packet, int length);
-static int rtl_poll(struct eth_device *dev);
-static void rtl_disable(struct eth_device *dev);
-static int rtl_bcast_addr(struct eth_device *dev, const u8 *bcast_mac, int join)
-{
-	return (0);
-}
-
-static struct pci_device_id supported[] = {
-       {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139},
-       {PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139},
-       {}
-};
-
-int rtl8139_initialize(bd_t *bis)
-{
-	pci_dev_t devno;
-	int card_number = 0;
-	struct eth_device *dev;
-	u32 iobase;
-	int idx=0;
-
-	while(1){
-		/* Find RTL8139 */
-		if ((devno = pci_find_devices(supported, idx++)) < 0)
-			break;
-
-		pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
-		iobase &= ~0xf;
-
-		debug ("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
-
-		dev = (struct eth_device *)malloc(sizeof *dev);
-		if (!dev) {
-			printf("Can not allocate memory of rtl8139\n");
-			break;
-		}
-		memset(dev, 0, sizeof(*dev));
-
-		sprintf (dev->name, "RTL8139#%d", card_number);
-
-		dev->priv = (void *) devno;
-		dev->iobase = (int)bus_to_phys(iobase);
-		dev->init = rtl8139_probe;
-		dev->halt = rtl_disable;
-		dev->send = rtl_transmit;
-		dev->recv = rtl_poll;
-		dev->mcast = rtl_bcast_addr;
-
-		eth_register (dev);
-
-		card_number++;
-
-		pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
-
-		udelay (10 * 1000);
-	}
-
-	return card_number;
-}
-
-static int rtl8139_probe(struct eth_device *dev, bd_t *bis)
-{
-	int i;
-	int addr_len;
-	unsigned short *ap = (unsigned short *)dev->enetaddr;
-
-	ioaddr = dev->iobase;
-
-	/* Bring the chip out of low-power mode. */
-	outb(0x00, ioaddr + Config1);
-
-	addr_len = read_eeprom(0,8) == 0x8129 ? 8 : 6;
-	for (i = 0; i < 3; i++)
-		*ap++ = le16_to_cpu (read_eeprom(i + 7, addr_len));
-
-	rtl_reset(dev);
-
-	if (inb(ioaddr + MediaStatus) & MSRLinkFail) {
-		printf("Cable not connected or other link failure\n");
-		return -1 ;
-	}
-
-	return 0;
-}
+static unsigned char tx_buffer[TX_BUF_SIZE] __aligned(4);
+static unsigned char rx_ring[RX_BUF_LEN + 16] __aligned(4);
 
 /* Serial EEPROM section. */
 
@@ -278,51 +206,57 @@
 #define EE_DATA_READ	0x01	/* EEPROM chip data out. */
 #define EE_ENB		(0x80 | EE_CS)
 
-/*
-	Delay between EEPROM clock transitions.
-	No extra delay is needed with 33MHz PCI, but 66MHz may change this.
-*/
-
-#define eeprom_delay()	inl(ee_addr)
-
 /* The EEPROM commands include the alway-set leading bit. */
-#define EE_WRITE_CMD	(5)
-#define EE_READ_CMD	(6)
-#define EE_ERASE_CMD	(7)
+#define EE_WRITE_CMD	5
+#define EE_READ_CMD	6
+#define EE_ERASE_CMD	7
 
-static int read_eeprom(int location, int addr_len)
+static void rtl8139_eeprom_delay(uintptr_t regbase)
 {
-	int i;
+	/*
+	 * Delay between EEPROM clock transitions.
+	 * No extra delay is needed with 33MHz PCI, but 66MHz may change this.
+	 */
+	inl(regbase + RTL_REG_CFG9346);
+}
+
+static int rtl8139_read_eeprom(unsigned int location, unsigned int addr_len)
+{
+	unsigned int read_cmd = location | (EE_READ_CMD << addr_len);
+	uintptr_t ee_addr = ioaddr + RTL_REG_CFG9346;
 	unsigned int retval = 0;
-	long ee_addr = ioaddr + Cfg9346;
-	int read_cmd = location | (EE_READ_CMD << addr_len);
+	u8 dataval;
+	int i;
 
 	outb(EE_ENB & ~EE_CS, ee_addr);
 	outb(EE_ENB, ee_addr);
-	eeprom_delay();
+	rtl8139_eeprom_delay(ioaddr);
 
 	/* Shift the read command bits out. */
 	for (i = 4 + addr_len; i >= 0; i--) {
-		int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
+		dataval = (read_cmd & BIT(i)) ? EE_DATA_WRITE : 0;
 		outb(EE_ENB | dataval, ee_addr);
-		eeprom_delay();
+		rtl8139_eeprom_delay(ioaddr);
 		outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
-		eeprom_delay();
+		rtl8139_eeprom_delay(ioaddr);
 	}
+
 	outb(EE_ENB, ee_addr);
-	eeprom_delay();
+	rtl8139_eeprom_delay(ioaddr);
 
 	for (i = 16; i > 0; i--) {
 		outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
-		eeprom_delay();
-		retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0);
+		rtl8139_eeprom_delay(ioaddr);
+		retval <<= 1;
+		retval |= inb(ee_addr) & EE_DATA_READ;
 		outb(EE_ENB, ee_addr);
-		eeprom_delay();
+		rtl8139_eeprom_delay(ioaddr);
 	}
 
 	/* Terminate the EEPROM access. */
 	outb(~EE_CS, ee_addr);
-	eeprom_delay();
+	rtl8139_eeprom_delay(ioaddr);
+
 	return retval;
 }
 
@@ -331,149 +265,174 @@
 	(RX_FIFO_THRESH << 13) |
 	(RX_DMA_BURST << 8);
 
-static void set_rx_mode(struct eth_device *dev) {
-	unsigned int mc_filter[2];
-	int rx_mode;
+static void rtl8139_set_rx_mode(struct eth_device *dev)
+{
 	/* !IFF_PROMISC */
-	rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
-	mc_filter[1] = mc_filter[0] = 0xffffffff;
+	unsigned int rx_mode = RTL_REG_RXCONFIG_ACCEPTBROADCAST |
+			       RTL_REG_RXCONFIG_ACCEPTMULTICAST |
+			       RTL_REG_RXCONFIG_ACCEPTMYPHYS;
 
-	outl(rtl8139_rx_config | rx_mode, ioaddr + RxConfig);
+	outl(rtl8139_rx_config | rx_mode, ioaddr + RTL_REG_RXCONFIG);
 
-	outl(mc_filter[0], ioaddr + MAR0 + 0);
-	outl(mc_filter[1], ioaddr + MAR0 + 4);
+	outl(0xffffffff, ioaddr + RTL_REG_MAR0 + 0);
+	outl(0xffffffff, ioaddr + RTL_REG_MAR0 + 4);
 }
 
-static void rtl_reset(struct eth_device *dev)
+static void rtl8139_hw_reset(struct eth_device *dev)
 {
+	u8 reg;
 	int i;
 
-	outb(CmdReset, ioaddr + ChipCmd);
-
-	cur_rx = 0;
-	cur_tx = 0;
+	outb(RTL_REG_CHIPCMD_CMDRESET, ioaddr + RTL_REG_CHIPCMD);
 
 	/* Give the chip 10ms to finish the reset. */
-	for (i=0; i<100; ++i){
-		if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
-		udelay (100); /* wait 100us */
+	for (i = 0; i < 100; i++) {
+		reg = inb(ioaddr + RTL_REG_CHIPCMD);
+		if (!(reg & RTL_REG_CHIPCMD_CMDRESET))
+			break;
+
+		udelay(100);
 	}
+}
+
+static void rtl8139_reset(struct eth_device *dev)
+{
+	int i;
 
+	cur_rx = 0;
+	cur_tx = 0;
+
+	rtl8139_hw_reset(dev);
 
 	for (i = 0; i < ETH_ALEN; i++)
-		outb(dev->enetaddr[i], ioaddr + MAC0 + i);
+		outb(dev->enetaddr[i], ioaddr + RTL_REG_MAC0 + i);
 
 	/* Must enable Tx/Rx before setting transfer thresholds! */
-	outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
-	outl((RX_FIFO_THRESH<<13) | (RX_BUF_LEN_IDX<<11) | (RX_DMA_BURST<<8),
-		ioaddr + RxConfig);		/* accept no frames yet!  */
-	outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + TxConfig);
+	outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB,
+	     ioaddr + RTL_REG_CHIPCMD);
 
-	/* The Linux driver changes Config1 here to use a different LED pattern
-	 * for half duplex or full/autodetect duplex (for full/autodetect, the
-	 * outputs are TX/RX, Link10/100, FULL, while for half duplex it uses
-	 * TX/RX, Link100, Link10).  This is messy, because it doesn't match
-	 * the inscription on the mounting bracket.  It should not be changed
-	 * from the configuration EEPROM default, because the card manufacturer
-	 * should have set that to match the card.  */
+	/* accept no frames yet! */
+	outl(rtl8139_rx_config, ioaddr + RTL_REG_RXCONFIG);
+	outl((TX_DMA_BURST << 8) | 0x03000000, ioaddr + RTL_REG_TXCONFIG);
 
-	debug_cond(DEBUG_RX,
-		"rx ring address is %lX\n",(unsigned long)rx_ring);
-	flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
-	outl(phys_to_bus((int)rx_ring), ioaddr + RxBuf);
+	/*
+	 * The Linux driver changes RTL_REG_CONFIG1 here to use a different
+	 * LED pattern for half duplex or full/autodetect duplex (for
+	 * full/autodetect, the outputs are TX/RX, Link10/100, FULL, while
+	 * for half duplex it uses TX/RX, Link100, Link10).  This is messy,
+	 * because it doesn't match the inscription on the mounting bracket.
+	 * It should not be changed from the configuration EEPROM default,
+	 * because the card manufacturer should have set that to match the
+	 * card.
+	 */
+	debug_cond(DEBUG_RX, "rx ring address is %p\n", rx_ring);
 
-	/* If we add multicast support, the MAR0 register would have to be
-	 * initialized to 0xffffffffffffffff (two 32 bit accesses).  Etherboot
-	 * only needs broadcast (for ARP/RARP/BOOTP/DHCP) and unicast.	*/
+	flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
+	outl(phys_to_bus((int)rx_ring), ioaddr + RTL_REG_RXBUF);
 
-	outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
+	/*
+	 * If we add multicast support, the RTL_REG_MAR0 register would have
+	 * to be initialized to 0xffffffffffffffff (two 32 bit accesses).
+	 * Etherboot only needs broadcast (for ARP/RARP/BOOTP/DHCP) and
+	 * unicast.
+	 */
+	outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB,
+	     ioaddr + RTL_REG_CHIPCMD);
 
-	outl(rtl8139_rx_config, ioaddr + RxConfig);
+	outl(rtl8139_rx_config, ioaddr + RTL_REG_RXCONFIG);
 
 	/* Start the chip's Tx and Rx process. */
-	outl(0, ioaddr + RxMissed);
+	outl(0, ioaddr + RTL_REG_RXMISSED);
 
-	/* set_rx_mode */
-	set_rx_mode(dev);
+	rtl8139_set_rx_mode(dev);
 
 	/* Disable all known interrupts by setting the interrupt mask. */
-	outw(0, ioaddr + IntrMask);
+	outw(0, ioaddr + RTL_REG_INTRMASK);
 }
 
-static int rtl_transmit(struct eth_device *dev, void *packet, int length)
+static int rtl8139_send(struct eth_device *dev, void *packet, int length)
 {
-	unsigned int status;
-	unsigned long txstatus;
 	unsigned int len = length;
+	unsigned long txstatus;
+	unsigned int status;
 	int i = 0;
 
 	ioaddr = dev->iobase;
 
-	memcpy((char *)tx_buffer, (char *)packet, (int)length);
+	memcpy(tx_buffer, packet, length);
 
 	debug_cond(DEBUG_TX, "sending %d bytes\n", len);
 
-	/* Note: RTL8139 doesn't auto-pad, send minimum payload (another 4
-	 * bytes are sent automatically for the FCS, totalling to 64 bytes). */
-	while (len < ETH_ZLEN) {
+	/*
+	 * Note: RTL8139 doesn't auto-pad, send minimum payload (another 4
+	 * bytes are sent automatically for the FCS, totalling to 64 bytes).
+	 */
+	while (len < ETH_ZLEN)
 		tx_buffer[len++] = '\0';
-	}
 
 	flush_cache((unsigned long)tx_buffer, length);
-	outl(phys_to_bus((int)tx_buffer), ioaddr + TxAddr0 + cur_tx*4);
-	outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len,
-		ioaddr + TxStatus0 + cur_tx*4);
+	outl(phys_to_bus((unsigned long)tx_buffer),
+	     ioaddr + RTL_REG_TXADDR0 + cur_tx * 4);
+	outl(((TX_FIFO_THRESH << 11) & 0x003f0000) | len,
+	     ioaddr + RTL_REG_TXSTATUS0 + cur_tx * 4);
 
 	do {
-		status = inw(ioaddr + IntrStatus);
-		/* Only acknlowledge interrupt sources we can properly handle
-		 * here - the RxOverflow/RxFIFOOver MUST be handled in the
-		 * rtl_poll() function.	 */
-		outw(status & (TxOK | TxErr | PCIErr), ioaddr + IntrStatus);
-		if ((status & (TxOK | TxErr | PCIErr)) != 0) break;
+		status = inw(ioaddr + RTL_REG_INTRSTATUS);
+		/*
+		 * Only acknlowledge interrupt sources we can properly
+		 * handle here - the RTL_REG_INTRSTATUS_RXOVERFLOW/
+		 * RTL_REG_INTRSTATUS_RXFIFOOVER MUST be handled in the
+		 * rtl8139_recv() function.
+		 */
+		status &= RTL_REG_INTRSTATUS_TXOK | RTL_REG_INTRSTATUS_TXERR |
+			  RTL_REG_INTRSTATUS_PCIERR;
+		outw(status, ioaddr + RTL_REG_INTRSTATUS);
+		if (status)
+			break;
+
 		udelay(10);
 	} while (i++ < RTL_TIMEOUT);
 
-	txstatus = inl(ioaddr + TxStatus0 + cur_tx*4);
+	txstatus = inl(ioaddr + RTL_REG_TXSTATUS0 + cur_tx * 4);
 
-	if (status & TxOK) {
-		cur_tx = (cur_tx + 1) % NUM_TX_DESC;
-
-		debug_cond(DEBUG_TX,
-			"tx done, status %hX txstatus %lX\n",
-			status, txstatus);
-
-		return length;
-	} else {
-
+	if (!(status & RTL_REG_INTRSTATUS_TXOK)) {
 		debug_cond(DEBUG_TX,
-			"tx timeout/error (%d usecs), status %hX txstatus %lX\n",
-			10*i, status, txstatus);
+			   "tx timeout/error (%d usecs), status %hX txstatus %lX\n",
+			   10 * i, status, txstatus);
 
-		rtl_reset(dev);
+		rtl8139_reset(dev);
 
 		return 0;
 	}
+
+	cur_tx = (cur_tx + 1) % NUM_TX_DESC;
+
+	debug_cond(DEBUG_TX, "tx done, status %hX txstatus %lX\n",
+		   status, txstatus);
+
+	return length;
 }
 
-static int rtl_poll(struct eth_device *dev)
+static int rtl8139_recv(struct eth_device *dev)
 {
-	unsigned int status;
-	unsigned int ring_offs;
+	const unsigned int rxstat = RTL_REG_INTRSTATUS_RXFIFOOVER |
+				    RTL_REG_INTRSTATUS_RXOVERFLOW |
+				    RTL_REG_INTRSTATUS_RXOK;
 	unsigned int rx_size, rx_status;
-	int length=0;
+	unsigned int ring_offs;
+	unsigned int status;
+	int length = 0;
 
 	ioaddr = dev->iobase;
 
-	if (inb(ioaddr + ChipCmd) & RxBufEmpty) {
+	if (inb(ioaddr + RTL_REG_CHIPCMD) & RTL_REG_CHIPCMD_RXBUFEMPTY)
 		return 0;
-	}
 
-	status = inw(ioaddr + IntrStatus);
+	status = inw(ioaddr + RTL_REG_INTRSTATUS);
 	/* See below for the rest of the interrupt acknowledges.  */
-	outw(status & ~(RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
+	outw(status & ~rxstat, ioaddr + RTL_REG_INTRSTATUS);
 
-	debug_cond(DEBUG_RX, "rtl_poll: int %hX ", status);
+	debug_cond(DEBUG_RX, "%s: int %hX ", __func__, status);
 
 	ring_offs = cur_rx % RX_BUF_LEN;
 	/* ring_offs is guaranteed being 4-byte aligned */
@@ -481,52 +440,137 @@
 	rx_size = rx_status >> 16;
 	rx_status &= 0xffff;
 
-	if ((rx_status & (RxBadSymbol|RxRunt|RxTooLong|RxCRCErr|RxBadAlign)) ||
-	    (rx_size < ETH_ZLEN) || (rx_size > ETH_FRAME_LEN + 4)) {
+	if ((rx_status & (RTL_STS_RXBADSYMBOL | RTL_STS_RXRUNT |
+			  RTL_STS_RXTOOLONG | RTL_STS_RXCRCERR |
+			  RTL_STS_RXBADALIGN)) ||
+	    (rx_size < ETH_ZLEN) ||
+	    (rx_size > ETH_FRAME_LEN + 4)) {
 		printf("rx error %hX\n", rx_status);
-		rtl_reset(dev); /* this clears all interrupts still pending */
+		/* this clears all interrupts still pending */
+		rtl8139_reset(dev);
 		return 0;
 	}
 
 	/* Received a good packet */
 	length = rx_size - 4;	/* no one cares about the FCS */
-	if (ring_offs+4+rx_size-4 > RX_BUF_LEN) {
-		int semi_count = RX_BUF_LEN - ring_offs - 4;
+	if (ring_offs + 4 + rx_size - 4 > RX_BUF_LEN) {
 		unsigned char rxdata[RX_BUF_LEN];
+		int semi_count = RX_BUF_LEN - ring_offs - 4;
 
 		memcpy(rxdata, rx_ring + ring_offs + 4, semi_count);
-		memcpy(&(rxdata[semi_count]), rx_ring, rx_size-4-semi_count);
+		memcpy(&rxdata[semi_count], rx_ring,
+		       rx_size - 4 - semi_count);
 
 		net_process_received_packet(rxdata, length);
 		debug_cond(DEBUG_RX, "rx packet %d+%d bytes",
-			semi_count, rx_size-4-semi_count);
+			   semi_count, rx_size - 4 - semi_count);
 	} else {
 		net_process_received_packet(rx_ring + ring_offs + 4, length);
-		debug_cond(DEBUG_RX, "rx packet %d bytes", rx_size-4);
+		debug_cond(DEBUG_RX, "rx packet %d bytes", rx_size - 4);
 	}
 	flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
 
-	cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
-	outw(cur_rx - 16, ioaddr + RxBufPtr);
-	/* See RTL8139 Programming Guide V0.1 for the official handling of
-	 * Rx overflow situations.  The document itself contains basically no
-	 * usable information, except for a few exception handling rules.  */
-	outw(status & (RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
+	cur_rx = ROUND(cur_rx + rx_size + 4, 4);
+	outw(cur_rx - 16, ioaddr + RTL_REG_RXBUFPTR);
+	/*
+	 * See RTL8139 Programming Guide V0.1 for the official handling of
+	 * Rx overflow situations. The document itself contains basically
+	 * no usable information, except for a few exception handling rules.
+	 */
+	outw(status & rxstat, ioaddr + RTL_REG_INTRSTATUS);
+
 	return length;
 }
 
-static void rtl_disable(struct eth_device *dev)
+static int rtl8139_init(struct eth_device *dev, bd_t *bis)
 {
-	int i;
+	unsigned short *ap = (unsigned short *)dev->enetaddr;
+	int addr_len, i;
+	u8 reg;
 
 	ioaddr = dev->iobase;
 
-	/* reset the chip */
-	outb(CmdReset, ioaddr + ChipCmd);
+	/* Bring the chip out of low-power mode. */
+	outb(0x00, ioaddr + RTL_REG_CONFIG1);
 
-	/* Give the chip 10ms to finish the reset. */
-	for (i=0; i<100; ++i){
-		if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
-		udelay (100); /* wait 100us */
+	addr_len = rtl8139_read_eeprom(0, 8) == 0x8129 ? 8 : 6;
+	for (i = 0; i < 3; i++)
+		*ap++ = le16_to_cpu(rtl8139_read_eeprom(i + 7, addr_len));
+
+	rtl8139_reset(dev);
+
+	reg = inb(ioaddr + RTL_REG_MEDIASTATUS);
+	if (reg & RTL_REG_MEDIASTATUS_MSRLINKFAIL) {
+		printf("Cable not connected or other link failure\n");
+		return -1;
 	}
+
+	return 0;
+}
+
+static void rtl8139_stop(struct eth_device *dev)
+{
+	ioaddr = dev->iobase;
+
+	rtl8139_hw_reset(dev);
+}
+
+static int rtl8139_bcast_addr(struct eth_device *dev, const u8 *bcast_mac,
+			      int join)
+{
+	return 0;
+}
+
+static struct pci_device_id supported[] = {
+	{ PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139 },
+	{ PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139 },
+	{ }
+};
+
+int rtl8139_initialize(bd_t *bis)
+{
+	struct eth_device *dev;
+	int card_number = 0;
+	pci_dev_t devno;
+	int idx = 0;
+	u32 iobase;
+
+	while (1) {
+		/* Find RTL8139 */
+		devno = pci_find_devices(supported, idx++);
+		if (devno < 0)
+			break;
+
+		pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
+		iobase &= ~0xf;
+
+		debug("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
+
+		dev = (struct eth_device *)malloc(sizeof(*dev));
+		if (!dev) {
+			printf("Can not allocate memory of rtl8139\n");
+			break;
+		}
+		memset(dev, 0, sizeof(*dev));
+
+		sprintf(dev->name, "RTL8139#%d", card_number);
+
+		dev->priv = (void *)devno;
+		dev->iobase = (int)bus_to_phys(iobase);
+		dev->init = rtl8139_init;
+		dev->halt = rtl8139_stop;
+		dev->send = rtl8139_send;
+		dev->recv = rtl8139_recv;
+		dev->mcast = rtl8139_bcast_addr;
+
+		eth_register(dev);
+
+		card_number++;
+
+		pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
+
+		udelay(10 * 1000);
+	}
+
+	return card_number;
 }
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 257b038..45ecd6a 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -10,84 +10,239 @@
 #include <malloc.h>
 #include <net.h>
 #include <miiphy.h>
+#include <linux/io.h>
+#include <linux/types.h>
 
 #include "smc911x.h"
 
-u32 pkt_data_pull(struct eth_device *dev, u32 addr) \
-	__attribute__ ((weak, alias ("smc911x_reg_read")));
-void pkt_data_push(struct eth_device *dev, u32 addr, u32 val) \
-	__attribute__ ((weak, alias ("smc911x_reg_write")));
+struct chip_id {
+	u16 id;
+	char *name;
+};
 
-static void smc911x_handle_mac_address(struct eth_device *dev)
+struct smc911x_priv {
+#ifndef CONFIG_DM_ETH
+	struct eth_device	dev;
+#endif
+	phys_addr_t		iobase;
+	const struct chip_id	*chipid;
+	unsigned char		enetaddr[6];
+};
+
+static const struct chip_id chip_ids[] =  {
+	{ CHIP_89218, "LAN89218" },
+	{ CHIP_9115, "LAN9115" },
+	{ CHIP_9116, "LAN9116" },
+	{ CHIP_9117, "LAN9117" },
+	{ CHIP_9118, "LAN9118" },
+	{ CHIP_9211, "LAN9211" },
+	{ CHIP_9215, "LAN9215" },
+	{ CHIP_9216, "LAN9216" },
+	{ CHIP_9217, "LAN9217" },
+	{ CHIP_9218, "LAN9218" },
+	{ CHIP_9220, "LAN9220" },
+	{ CHIP_9221, "LAN9221" },
+	{ 0, NULL },
+};
+
+#define DRIVERNAME "smc911x"
+
+#if defined (CONFIG_SMC911X_32_BIT) && \
+	defined (CONFIG_SMC911X_16_BIT)
+#error "SMC911X: Only one of CONFIG_SMC911X_32_BIT and \
+	CONFIG_SMC911X_16_BIT shall be set"
+#endif
+
+#if defined (CONFIG_SMC911X_32_BIT)
+static u32 smc911x_reg_read(struct smc911x_priv *priv, u32 offset)
+{
+	return readl(priv->iobase + offset);
+}
+
+static void smc911x_reg_write(struct smc911x_priv *priv, u32 offset, u32 val)
+{
+	writel(val, priv->iobase + offset);
+}
+#elif defined (CONFIG_SMC911X_16_BIT)
+static u32 smc911x_reg_read(struct smc911x_priv *priv, u32 offset)
+{
+	return (readw(priv->iobase + offset) & 0xffff) |
+	       (readw(priv->iobase + offset + 2) << 16);
+}
+static void smc911x_reg_write(struct smc911x_priv *priv, u32 offset, u32 val)
+{
+	writew(val & 0xffff, priv->iobase + offset);
+	writew(val >> 16, priv->iobase + offset + 2);
+}
+#else
+#error "SMC911X: undefined bus width"
+#endif /* CONFIG_SMC911X_16_BIT */
+
+static u32 smc911x_get_mac_csr(struct smc911x_priv *priv, u8 reg)
+{
+	while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+		;
+	smc911x_reg_write(priv, MAC_CSR_CMD,
+			MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
+	while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+		;
+
+	return smc911x_reg_read(priv, MAC_CSR_DATA);
+}
+
+static void smc911x_set_mac_csr(struct smc911x_priv *priv, u8 reg, u32 data)
+{
+	while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+		;
+	smc911x_reg_write(priv, MAC_CSR_DATA, data);
+	smc911x_reg_write(priv, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
+	while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+		;
+}
+
+static int smc911x_detect_chip(struct smc911x_priv *priv)
+{
+	unsigned long val, i;
+
+	val = smc911x_reg_read(priv, BYTE_TEST);
+	if (val == 0xffffffff) {
+		/* Special case -- no chip present */
+		return -1;
+	} else if (val != 0x87654321) {
+		printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
+		return -1;
+	}
+
+	val = smc911x_reg_read(priv, ID_REV) >> 16;
+	for (i = 0; chip_ids[i].id != 0; i++) {
+		if (chip_ids[i].id == val) break;
+	}
+	if (!chip_ids[i].id) {
+		printf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
+		return -1;
+	}
+
+	priv->chipid = &chip_ids[i];
+
+	return 0;
+}
+
+static void smc911x_reset(struct smc911x_priv *priv)
+{
+	int timeout;
+
+	/*
+	 *  Take out of PM setting first
+	 *  Device is already wake up if PMT_CTRL_READY bit is set
+	 */
+	if ((smc911x_reg_read(priv, PMT_CTRL) & PMT_CTRL_READY) == 0) {
+		/* Write to the bytetest will take out of powerdown */
+		smc911x_reg_write(priv, BYTE_TEST, 0x0);
+
+		timeout = 10;
+
+		while (timeout-- &&
+			!(smc911x_reg_read(priv, PMT_CTRL) & PMT_CTRL_READY))
+			udelay(10);
+		if (timeout < 0) {
+			printf(DRIVERNAME
+				": timeout waiting for PM restore\n");
+			return;
+		}
+	}
+
+	/* Disable interrupts */
+	smc911x_reg_write(priv, INT_EN, 0);
+
+	smc911x_reg_write(priv, HW_CFG, HW_CFG_SRST);
+
+	timeout = 1000;
+	while (timeout-- && smc911x_reg_read(priv, E2P_CMD) & E2P_CMD_EPC_BUSY)
+		udelay(10);
+
+	if (timeout < 0) {
+		printf(DRIVERNAME ": reset timeout\n");
+		return;
+	}
+
+	/* Reset the FIFO level and flow control settings */
+	smc911x_set_mac_csr(priv, FLOW, FLOW_FCPT | FLOW_FCEN);
+	smc911x_reg_write(priv, AFC_CFG, 0x0050287F);
+
+	/* Set to LED outputs */
+	smc911x_reg_write(priv, GPIO_CFG, 0x70070000);
+}
+
+static void smc911x_handle_mac_address(struct smc911x_priv *priv)
 {
 	unsigned long addrh, addrl;
-	uchar *m = dev->enetaddr;
+	unsigned char *m = priv->enetaddr;
 
 	addrl = m[0] | (m[1] << 8) | (m[2] << 16) | (m[3] << 24);
 	addrh = m[4] | (m[5] << 8);
-	smc911x_set_mac_csr(dev, ADDRL, addrl);
-	smc911x_set_mac_csr(dev, ADDRH, addrh);
+	smc911x_set_mac_csr(priv, ADDRL, addrl);
+	smc911x_set_mac_csr(priv, ADDRH, addrh);
 
 	printf(DRIVERNAME ": MAC %pM\n", m);
 }
 
-static int smc911x_eth_phy_read(struct eth_device *dev,
+static int smc911x_eth_phy_read(struct smc911x_priv *priv,
 				u8 phy, u8 reg, u16 *val)
 {
-	while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
+	while (smc911x_get_mac_csr(priv, MII_ACC) & MII_ACC_MII_BUSY)
 		;
 
-	smc911x_set_mac_csr(dev, MII_ACC, phy << 11 | reg << 6 |
+	smc911x_set_mac_csr(priv, MII_ACC, phy << 11 | reg << 6 |
 				MII_ACC_MII_BUSY);
 
-	while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
+	while (smc911x_get_mac_csr(priv, MII_ACC) & MII_ACC_MII_BUSY)
 		;
 
-	*val = smc911x_get_mac_csr(dev, MII_DATA);
+	*val = smc911x_get_mac_csr(priv, MII_DATA);
 
 	return 0;
 }
 
-static int smc911x_eth_phy_write(struct eth_device *dev,
+static int smc911x_eth_phy_write(struct smc911x_priv *priv,
 				u8 phy, u8 reg, u16  val)
 {
-	while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
+	while (smc911x_get_mac_csr(priv, MII_ACC) & MII_ACC_MII_BUSY)
 		;
 
-	smc911x_set_mac_csr(dev, MII_DATA, val);
-	smc911x_set_mac_csr(dev, MII_ACC,
+	smc911x_set_mac_csr(priv, MII_DATA, val);
+	smc911x_set_mac_csr(priv, MII_ACC,
 		phy << 11 | reg << 6 | MII_ACC_MII_BUSY | MII_ACC_MII_WRITE);
 
-	while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
+	while (smc911x_get_mac_csr(priv, MII_ACC) & MII_ACC_MII_BUSY)
 		;
 	return 0;
 }
 
-static int smc911x_phy_reset(struct eth_device *dev)
+static int smc911x_phy_reset(struct smc911x_priv *priv)
 {
 	u32 reg;
 
-	reg = smc911x_reg_read(dev, PMT_CTRL);
+	reg = smc911x_reg_read(priv, PMT_CTRL);
 	reg &= ~0xfffff030;
 	reg |= PMT_CTRL_PHY_RST;
-	smc911x_reg_write(dev, PMT_CTRL, reg);
+	smc911x_reg_write(priv, PMT_CTRL, reg);
 
 	mdelay(100);
 
 	return 0;
 }
 
-static void smc911x_phy_configure(struct eth_device *dev)
+static void smc911x_phy_configure(struct smc911x_priv *priv)
 {
 	int timeout;
 	u16 status;
 
-	smc911x_phy_reset(dev);
+	smc911x_phy_reset(priv);
 
-	smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_RESET);
+	smc911x_eth_phy_write(priv, 1, MII_BMCR, BMCR_RESET);
 	mdelay(1);
-	smc911x_eth_phy_write(dev, 1, MII_ADVERTISE, 0x01e1);
-	smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_ANENABLE |
+	smc911x_eth_phy_write(priv, 1, MII_ADVERTISE, 0x01e1);
+	smc911x_eth_phy_write(priv, 1, MII_BMCR, BMCR_ANENABLE |
 				BMCR_ANRESTART);
 
 	timeout = 5000;
@@ -96,7 +251,7 @@
 		if ((timeout--) == 0)
 			goto err_out;
 
-		if (smc911x_eth_phy_read(dev, 1, MII_BMSR, &status) != 0)
+		if (smc911x_eth_phy_read(priv, 1, MII_BMSR, &status) != 0)
 			goto err_out;
 	} while (!(status & BMSR_LSTATUS));
 
@@ -108,65 +263,65 @@
 	printf(DRIVERNAME ": autonegotiation timed out\n");
 }
 
-static void smc911x_enable(struct eth_device *dev)
+static void smc911x_enable(struct smc911x_priv *priv)
 {
 	/* Enable TX */
-	smc911x_reg_write(dev, HW_CFG, 8 << 16 | HW_CFG_SF);
+	smc911x_reg_write(priv, HW_CFG, 8 << 16 | HW_CFG_SF);
 
-	smc911x_reg_write(dev, GPT_CFG, GPT_CFG_TIMER_EN | 10000);
+	smc911x_reg_write(priv, GPT_CFG, GPT_CFG_TIMER_EN | 10000);
 
-	smc911x_reg_write(dev, TX_CFG, TX_CFG_TX_ON);
+	smc911x_reg_write(priv, TX_CFG, TX_CFG_TX_ON);
 
 	/* no padding to start of packets */
-	smc911x_reg_write(dev, RX_CFG, 0);
+	smc911x_reg_write(priv, RX_CFG, 0);
 
-	smc911x_set_mac_csr(dev, MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN |
+	smc911x_set_mac_csr(priv, MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN |
 				MAC_CR_HBDIS);
-
 }
 
-static int smc911x_init(struct eth_device *dev, bd_t * bd)
+static int smc911x_init_common(struct smc911x_priv *priv)
 {
-	struct chip_id *id = dev->priv;
+	const struct chip_id *id = priv->chipid;
 
 	printf(DRIVERNAME ": detected %s controller\n", id->name);
 
-	smc911x_reset(dev);
+	smc911x_reset(priv);
 
 	/* Configure the PHY, initialize the link state */
-	smc911x_phy_configure(dev);
+	smc911x_phy_configure(priv);
 
-	smc911x_handle_mac_address(dev);
+	smc911x_handle_mac_address(priv);
 
 	/* Turn on Tx + Rx */
-	smc911x_enable(dev);
+	smc911x_enable(priv);
 
 	return 0;
 }
 
-static int smc911x_send(struct eth_device *dev, void *packet, int length)
+static int smc911x_send_common(struct smc911x_priv *priv,
+			       void *packet, int length)
 {
 	u32 *data = (u32*)packet;
 	u32 tmplen;
 	u32 status;
 
-	smc911x_reg_write(dev, TX_DATA_FIFO, TX_CMD_A_INT_FIRST_SEG |
+	smc911x_reg_write(priv, TX_DATA_FIFO, TX_CMD_A_INT_FIRST_SEG |
 				TX_CMD_A_INT_LAST_SEG | length);
-	smc911x_reg_write(dev, TX_DATA_FIFO, length);
+	smc911x_reg_write(priv, TX_DATA_FIFO, length);
 
 	tmplen = (length + 3) / 4;
 
 	while (tmplen--)
-		pkt_data_push(dev, TX_DATA_FIFO, *data++);
+		smc911x_reg_write(priv, TX_DATA_FIFO, *data++);
 
 	/* wait for transmission */
-	while (!((smc911x_reg_read(dev, TX_FIFO_INF) &
+	while (!((smc911x_reg_read(priv, TX_FIFO_INF) &
 					TX_FIFO_INF_TSUSED) >> 16));
 
 	/* get status. Ignore 'no carrier' error, it has no meaning for
 	 * full duplex operation
 	 */
-	status = smc911x_reg_read(dev, TX_STATUS_FIFO) &
+	status = smc911x_reg_read(priv, TX_STATUS_FIFO) &
 			(TX_STS_LOC | TX_STS_LATE_COLL | TX_STS_MANY_COLL |
 			TX_STS_MANY_DEFER | TX_STS_UNDERRUN);
 
@@ -183,117 +338,296 @@
 	return -1;
 }
 
-static void smc911x_halt(struct eth_device *dev)
+static void smc911x_halt_common(struct smc911x_priv *priv)
 {
-	smc911x_reset(dev);
-	smc911x_handle_mac_address(dev);
+	smc911x_reset(priv);
+	smc911x_handle_mac_address(priv);
 }
 
-static int smc911x_rx(struct eth_device *dev)
+static int smc911x_recv_common(struct smc911x_priv *priv, u32 *data)
 {
-	u32 *data = (u32 *)net_rx_packets[0];
 	u32 pktlen, tmplen;
 	u32 status;
 
-	if ((smc911x_reg_read(dev, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED) >> 16) {
-		status = smc911x_reg_read(dev, RX_STATUS_FIFO);
-		pktlen = (status & RX_STS_PKT_LEN) >> 16;
+	status = smc911x_reg_read(priv, RX_FIFO_INF);
+	if (!(status & RX_FIFO_INF_RXSUSED))
+		return 0;
 
-		smc911x_reg_write(dev, RX_CFG, 0);
+	status = smc911x_reg_read(priv, RX_STATUS_FIFO);
+	pktlen = (status & RX_STS_PKT_LEN) >> 16;
 
-		tmplen = (pktlen + 3) / 4;
-		while (tmplen--)
-			*data++ = pkt_data_pull(dev, RX_DATA_FIFO);
+	smc911x_reg_write(priv, RX_CFG, 0);
 
-		if (status & RX_STS_ES)
-			printf(DRIVERNAME
-				": dropped bad packet. Status: 0x%08x\n",
-				status);
-		else
-			net_process_received_packet(net_rx_packets[0], pktlen);
+	tmplen = (pktlen + 3) / 4;
+	while (tmplen--)
+		*data++ = smc911x_reg_read(priv, RX_DATA_FIFO);
+
+	if (status & RX_STS_ES) {
+		printf(DRIVERNAME
+			": dropped bad packet. Status: 0x%08x\n",
+			status);
+		return 0;
 	}
 
-	return 0;
+	return pktlen;
 }
 
+#ifndef CONFIG_DM_ETH
+
 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 /* wrapper for smc911x_eth_phy_read */
 static int smc911x_miiphy_read(struct mii_dev *bus, int phy, int devad,
 			       int reg)
 {
-	u16 val = 0;
 	struct eth_device *dev = eth_get_dev_by_name(bus->name);
-	if (dev) {
-		int retval = smc911x_eth_phy_read(dev, phy, reg, &val);
-		if (retval < 0)
-			return retval;
-		return val;
-	}
-	return -ENODEV;
+	struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
+	u16 val = 0;
+	int ret;
+
+	if (!dev || !priv)
+		return -ENODEV;
+
+	ret = smc911x_eth_phy_read(priv, phy, reg, &val);
+	if (ret < 0)
+		return ret;
+
+	return val;
 }
+
 /* wrapper for smc911x_eth_phy_write */
 static int smc911x_miiphy_write(struct mii_dev *bus, int phy, int devad,
 				int reg, u16 val)
 {
 	struct eth_device *dev = eth_get_dev_by_name(bus->name);
-	if (dev)
-		return smc911x_eth_phy_write(dev, phy, reg, val);
-	return -ENODEV;
+	struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
+
+	if (!dev || !priv)
+		return -ENODEV;
+
+	return smc911x_eth_phy_write(priv, phy, reg, val);
+}
+
+static int smc911x_initialize_mii(struct smc911x_priv *priv)
+{
+	struct mii_dev *mdiodev = mdio_alloc();
+	int ret;
+
+	if (!mdiodev)
+		return -ENOMEM;
+
+	strncpy(mdiodev->name, priv->dev.name, MDIO_NAME_LEN);
+	mdiodev->read = smc911x_miiphy_read;
+	mdiodev->write = smc911x_miiphy_write;
+
+	ret = mdio_register(mdiodev);
+	if (ret < 0) {
+		mdio_free(mdiodev);
+		return ret;
+	}
+
+	return 0;
+}
+#else
+static int smc911x_initialize_mii(struct smc911x_priv *priv)
+{
+	return 0;
 }
 #endif
 
+static int smc911x_init(struct eth_device *dev, bd_t *bd)
+{
+	struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
+
+	return smc911x_init_common(priv);
+}
+
+static void smc911x_halt(struct eth_device *dev)
+{
+	struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
+
+	smc911x_halt_common(priv);
+}
+
+static int smc911x_send(struct eth_device *dev, void *packet, int length)
+{
+	struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
+
+	return smc911x_send_common(priv, packet, length);
+}
+
+static int smc911x_recv(struct eth_device *dev)
+{
+	struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
+	u32 *data = (u32 *)net_rx_packets[0];
+	int ret;
+
+	ret = smc911x_recv_common(priv, data);
+	if (ret)
+		net_process_received_packet(net_rx_packets[0], ret);
+
+	return ret;
+}
+
 int smc911x_initialize(u8 dev_num, int base_addr)
 {
 	unsigned long addrl, addrh;
-	struct eth_device *dev;
+	struct smc911x_priv *priv;
+	int ret;
 
-	dev = malloc(sizeof(*dev));
-	if (!dev) {
-		return -1;
-	}
-	memset(dev, 0, sizeof(*dev));
+	priv = calloc(1, sizeof(*priv));
+	if (!priv)
+		return -ENOMEM;
 
-	dev->iobase = base_addr;
+	priv->iobase = base_addr;
+	priv->dev.iobase = base_addr;
 
 	/* Try to detect chip. Will fail if not present. */
-	if (smc911x_detect_chip(dev)) {
-		free(dev);
-		return 0;
+	ret = smc911x_detect_chip(priv);
+	if (ret) {
+		ret = 0;	/* Card not detected is not an error */
+		goto err_detect;
 	}
 
-	addrh = smc911x_get_mac_csr(dev, ADDRH);
-	addrl = smc911x_get_mac_csr(dev, ADDRL);
+	addrh = smc911x_get_mac_csr(priv, ADDRH);
+	addrl = smc911x_get_mac_csr(priv, ADDRL);
 	if (!(addrl == 0xffffffff && addrh == 0x0000ffff)) {
 		/* address is obtained from optional eeprom */
-		dev->enetaddr[0] = addrl;
-		dev->enetaddr[1] = addrl >>  8;
-		dev->enetaddr[2] = addrl >> 16;
-		dev->enetaddr[3] = addrl >> 24;
-		dev->enetaddr[4] = addrh;
-		dev->enetaddr[5] = addrh >> 8;
+		priv->enetaddr[0] = addrl;
+		priv->enetaddr[1] = addrl >>  8;
+		priv->enetaddr[2] = addrl >> 16;
+		priv->enetaddr[3] = addrl >> 24;
+		priv->enetaddr[4] = addrh;
+		priv->enetaddr[5] = addrh >> 8;
+		memcpy(priv->dev.enetaddr, priv->enetaddr, 6);
 	}
 
-	dev->init = smc911x_init;
-	dev->halt = smc911x_halt;
-	dev->send = smc911x_send;
-	dev->recv = smc911x_rx;
-	sprintf(dev->name, "%s-%hu", DRIVERNAME, dev_num);
-
-	eth_register(dev);
+	priv->dev.init = smc911x_init;
+	priv->dev.halt = smc911x_halt;
+	priv->dev.send = smc911x_send;
+	priv->dev.recv = smc911x_recv;
+	sprintf(priv->dev.name, "%s-%hu", DRIVERNAME, dev_num);
 
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-	int retval;
-	struct mii_dev *mdiodev = mdio_alloc();
-	if (!mdiodev)
-		return -ENOMEM;
-	strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
-	mdiodev->read = smc911x_miiphy_read;
-	mdiodev->write = smc911x_miiphy_write;
+	eth_register(&priv->dev);
 
-	retval = mdio_register(mdiodev);
-	if (retval < 0)
-		return retval;
-#endif
+	ret = smc911x_initialize_mii(priv);
+	if (ret)
+		goto err_mii;
 
 	return 1;
+
+err_mii:
+	eth_unregister(&priv->dev);
+err_detect:
+	free(priv);
+	return ret;
 }
+
+#else	/* ifdef CONFIG_DM_ETH */
+
+static int smc911x_start(struct udevice *dev)
+{
+	struct eth_pdata *plat = dev_get_platdata(dev);
+	struct smc911x_priv *priv = dev_get_priv(dev);
+
+	memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
+
+	return smc911x_init_common(priv);
+}
+
+static void smc911x_stop(struct udevice *dev)
+{
+	struct smc911x_priv *priv = dev_get_priv(dev);
+
+	smc911x_halt_common(priv);
+}
+
+static int smc911x_send(struct udevice *dev, void *packet, int length)
+{
+	struct smc911x_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = smc911x_send_common(priv, packet, length);
+
+	return ret ? 0 : -ETIMEDOUT;
+}
+
+static int smc911x_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+	struct smc911x_priv *priv = dev_get_priv(dev);
+	u32 *data = (u32 *)net_rx_packets[0];
+	int ret;
+
+	ret = smc911x_recv_common(priv, data);
+	if (ret)
+		*packetp = (void *)data;
+
+	return ret ? ret : -EAGAIN;
+}
+
+static int smc911x_bind(struct udevice *dev)
+{
+	return device_set_name(dev, dev->name);
+}
+
+static int smc911x_probe(struct udevice *dev)
+{
+	struct smc911x_priv *priv = dev_get_priv(dev);
+	unsigned long addrh, addrl;
+	int ret;
+
+	/* Try to detect chip. Will fail if not present. */
+	ret = smc911x_detect_chip(priv);
+	if (ret)
+		return ret;
+
+	addrh = smc911x_get_mac_csr(priv, ADDRH);
+	addrl = smc911x_get_mac_csr(priv, ADDRL);
+	if (!(addrl == 0xffffffff && addrh == 0x0000ffff)) {
+		/* address is obtained from optional eeprom */
+		priv->enetaddr[0] = addrl;
+		priv->enetaddr[1] = addrl >>  8;
+		priv->enetaddr[2] = addrl >> 16;
+		priv->enetaddr[3] = addrl >> 24;
+		priv->enetaddr[4] = addrh;
+		priv->enetaddr[5] = addrh >> 8;
+	}
+
+	return 0;
+}
+
+static int smc911x_ofdata_to_platdata(struct udevice *dev)
+{
+	struct smc911x_priv *priv = dev_get_priv(dev);
+	struct eth_pdata *pdata = dev_get_platdata(dev);
+
+	pdata->iobase = devfdt_get_addr(dev);
+	priv->iobase = pdata->iobase;
+
+	return 0;
+}
+
+static const struct eth_ops smc911x_ops = {
+	.start	= smc911x_start,
+	.send	= smc911x_send,
+	.recv	= smc911x_recv,
+	.stop	= smc911x_stop,
+};
+
+static const struct udevice_id smc911x_ids[] = {
+	{ .compatible = "smsc,lan9115" },
+	{ }
+};
+
+U_BOOT_DRIVER(smc911x) = {
+	.name		= "eth_smc911x",
+	.id		= UCLASS_ETH,
+	.of_match	= smc911x_ids,
+	.bind		= smc911x_bind,
+	.ofdata_to_platdata = smc911x_ofdata_to_platdata,
+	.probe		= smc911x_probe,
+	.ops		= &smc911x_ops,
+	.priv_auto_alloc_size = sizeof(struct smc911x_priv),
+	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
+	.flags		= DM_FLAG_ALLOC_PRIV_DMA,
+};
+#endif
diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h
index 3145fbd..ce66900 100644
--- a/drivers/net/smc911x.h
+++ b/drivers/net/smc911x.h
@@ -8,47 +8,6 @@
 #ifndef _SMC911X_H_
 #define _SMC911X_H_
 
-#include <linux/types.h>
-
-#define DRIVERNAME "smc911x"
-
-#if defined (CONFIG_SMC911X_32_BIT) && \
-	defined (CONFIG_SMC911X_16_BIT)
-#error "SMC911X: Only one of CONFIG_SMC911X_32_BIT and \
-	CONFIG_SMC911X_16_BIT shall be set"
-#endif
-
-#if defined (CONFIG_SMC911X_32_BIT)
-static inline u32 __smc911x_reg_read(struct eth_device *dev, u32 offset)
-{
-	return *(volatile u32*)(dev->iobase + offset);
-}
-u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
-	__attribute__((weak, alias("__smc911x_reg_read")));
-
-static inline void __smc911x_reg_write(struct eth_device *dev,
-					u32 offset, u32 val)
-{
-	*(volatile u32*)(dev->iobase + offset) = val;
-}
-void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
-	__attribute__((weak, alias("__smc911x_reg_write")));
-#elif defined (CONFIG_SMC911X_16_BIT)
-static inline u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
-{
-	volatile u16 *addr_16 = (u16 *)(dev->iobase + offset);
-	return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16));
-}
-static inline void smc911x_reg_write(struct eth_device *dev,
-					u32 offset, u32 val)
-{
-	*(volatile u16 *)(dev->iobase + offset) = (u16)val;
-	*(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16);
-}
-#else
-#error "SMC911X: undefined bus width"
-#endif /* CONFIG_SMC911X_16_BIT */
-
 /* Below are the register offsets and bit definitions
  * of the Lan911x memory space
  */
@@ -380,120 +339,4 @@
 #define CHIP_9220	0x9220
 #define CHIP_9221	0x9221
 
-struct chip_id {
-	u16 id;
-	char *name;
-};
-
-static const struct chip_id chip_ids[] =  {
-	{ CHIP_89218, "LAN89218" },
-	{ CHIP_9115, "LAN9115" },
-	{ CHIP_9116, "LAN9116" },
-	{ CHIP_9117, "LAN9117" },
-	{ CHIP_9118, "LAN9118" },
-	{ CHIP_9211, "LAN9211" },
-	{ CHIP_9215, "LAN9215" },
-	{ CHIP_9216, "LAN9216" },
-	{ CHIP_9217, "LAN9217" },
-	{ CHIP_9218, "LAN9218" },
-	{ CHIP_9220, "LAN9220" },
-	{ CHIP_9221, "LAN9221" },
-	{ 0, NULL },
-};
-
-static u32 smc911x_get_mac_csr(struct eth_device *dev, u8 reg)
-{
-	while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
-		;
-	smc911x_reg_write(dev, MAC_CSR_CMD,
-			MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
-	while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
-		;
-
-	return smc911x_reg_read(dev, MAC_CSR_DATA);
-}
-
-static void smc911x_set_mac_csr(struct eth_device *dev, u8 reg, u32 data)
-{
-	while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
-		;
-	smc911x_reg_write(dev, MAC_CSR_DATA, data);
-	smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
-	while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
-		;
-}
-
-static int smc911x_detect_chip(struct eth_device *dev)
-{
-	unsigned long val, i;
-
-	val = smc911x_reg_read(dev, BYTE_TEST);
-	if (val == 0xffffffff) {
-		/* Special case -- no chip present */
-		return -1;
-	} else if (val != 0x87654321) {
-		printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
-		return -1;
-	}
-
-	val = smc911x_reg_read(dev, ID_REV) >> 16;
-	for (i = 0; chip_ids[i].id != 0; i++) {
-		if (chip_ids[i].id == val) break;
-	}
-	if (!chip_ids[i].id) {
-		printf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
-		return -1;
-	}
-
-	dev->priv = (void *)&chip_ids[i];
-
-	return 0;
-}
-
-static void smc911x_reset(struct eth_device *dev)
-{
-	int timeout;
-
-	/*
-	 *  Take out of PM setting first
-	 *  Device is already wake up if PMT_CTRL_READY bit is set
-	 */
-	if ((smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) == 0) {
-		/* Write to the bytetest will take out of powerdown */
-		smc911x_reg_write(dev, BYTE_TEST, 0x0);
-
-		timeout = 10;
-
-		while (timeout-- &&
-			!(smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY))
-			udelay(10);
-		if (timeout < 0) {
-			printf(DRIVERNAME
-				": timeout waiting for PM restore\n");
-			return;
-		}
-	}
-
-	/* Disable interrupts */
-	smc911x_reg_write(dev, INT_EN, 0);
-
-	smc911x_reg_write(dev, HW_CFG, HW_CFG_SRST);
-
-	timeout = 1000;
-	while (timeout-- && smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
-		udelay(10);
-
-	if (timeout < 0) {
-		printf(DRIVERNAME ": reset timeout\n");
-		return;
-	}
-
-	/* Reset the FIFO level and flow control settings */
-	smc911x_set_mac_csr(dev, FLOW, FLOW_FCPT | FLOW_FCEN);
-	smc911x_reg_write(dev, AFC_CFG, 0x0050287F);
-
-	/* Set to LED outputs */
-	smc911x_reg_write(dev, GPIO_CFG, 0x70070000);
-}
-
 #endif
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index d2e10d6..7f46e90 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -1009,7 +1009,7 @@
 	if (ret)
 		return ret;
 
-	if (CONFIG_IS_ENABLED(PCI_PNP) &&
+	if (CONFIG_IS_ENABLED(PCI_PNP) && ll_boot_init() &&
 	    (!hose->skip_auto_config_until_reloc ||
 	     (gd->flags & GD_FLG_RELOC))) {
 		ret = pci_auto_config_devices(bus);
@@ -1031,7 +1031,7 @@
 	 * Note we only call this 1) after U-Boot is relocated, and 2)
 	 * root bus has finished probing.
 	 */
-	if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) {
+	if ((gd->flags & GD_FLG_RELOC) && bus->seq == 0 && ll_boot_init()) {
 		ret = fsp_init_phase_pci();
 		if (ret)
 			return ret;
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index a72f34f..1e38c87 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -154,6 +154,14 @@
 	  between an HS USB OTG controller and an HS USB Host controller,
 	  selected by an USB switch.
 
+config MESON_GXBB_USB_PHY
+	bool "Amlogic Meson GXBB USB PHY"
+	depends on PHY && ARCH_MESON && MESON_GXBB
+	imply REGMAP
+	help
+	  This is the generic phy driver for the Amlogic Meson GXBB
+	  USB2 PHY.
+
 config MESON_GXL_USB_PHY
 	bool "Amlogic Meson GXL USB PHYs"
 	depends on PHY && ARCH_MESON && (MESON_GXL || MESON_GXM)
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 43ce62e..74e8d93 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -16,6 +16,7 @@
 obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o
 obj-$(CONFIG_PHY_RCAR_GEN3) += phy-rcar-gen3.o
 obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o
+obj-$(CONFIG_MESON_GXBB_USB_PHY) += meson-gxbb-usb2.o
 obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o meson-gxl-usb3.o
 obj-$(CONFIG_MESON_G12A_USB_PHY) += meson-g12a-usb2.o meson-g12a-usb3-pcie.o
 obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o
diff --git a/drivers/phy/meson-gxbb-usb2.c b/drivers/phy/meson-gxbb-usb2.c
new file mode 100644
index 0000000..88c2ec6
--- /dev/null
+++ b/drivers/phy/meson-gxbb-usb2.c
@@ -0,0 +1,235 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Meson8, Meson8b and GXBB USB2 PHY driver
+ *
+ * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ * Copyright (C) 2018 BayLibre, SAS
+ *
+ * Author: Beniamino Galvani <b.galvani@gmail.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <power/regulator.h>
+#include <regmap.h>
+#include <reset.h>
+
+#define REG_CONFIG					0x00
+	#define REG_CONFIG_CLK_EN			BIT(0)
+	#define REG_CONFIG_CLK_SEL_MASK			GENMASK(3, 1)
+	#define REG_CONFIG_CLK_DIV_MASK			GENMASK(10, 4)
+	#define REG_CONFIG_CLK_32k_ALTSEL		BIT(15)
+	#define REG_CONFIG_TEST_TRIG			BIT(31)
+
+#define REG_CTRL					0x04
+	#define REG_CTRL_SOFT_PRST			BIT(0)
+	#define REG_CTRL_SOFT_HRESET			BIT(1)
+	#define REG_CTRL_SS_SCALEDOWN_MODE_MASK		GENMASK(3, 2)
+	#define REG_CTRL_CLK_DET_RST			BIT(4)
+	#define REG_CTRL_INTR_SEL			BIT(5)
+	#define REG_CTRL_CLK_DETECTED			BIT(8)
+	#define REG_CTRL_SOF_SENT_RCVD_TGL		BIT(9)
+	#define REG_CTRL_SOF_TOGGLE_OUT			BIT(10)
+	#define REG_CTRL_POWER_ON_RESET			BIT(15)
+	#define REG_CTRL_SLEEPM				BIT(16)
+	#define REG_CTRL_TX_BITSTUFF_ENN_H		BIT(17)
+	#define REG_CTRL_TX_BITSTUFF_ENN		BIT(18)
+	#define REG_CTRL_COMMON_ON			BIT(19)
+	#define REG_CTRL_REF_CLK_SEL_MASK		GENMASK(21, 20)
+	#define REG_CTRL_REF_CLK_SEL_SHIFT		20
+	#define REG_CTRL_FSEL_MASK			GENMASK(24, 22)
+	#define REG_CTRL_FSEL_SHIFT			22
+	#define REG_CTRL_PORT_RESET			BIT(25)
+	#define REG_CTRL_THREAD_ID_MASK			GENMASK(31, 26)
+
+/* bits [31:26], [24:21] and [15:3] seem to be read-only */
+#define REG_ADP_BC					0x0c
+	#define REG_ADP_BC_VBUS_VLD_EXT_SEL		BIT(0)
+	#define REG_ADP_BC_VBUS_VLD_EXT			BIT(1)
+	#define REG_ADP_BC_OTG_DISABLE			BIT(2)
+	#define REG_ADP_BC_ID_PULLUP			BIT(3)
+	#define REG_ADP_BC_DRV_VBUS			BIT(4)
+	#define REG_ADP_BC_ADP_PRB_EN			BIT(5)
+	#define REG_ADP_BC_ADP_DISCHARGE		BIT(6)
+	#define REG_ADP_BC_ADP_CHARGE			BIT(7)
+	#define REG_ADP_BC_SESS_END			BIT(8)
+	#define REG_ADP_BC_DEVICE_SESS_VLD		BIT(9)
+	#define REG_ADP_BC_B_VALID			BIT(10)
+	#define REG_ADP_BC_A_VALID			BIT(11)
+	#define REG_ADP_BC_ID_DIG			BIT(12)
+	#define REG_ADP_BC_VBUS_VALID			BIT(13)
+	#define REG_ADP_BC_ADP_PROBE			BIT(14)
+	#define REG_ADP_BC_ADP_SENSE			BIT(15)
+	#define REG_ADP_BC_ACA_ENABLE			BIT(16)
+	#define REG_ADP_BC_DCD_ENABLE			BIT(17)
+	#define REG_ADP_BC_VDAT_DET_EN_B		BIT(18)
+	#define REG_ADP_BC_VDAT_SRC_EN_B		BIT(19)
+	#define REG_ADP_BC_CHARGE_SEL			BIT(20)
+	#define REG_ADP_BC_CHARGE_DETECT		BIT(21)
+	#define REG_ADP_BC_ACA_PIN_RANGE_C		BIT(22)
+	#define REG_ADP_BC_ACA_PIN_RANGE_B		BIT(23)
+	#define REG_ADP_BC_ACA_PIN_RANGE_A		BIT(24)
+	#define REG_ADP_BC_ACA_PIN_GND			BIT(25)
+	#define REG_ADP_BC_ACA_PIN_FLOAT		BIT(26)
+
+#define RESET_COMPLETE_TIME				500
+#define ACA_ENABLE_COMPLETE_TIME			50
+
+struct phy_meson_gxbb_usb2_priv {
+	struct regmap *regmap;
+	struct reset_ctl_bulk resets;
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+	struct udevice *phy_supply;
+#endif
+};
+
+static int phy_meson_gxbb_usb2_power_on(struct phy *phy)
+{
+	struct udevice *dev = phy->dev;
+	struct phy_meson_gxbb_usb2_priv *priv = dev_get_priv(dev);
+	uint val;
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+	if (priv->phy_supply) {
+		int ret = regulator_set_enable(priv->phy_supply, true);
+
+		if (ret)
+			return ret;
+	}
+#endif
+
+	regmap_update_bits(priv->regmap, REG_CONFIG,
+			   REG_CONFIG_CLK_32k_ALTSEL,
+			   REG_CONFIG_CLK_32k_ALTSEL);
+	regmap_update_bits(priv->regmap, REG_CTRL,
+			   REG_CTRL_REF_CLK_SEL_MASK,
+			   0x2 << REG_CTRL_REF_CLK_SEL_SHIFT);
+	regmap_update_bits(priv->regmap, REG_CTRL,
+			   REG_CTRL_FSEL_MASK,
+			   0x5 << REG_CTRL_FSEL_SHIFT);
+
+	/* reset the PHY */
+	regmap_update_bits(priv->regmap, REG_CTRL,
+			   REG_CTRL_POWER_ON_RESET,
+			   REG_CTRL_POWER_ON_RESET);
+	udelay(RESET_COMPLETE_TIME);
+	regmap_update_bits(priv->regmap, REG_CTRL,
+			   REG_CTRL_POWER_ON_RESET,
+			   0);
+	udelay(RESET_COMPLETE_TIME);
+
+	regmap_update_bits(priv->regmap, REG_CTRL,
+			   REG_CTRL_SOF_TOGGLE_OUT,
+			   REG_CTRL_SOF_TOGGLE_OUT);
+
+	/* Set host mode */
+	regmap_update_bits(priv->regmap, REG_ADP_BC,
+			   REG_ADP_BC_ACA_ENABLE,
+			   REG_ADP_BC_ACA_ENABLE);
+	udelay(ACA_ENABLE_COMPLETE_TIME);
+
+	regmap_read(priv->regmap, REG_ADP_BC, &val);
+	if (val & REG_ADP_BC_ACA_PIN_FLOAT) {
+		pr_err("Error powering on GXBB USB PHY\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int phy_meson_gxbb_usb2_power_off(struct phy *phy)
+{
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+	struct udevice *dev = phy->dev;
+	struct phy_meson_gxbb_usb2_priv *priv = dev_get_priv(dev);
+
+	if (priv->phy_supply) {
+		int ret = regulator_set_enable(priv->phy_supply, false);
+
+		if (ret)
+			return ret;
+	}
+#endif
+
+	return 0;
+}
+
+static struct phy_ops meson_gxbb_usb2_phy_ops = {
+	.power_on = phy_meson_gxbb_usb2_power_on,
+	.power_off = phy_meson_gxbb_usb2_power_off,
+};
+
+static int meson_gxbb_usb2_phy_probe(struct udevice *dev)
+{
+	struct phy_meson_gxbb_usb2_priv *priv = dev_get_priv(dev);
+	struct clk clk_usb_general, clk_usb;
+	int ret;
+
+	ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
+	if (ret)
+		return ret;
+
+	ret = clk_get_by_name(dev, "usb_general", &clk_usb_general);
+	if (ret)
+		return ret;
+
+	ret = clk_enable(&clk_usb_general);
+	if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
+		pr_err("Failed to enable PHY general clock\n");
+		return ret;
+	}
+
+	ret = clk_get_by_name(dev, "usb", &clk_usb);
+	if (ret)
+		return ret;
+
+	ret = clk_enable(&clk_usb);
+	if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
+		pr_err("Failed to enable PHY clock\n");
+		return ret;
+	}
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+	ret = device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
+	if (ret && ret != -ENOENT) {
+		pr_err("Failed to get PHY regulator\n");
+		return ret;
+	}
+#endif
+	ret = reset_get_bulk(dev, &priv->resets);
+	if (!ret) {
+		ret = reset_deassert_bulk(&priv->resets);
+		if (ret) {
+			pr_err("Failed to deassert reset\n");
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int meson_gxbb_usb2_phy_remove(struct udevice *dev)
+{
+	struct phy_meson_gxbb_usb2_priv *priv = dev_get_priv(dev);
+
+	return reset_release_bulk(&priv->resets);
+}
+
+static const struct udevice_id meson_gxbb_usb2_phy_ids[] = {
+	{ .compatible = "amlogic,meson8-usb2-phy" },
+	{ .compatible = "amlogic,meson8b-usb2-phy" },
+	{ .compatible = "amlogic,meson-gxbb-usb2-phy" },
+	{ }
+};
+
+U_BOOT_DRIVER(meson_gxbb_usb2_phy) = {
+	.name = "meson_gxbb_usb2_phy",
+	.id = UCLASS_PHY,
+	.of_match = meson_gxbb_usb2_phy_ids,
+	.probe = meson_gxbb_usb2_phy_probe,
+	.remove = meson_gxbb_usb2_phy_remove,
+	.ops = &meson_gxbb_usb2_phy_ops,
+	.priv_auto_alloc_size = sizeof(struct phy_meson_gxbb_usb2_priv),
+};
diff --git a/drivers/rtc/pcf2127.c b/drivers/rtc/pcf2127.c
index f695350..b34ed63 100644
--- a/drivers/rtc/pcf2127.c
+++ b/drivers/rtc/pcf2127.c
@@ -56,7 +56,7 @@
 	buf[i++] = tm->tm_wday & 0x07;
 
 	/* month, 1 - 12 */
-	buf[i++] = bin2bcd(tm->tm_mon + 1);
+	buf[i++] = bin2bcd(tm->tm_mon);
 
 	/* year */
 	buf[i++] = bin2bcd(tm->tm_year % 100);
@@ -83,7 +83,7 @@
 	tm->tm_min  = bcd2bin(buf[PCF2127_REG_MN] & 0x7F);
 	tm->tm_hour = bcd2bin(buf[PCF2127_REG_HR] & 0x3F);
 	tm->tm_mday = bcd2bin(buf[PCF2127_REG_DM] & 0x3F);
-	tm->tm_mon  = bcd2bin(buf[PCF2127_REG_MO] & 0x1F) - 1;
+	tm->tm_mon  = bcd2bin(buf[PCF2127_REG_MO] & 0x1F);
 	tm->tm_year = bcd2bin(buf[PCF2127_REG_YR]) + 1900;
 	if (tm->tm_year < 1970)
 		tm->tm_year += 100;	/* assume we are in 1970...2069 */
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 83b114f..994a594 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -166,11 +166,28 @@
 {
 	struct cadence_spi_platdata *plat = bus->platdata;
 	struct cadence_spi_priv *priv = dev_get_priv(bus);
+	struct clk clk;
 	int ret;
 
 	priv->regbase = plat->regbase;
 	priv->ahbbase = plat->ahbbase;
 
+	if (plat->ref_clk_hz == 0) {
+		ret = clk_get_by_index(bus, 0, &clk);
+		if (ret) {
+#ifdef CONFIG_CQSPI_REF_CLK
+			plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
+#else
+			return ret;
+#endif
+		} else {
+			plat->ref_clk_hz = clk_get_rate(&clk);
+			clk_free(&clk);
+			if (IS_ERR_VALUE(plat->ref_clk_hz))
+				return plat->ref_clk_hz;
+		}
+	}
+
 	ret = reset_get_bulk(bus, &priv->resets);
 	if (ret)
 		dev_warn(bus, "Can't get reset: %d\n", ret);
@@ -268,8 +285,6 @@
 {
 	struct cadence_spi_platdata *plat = bus->platdata;
 	ofnode subnode;
-	struct clk clk;
-	int ret;
 
 	plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
 	plat->ahbbase = (void *)devfdt_get_addr_size_index(bus, 1,
@@ -305,20 +320,6 @@
 	plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
 	plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
 
-	ret = clk_get_by_index(bus, 0, &clk);
-	if (ret) {
-#ifdef CONFIG_CQSPI_REF_CLK
-		plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
-#else
-		return ret;
-#endif
-	} else {
-		plat->ref_clk_hz = clk_get_rate(&clk);
-		clk_free(&clk);
-		if (IS_ERR_VALUE(plat->ref_clk_hz))
-			return plat->ref_clk_hz;
-	}
-
 	debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
 	      __func__, plat->regbase, plat->ahbbase, plat->max_hz,
 	      plat->page_size);
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 8e2a09d..ee2c8b6 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -1,1142 +1,781 @@
 // SPDX-License-Identifier: GPL-2.0+
+
 /*
- * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ * Freescale QuadSPI driver.
+ *
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2018 Bootlin
+ * Copyright (C) 2018 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ * Copyright 2019-2020 NXP
  *
- * Freescale Quad Serial Peripheral Interface (QSPI) driver
+ * This driver is a ported version of Linux Freescale QSPI driver taken from
+ * v5.5-rc1 tag having following information.
+ *
+ * Transition to SPI MEM interface:
+ * Authors:
+ *     Boris Brezillon <bbrezillon@kernel.org>
+ *     Frieder Schrempf <frieder.schrempf@kontron.de>
+ *     Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
+ *     Suresh Gupta <suresh.gupta@nxp.com>
+ *
+ * Based on the original fsl-quadspi.c spi-nor driver.
+ * Transition to spi-mem in spi-fsl-qspi.c
  */
 
 #include <common.h>
-#include <malloc.h>
-#include <spi.h>
 #include <asm/io.h>
-#include <linux/sizes.h>
-#include <linux/iopoll.h>
 #include <dm.h>
-#include <errno.h>
-#include <watchdog.h>
-#include <wait_bit.h>
-#include "fsl_qspi.h"
+#include <linux/iopoll.h>
+#include <linux/sizes.h>
+#include <linux/err.h>
+#include <spi.h>
+#include <spi-mem.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define OFFSET_BITS_MASK	GENMASK(23, 0)
+/*
+ * The driver only uses one single LUT entry, that is updated on
+ * each call of exec_op(). Index 0 is preset at boot with a basic
+ * read operation, so let's use the last entry (15).
+ */
+#define	SEQID_LUT			15
 
-#define FLASH_STATUS_WEL	0x02
+/* Registers used by the driver */
+#define QUADSPI_MCR			0x00
+#define QUADSPI_MCR_RESERVED_MASK	GENMASK(19, 16)
+#define QUADSPI_MCR_MDIS_MASK		BIT(14)
+#define QUADSPI_MCR_CLR_TXF_MASK	BIT(11)
+#define QUADSPI_MCR_CLR_RXF_MASK	BIT(10)
+#define QUADSPI_MCR_DDR_EN_MASK		BIT(7)
+#define QUADSPI_MCR_END_CFG_MASK	GENMASK(3, 2)
+#define QUADSPI_MCR_SWRSTHD_MASK	BIT(1)
+#define QUADSPI_MCR_SWRSTSD_MASK	BIT(0)
 
-/* SEQID */
-#define SEQID_WREN		1
-#define SEQID_FAST_READ		2
-#define SEQID_RDSR		3
-#define SEQID_SE		4
-#define SEQID_CHIP_ERASE	5
-#define SEQID_PP		6
-#define SEQID_RDID		7
-#define SEQID_BE_4K		8
-#ifdef CONFIG_SPI_FLASH_BAR
-#define SEQID_BRRD		9
-#define SEQID_BRWR		10
-#define SEQID_RDEAR		11
-#define SEQID_WREAR		12
-#endif
-#define SEQID_WRAR		13
-#define SEQID_RDAR		14
+#define QUADSPI_IPCR			0x08
+#define QUADSPI_IPCR_SEQID(x)		((x) << 24)
+#define QUADSPI_FLSHCR			0x0c
+#define QUADSPI_FLSHCR_TCSS_MASK	GENMASK(3, 0)
+#define QUADSPI_FLSHCR_TCSH_MASK	GENMASK(11, 8)
+#define QUADSPI_FLSHCR_TDH_MASK		GENMASK(17, 16)
 
-/* QSPI CMD */
-#define QSPI_CMD_PP		0x02	/* Page program (up to 256 bytes) */
-#define QSPI_CMD_RDSR		0x05	/* Read status register */
-#define QSPI_CMD_WREN		0x06	/* Write enable */
-#define QSPI_CMD_FAST_READ	0x0b	/* Read data bytes (high frequency) */
-#define QSPI_CMD_BE_4K		0x20    /* 4K erase */
-#define QSPI_CMD_CHIP_ERASE	0xc7	/* Erase whole flash chip */
-#define QSPI_CMD_SE		0xd8	/* Sector erase (usually 64KiB) */
-#define QSPI_CMD_RDID		0x9f	/* Read JEDEC ID */
+#define QUADSPI_BUF3CR			0x1c
+#define QUADSPI_BUF3CR_ALLMST_MASK	BIT(31)
+#define QUADSPI_BUF3CR_ADATSZ(x)	((x) << 8)
+#define QUADSPI_BUF3CR_ADATSZ_MASK	GENMASK(15, 8)
 
-/* Used for Micron, winbond and Macronix flashes */
-#define	QSPI_CMD_WREAR		0xc5	/* EAR register write */
-#define	QSPI_CMD_RDEAR		0xc8	/* EAR reigster read */
+#define QUADSPI_BFGENCR			0x20
+#define QUADSPI_BFGENCR_SEQID(x)	((x) << 12)
 
-/* Used for Spansion flashes only. */
-#define	QSPI_CMD_BRRD		0x16	/* Bank register read */
-#define	QSPI_CMD_BRWR		0x17	/* Bank register write */
+#define QUADSPI_BUF0IND			0x30
+#define QUADSPI_BUF1IND			0x34
+#define QUADSPI_BUF2IND			0x38
+#define QUADSPI_SFAR			0x100
 
-/* Used for Spansion S25FS-S family flash only. */
-#define QSPI_CMD_RDAR		0x65	/* Read any device register */
-#define QSPI_CMD_WRAR		0x71	/* Write any device register */
+#define QUADSPI_SMPR			0x108
+#define QUADSPI_SMPR_DDRSMP_MASK	GENMASK(18, 16)
+#define QUADSPI_SMPR_FSDLY_MASK		BIT(6)
+#define QUADSPI_SMPR_FSPHS_MASK		BIT(5)
+#define QUADSPI_SMPR_HSENA_MASK		BIT(0)
 
-/* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
-#define QSPI_CMD_FAST_READ_4B	0x0c    /* Read data bytes (high frequency) */
-#define QSPI_CMD_PP_4B		0x12    /* Page program (up to 256 bytes) */
-#define QSPI_CMD_SE_4B		0xdc    /* Sector erase (usually 64KiB) */
+#define QUADSPI_RBCT			0x110
+#define QUADSPI_RBCT_WMRK_MASK		GENMASK(4, 0)
+#define QUADSPI_RBCT_RXBRD_USEIPS	BIT(8)
 
-/* fsl_qspi_platdata flags */
-#define QSPI_FLAG_REGMAP_ENDIAN_BIG	BIT(0)
+#define QUADSPI_TBDR			0x154
 
-/* default SCK frequency, unit: HZ */
-#define FSL_QSPI_DEFAULT_SCK_FREQ	50000000
+#define QUADSPI_SR			0x15c
+#define QUADSPI_SR_IP_ACC_MASK		BIT(1)
+#define QUADSPI_SR_AHB_ACC_MASK		BIT(2)
 
-/* QSPI max chipselect signals number */
-#define FSL_QSPI_MAX_CHIPSELECT_NUM     4
+#define QUADSPI_FR			0x160
+#define QUADSPI_FR_TFF_MASK		BIT(0)
 
-/* Controller needs driver to swap endian */
-#define QUADSPI_QUIRK_SWAP_ENDIAN	BIT(0)
+#define QUADSPI_RSER			0x164
+#define QUADSPI_RSER_TFIE		BIT(0)
 
-enum fsl_qspi_devtype {
-	FSL_QUADSPI_VYBRID,
-	FSL_QUADSPI_IMX6SX,
-	FSL_QUADSPI_IMX6UL_7D,
-	FSL_QUADSPI_IMX7ULP,
-};
+#define QUADSPI_SPTRCLR			0x16c
+#define QUADSPI_SPTRCLR_IPPTRC		BIT(8)
+#define QUADSPI_SPTRCLR_BFPTRC		BIT(0)
 
-struct fsl_qspi_devtype_data {
-	enum fsl_qspi_devtype devtype;
-	u32 rxfifo;
-	u32 txfifo;
-	u32 ahb_buf_size;
-	u32 driver_data;
-};
+#define QUADSPI_SFA1AD			0x180
+#define QUADSPI_SFA2AD			0x184
+#define QUADSPI_SFB1AD			0x188
+#define QUADSPI_SFB2AD			0x18c
+#define QUADSPI_RBDR(x)			(0x200 + ((x) * 4))
 
-/**
- * struct fsl_qspi_platdata - platform data for Freescale QSPI
+#define QUADSPI_LUTKEY			0x300
+#define QUADSPI_LUTKEY_VALUE		0x5AF05AF0
+
+#define QUADSPI_LCKCR			0x304
+#define QUADSPI_LCKER_LOCK		BIT(0)
+#define QUADSPI_LCKER_UNLOCK		BIT(1)
+
+#define QUADSPI_LUT_BASE		0x310
+#define QUADSPI_LUT_OFFSET		(SEQID_LUT * 4 * 4)
+#define QUADSPI_LUT_REG(idx) \
+	(QUADSPI_LUT_BASE + QUADSPI_LUT_OFFSET + (idx) * 4)
+
+/* Instruction set for the LUT register */
+#define LUT_STOP		0
+#define LUT_CMD			1
+#define LUT_ADDR		2
+#define LUT_DUMMY		3
+#define LUT_MODE		4
+#define LUT_MODE2		5
+#define LUT_MODE4		6
+#define LUT_FSL_READ		7
+#define LUT_FSL_WRITE		8
+#define LUT_JMP_ON_CS		9
+#define LUT_ADDR_DDR		10
+#define LUT_MODE_DDR		11
+#define LUT_MODE2_DDR		12
+#define LUT_MODE4_DDR		13
+#define LUT_FSL_READ_DDR	14
+#define LUT_FSL_WRITE_DDR	15
+#define LUT_DATA_LEARN		16
+
+/*
+ * The PAD definitions for LUT register.
  *
- * @flags: Flags for QSPI QSPI_FLAG_...
- * @speed_hz: Default SCK frequency
- * @reg_base: Base address of QSPI registers
- * @amba_base: Base address of QSPI memory mapping
- * @amba_total_size: size of QSPI memory mapping
- * @flash_num: Number of active slave devices
- * @num_chipselect: Number of QSPI chipselect signals
+ * The pad stands for the number of IO lines [0:3].
+ * For example, the quad read needs four IO lines,
+ * so you should use LUT_PAD(4).
  */
-struct fsl_qspi_platdata {
-	u32 flags;
-	u32 speed_hz;
-	fdt_addr_t reg_base;
-	fdt_addr_t amba_base;
-	fdt_size_t amba_total_size;
-	u32 flash_num;
-	u32 num_chipselect;
-};
+#define LUT_PAD(x) (fls(x) - 1)
 
-/**
- * struct fsl_qspi_priv - private data for Freescale QSPI
+/*
+ * Macro for constructing the LUT entries with the following
+ * register layout:
  *
- * @flags: Flags for QSPI QSPI_FLAG_...
- * @bus_clk: QSPI input clk frequency
- * @speed_hz: Default SCK frequency
- * @cur_seqid: current LUT table sequence id
- * @sf_addr: flash access offset
- * @amba_base: Base address of QSPI memory mapping of every CS
- * @amba_total_size: size of QSPI memory mapping
- * @cur_amba_base: Base address of QSPI memory mapping of current CS
- * @flash_num: Number of active slave devices
- * @num_chipselect: Number of QSPI chipselect signals
- * @regs: Point to QSPI register structure for I/O access
+ *  ---------------------------------------------------
+ *  | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
+ *  ---------------------------------------------------
+ */
+#define LUT_DEF(idx, ins, pad, opr)					\
+	((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16))
+
+/* Controller needs driver to swap endianness */
+#define QUADSPI_QUIRK_SWAP_ENDIAN	BIT(0)
+
+/* Controller needs 4x internal clock */
+#define QUADSPI_QUIRK_4X_INT_CLK	BIT(1)
+
+/*
+ * TKT253890, the controller needs the driver to fill the txfifo with
+ * 16 bytes at least to trigger a data transfer, even though the extra
+ * data won't be transferred.
+ */
+#define QUADSPI_QUIRK_TKT253890		BIT(2)
+
+/* TKT245618, the controller cannot wake up from wait mode */
+#define QUADSPI_QUIRK_TKT245618		BIT(3)
+
+/*
+ * Controller adds QSPI_AMBA_BASE (base address of the mapped memory)
+ * internally. No need to add it when setting SFXXAD and SFAR registers
+ */
+#define QUADSPI_QUIRK_BASE_INTERNAL	BIT(4)
+
+/*
+ * Controller uses TDH bits in register QUADSPI_FLSHCR.
+ * They need to be set in accordance with the DDR/SDR mode.
  */
-struct fsl_qspi_priv {
-	u32 flags;
-	u32 bus_clk;
-	u32 speed_hz;
-	u32 cur_seqid;
-	u32 sf_addr;
-	u32 amba_base[FSL_QSPI_MAX_CHIPSELECT_NUM];
-	u32 amba_total_size;
-	u32 cur_amba_base;
-	u32 flash_num;
-	u32 num_chipselect;
-	struct fsl_qspi_regs *regs;
-	struct fsl_qspi_devtype_data *devtype_data;
+#define QUADSPI_QUIRK_USE_TDH_SETTING	BIT(5)
+
+struct fsl_qspi_devtype_data {
+	unsigned int rxfifo;
+	unsigned int txfifo;
+	unsigned int ahb_buf_size;
+	unsigned int quirks;
+	bool little_endian;
 };
 
 static const struct fsl_qspi_devtype_data vybrid_data = {
-	.devtype = FSL_QUADSPI_VYBRID,
-	.rxfifo = 128,
-	.txfifo = 64,
-	.ahb_buf_size = 1024,
-	.driver_data = QUADSPI_QUIRK_SWAP_ENDIAN,
+	.rxfifo = SZ_128,
+	.txfifo = SZ_64,
+	.ahb_buf_size = SZ_1K,
+	.quirks = QUADSPI_QUIRK_SWAP_ENDIAN,
+	.little_endian = true,
 };
 
 static const struct fsl_qspi_devtype_data imx6sx_data = {
-	.devtype = FSL_QUADSPI_IMX6SX,
-	.rxfifo = 128,
-	.txfifo = 512,
-	.ahb_buf_size = 1024,
-	.driver_data = 0,
+	.rxfifo = SZ_128,
+	.txfifo = SZ_512,
+	.ahb_buf_size = SZ_1K,
+	.quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618,
+	.little_endian = true,
 };
 
-static const struct fsl_qspi_devtype_data imx6ul_7d_data = {
-	.devtype = FSL_QUADSPI_IMX6UL_7D,
-	.rxfifo = 128,
-	.txfifo = 512,
-	.ahb_buf_size = 1024,
-	.driver_data = 0,
+static const struct fsl_qspi_devtype_data imx7d_data = {
+	.rxfifo = SZ_128,
+	.txfifo = SZ_512,
+	.ahb_buf_size = SZ_1K,
+	.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
+		  QUADSPI_QUIRK_USE_TDH_SETTING,
+	.little_endian = true,
 };
 
-static const struct fsl_qspi_devtype_data imx7ulp_data = {
-	.devtype = FSL_QUADSPI_IMX7ULP,
-	.rxfifo = 64,
-	.txfifo = 64,
-	.ahb_buf_size = 128,
-	.driver_data = 0,
+static const struct fsl_qspi_devtype_data imx6ul_data = {
+	.rxfifo = SZ_128,
+	.txfifo = SZ_512,
+	.ahb_buf_size = SZ_1K,
+	.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
+		  QUADSPI_QUIRK_USE_TDH_SETTING,
+	.little_endian = true,
 };
 
-static u32 qspi_read32(u32 flags, u32 *addr)
+static const struct fsl_qspi_devtype_data ls1021a_data = {
+	.rxfifo = SZ_128,
+	.txfifo = SZ_64,
+	.ahb_buf_size = SZ_1K,
+	.quirks = 0,
+	.little_endian = false,
+};
+
+static const struct fsl_qspi_devtype_data ls1088a_data = {
+	.rxfifo = SZ_128,
+	.txfifo = SZ_128,
+	.ahb_buf_size = SZ_1K,
+	.quirks = QUADSPI_QUIRK_TKT253890,
+	.little_endian = true,
+};
+
+static const struct fsl_qspi_devtype_data ls2080a_data = {
+	.rxfifo = SZ_128,
+	.txfifo = SZ_64,
+	.ahb_buf_size = SZ_1K,
+	.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_BASE_INTERNAL,
+	.little_endian = true,
+};
+
+struct fsl_qspi {
+	struct udevice *dev;
+	void __iomem *iobase;
+	void __iomem *ahb_addr;
+	u32 memmap_phy;
+	const struct fsl_qspi_devtype_data *devtype_data;
+	int selected;
+};
+
+static inline int needs_swap_endian(struct fsl_qspi *q)
 {
-	return flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
-		in_be32(addr) : in_le32(addr);
+	return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN;
 }
 
-static void qspi_write32(u32 flags, u32 *addr, u32 val)
+static inline int needs_4x_clock(struct fsl_qspi *q)
 {
-	flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
-		out_be32(addr, val) : out_le32(addr, val);
+	return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK;
 }
 
-static inline int is_controller_busy(const struct fsl_qspi_priv *priv)
+static inline int needs_fill_txfifo(struct fsl_qspi *q)
 {
-	u32 val;
-	u32 mask = QSPI_SR_BUSY_MASK | QSPI_SR_AHB_ACC_MASK |
-		   QSPI_SR_IP_ACC_MASK;
-
-	if (priv->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG)
-		mask = (u32)cpu_to_be32(mask);
-
-	return readl_poll_timeout(&priv->regs->sr, val, !(val & mask), 1000);
+	return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890;
 }
 
-/* QSPI support swapping the flash read/write data
- * in hardware for LS102xA, but not for VF610 */
-static inline u32 qspi_endian_xchg(struct fsl_qspi_priv *priv, u32 data)
+static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
 {
-	if (priv->devtype_data->driver_data & QUADSPI_QUIRK_SWAP_ENDIAN)
-		return swab32(data);
-	else
-		return data;
+	return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618;
 }
 
-static void qspi_set_lut(struct fsl_qspi_priv *priv)
+static inline int needs_amba_base_offset(struct fsl_qspi *q)
 {
-	struct fsl_qspi_regs *regs = priv->regs;
-	u32 lut_base;
+	return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL);
+}
 
-	/* Unlock the LUT */
-	qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
-	qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_UNLOCK);
+static inline int needs_tdh_setting(struct fsl_qspi *q)
+{
+	return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING;
+}
 
-	/* Write Enable */
-	lut_base = SEQID_WREN * 4;
-	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREN) |
-		PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
-	qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
-	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
-	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
+/*
+ * An IC bug makes it necessary to rearrange the 32-bit data.
+ * Later chips, such as IMX6SLX, have fixed this bug.
+ */
+static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
+{
+	return needs_swap_endian(q) ? __swab32(a) : a;
+}
 
-	/* Fast Read */
-	lut_base = SEQID_FAST_READ * 4;
-#ifdef CONFIG_SPI_FLASH_BAR
-	qspi_write32(priv->flags, &regs->lut[lut_base],
-		     OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
-		     INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
-		     PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
-#else
-	if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
-		qspi_write32(priv->flags, &regs->lut[lut_base],
-			     OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
-			     INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
-			     PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
+/*
+ * R/W functions for big- or little-endian registers:
+ * The QSPI controller's endianness is independent of
+ * the CPU core's endianness. So far, although the CPU
+ * core is little-endian the QSPI controller can use
+ * big-endian or little-endian.
+ */
+static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
+{
+	if (q->devtype_data->little_endian)
+		out_le32(addr, val);
 	else
-		qspi_write32(priv->flags, &regs->lut[lut_base],
-			     OPRND0(QSPI_CMD_FAST_READ_4B) |
-			     PAD0(LUT_PAD1) | INSTR0(LUT_CMD) |
-			     OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) |
-			     INSTR1(LUT_ADDR));
-#endif
-	qspi_write32(priv->flags, &regs->lut[lut_base + 1],
-		     OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
-		     OPRND1(priv->devtype_data->rxfifo) | PAD1(LUT_PAD1) |
-		     INSTR1(LUT_READ));
-	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
-	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
+		out_be32(addr, val);
+}
 
-	/* Read Status */
-	lut_base = SEQID_RDSR * 4;
-	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDSR) |
-		PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
-		PAD1(LUT_PAD1) | INSTR1(LUT_READ));
-	qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
-	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
-	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
+static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
+{
+	if (q->devtype_data->little_endian)
+		return in_le32(addr);
 
-	/* Erase a sector */
-	lut_base = SEQID_SE * 4;
-#ifdef CONFIG_SPI_FLASH_BAR
-	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_SE) |
-		     PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
-		     PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
-#else
-	if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
-		qspi_write32(priv->flags, &regs->lut[lut_base],
-			     OPRND0(QSPI_CMD_SE) | PAD0(LUT_PAD1) |
-			     INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
-			     PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
-	else
-		qspi_write32(priv->flags, &regs->lut[lut_base],
-			     OPRND0(QSPI_CMD_SE_4B) | PAD0(LUT_PAD1) |
-			     INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
-			     PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
-#endif
-	qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
-	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
-	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
+	return in_be32(addr);
+}
 
-	/* Erase the whole chip */
-	lut_base = SEQID_CHIP_ERASE * 4;
-	qspi_write32(priv->flags, &regs->lut[lut_base],
-		     OPRND0(QSPI_CMD_CHIP_ERASE) |
-		     PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
-	qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
-	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
-	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
+static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width)
+{
+	switch (width) {
+	case 1:
+	case 2:
+	case 4:
+		return 0;
+	}
 
-	/* Page Program */
-	lut_base = SEQID_PP * 4;
-#ifdef CONFIG_SPI_FLASH_BAR
-	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_PP) |
-		     PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
-		     PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
-#else
-	if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
-		qspi_write32(priv->flags, &regs->lut[lut_base],
-			     OPRND0(QSPI_CMD_PP) | PAD0(LUT_PAD1) |
-			     INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
-			     PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
-	else
-		qspi_write32(priv->flags, &regs->lut[lut_base],
-			     OPRND0(QSPI_CMD_PP_4B) | PAD0(LUT_PAD1) |
-			     INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
-			     PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
-#endif
-	/* Use IDATSZ in IPCR to determine the size and here set 0. */
-	qspi_write32(priv->flags, &regs->lut[lut_base + 1], OPRND0(0) |
-		     PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
-	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
-	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
+	return -ENOTSUPP;
+}
 
-	/* READ ID */
-	lut_base = SEQID_RDID * 4;
-	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDID) |
-		PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) |
-		PAD1(LUT_PAD1) | INSTR1(LUT_READ));
-	qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
-	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
-	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
+static bool fsl_qspi_supports_op(struct spi_slave *slave,
+				 const struct spi_mem_op *op)
+{
+	struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
+	int ret;
 
-	/* SUB SECTOR 4K ERASE */
-	lut_base = SEQID_BE_4K * 4;
-	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) |
-		     PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
-		     PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
+	ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth);
 
-#ifdef CONFIG_SPI_FLASH_BAR
-	/*
-	 * BRRD BRWR RDEAR WREAR are all supported, because it is hard to
-	 * dynamically check whether to set BRRD BRWR or RDEAR WREAR during
-	 * initialization.
-	 */
-	lut_base = SEQID_BRRD * 4;
-	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRRD) |
-		     PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
-		     PAD1(LUT_PAD1) | INSTR1(LUT_READ));
+	if (op->addr.nbytes)
+		ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth);
 
-	lut_base = SEQID_BRWR * 4;
-	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRWR) |
-		     PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
-		     PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
+	if (op->dummy.nbytes)
+		ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth);
 
-	lut_base = SEQID_RDEAR * 4;
-	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) |
-		     PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
-		     PAD1(LUT_PAD1) | INSTR1(LUT_READ));
+	if (op->data.nbytes)
+		ret |= fsl_qspi_check_buswidth(q, op->data.buswidth);
 
-	lut_base = SEQID_WREAR * 4;
-	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREAR) |
-		     PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
-		     PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
-#endif
+	if (ret)
+		return false;
 
 	/*
-	 * Read any device register.
-	 * Used for Spansion S25FS-S family flash only.
+	 * The number of instructions needed for the op, needs
+	 * to fit into a single LUT entry.
 	 */
-	lut_base = SEQID_RDAR * 4;
-	qspi_write32(priv->flags, &regs->lut[lut_base],
-		     OPRND0(QSPI_CMD_RDAR) | PAD0(LUT_PAD1) |
-		     INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
-		     PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
-	qspi_write32(priv->flags, &regs->lut[lut_base + 1],
-		     OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
-		     OPRND1(1) | PAD1(LUT_PAD1) |
-		     INSTR1(LUT_READ));
+	if (op->addr.nbytes +
+	   (op->dummy.nbytes ? 1 : 0) +
+	   (op->data.nbytes ? 1 : 0) > 6)
+		return false;
 
-	/*
-	 * Write any device register.
-	 * Used for Spansion S25FS-S family flash only.
-	 */
-	lut_base = SEQID_WRAR * 4;
-	qspi_write32(priv->flags, &regs->lut[lut_base],
-		     OPRND0(QSPI_CMD_WRAR) | PAD0(LUT_PAD1) |
-		     INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
-		     PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
-	qspi_write32(priv->flags, &regs->lut[lut_base + 1],
-		     OPRND0(1) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
+	/* Max 64 dummy clock cycles supported */
+	if (op->dummy.nbytes &&
+	    (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
+		return false;
 
-	/* Lock the LUT */
-	qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
-	qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_LOCK);
+	/* Max data length, check controller limits and alignment */
+	if (op->data.dir == SPI_MEM_DATA_IN &&
+	    (op->data.nbytes > q->devtype_data->ahb_buf_size ||
+	     (op->data.nbytes > q->devtype_data->rxfifo - 4 &&
+	      !IS_ALIGNED(op->data.nbytes, 8))))
+		return false;
+
+	if (op->data.dir == SPI_MEM_DATA_OUT &&
+	    op->data.nbytes > q->devtype_data->txfifo)
+		return false;
+
+	return true;
 }
 
-#if defined(CONFIG_SYS_FSL_QSPI_AHB)
-/*
- * If we have changed the content of the flash by writing or erasing,
- * we need to invalidate the AHB buffer. If we do not do so, we may read out
- * the wrong data. The spec tells us reset the AHB domain and Serial Flash
- * domain at the same time.
- */
-static inline void qspi_ahb_invalid(struct fsl_qspi_priv *priv)
+static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
+				 const struct spi_mem_op *op)
 {
-	struct fsl_qspi_regs *regs = priv->regs;
-	u32 reg;
+	void __iomem *base = q->iobase;
+	u32 lutval[4] = {};
+	int lutidx = 1, i;
 
-	reg = qspi_read32(priv->flags, &regs->mcr);
-	reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK;
-	qspi_write32(priv->flags, &regs->mcr, reg);
+	lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
+			     op->cmd.opcode);
 
 	/*
-	 * The minimum delay : 1 AHB + 2 SFCK clocks.
-	 * Delay 1 us is enough.
+	 * For some unknown reason, using LUT_ADDR doesn't work in some
+	 * cases (at least with only one byte long addresses), so
+	 * let's use LUT_MODE to write the address bytes one by one
 	 */
-	udelay(1);
-
-	reg &= ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK);
-	qspi_write32(priv->flags, &regs->mcr, reg);
-}
+	for (i = 0; i < op->addr.nbytes; i++) {
+		u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
 
-/* Read out the data from the AHB buffer. */
-static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
-{
-	struct fsl_qspi_regs *regs = priv->regs;
-	u32 mcr_reg;
-	void *rx_addr;
-
-	mcr_reg = qspi_read32(priv->flags, &regs->mcr);
-
-	qspi_write32(priv->flags, &regs->mcr,
-		     QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
-		     mcr_reg);
+		lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE,
+					      LUT_PAD(op->addr.buswidth),
+					      addrbyte);
+		lutidx++;
+	}
 
-	rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr);
-	/* Read out the data directly from the AHB buffer. */
-	memcpy(rxbuf, rx_addr, len);
+	if (op->dummy.nbytes) {
+		lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
+					      LUT_PAD(op->dummy.buswidth),
+					      op->dummy.nbytes * 8 /
+					      op->dummy.buswidth);
+		lutidx++;
+	}
 
-	qspi_write32(priv->flags, &regs->mcr, mcr_reg);
-}
+	if (op->data.nbytes) {
+		lutval[lutidx / 2] |= LUT_DEF(lutidx,
+					      op->data.dir == SPI_MEM_DATA_IN ?
+					      LUT_FSL_READ : LUT_FSL_WRITE,
+					      LUT_PAD(op->data.buswidth),
+					      0);
+		lutidx++;
+	}
 
-static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
-{
-	u32 reg, reg2;
-	struct fsl_qspi_regs *regs = priv->regs;
+	lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
 
-	reg = qspi_read32(priv->flags, &regs->mcr);
-	/* Disable the module */
-	qspi_write32(priv->flags, &regs->mcr, reg | QSPI_MCR_MDIS_MASK);
+	/* unlock LUT */
+	qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+	qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
 
-	/* Set the Sampling Register for DDR */
-	reg2 = qspi_read32(priv->flags, &regs->smpr);
-	reg2 &= ~QSPI_SMPR_DDRSMP_MASK;
-	reg2 |= (2 << QSPI_SMPR_DDRSMP_SHIFT);
-	qspi_write32(priv->flags, &regs->smpr, reg2);
+	dev_dbg(q->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n",
+		op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]);
 
-	/* Enable the module again (enable the DDR too) */
-	reg |= QSPI_MCR_DDR_EN_MASK;
-	/* Enable bit 29 for imx6sx */
-	reg |= BIT(29);
-	qspi_write32(priv->flags, &regs->mcr, reg);
+	/* fill LUT */
+	for (i = 0; i < ARRAY_SIZE(lutval); i++)
+		qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
 
-	/* Enable the TDH to 1 for some platforms like imx6ul, imx7d, etc
-	 * These two bits are reserved on other platforms
-	 */
-	reg = qspi_read32(priv->flags, &regs->flshcr);
-	reg &= ~(BIT(17));
-	reg |= BIT(16);
-	qspi_write32(priv->flags, &regs->flshcr, reg);
+	/* lock LUT */
+	qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+	qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
 }
 
 /*
- * There are two different ways to read out the data from the flash:
- *  the "IP Command Read" and the "AHB Command Read".
- *
- * The IC guy suggests we use the "AHB Command Read" which is faster
- * then the "IP Command Read". (What's more is that there is a bug in
- * the "IP Command Read" in the Vybrid.)
- *
- * After we set up the registers for the "AHB Command Read", we can use
- * the memcpy to read the data directly. A "missed" access to the buffer
- * causes the controller to clear the buffer, and use the sequence pointed
- * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
+ * If we have changed the content of the flash by writing or erasing, or if we
+ * read from flash with a different offset into the page buffer, we need to
+ * invalidate the AHB buffer. If we do not do so, we may read out the wrong
+ * data. The spec tells us reset the AHB domain and Serial Flash domain at
+ * the same time.
  */
-static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
+static void fsl_qspi_invalidate(struct fsl_qspi *q)
 {
-	struct fsl_qspi_regs *regs = priv->regs;
-
-	/* AHB configuration for access buffer 0/1/2 .*/
-	qspi_write32(priv->flags, &regs->buf0cr, QSPI_BUFXCR_INVALID_MSTRID);
-	qspi_write32(priv->flags, &regs->buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
-	qspi_write32(priv->flags, &regs->buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
-	qspi_write32(priv->flags, &regs->buf3cr, QSPI_BUF3CR_ALLMST_MASK |
-		     ((priv->devtype_data->ahb_buf_size >> 3) << QSPI_BUF3CR_ADATSZ_SHIFT));
+	u32 reg;
 
-	/* We only use the buffer3 */
-	qspi_write32(priv->flags, &regs->buf0ind, 0);
-	qspi_write32(priv->flags, &regs->buf1ind, 0);
-	qspi_write32(priv->flags, &regs->buf2ind, 0);
+	reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
+	reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
+	qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
 
 	/*
-	 * Set the default lut sequence for AHB Read.
-	 * Parallel mode is disabled.
+	 * The minimum delay : 1 AHB + 2 SFCK clocks.
+	 * Delay 1 us is enough.
 	 */
-	qspi_write32(priv->flags, &regs->bfgencr,
-		     SEQID_FAST_READ << QSPI_BFGENCR_SEQID_SHIFT);
+	udelay(1);
 
-	/*Enable DDR Mode*/
-	qspi_enable_ddr_mode(priv);
+	reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
+	qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
 }
-#endif
 
-#ifdef CONFIG_SPI_FLASH_BAR
-/* Bank register read/write, EAR register read/write */
-static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len)
+static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_slave *slave)
 {
-	struct fsl_qspi_regs *regs = priv->regs;
-	u32 reg, mcr_reg, data, seqid;
-
-	mcr_reg = qspi_read32(priv->flags, &regs->mcr);
-	qspi_write32(priv->flags, &regs->mcr,
-		     QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
-		     mcr_reg);
-	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
-
-	qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
+	struct dm_spi_slave_platdata *plat =
+		dev_get_parent_platdata(slave->dev);
 
-	if (priv->cur_seqid == QSPI_CMD_BRRD)
-		seqid = SEQID_BRRD;
-	else
-		seqid = SEQID_RDEAR;
-
-	qspi_write32(priv->flags, &regs->ipcr,
-		     (seqid << QSPI_IPCR_SEQID_SHIFT) | len);
-
-	/* Wait previous command complete */
-	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
-		;
-
-	while (1) {
-		WATCHDOG_RESET();
+	if (q->selected == plat->cs)
+		return;
 
-		reg = qspi_read32(priv->flags, &regs->rbsr);
-		if (reg & QSPI_RBSR_RDBFL_MASK) {
-			data = qspi_read32(priv->flags, &regs->rbdr[0]);
-			data = qspi_endian_xchg(priv, data);
-			memcpy(rxbuf, &data, len);
-			qspi_write32(priv->flags, &regs->mcr,
-				     qspi_read32(priv->flags, &regs->mcr) |
-				     QSPI_MCR_CLR_RXF_MASK);
-			break;
-		}
-	}
-
-	qspi_write32(priv->flags, &regs->mcr, mcr_reg);
+	q->selected = plat->cs;
+	fsl_qspi_invalidate(q);
 }
-#endif
 
-static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
+static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)
 {
-	struct fsl_qspi_regs *regs = priv->regs;
-	u32 mcr_reg, rbsr_reg, data, size;
-	int i;
-
-	mcr_reg = qspi_read32(priv->flags, &regs->mcr);
-	qspi_write32(priv->flags, &regs->mcr,
-		     QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
-		     mcr_reg);
-	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
-
-	qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
-
-	qspi_write32(priv->flags, &regs->ipcr,
-		     (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0);
-	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
-		;
-
-	i = 0;
-	while ((priv->devtype_data->rxfifo >= len) && (len > 0)) {
-		WATCHDOG_RESET();
-
-		rbsr_reg = qspi_read32(priv->flags, &regs->rbsr);
-		if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
-			data = qspi_read32(priv->flags, &regs->rbdr[i]);
-			data = qspi_endian_xchg(priv, data);
-			size = (len < 4) ? len : 4;
-			memcpy(rxbuf, &data, size);
-			len -= size;
-			rxbuf++;
-			i++;
-		}
-	}
-
-	qspi_write32(priv->flags, &regs->mcr, mcr_reg);
+	memcpy_fromio(op->data.buf.in,
+		      q->ahb_addr + q->selected * q->devtype_data->ahb_buf_size,
+		      op->data.nbytes);
 }
 
-/* If not use AHB read, read data from ip interface */
-static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
+static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,
+				 const struct spi_mem_op *op)
 {
-	struct fsl_qspi_regs *regs = priv->regs;
-	u32 mcr_reg, data;
-	int i, size;
-	u32 to_or_from;
-	u32 seqid;
-
-	if (priv->cur_seqid == QSPI_CMD_RDAR)
-		seqid = SEQID_RDAR;
-	else
-		seqid = SEQID_FAST_READ;
-
-	mcr_reg = qspi_read32(priv->flags, &regs->mcr);
-	qspi_write32(priv->flags, &regs->mcr,
-		     QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
-		     mcr_reg);
-	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
-
-	to_or_from = priv->sf_addr + priv->cur_amba_base;
-
-	while (len > 0) {
-		WATCHDOG_RESET();
-
-		qspi_write32(priv->flags, &regs->sfar, to_or_from);
-
-		size = (len > priv->devtype_data->rxfifo) ?
-			priv->devtype_data->rxfifo : len;
-
-		qspi_write32(priv->flags, &regs->ipcr,
-			     (seqid << QSPI_IPCR_SEQID_SHIFT) |
-			     size);
-		while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
-			;
+	void __iomem *base = q->iobase;
+	int i;
+	u32 val;
 
-		to_or_from += size;
-		len -= size;
+	for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
+		memcpy(&val, op->data.buf.out + i, 4);
+		val = fsl_qspi_endian_xchg(q, val);
+		qspi_writel(q, val, base + QUADSPI_TBDR);
+	}
 
-		i = 0;
-		while ((priv->devtype_data->rxfifo >= size) && (size > 0)) {
-			data = qspi_read32(priv->flags, &regs->rbdr[i]);
-			data = qspi_endian_xchg(priv, data);
-			if (size < 4)
-				memcpy(rxbuf, &data, size);
-			else
-				memcpy(rxbuf, &data, 4);
-			rxbuf++;
-			size -= 4;
-			i++;
-		}
-		qspi_write32(priv->flags, &regs->mcr,
-			     qspi_read32(priv->flags, &regs->mcr) |
-			     QSPI_MCR_CLR_RXF_MASK);
+	if (i < op->data.nbytes) {
+		memcpy(&val, op->data.buf.out + i, op->data.nbytes - i);
+		val = fsl_qspi_endian_xchg(q, val);
+		qspi_writel(q, val, base + QUADSPI_TBDR);
 	}
 
-	qspi_write32(priv->flags, &regs->mcr, mcr_reg);
+	if (needs_fill_txfifo(q)) {
+		for (i = op->data.nbytes; i < 16; i += 4)
+			qspi_writel(q, 0, base + QUADSPI_TBDR);
+	}
 }
 
-static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)
+static void fsl_qspi_read_rxfifo(struct fsl_qspi *q,
+				 const struct spi_mem_op *op)
 {
-	struct fsl_qspi_regs *regs = priv->regs;
-	u32 mcr_reg, data, reg, status_reg, seqid;
-	int i, size, tx_size;
-	u32 to_or_from = 0;
-
-	mcr_reg = qspi_read32(priv->flags, &regs->mcr);
-	qspi_write32(priv->flags, &regs->mcr,
-		     QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
-		     mcr_reg);
-	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
-
-	status_reg = 0;
-	while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) {
-		WATCHDOG_RESET();
-
-		qspi_write32(priv->flags, &regs->ipcr,
-			     (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
-		while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
-			;
-
-		qspi_write32(priv->flags, &regs->ipcr,
-			     (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1);
-		while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
-			;
+	void __iomem *base = q->iobase;
+	int i;
+	u8 *buf = op->data.buf.in;
+	u32 val;
 
-		reg = qspi_read32(priv->flags, &regs->rbsr);
-		if (reg & QSPI_RBSR_RDBFL_MASK) {
-			status_reg = qspi_read32(priv->flags, &regs->rbdr[0]);
-			status_reg = qspi_endian_xchg(priv, status_reg);
-		}
-		qspi_write32(priv->flags, &regs->mcr,
-			     qspi_read32(priv->flags, &regs->mcr) |
-			     QSPI_MCR_CLR_RXF_MASK);
+	for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
+		val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
+		val = fsl_qspi_endian_xchg(q, val);
+		memcpy(buf + i, &val, 4);
 	}
 
-	/* Default is page programming */
-	seqid = SEQID_PP;
-	if (priv->cur_seqid == QSPI_CMD_WRAR)
-		seqid = SEQID_WRAR;
-#ifdef CONFIG_SPI_FLASH_BAR
-	if (priv->cur_seqid == QSPI_CMD_BRWR)
-		seqid = SEQID_BRWR;
-	else if (priv->cur_seqid == QSPI_CMD_WREAR)
-		seqid = SEQID_WREAR;
-#endif
-
-	to_or_from = priv->sf_addr + priv->cur_amba_base;
-
-	qspi_write32(priv->flags, &regs->sfar, to_or_from);
-
-	tx_size = (len > priv->devtype_data->txfifo) ?
-		priv->devtype_data->txfifo : len;
-
-	size = tx_size / 16;
-	/*
-	 * There must be atleast 128bit data
-	 * available in TX FIFO for any pop operation
-	 */
-	if (tx_size % 16)
-		size++;
-	for (i = 0; i < size * 4; i++) {
-		memcpy(&data, txbuf, 4);
-		data = qspi_endian_xchg(priv, data);
-		qspi_write32(priv->flags, &regs->tbdr, data);
-		txbuf += 4;
+	if (i < op->data.nbytes) {
+		val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
+		val = fsl_qspi_endian_xchg(q, val);
+		memcpy(buf + i, &val, op->data.nbytes - i);
 	}
-
-	qspi_write32(priv->flags, &regs->ipcr,
-		     (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size);
-	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
-		;
-
-	qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 }
 
-static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len)
+static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base,
+				    u32 mask, u32 delay_us, u32 timeout_us)
 {
-	struct fsl_qspi_regs *regs = priv->regs;
-	u32 mcr_reg, reg, data;
-
-	mcr_reg = qspi_read32(priv->flags, &regs->mcr);
-	qspi_write32(priv->flags, &regs->mcr,
-		     QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
-		     mcr_reg);
-	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
-
-	qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
-
-	qspi_write32(priv->flags, &regs->ipcr,
-		     (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0);
-	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
-		;
-
-	while (1) {
-		WATCHDOG_RESET();
+	u32 reg;
 
-		reg = qspi_read32(priv->flags, &regs->rbsr);
-		if (reg & QSPI_RBSR_RDBFL_MASK) {
-			data = qspi_read32(priv->flags, &regs->rbdr[0]);
-			data = qspi_endian_xchg(priv, data);
-			memcpy(rxbuf, &data, len);
-			qspi_write32(priv->flags, &regs->mcr,
-				     qspi_read32(priv->flags, &regs->mcr) |
-				     QSPI_MCR_CLR_RXF_MASK);
-			break;
-		}
-	}
+	if (!q->devtype_data->little_endian)
+		mask = (u32)cpu_to_be32(mask);
 
-	qspi_write32(priv->flags, &regs->mcr, mcr_reg);
+	return readl_poll_timeout(base, reg, !(reg & mask), timeout_us);
 }
 
-static void qspi_op_erase(struct fsl_qspi_priv *priv)
+static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op *op)
 {
-	struct fsl_qspi_regs *regs = priv->regs;
-	u32 mcr_reg;
-	u32 to_or_from = 0;
+	void __iomem *base = q->iobase;
+	int err = 0;
 
-	mcr_reg = qspi_read32(priv->flags, &regs->mcr);
-	qspi_write32(priv->flags, &regs->mcr,
-		     QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
-		     mcr_reg);
-	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
-
-	to_or_from = priv->sf_addr + priv->cur_amba_base;
-	qspi_write32(priv->flags, &regs->sfar, to_or_from);
+	/*
+	 * Always start the sequence at the same index since we update
+	 * the LUT at each exec_op() call. And also specify the DATA
+	 * length, since it's has not been specified in the LUT.
+	 */
+	qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT),
+		    base + QUADSPI_IPCR);
 
-	qspi_write32(priv->flags, &regs->ipcr,
-		     (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
-	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
-		;
+	/* wait for the controller being ready */
+	err = fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR,
+				       (QUADSPI_SR_IP_ACC_MASK |
+					QUADSPI_SR_AHB_ACC_MASK),
+					10, 1000);
 
-	if (priv->cur_seqid == QSPI_CMD_SE) {
-		qspi_write32(priv->flags, &regs->ipcr,
-			     (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0);
-	} else if (priv->cur_seqid == QSPI_CMD_BE_4K) {
-		qspi_write32(priv->flags, &regs->ipcr,
-			     (SEQID_BE_4K << QSPI_IPCR_SEQID_SHIFT) | 0);
-	}
-	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
-		;
+	if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
+		fsl_qspi_read_rxfifo(q, op);
 
-	qspi_write32(priv->flags, &regs->mcr, mcr_reg);
+	return err;
 }
 
-int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
-		const void *dout, void *din, unsigned long flags)
+static int fsl_qspi_exec_op(struct spi_slave *slave,
+			    const struct spi_mem_op *op)
 {
-	u32 bytes = DIV_ROUND_UP(bitlen, 8);
-	static u32 wr_sfaddr;
-	u32 txbuf;
+	struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
+	void __iomem *base = q->iobase;
+	u32 addr_offset = 0;
+	int err = 0;
 
-	WATCHDOG_RESET();
+	/* wait for the controller being ready */
+	fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK |
+				 QUADSPI_SR_AHB_ACC_MASK), 10, 1000);
 
-	if (dout) {
-		if (flags & SPI_XFER_BEGIN) {
-			priv->cur_seqid = *(u8 *)dout;
-			memcpy(&txbuf, dout, 4);
-		}
+	fsl_qspi_select_mem(q, slave);
 
-		if (flags == SPI_XFER_END) {
-			priv->sf_addr = wr_sfaddr;
-			qspi_op_write(priv, (u8 *)dout, bytes);
-			return 0;
-		}
+	if (needs_amba_base_offset(q))
+		addr_offset = q->memmap_phy;
 
-		if (priv->cur_seqid == QSPI_CMD_FAST_READ ||
-		    priv->cur_seqid == QSPI_CMD_RDAR) {
-			priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
-		} else if ((priv->cur_seqid == QSPI_CMD_SE) ||
-			   (priv->cur_seqid == QSPI_CMD_BE_4K)) {
-			priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
-			qspi_op_erase(priv);
-		} else if (priv->cur_seqid == QSPI_CMD_PP ||
-			   priv->cur_seqid == QSPI_CMD_WRAR) {
-			wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
-		} else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||
-			 (priv->cur_seqid == QSPI_CMD_WREAR)) {
-#ifdef CONFIG_SPI_FLASH_BAR
-			wr_sfaddr = 0;
-#endif
-		}
-	}
+	qspi_writel(q,
+		    q->selected * q->devtype_data->ahb_buf_size + addr_offset,
+		    base + QUADSPI_SFAR);
 
-	if (din) {
-		if (priv->cur_seqid == QSPI_CMD_FAST_READ) {
-#ifdef CONFIG_SYS_FSL_QSPI_AHB
-			qspi_ahb_read(priv, din, bytes);
-#else
-			qspi_op_read(priv, din, bytes);
-#endif
-		} else if (priv->cur_seqid == QSPI_CMD_RDAR) {
-			qspi_op_read(priv, din, bytes);
-		} else if (priv->cur_seqid == QSPI_CMD_RDID)
-			qspi_op_rdid(priv, din, bytes);
-		else if (priv->cur_seqid == QSPI_CMD_RDSR)
-			qspi_op_rdsr(priv, din, bytes);
-#ifdef CONFIG_SPI_FLASH_BAR
-		else if ((priv->cur_seqid == QSPI_CMD_BRRD) ||
-			 (priv->cur_seqid == QSPI_CMD_RDEAR)) {
-			priv->sf_addr = 0;
-			qspi_op_rdbank(priv, din, bytes);
-		}
-#endif
-	}
+	qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
+		    QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK,
+		    base + QUADSPI_MCR);
 
-#ifdef CONFIG_SYS_FSL_QSPI_AHB
-	if ((priv->cur_seqid == QSPI_CMD_SE) ||
-	    (priv->cur_seqid == QSPI_CMD_PP) ||
-	    (priv->cur_seqid == QSPI_CMD_BE_4K) ||
-	    (priv->cur_seqid == QSPI_CMD_WREAR) ||
-	    (priv->cur_seqid == QSPI_CMD_BRWR))
-		qspi_ahb_invalid(priv);
-#endif
+	qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,
+		    base + QUADSPI_SPTRCLR);
 
-	return 0;
-}
+	fsl_qspi_prepare_lut(q, op);
 
-void qspi_module_disable(struct fsl_qspi_priv *priv, u8 disable)
-{
-	u32 mcr_val;
+	/*
+	 * If we have large chunks of data, we read them through the AHB bus
+	 * by accessing the mapped memory. In all other cases we use
+	 * IP commands to access the flash.
+	 */
+	if (op->data.nbytes > (q->devtype_data->rxfifo - 4) &&
+	    op->data.dir == SPI_MEM_DATA_IN) {
+		fsl_qspi_read_ahb(q, op);
+	} else {
+		qspi_writel(q, QUADSPI_RBCT_WMRK_MASK |
+			    QUADSPI_RBCT_RXBRD_USEIPS, base + QUADSPI_RBCT);
 
-	mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
-	if (disable)
-		mcr_val |= QSPI_MCR_MDIS_MASK;
-	else
-		mcr_val &= ~QSPI_MCR_MDIS_MASK;
-	qspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
-}
+		if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
+			fsl_qspi_fill_txfifo(q, op);
 
-void qspi_cfg_smpr(struct fsl_qspi_priv *priv, u32 clear_bits, u32 set_bits)
-{
-	u32 smpr_val;
+		err = fsl_qspi_do_op(q, op);
+	}
+
+	/* Invalidate the data in the AHB buffer. */
+	fsl_qspi_invalidate(q);
 
-	smpr_val = qspi_read32(priv->flags, &priv->regs->smpr);
-	smpr_val &= ~clear_bits;
-	smpr_val |= set_bits;
-	qspi_write32(priv->flags, &priv->regs->smpr, smpr_val);
+	return err;
 }
 
-static int fsl_qspi_child_pre_probe(struct udevice *dev)
+static int fsl_qspi_adjust_op_size(struct spi_slave *slave,
+				   struct spi_mem_op *op)
 {
-	struct spi_slave *slave = dev_get_parent_priv(dev);
-	struct fsl_qspi_priv *priv = dev_get_priv(dev_get_parent(dev));
+	struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
 
-	slave->max_write_size = priv->devtype_data->txfifo;
+	if (op->data.dir == SPI_MEM_DATA_OUT) {
+		if (op->data.nbytes > q->devtype_data->txfifo)
+			op->data.nbytes = q->devtype_data->txfifo;
+	} else {
+		if (op->data.nbytes > q->devtype_data->ahb_buf_size)
+			op->data.nbytes = q->devtype_data->ahb_buf_size;
+		else if (op->data.nbytes > (q->devtype_data->rxfifo - 4))
+			op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
+	}
 
 	return 0;
 }
 
-static int fsl_qspi_probe(struct udevice *bus)
+static int fsl_qspi_default_setup(struct fsl_qspi *q)
 {
-	u32 amba_size_per_chip;
-	struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
-	struct fsl_qspi_priv *priv = dev_get_priv(bus);
-	struct dm_spi_bus *dm_spi_bus;
-	int i, ret;
+	void __iomem *base = q->iobase;
+	u32 reg, addr_offset = 0;
 
-	dm_spi_bus = bus->uclass_priv;
-
-	dm_spi_bus->max_hz = plat->speed_hz;
+	/* Reset the module */
+	qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
+		    base + QUADSPI_MCR);
+	udelay(1);
 
-	priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base;
-	priv->flags = plat->flags;
+	/* Disable the module */
+	qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
+		    base + QUADSPI_MCR);
 
-	priv->speed_hz = plat->speed_hz;
 	/*
-	 * QSPI SFADR width is 32bits, the max dest addr is 4GB-1.
-	 * AMBA memory zone should be located on the 0~4GB space
-	 * even on a 64bits cpu.
+	 * Previous boot stages (BootROM, bootloader) might have used DDR
+	 * mode and did not clear the TDH bits. As we currently use SDR mode
+	 * only, clear the TDH bits if necessary.
 	 */
-	priv->amba_base[0] = (u32)plat->amba_base;
-	priv->amba_total_size = (u32)plat->amba_total_size;
-	priv->flash_num = plat->flash_num;
-	priv->num_chipselect = plat->num_chipselect;
+	if (needs_tdh_setting(q))
+		qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) &
+			    ~QUADSPI_FLSHCR_TDH_MASK,
+			    base + QUADSPI_FLSHCR);
 
-	priv->devtype_data = (struct fsl_qspi_devtype_data *)dev_get_driver_data(bus);
-	if (!priv->devtype_data) {
-		printf("ERROR : No devtype_data found\n");
-		return -ENODEV;
-	}
-
-	debug("devtype=%d, txfifo=%d, rxfifo=%d, ahb=%d, data=0x%x\n",
-		priv->devtype_data->devtype,
-		priv->devtype_data->txfifo,
-		priv->devtype_data->rxfifo,
-		priv->devtype_data->ahb_buf_size,
-		priv->devtype_data->driver_data);
+	reg = qspi_readl(q, base + QUADSPI_SMPR);
+	qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
+			| QUADSPI_SMPR_FSPHS_MASK
+			| QUADSPI_SMPR_HSENA_MASK
+			| QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
 
-	/* make sure controller is not busy anywhere */
-	ret = is_controller_busy(priv);
+	/* We only use the buffer3 for AHB read */
+	qspi_writel(q, 0, base + QUADSPI_BUF0IND);
+	qspi_writel(q, 0, base + QUADSPI_BUF1IND);
+	qspi_writel(q, 0, base + QUADSPI_BUF2IND);
 
-	if (ret) {
-		debug("ERROR : The controller is busy\n");
-		return ret;
-	}
+	qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT),
+		    q->iobase + QUADSPI_BFGENCR);
+	qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);
+	qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
+		    QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8),
+		    base + QUADSPI_BUF3CR);
 
-	qspi_write32(priv->flags, &priv->regs->mcr,
-		     QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
-		     QSPI_MCR_END_CFD_LE);
-
-	qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
-		QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
+	if (needs_amba_base_offset(q))
+		addr_offset = q->memmap_phy;
 
 	/*
-	 * Assign AMBA memory zone for every chipselect
-	 * QuadSPI has two channels, every channel has two chipselects.
-	 * If the property 'num-cs' in dts is 2, the AMBA memory will be divided
-	 * into two parts and assign to every channel. This indicate that every
-	 * channel only has one valid chipselect.
-	 * If the property 'num-cs' in dts is 4, the AMBA memory will be divided
-	 * into four parts and assign to every chipselect.
-	 * Every channel will has two valid chipselects.
+	 * In HW there can be a maximum of four chips on two buses with
+	 * two chip selects on each bus. We use four chip selects in SW
+	 * to differentiate between the four chips.
+	 * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD,
+	 * SFB2AD accordingly.
 	 */
-	amba_size_per_chip = priv->amba_total_size >>
-			     (priv->num_chipselect >> 1);
-	for (i = 1 ; i < priv->num_chipselect ; i++)
-		priv->amba_base[i] =
-			amba_size_per_chip + priv->amba_base[i - 1];
-
-	/*
-	 * Any read access to non-implemented addresses will provide
-	 * undefined results.
-	 *
-	 * In case single die flash devices, TOP_ADDR_MEMA2 and
-	 * TOP_ADDR_MEMB2 should be initialized/programmed to
-	 * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
-	 * setting the size of these devices to 0.  This would ensure
-	 * that the complete memory map is assigned to only one flash device.
-	 */
-	qspi_write32(priv->flags, &priv->regs->sfa1ad,
-		     priv->amba_base[0] + amba_size_per_chip);
-	switch (priv->num_chipselect) {
-	case 1:
-		break;
-	case 2:
-		qspi_write32(priv->flags, &priv->regs->sfa2ad,
-			     priv->amba_base[1]);
-		qspi_write32(priv->flags, &priv->regs->sfb1ad,
-			     priv->amba_base[1] + amba_size_per_chip);
-		qspi_write32(priv->flags, &priv->regs->sfb2ad,
-			     priv->amba_base[1] + amba_size_per_chip);
-		break;
-	case 4:
-		qspi_write32(priv->flags, &priv->regs->sfa2ad,
-			     priv->amba_base[2]);
-		qspi_write32(priv->flags, &priv->regs->sfb1ad,
-			     priv->amba_base[3]);
-		qspi_write32(priv->flags, &priv->regs->sfb2ad,
-			     priv->amba_base[3] + amba_size_per_chip);
-		break;
-	default:
-		debug("Error: Unsupported chipselect number %u!\n",
-		      priv->num_chipselect);
-		qspi_module_disable(priv, 1);
-		return -EINVAL;
-	}
-
-	qspi_set_lut(priv);
+	qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset,
+		    base + QUADSPI_SFA1AD);
+	qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset,
+		    base + QUADSPI_SFA2AD);
+	qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset,
+		    base + QUADSPI_SFB1AD);
+	qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset,
+		    base + QUADSPI_SFB2AD);
 
-#ifdef CONFIG_SYS_FSL_QSPI_AHB
-	qspi_init_ahb_read(priv);
-#endif
+	q->selected = -1;
 
-	qspi_module_disable(priv, 0);
-
+	/* Enable the module */
+	qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
+		    base + QUADSPI_MCR);
 	return 0;
 }
 
+static const struct spi_controller_mem_ops fsl_qspi_mem_ops = {
+	.adjust_op_size = fsl_qspi_adjust_op_size,
+	.supports_op = fsl_qspi_supports_op,
+	.exec_op = fsl_qspi_exec_op,
+};
+
-static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
+static int fsl_qspi_probe(struct udevice *bus)
 {
-	struct fdt_resource res_regs, res_mem;
-	struct fsl_qspi_platdata *plat = bus->platdata;
+	struct dm_spi_bus *dm_bus = bus->uclass_priv;
+	struct fsl_qspi *q = dev_get_priv(bus);
 	const void *blob = gd->fdt_blob;
 	int node = dev_of_offset(bus);
-	int ret, flash_num = 0, subnode;
+	struct fdt_resource res;
+	int ret;
 
-	if (fdtdec_get_bool(blob, node, "big-endian"))
-		plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
+	q->dev = bus;
+	q->devtype_data = (struct fsl_qspi_devtype_data *)
+			   dev_get_driver_data(bus);
 
-	ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
-				     "QuadSPI", &res_regs);
+	/* find the resources */
+	ret = fdt_get_named_resource(blob, node, "reg", "reg-names", "QuadSPI",
+				     &res);
 	if (ret) {
-		debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
+		dev_err(bus, "Can't get regs base addresses(ret = %d)!\n", ret);
 		return -ENOMEM;
 	}
+
+	q->iobase = map_physmem(res.start, res.end - res.start, MAP_NOCACHE);
+
 	ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
-				     "QuadSPI-memory", &res_mem);
+				     "QuadSPI-memory", &res);
 	if (ret) {
-		debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret);
+		dev_err(bus, "Can't get AMBA base addresses(ret = %d)!\n", ret);
 		return -ENOMEM;
 	}
 
-	/* Count flash numbers */
-	fdt_for_each_subnode(subnode, blob, node)
-		++flash_num;
-
-	if (flash_num == 0) {
-		debug("Error: Missing flashes!\n");
-		return -ENODEV;
-	}
-
-	plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
-					FSL_QSPI_DEFAULT_SCK_FREQ);
-	plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs",
-					      FSL_QSPI_MAX_CHIPSELECT_NUM);
+	q->ahb_addr = map_physmem(res.start, res.end - res.start, MAP_NOCACHE);
+	q->memmap_phy = res.start;
 
-	plat->reg_base = res_regs.start;
-	plat->amba_base = res_mem.start;
-	plat->amba_total_size = res_mem.end - res_mem.start + 1;
-	plat->flash_num = flash_num;
+	dm_bus->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
+					66000000);
 
-	debug("%s: regs=<0x%llx> <0x%llx, 0x%llx>, max-frequency=%d, endianess=%s\n",
-	      __func__,
-	      (u64)plat->reg_base,
-	      (u64)plat->amba_base,
-	      (u64)plat->amba_total_size,
-	      plat->speed_hz,
-	      plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le"
-	      );
+	fsl_qspi_default_setup(q);
 
 	return 0;
 }
 
 static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen,
-		const void *dout, void *din, unsigned long flags)
+			 const void *dout, void *din, unsigned long flags)
 {
-	struct fsl_qspi_priv *priv;
-	struct udevice *bus;
-
-	bus = dev->parent;
-	priv = dev_get_priv(bus);
-
-	return qspi_xfer(priv, bitlen, dout, din, flags);
+	return 0;
 }
 
 static int fsl_qspi_claim_bus(struct udevice *dev)
 {
-	struct fsl_qspi_priv *priv;
-	struct udevice *bus;
-	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
-	int ret;
-
-	bus = dev->parent;
-	priv = dev_get_priv(bus);
-
-	/* make sure controller is not busy anywhere */
-	ret = is_controller_busy(priv);
-
-	if (ret) {
-		debug("ERROR : The controller is busy\n");
-		return ret;
-	}
-
-	priv->cur_amba_base = priv->amba_base[slave_plat->cs];
-
-	qspi_module_disable(priv, 0);
-
 	return 0;
 }
 
 static int fsl_qspi_release_bus(struct udevice *dev)
 {
-	struct fsl_qspi_priv *priv;
-	struct udevice *bus;
-
-	bus = dev->parent;
-	priv = dev_get_priv(bus);
-
-	qspi_module_disable(priv, 1);
-
 	return 0;
 }
 
 static int fsl_qspi_set_speed(struct udevice *bus, uint speed)
 {
-	/* Nothing to do */
 	return 0;
 }
 
 static int fsl_qspi_set_mode(struct udevice *bus, uint mode)
 {
-	/* Nothing to do */
 	return 0;
 }
 
@@ -1146,14 +785,17 @@
 	.xfer		= fsl_qspi_xfer,
 	.set_speed	= fsl_qspi_set_speed,
 	.set_mode	= fsl_qspi_set_mode,
+	.mem_ops	= &fsl_qspi_mem_ops,
 };
 
 static const struct udevice_id fsl_qspi_ids[] = {
-	{ .compatible = "fsl,vf610-qspi", .data = (ulong)&vybrid_data },
-	{ .compatible = "fsl,imx6sx-qspi", .data = (ulong)&imx6sx_data },
-	{ .compatible = "fsl,imx6ul-qspi", .data = (ulong)&imx6ul_7d_data },
-	{ .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx6ul_7d_data },
-	{ .compatible = "fsl,imx7ulp-qspi", .data = (ulong)&imx7ulp_data },
+	{ .compatible = "fsl,vf610-qspi", .data = (ulong)&vybrid_data, },
+	{ .compatible = "fsl,imx6sx-qspi", .data = (ulong)&imx6sx_data, },
+	{ .compatible = "fsl,imx6ul-qspi", .data = (ulong)&imx6ul_data, },
+	{ .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx7d_data, },
+	{ .compatible = "fsl,ls1021a-qspi", .data = (ulong)&ls1021a_data, },
+	{ .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls1088a_data, },
+	{ .compatible = "fsl,ls2080a-qspi", .data = (ulong)&ls2080a_data, },
 	{ }
 };
 
@@ -1162,9 +804,6 @@
 	.id	= UCLASS_SPI,
 	.of_match = fsl_qspi_ids,
 	.ops	= &fsl_qspi_ops,
-	.ofdata_to_platdata = fsl_qspi_ofdata_to_platdata,
-	.platdata_auto_alloc_size = sizeof(struct fsl_qspi_platdata),
-	.priv_auto_alloc_size = sizeof(struct fsl_qspi_priv),
+	.priv_auto_alloc_size = sizeof(struct fsl_qspi),
 	.probe	= fsl_qspi_probe,
-	.child_pre_probe = fsl_qspi_child_pre_probe,
 };
diff --git a/drivers/spi/fsl_qspi.h b/drivers/spi/fsl_qspi.h
deleted file mode 100644
index 9e61a85..0000000
--- a/drivers/spi/fsl_qspi.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013-2014 Freescale Semiconductor, Inc.
- *
- * Register definitions for Freescale QSPI
- */
-
-#ifndef _FSL_QSPI_H_
-#define _FSL_QSPI_H_
-
-struct fsl_qspi_regs {
-	u32 mcr;
-	u32 rsvd0[1];
-	u32 ipcr;
-	u32 flshcr;
-	u32 buf0cr;
-	u32 buf1cr;
-	u32 buf2cr;
-	u32 buf3cr;
-	u32 bfgencr;
-	u32 soccr;
-	u32 rsvd1[2];
-	u32 buf0ind;
-	u32 buf1ind;
-	u32 buf2ind;
-	u32 rsvd2[49];
-	u32 sfar;
-	u32 rsvd3[1];
-	u32 smpr;
-	u32 rbsr;
-	u32 rbct;
-	u32 rsvd4[15];
-	u32 tbsr;
-	u32 tbdr;
-	u32 rsvd5[1];
-	u32 sr;
-	u32 fr;
-	u32 rser;
-	u32 spndst;
-	u32 sptrclr;
-	u32 rsvd6[4];
-	u32 sfa1ad;
-	u32 sfa2ad;
-	u32 sfb1ad;
-	u32 sfb2ad;
-	u32 rsvd7[28];
-	u32 rbdr[32];
-	u32 rsvd8[32];
-	u32 lutkey;
-	u32 lckcr;
-	u32 rsvd9[2];
-	u32 lut[64];
-};
-
-#define QSPI_IPCR_SEQID_SHIFT		24
-#define QSPI_IPCR_SEQID_MASK		(0xf << QSPI_IPCR_SEQID_SHIFT)
-
-#define QSPI_MCR_END_CFD_SHIFT		2
-#define QSPI_MCR_END_CFD_MASK		(3 << QSPI_MCR_END_CFD_SHIFT)
-#ifdef CONFIG_SYS_FSL_QSPI_AHB
-/* AHB needs 64bit operation */
-#define QSPI_MCR_END_CFD_LE		(3 << QSPI_MCR_END_CFD_SHIFT)
-#else
-#define QSPI_MCR_END_CFD_LE		(1 << QSPI_MCR_END_CFD_SHIFT)
-#endif
-#define QSPI_MCR_DDR_EN_SHIFT		7
-#define QSPI_MCR_DDR_EN_MASK		(1 << QSPI_MCR_DDR_EN_SHIFT)
-#define QSPI_MCR_CLR_RXF_SHIFT		10
-#define QSPI_MCR_CLR_RXF_MASK		(1 << QSPI_MCR_CLR_RXF_SHIFT)
-#define QSPI_MCR_CLR_TXF_SHIFT		11
-#define QSPI_MCR_CLR_TXF_MASK		(1 << QSPI_MCR_CLR_TXF_SHIFT)
-#define QSPI_MCR_MDIS_SHIFT		14
-#define QSPI_MCR_MDIS_MASK		(1 << QSPI_MCR_MDIS_SHIFT)
-#define QSPI_MCR_RESERVED_SHIFT		16
-#define QSPI_MCR_RESERVED_MASK		(0xf << QSPI_MCR_RESERVED_SHIFT)
-#define QSPI_MCR_SWRSTHD_SHIFT		1
-#define QSPI_MCR_SWRSTHD_MASK		(1 << QSPI_MCR_SWRSTHD_SHIFT)
-#define QSPI_MCR_SWRSTSD_SHIFT		0
-#define QSPI_MCR_SWRSTSD_MASK		(1 << QSPI_MCR_SWRSTSD_SHIFT)
-
-#define QSPI_SMPR_HSENA_SHIFT		0
-#define QSPI_SMPR_HSENA_MASK		(1 << QSPI_SMPR_HSENA_SHIFT)
-#define QSPI_SMPR_FSPHS_SHIFT		5
-#define QSPI_SMPR_FSPHS_MASK		(1 << QSPI_SMPR_FSPHS_SHIFT)
-#define QSPI_SMPR_FSDLY_SHIFT		6
-#define QSPI_SMPR_FSDLY_MASK		(1 << QSPI_SMPR_FSDLY_SHIFT)
-#define QSPI_SMPR_DDRSMP_SHIFT		16
-#define QSPI_SMPR_DDRSMP_MASK		(7 << QSPI_SMPR_DDRSMP_SHIFT)
-
-#define QSPI_BUFXCR_INVALID_MSTRID	0xe
-#define QSPI_BUF3CR_ALLMST_SHIFT	31
-#define QSPI_BUF3CR_ALLMST_MASK		(1 << QSPI_BUF3CR_ALLMST_SHIFT)
-#define QSPI_BUF3CR_ADATSZ_SHIFT	8
-#define QSPI_BUF3CR_ADATSZ_MASK		(0xFF << QSPI_BUF3CR_ADATSZ_SHIFT)
-
-#define QSPI_BFGENCR_SEQID_SHIFT	12
-#define QSPI_BFGENCR_SEQID_MASK		(0xf << QSPI_BFGENCR_SEQID_SHIFT)
-#define QSPI_BFGENCR_PAR_EN_SHIFT	16
-#define QSPI_BFGENCR_PAR_EN_MASK	(1 << QSPI_BFGENCR_PAR_EN_SHIFT)
-
-#define QSPI_RBSR_RDBFL_SHIFT		8
-#define QSPI_RBSR_RDBFL_MASK		(0x3f << QSPI_RBSR_RDBFL_SHIFT)
-
-#define QSPI_RBCT_RXBRD_SHIFT		8
-#define QSPI_RBCT_RXBRD_USEIPS		(1 << QSPI_RBCT_RXBRD_SHIFT)
-
-#define QSPI_SR_AHB_ACC_SHIFT		2
-#define QSPI_SR_AHB_ACC_MASK		(1 << QSPI_SR_AHB_ACC_SHIFT)
-#define QSPI_SR_IP_ACC_SHIFT		1
-#define QSPI_SR_IP_ACC_MASK		(1 << QSPI_SR_IP_ACC_SHIFT)
-#define QSPI_SR_BUSY_SHIFT		0
-#define QSPI_SR_BUSY_MASK		(1 << QSPI_SR_BUSY_SHIFT)
-
-#define QSPI_LCKCR_LOCK			0x1
-#define QSPI_LCKCR_UNLOCK		0x2
-
-#define LUT_KEY_VALUE			0x5af05af0
-
-#define OPRND0_SHIFT			0
-#define OPRND0(x)			((x) << OPRND0_SHIFT)
-#define PAD0_SHIFT			8
-#define PAD0(x)				((x) << PAD0_SHIFT)
-#define INSTR0_SHIFT			10
-#define INSTR0(x)			((x) << INSTR0_SHIFT)
-#define OPRND1_SHIFT			16
-#define OPRND1(x)			((x) << OPRND1_SHIFT)
-#define PAD1_SHIFT			24
-#define PAD1(x)				((x) << PAD1_SHIFT)
-#define INSTR1_SHIFT			26
-#define INSTR1(x)			((x) << INSTR1_SHIFT)
-
-#define LUT_CMD				1
-#define LUT_ADDR			2
-#define LUT_DUMMY			3
-#define LUT_READ			7
-#define LUT_WRITE			8
-
-#define LUT_PAD1			0
-#define LUT_PAD2			1
-#define LUT_PAD4			2
-
-#define ADDR24BIT			0x18
-#define ADDR32BIT			0x20
-
-#endif /* _FSL_QSPI_H_ */
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index e900c99..ffbe20c 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -153,7 +153,7 @@
 	    spi_check_buswidth_req(slave, op->dummy.buswidth, true))
 		return false;
 
-	if (op->data.nbytes &&
+	if (op->data.dir != SPI_MEM_NO_DATA &&
 	    spi_check_buswidth_req(slave, op->data.buswidth,
 				   op->data.dir == SPI_MEM_DATA_OUT))
 		return false;
diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c
index 969bd4b..4cab039 100644
--- a/drivers/spi/spi-sifive.c
+++ b/drivers/spi/spi-sifive.c
@@ -8,8 +8,10 @@
 
 #include <common.h>
 #include <dm.h>
+#include <dm/device_compat.h>
 #include <malloc.h>
-#include <spi.h>
+#include <spi-mem.h>
+#include <wait_bit.h>
 #include <asm/io.h>
 #include <linux/log2.h>
 #include <clk.h>
@@ -85,6 +87,11 @@
 #define SIFIVE_SPI_IP_TXWM               BIT(0)
 #define SIFIVE_SPI_IP_RXWM               BIT(1)
 
+/* format protocol */
+#define SIFIVE_SPI_PROTO_QUAD		4 /* 4 lines I/O protocol transfer */
+#define SIFIVE_SPI_PROTO_DUAL		2 /* 2 lines I/O protocol transfer */
+#define SIFIVE_SPI_PROTO_SINGLE		1 /* 1 line I/O protocol transfer */
+
 struct sifive_spi {
 	void		*regs;		/* base address of the registers */
 	u32		fifo_depth;
@@ -92,28 +99,29 @@
 	u32		cs_inactive;	/* Level of the CS pins when inactive*/
 	u32		freq;
 	u32		num_cs;
+	u8		fmt_proto;
 };
 
 static void sifive_spi_prep_device(struct sifive_spi *spi,
-				   struct dm_spi_slave_platdata *slave)
+				   struct dm_spi_slave_platdata *slave_plat)
 {
 	/* Update the chip select polarity */
-	if (slave->mode & SPI_CS_HIGH)
-		spi->cs_inactive &= ~BIT(slave->cs);
+	if (slave_plat->mode & SPI_CS_HIGH)
+		spi->cs_inactive &= ~BIT(slave_plat->cs);
 	else
-		spi->cs_inactive |= BIT(slave->cs);
+		spi->cs_inactive |= BIT(slave_plat->cs);
 	writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF);
 
 	/* Select the correct device */
-	writel(slave->cs, spi->regs + SIFIVE_SPI_REG_CSID);
+	writel(slave_plat->cs, spi->regs + SIFIVE_SPI_REG_CSID);
 }
 
 static int sifive_spi_set_cs(struct sifive_spi *spi,
-			     struct dm_spi_slave_platdata *slave)
+			     struct dm_spi_slave_platdata *slave_plat)
 {
 	u32 cs_mode = SIFIVE_SPI_CSMODE_MODE_HOLD;
 
-	if (slave->mode & SPI_CS_HIGH)
+	if (slave_plat->mode & SPI_CS_HIGH)
 		cs_mode = SIFIVE_SPI_CSMODE_MODE_AUTO;
 
 	writel(cs_mode, spi->regs + SIFIVE_SPI_REG_CSMODE);
@@ -127,8 +135,8 @@
 }
 
 static void sifive_spi_prep_transfer(struct sifive_spi *spi,
-				     bool is_rx_xfer,
-				     struct dm_spi_slave_platdata *slave)
+				     struct dm_spi_slave_platdata *slave_plat,
+				     u8 *rx_ptr)
 {
 	u32 cr;
 
@@ -141,21 +149,26 @@
 
 	/* LSB first? */
 	cr &= ~SIFIVE_SPI_FMT_ENDIAN;
-	if (slave->mode & SPI_LSB_FIRST)
+	if (slave_plat->mode & SPI_LSB_FIRST)
 		cr |= SIFIVE_SPI_FMT_ENDIAN;
 
 	/* Number of wires ? */
 	cr &= ~SIFIVE_SPI_FMT_PROTO_MASK;
-	if ((slave->mode & SPI_TX_QUAD) || (slave->mode & SPI_RX_QUAD))
+	switch (spi->fmt_proto) {
+	case SIFIVE_SPI_PROTO_QUAD:
 		cr |= SIFIVE_SPI_FMT_PROTO_QUAD;
-	else if ((slave->mode & SPI_TX_DUAL) || (slave->mode & SPI_RX_DUAL))
+		break;
+	case SIFIVE_SPI_PROTO_DUAL:
 		cr |= SIFIVE_SPI_FMT_PROTO_DUAL;
-	else
+		break;
+	default:
 		cr |= SIFIVE_SPI_FMT_PROTO_SINGLE;
+		break;
+	}
 
 	/* SPI direction in/out ? */
 	cr &= ~SIFIVE_SPI_FMT_DIR;
-	if (!is_rx_xfer)
+	if (!rx_ptr)
 		cr |= SIFIVE_SPI_FMT_DIR;
 
 	writel(cr, spi->regs + SIFIVE_SPI_REG_FMT);
@@ -186,50 +199,62 @@
 	writel(tx_data, spi->regs + SIFIVE_SPI_REG_TXDATA);
 }
 
+static int sifive_spi_wait(struct sifive_spi *spi, u32 bit)
+{
+	return wait_for_bit_le32(spi->regs + SIFIVE_SPI_REG_IP,
+				 bit, true, 100, false);
+}
+
 static int sifive_spi_xfer(struct udevice *dev, unsigned int bitlen,
 			   const void *dout, void *din, unsigned long flags)
 {
 	struct udevice *bus = dev->parent;
 	struct sifive_spi *spi = dev_get_priv(bus);
-	struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
-	const unsigned char *tx_ptr = dout;
+	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+	const u8 *tx_ptr = dout;
 	u8 *rx_ptr = din;
 	u32 remaining_len;
 	int ret;
 
 	if (flags & SPI_XFER_BEGIN) {
-		sifive_spi_prep_device(spi, slave);
+		sifive_spi_prep_device(spi, slave_plat);
 
-		ret = sifive_spi_set_cs(spi, slave);
+		ret = sifive_spi_set_cs(spi, slave_plat);
 		if (ret)
 			return ret;
 	}
 
-	sifive_spi_prep_transfer(spi, true, slave);
+	sifive_spi_prep_transfer(spi, slave_plat, rx_ptr);
 
 	remaining_len = bitlen / 8;
 
 	while (remaining_len) {
-		int n_words, tx_words, rx_words;
-
-		n_words = min(remaining_len, spi->fifo_depth);
+		unsigned int n_words = min(remaining_len, spi->fifo_depth);
+		unsigned int tx_words, rx_words;
 
 		/* Enqueue n_words for transmission */
-		if (tx_ptr) {
-			for (tx_words = 0; tx_words < n_words; ++tx_words) {
-				sifive_spi_tx(spi, tx_ptr);
-				sifive_spi_rx(spi, NULL);
-				tx_ptr++;
-			}
+		for (tx_words = 0; tx_words < n_words; tx_words++) {
+			if (!tx_ptr)
+				sifive_spi_tx(spi, NULL);
+			else
+				sifive_spi_tx(spi, tx_ptr++);
 		}
 
-		/* Read out all the data from the RX FIFO */
 		if (rx_ptr) {
-			for (rx_words = 0; rx_words < n_words; ++rx_words) {
-				sifive_spi_tx(spi, NULL);
-				sifive_spi_rx(spi, rx_ptr);
-				rx_ptr++;
-			}
+			/* Wait for transmission + reception to complete */
+			writel(n_words - 1, spi->regs + SIFIVE_SPI_REG_RXMARK);
+			ret = sifive_spi_wait(spi, SIFIVE_SPI_IP_RXWM);
+			if (ret)
+				return ret;
+
+			/* Read out all the data from the RX FIFO */
+			for (rx_words = 0; rx_words < n_words; rx_words++)
+				sifive_spi_rx(spi, rx_ptr++);
+		} else {
+			/* Wait for transmission to complete */
+			ret = sifive_spi_wait(spi, SIFIVE_SPI_IP_TXWM);
+			if (ret)
+				return ret;
 		}
 
 		remaining_len -= n_words;
@@ -241,6 +266,80 @@
 	return 0;
 }
 
+static int sifive_spi_exec_op(struct spi_slave *slave,
+			      const struct spi_mem_op *op)
+{
+	struct udevice *dev = slave->dev;
+	struct sifive_spi *spi = dev_get_priv(dev->parent);
+	unsigned long flags = SPI_XFER_BEGIN;
+	u8 opcode = op->cmd.opcode;
+	unsigned int pos = 0;
+	const void *tx_buf = NULL;
+	void *rx_buf = NULL;
+	int op_len, i;
+	int ret;
+
+	if (!op->addr.nbytes && !op->dummy.nbytes && !op->data.nbytes)
+		flags |= SPI_XFER_END;
+
+	spi->fmt_proto = op->cmd.buswidth;
+
+	/* send the opcode */
+	ret = sifive_spi_xfer(dev, 8, (void *)&opcode, NULL, flags);
+	if (ret < 0) {
+		dev_err(dev, "failed to xfer opcode\n");
+		return ret;
+	}
+
+	op_len = op->addr.nbytes + op->dummy.nbytes;
+	u8 op_buf[op_len];
+
+	/* send the addr + dummy */
+	if (op->addr.nbytes) {
+		/* fill address */
+		for (i = 0; i < op->addr.nbytes; i++)
+			op_buf[pos + i] = op->addr.val >>
+				(8 * (op->addr.nbytes - i - 1));
+
+		pos += op->addr.nbytes;
+
+		/* fill dummy */
+		if (op->dummy.nbytes)
+			memset(op_buf + pos, 0xff, op->dummy.nbytes);
+
+		/* make sure to set end flag, if no data bytes */
+		if (!op->data.nbytes)
+			flags |= SPI_XFER_END;
+
+		spi->fmt_proto = op->addr.buswidth;
+
+		ret = sifive_spi_xfer(dev, op_len * 8, op_buf, NULL, flags);
+		if (ret < 0) {
+			dev_err(dev, "failed to xfer addr + dummy\n");
+			return ret;
+		}
+	}
+
+	/* send/received the data */
+	if (op->data.nbytes) {
+		if (op->data.dir == SPI_MEM_DATA_IN)
+			rx_buf = op->data.buf.in;
+		else
+			tx_buf = op->data.buf.out;
+
+		spi->fmt_proto = op->data.buswidth;
+
+		ret = sifive_spi_xfer(dev, op->data.nbytes * 8,
+				      tx_buf, rx_buf, SPI_XFER_END);
+		if (ret) {
+			dev_err(dev, "failed to xfer data\n");
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
 static int sifive_spi_set_speed(struct udevice *bus, uint speed)
 {
 	struct sifive_spi *spi = dev_get_priv(bus);
@@ -309,6 +408,10 @@
 	/* Watermark interrupts are disabled by default */
 	writel(0, spi->regs + SIFIVE_SPI_REG_IE);
 
+	/* Default watermark FIFO threshold values */
+	writel(1, spi->regs + SIFIVE_SPI_REG_TXMARK);
+	writel(0, spi->regs + SIFIVE_SPI_REG_RXMARK);
+
 	/* Set CS/SCK Delays and Inactive Time to defaults */
 	writel(SIFIVE_SPI_DELAY0_CSSCK(1) | SIFIVE_SPI_DELAY0_SCKCS(1),
 	       spi->regs + SIFIVE_SPI_REG_DELAY0);
@@ -348,11 +451,16 @@
 	return 0;
 }
 
+static const struct spi_controller_mem_ops sifive_spi_mem_ops = {
+	.exec_op	= sifive_spi_exec_op,
+};
+
 static const struct dm_spi_ops sifive_spi_ops = {
 	.xfer		= sifive_spi_xfer,
 	.set_speed	= sifive_spi_set_speed,
 	.set_mode	= sifive_spi_set_mode,
 	.cs_info        = sifive_spi_cs_info,
+	.mem_ops	= &sifive_spi_mem_ops,
 };
 
 static const struct udevice_id sifive_spi_ids[] = {
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index f09e138..4be7433 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -101,6 +101,12 @@
 	help
 	  Reboot support for generic watchdog reset.
 
+config SYSRESET_RESETCTL
+	bool "Enable support for reset controller reboot driver"
+	select DM_RESET
+	help
+	  Reboot support using generic reset controller.
+
 config SYSRESET_X86
 	bool "Enable support for x86 processor reboot driver"
 	depends on X86
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index 51af68f..3ed4bab 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -16,5 +16,6 @@
 obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o
 obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
 obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
+obj-$(CONFIG_SYSRESET_RESETCTL) += sysreset_resetctl.o
 obj-$(CONFIG_$(SPL_TPL_)SYSRESET_X86) += sysreset_x86.o
 obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
diff --git a/drivers/sysreset/sysreset_resetctl.c b/drivers/sysreset/sysreset_resetctl.c
new file mode 100644
index 0000000..b8203ba
--- /dev/null
+++ b/drivers/sysreset/sysreset_resetctl.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ *
+ * Author:  Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <reset.h>
+
+struct resetctl_reboot_priv {
+	struct reset_ctl_bulk resets;
+};
+
+static int resetctl_reboot_request(struct udevice *dev, enum sysreset_t type)
+{
+	struct resetctl_reboot_priv *priv = dev_get_priv(dev);
+
+	return reset_assert_bulk(&priv->resets);
+}
+
+static struct sysreset_ops resetctl_reboot_ops = {
+	.request = resetctl_reboot_request,
+};
+
+int resetctl_reboot_probe(struct udevice *dev)
+{
+	struct resetctl_reboot_priv *priv = dev_get_priv(dev);
+
+	return reset_get_bulk(dev, &priv->resets);
+}
+
+static const struct udevice_id resetctl_reboot_ids[] = {
+	{ .compatible = "resetctl-reboot" },
+	{ }
+};
+
+U_BOOT_DRIVER(resetctl_reboot) = {
+	.id = UCLASS_SYSRESET,
+	.name = "resetctl_reboot",
+	.of_match = resetctl_reboot_ids,
+	.ops = &resetctl_reboot_ops,
+	.priv_auto_alloc_size = sizeof(struct resetctl_reboot_priv),
+	.probe = resetctl_reboot_probe,
+};
diff --git a/drivers/timer/mtk_timer.c b/drivers/timer/mtk_timer.c
index b5e76bd..e99135e 100644
--- a/drivers/timer/mtk_timer.c
+++ b/drivers/timer/mtk_timer.c
@@ -71,6 +71,7 @@
 
 static const struct udevice_id mtk_timer_ids[] = {
 	{ .compatible = "mediatek,timer" },
+	{ .compatible = "mediatek,mt6577-timer" },
 	{ }
 };
 
diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c
index d4453f8..de964d6 100644
--- a/drivers/usb/dwc3/dwc3-meson-g12a.c
+++ b/drivers/usb/dwc3/dwc3-meson-g12a.c
@@ -408,6 +408,15 @@
 			goto err_phy_init;
 	}
 
+	for (i = 0; i < PHY_COUNT; ++i) {
+		if (!priv->phys[i].dev)
+			continue;
+
+		ret = generic_phy_power_on(&priv->phys[i]);
+		if (ret)
+			goto err_phy_init;
+	}
+
 	return 0;
 
 err_phy_init:
@@ -430,6 +439,13 @@
 
 	clk_release_all(&priv->clk, 1);
 
+	for (i = 0; i < PHY_COUNT; ++i) {
+		if (!priv->phys[i].dev)
+			continue;
+
+		 generic_phy_power_off(&priv->phys[i]);
+	}
+
 	for (i = 0 ; i < PHY_COUNT ; ++i) {
 		if (!priv->phys[i].dev)
 			continue;
diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c
index a118283..8533abf 100644
--- a/drivers/usb/gadget/ether.c
+++ b/drivers/usb/gadget/ether.c
@@ -2472,8 +2472,7 @@
 		}
 		usb_gadget_handle_interrupts(0);
 	}
-	if (rndis_pkt)
-		free(rndis_pkt);
+	free(rndis_pkt);
 
 	return 0;
 drop:
diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index e4efaf1..f25ed2d 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -5,13 +5,15 @@
  */
 
 #include <common.h>
+#include <clk.h>
 #include <cpu_func.h>
 #include <dm.h>
 #include <errno.h>
-#include <usb.h>
+#include <generic-phy.h>
 #include <malloc.h>
 #include <memalign.h>
 #include <phys2bus.h>
+#include <usb.h>
 #include <usbroothubdes.h>
 #include <wait_bit.h>
 #include <asm/io.h>
@@ -37,6 +39,8 @@
 #ifdef CONFIG_DM_REGULATOR
 	struct udevice *vbus_supply;
 #endif
+	struct phy phy;
+	struct clk_bulk clks;
 #else
 	uint8_t *aligned_buffer;
 	uint8_t *status_buffer;
@@ -1147,6 +1151,8 @@
 			return ret;
 	}
 
+	/* force reset to clear all IP register */
+	reset_assert_bulk(&priv->resets);
 	ret = reset_deassert_bulk(&priv->resets);
 	if (ret) {
 		reset_release_bulk(&priv->resets);
@@ -1213,6 +1219,8 @@
 	if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
 		mdelay(1000);
 
+	printf("USB DWC2\n");
+
 	return 0;
 }
 
@@ -1322,13 +1330,95 @@
 	return 0;
 }
 
+static int dwc2_setup_phy(struct udevice *dev)
+{
+	struct dwc2_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = generic_phy_get_by_index(dev, 0, &priv->phy);
+	if (ret) {
+		if (ret == -ENOENT)
+			return 0; /* no PHY, nothing to do */
+		dev_err(dev, "Failed to get USB PHY: %d.\n", ret);
+		return ret;
+	}
+
+	ret = generic_phy_init(&priv->phy);
+	if (ret) {
+		dev_dbg(dev, "Failed to init USB PHY: %d.\n", ret);
+		return ret;
+	}
+
+	ret = generic_phy_power_on(&priv->phy);
+	if (ret) {
+		dev_dbg(dev, "Failed to power on USB PHY: %d.\n", ret);
+		generic_phy_exit(&priv->phy);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int dwc2_shutdown_phy(struct udevice *dev)
+{
+	struct dwc2_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	/* PHY is not valid when generic_phy_get_by_index() = -ENOENT */
+	if (!generic_phy_valid(&priv->phy))
+		return 0; /* no PHY, nothing to do */
+
+	ret = generic_phy_power_off(&priv->phy);
+	if (ret) {
+		dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret);
+		return ret;
+	}
+
+	ret = generic_phy_exit(&priv->phy);
+	if (ret) {
+		dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int dwc2_clk_init(struct udevice *dev)
+{
+	struct dwc2_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = clk_get_bulk(dev, &priv->clks);
+	if (ret == -ENOSYS || ret == -ENOENT)
+		return 0;
+	if (ret)
+		return ret;
+
+	ret = clk_enable_bulk(&priv->clks);
+	if (ret) {
+		clk_release_bulk(&priv->clks);
+		return ret;
+	}
+
+	return 0;
+}
+
 static int dwc2_usb_probe(struct udevice *dev)
 {
 	struct dwc2_priv *priv = dev_get_priv(dev);
 	struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
+	int ret;
 
 	bus_priv->desc_before_addr = true;
 
+	ret = dwc2_clk_init(dev);
+	if (ret)
+		return ret;
+
+	ret = dwc2_setup_phy(dev);
+	if (ret)
+		return ret;
+
 	return dwc2_init_common(dev, priv);
 }
 
@@ -1341,9 +1431,17 @@
 	if (ret)
 		return ret;
 
+	ret = dwc2_shutdown_phy(dev);
+	if (ret) {
+		dev_dbg(dev, "Failed to shutdown USB PHY: %d.\n", ret);
+		return ret;
+	}
+
 	dwc2_uninit_common(priv->regs);
 
 	reset_release_bulk(&priv->resets);
+	clk_disable_bulk(&priv->clks);
+	clk_release_bulk(&priv->clks);
 
 	return 0;
 }
diff --git a/drivers/usb/host/dwc3-sti-glue.c b/drivers/usb/host/dwc3-sti-glue.c
index c99a198..99d4e29 100644
--- a/drivers/usb/host/dwc3-sti-glue.c
+++ b/drivers/usb/host/dwc3-sti-glue.c
@@ -239,7 +239,7 @@
 
 U_BOOT_DRIVER(dwc3_sti_glue) = {
 	.name = "dwc3_sti_glue",
-	.id = UCLASS_MISC,
+	.id = UCLASS_NOP,
 	.of_match = sti_dwc3_glue_ids,
 	.ofdata_to_platdata = sti_dwc3_glue_ofdata_to_platdata,
 	.probe = sti_dwc3_glue_probe,
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 1edb344..a2a85db 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -1413,13 +1413,10 @@
 	debug("Exit create_int_queue\n");
 	return result;
 fail3:
-	if (result->tds)
-		free(result->tds);
+	free(result->tds);
 fail2:
-	if (result->first)
-		free(result->first);
-	if (result)
-		free(result);
+	free(result->first);
+	free(result);
 fail1:
 	return NULL;
 }
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 6cafd24..bf06180 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -49,6 +49,7 @@
 config DESIGNWARE_WATCHDOG
 	bool "Designware watchdog timer support"
 	select HW_WATCHDOG if !WDT
+	default y if WDT && ROCKCHIP_RK3399
 	help
 	  Enable this to support Designware Watchdog Timer IP, present e.g.
 	  on Altera SoCFPGA SoCs.
diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
index 669a323..b3c597e 100644
--- a/drivers/watchdog/mtk_wdt.c
+++ b/drivers/watchdog/mtk_wdt.c
@@ -143,6 +143,7 @@
 
 static const struct udevice_id mtk_wdt_ids[] = {
 	{ .compatible = "mediatek,wdt"},
+	{ .compatible = "mediatek,mt6589-wdt"},
 	{}
 };
 
diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile
index 779e252..4a34813 100644
--- a/examples/standalone/Makefile
+++ b/examples/standalone/Makefile
@@ -5,10 +5,13 @@
 
 extra-y        := hello_world
 extra-$(CONFIG_SMC91111)           += smc91111_eeprom
-extra-$(CONFIG_SMC911X)            += smc911x_eeprom
 extra-$(CONFIG_SPI_FLASH_ATMEL)    += atmel_df_pow2
 extra-$(CONFIG_PPC)                += sched
 
+ifndef CONFIG_DM_ETH
+extra-$(CONFIG_SMC911X)            += smc911x_eeprom
+endif
+
 #
 # Some versions of make do not handle trailing white spaces properly;
 # leading to build failures. The problem was found with GNU Make 3.80.
diff --git a/examples/standalone/smc911x_eeprom.c b/examples/standalone/smc911x_eeprom.c
index 2c05ed9..270588b 100644
--- a/examples/standalone/smc911x_eeprom.c
+++ b/examples/standalone/smc911x_eeprom.c
@@ -18,8 +18,158 @@
 #include <console.h>
 #include <exports.h>
 #include <linux/ctype.h>
+#include <linux/types.h>
 #include "../drivers/net/smc911x.h"
 
+#define DRIVERNAME "smc911x"
+
+#if defined (CONFIG_SMC911X_32_BIT) && \
+	defined (CONFIG_SMC911X_16_BIT)
+#error "SMC911X: Only one of CONFIG_SMC911X_32_BIT and \
+	CONFIG_SMC911X_16_BIT shall be set"
+#endif
+
+struct chip_id {
+	u16 id;
+	char *name;
+};
+
+static const struct chip_id chip_ids[] =  {
+	{ CHIP_89218, "LAN89218" },
+	{ CHIP_9115, "LAN9115" },
+	{ CHIP_9116, "LAN9116" },
+	{ CHIP_9117, "LAN9117" },
+	{ CHIP_9118, "LAN9118" },
+	{ CHIP_9211, "LAN9211" },
+	{ CHIP_9215, "LAN9215" },
+	{ CHIP_9216, "LAN9216" },
+	{ CHIP_9217, "LAN9217" },
+	{ CHIP_9218, "LAN9218" },
+	{ CHIP_9220, "LAN9220" },
+	{ CHIP_9221, "LAN9221" },
+	{ 0, NULL },
+};
+
+#if defined (CONFIG_SMC911X_32_BIT)
+static u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
+{
+	return *(volatile u32*)(dev->iobase + offset);
+}
+
+static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
+{
+	*(volatile u32*)(dev->iobase + offset) = val;
+}
+#elif defined (CONFIG_SMC911X_16_BIT)
+static u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
+{
+	volatile u16 *addr_16 = (u16 *)(dev->iobase + offset);
+	return (*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16);
+}
+static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
+{
+	*(volatile u16 *)(dev->iobase + offset) = (u16)val;
+	*(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16);
+}
+#else
+#error "SMC911X: undefined bus width"
+#endif /* CONFIG_SMC911X_16_BIT */
+
+static u32 smc911x_get_mac_csr(struct eth_device *dev, u8 reg)
+{
+	while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+		;
+	smc911x_reg_write(dev, MAC_CSR_CMD,
+			MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
+	while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+		;
+
+	return smc911x_reg_read(dev, MAC_CSR_DATA);
+}
+
+static void smc911x_set_mac_csr(struct eth_device *dev, u8 reg, u32 data)
+{
+	while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+		;
+	smc911x_reg_write(dev, MAC_CSR_DATA, data);
+	smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
+	while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+		;
+}
+
+static int smc911x_detect_chip(struct eth_device *dev)
+{
+	unsigned long val, i;
+
+	val = smc911x_reg_read(dev, BYTE_TEST);
+	if (val == 0xffffffff) {
+		/* Special case -- no chip present */
+		return -1;
+	} else if (val != 0x87654321) {
+		printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
+		return -1;
+	}
+
+	val = smc911x_reg_read(dev, ID_REV) >> 16;
+	for (i = 0; chip_ids[i].id != 0; i++) {
+		if (chip_ids[i].id == val) break;
+	}
+	if (!chip_ids[i].id) {
+		printf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
+		return -1;
+	}
+
+	dev->priv = (void *)&chip_ids[i];
+
+	return 0;
+}
+
+static void smc911x_reset(struct eth_device *dev)
+{
+	int timeout;
+
+	/*
+	 *  Take out of PM setting first
+	 *  Device is already wake up if PMT_CTRL_READY bit is set
+	 */
+	if ((smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) == 0) {
+		/* Write to the bytetest will take out of powerdown */
+		smc911x_reg_write(dev, BYTE_TEST, 0x0);
+
+		timeout = 10;
+
+		while (timeout-- &&
+			!(smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY))
+			udelay(10);
+		if (timeout < 0) {
+			printf(DRIVERNAME
+				": timeout waiting for PM restore\n");
+			return;
+		}
+	}
+
+	/* Disable interrupts */
+	smc911x_reg_write(dev, INT_EN, 0);
+
+	smc911x_reg_write(dev, HW_CFG, HW_CFG_SRST);
+
+	timeout = 1000;
+	while (timeout-- && smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
+		udelay(10);
+
+	if (timeout < 0) {
+		printf(DRIVERNAME ": reset timeout\n");
+		return;
+	}
+
+	/* Reset the FIFO level and flow control settings */
+	smc911x_set_mac_csr(dev, FLOW, FLOW_FCPT | FLOW_FCEN);
+	smc911x_reg_write(dev, AFC_CFG, 0x0050287F);
+
+	/* Set to LED outputs */
+	smc911x_reg_write(dev, GPIO_CFG, 0x70070000);
+}
+
 /**
  *	smsc_ctrlc - detect press of CTRL+C (common ctrlc() isnt exported!?)
  */
diff --git a/fs/ext4/ext4_journal.c b/fs/ext4/ext4_journal.c
index 3559daf..0ceb73d 100644
--- a/fs/ext4/ext4_journal.c
+++ b/fs/ext4/ext4_journal.c
@@ -107,22 +107,18 @@
 	for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) {
 		if (dirty_block_ptr[i]->blknr == -1)
 			break;
-		if (dirty_block_ptr[i]->buf)
-			free(dirty_block_ptr[i]->buf);
+		free(dirty_block_ptr[i]->buf);
 	}
 
 	for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) {
 		if (journal_ptr[i]->blknr == -1)
 			break;
-		if (journal_ptr[i]->buf)
-			free(journal_ptr[i]->buf);
+		free(journal_ptr[i]->buf);
 	}
 
 	for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) {
-		if (journal_ptr[i])
-			free(journal_ptr[i]);
-		if (dirty_block_ptr[i])
-			free(dirty_block_ptr[i]);
+		free(journal_ptr[i]);
+		free(dirty_block_ptr[i]);
 	}
 	gindex = 0;
 	gd_index = 0;
@@ -272,8 +268,7 @@
 	struct revoke_blk_list *next_node = NULL;
 
 	while (tmp_node != NULL) {
-		if (tmp_node->content)
-			free(tmp_node->content);
+		free(tmp_node->content);
 		tmp_node = tmp_node->next;
 	}
 
@@ -409,6 +404,9 @@
 	char *temp_buff1 = NULL;
 	struct ext_filesystem *fs = get_fs();
 
+	if (le32_to_cpu(fs->sb->feature_ro_compat) & EXT4_FEATURE_RO_COMPAT_METADATA_CSUM)
+		return 0;
+
 	temp_buff = zalloc(fs->blksz);
 	if (!temp_buff)
 		return -ENOMEM;
diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h
index 194be9a..3681c5c 100644
--- a/include/acpi/acpi_table.h
+++ b/include/acpi/acpi_table.h
@@ -23,6 +23,8 @@
 
 #if !defined(__ACPI__)
 
+struct acpi_ctx;
+
 /*
  * RSDP (Root System Description Pointer)
  * Note: ACPI 1.0 didn't have length, xsdt_address, and ext_checksum
@@ -505,6 +507,69 @@
  */
 int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags);
 
+/**
+ * acpi_fill_header() - Set up a new table header
+ *
+ * This sets all fields except length, revision, checksum and aslc_revision
+ *
+ * @header: ACPI header to update
+ * @signature: Table signature to use (4 characters)
+ */
+void acpi_fill_header(struct acpi_table_header *header, char *signature);
+
+/**
+ * acpi_align() - Align the ACPI output pointer to a 16-byte boundary
+ *
+ * @ctx: ACPI context
+ */
+void acpi_align(struct acpi_ctx *ctx);
+
+/**
+ * acpi_align64() - Align the ACPI output pointer to a 64-byte boundary
+ *
+ * @ctx: ACPI context
+ */
+void acpi_align64(struct acpi_ctx *ctx);
+
+/**
+ * acpi_inc() - Increment the ACPI output pointer by a bit
+ *
+ * The pointer is NOT aligned afterwards.
+ *
+ * @ctx: ACPI context
+ * @amount: Amount to increment by
+ */
+void acpi_inc(struct acpi_ctx *ctx, uint amount);
+
+/**
+ * acpi_inc_align() - Increment the ACPI output pointer by a bit and align
+ *
+ * The pointer is aligned afterwards to a 16-byte boundary
+ *
+ * @ctx: ACPI context
+ * @amount: Amount to increment by
+ */
+void acpi_inc_align(struct acpi_ctx *ctx, uint amount);
+
+/**
+ * acpi_add_table() - Add a new table to the RSDP and XSDT
+ *
+ * @ctx: ACPI context
+ * @table: Table to add
+ * @return 0 if OK, -E2BIG if too many tables
+ */
+int acpi_add_table(struct acpi_ctx *ctx, void *table);
+
+/**
+ * acpi_setup_base_tables() - Set up context along with RSDP, RSDT and XSDT
+ *
+ * Set up the context with the given start position. Some basic tables are
+ * always needed, so set them up as well.
+ *
+ * @ctx: Context to set up
+ */
+void acpi_setup_base_tables(struct acpi_ctx *ctx, void *start);
+
 #endif /* !__ACPI__*/
 
 #include <asm/acpi_table.h>
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index d9e220c..8c78792 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -166,5 +166,6 @@
 #define GD_FLG_SPL_EARLY_INIT	0x04000 /* Early SPL init is done	   */
 #define GD_FLG_LOG_READY	0x08000 /* Log system is ready for use	   */
 #define GD_FLG_WDT_READY	0x10000 /* Watchdog is ready for use	   */
+#define GD_FLG_SKIP_LL_INIT	0x20000	/* Don't perform low-level init	   */
 
 #endif /* __ASM_GENERIC_GBL_DATA_H */
diff --git a/include/bedbug/type.h b/include/bedbug/type.h
index b7b447b..3754c7f 100644
--- a/include/bedbug/type.h
+++ b/include/bedbug/type.h
@@ -3,7 +3,7 @@
 
 /* Supporting routines */
 int bedbug_puts (const char *);
-void bedbug_init (void);
+int bedbug_init(void);
 void bedbug860_init (void);
 void do_bedbug_breakpoint (struct pt_regs *);
 void bedbug_main_loop (unsigned long, struct pt_regs *);
diff --git a/include/cbfs.h b/include/cbfs.h
index f3bc8ca..d915f94 100644
--- a/include/cbfs.h
+++ b/include/cbfs.h
@@ -135,7 +135,7 @@
  */
 const struct cbfs_cachenode *file_cbfs_find(const char *name);
 
-struct cbfs_priv *priv;
+struct cbfs_priv;
 
 /**
  * cbfs_find_file() - Find a file in a given CBFS
diff --git a/include/clk.h b/include/clk.h
index 3336301..60c4b7d 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -9,6 +9,7 @@
 #define _CLK_H_
 
 #include <dm/ofnode.h>
+#include <linux/err.h>
 #include <linux/errno.h>
 #include <linux/types.h>
 
@@ -312,6 +313,7 @@
 	return clk_release_all(bulk->clks, bulk->count);
 }
 
+#if CONFIG_IS_ENABLED(CLK)
 /**
  * clk_request - Request a clock by provider-specific ID.
  *
@@ -433,19 +435,6 @@
  */
 bool clk_is_match(const struct clk *p, const struct clk *q);
 
-int soc_clk_dump(void);
-
-/**
- * clk_valid() - check if clk is valid
- *
- * @clk:	the clock to check
- * @return true if valid, or false
- */
-static inline bool clk_valid(struct clk *clk)
-{
-	return clk && !!clk->dev;
-}
-
 /**
  * clk_get_by_id() - Get the clock by its ID
  *
@@ -465,6 +454,93 @@
  * @return true on binded, or false on no
  */
 bool clk_dev_binded(struct clk *clk);
+
+#else /* CONFIG_IS_ENABLED(CLK) */
+
+static inline int clk_request(struct udevice *dev, struct clk *clk)
+{
+	return -ENOSYS;
+}
+
+static inline int clk_free(struct clk *clk)
+{
+	return 0;
+}
+
+static inline ulong clk_get_rate(struct clk *clk)
+{
+	return -ENOSYS;
+}
+
+static inline struct clk *clk_get_parent(struct clk *clk)
+{
+	return ERR_PTR(-ENOSYS);
+}
+
+static inline long long clk_get_parent_rate(struct clk *clk)
+{
+	return -ENOSYS;
+}
+
+static inline ulong clk_set_rate(struct clk *clk, ulong rate)
+{
+	return -ENOSYS;
+}
+
+static inline int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	return -ENOSYS;
+}
+
+static inline int clk_enable(struct clk *clk)
+{
+	return 0;
+}
+
+static inline int clk_enable_bulk(struct clk_bulk *bulk)
+{
+	return 0;
+}
+
+static inline int clk_disable(struct clk *clk)
+{
+	return 0;
+}
+
+static inline int clk_disable_bulk(struct clk_bulk *bulk)
+{
+	return 0;
+}
+
+static inline bool clk_is_match(const struct clk *p, const struct clk *q)
+{
+	return false;
+}
+
+static inline int clk_get_by_id(ulong id, struct clk **clkp)
+{
+	return -ENOSYS;
+}
+
+static inline bool clk_dev_binded(struct clk *clk)
+{
+	return false;
+}
+#endif /* CONFIG_IS_ENABLED(CLK) */
+
+/**
+ * clk_valid() - check if clk is valid
+ *
+ * @clk:	the clock to check
+ * @return true if valid, or false
+ */
+static inline bool clk_valid(struct clk *clk)
+{
+	return clk && !!clk->dev;
+}
+
+int soc_clk_dump(void);
+
 #endif
 
 #define clk_prepare_enable(clk) clk_enable(clk)
diff --git a/include/config_phylib_all_drivers.h b/include/config_phylib_all_drivers.h
index 36df725..8e587bc 100644
--- a/include/config_phylib_all_drivers.h
+++ b/include/config_phylib_all_drivers.h
@@ -12,21 +12,4 @@
 #ifndef _CONFIG_PHYLIB_ALL_H
 #define _CONFIG_PHYLIB_ALL_H
 
-#ifdef CONFIG_PHYLIB
-
-#define CONFIG_PHY_VITESSE
-#define CONFIG_PHY_BROADCOM
-#define CONFIG_PHY_DAVICOM
-#define CONFIG_PHY_REALTEK
-#define CONFIG_PHY_NATSEMI
-#define CONFIG_PHY_LXT
-#define CONFIG_PHY_ATHEROS
-#define CONFIG_PHY_SMSC
-
-#ifdef CONFIG_PHYLIB_10G
-#define CONFIG_PHY_TERANETICS
-#endif /* CONFIG_PHYLIB_10G */
-
-#endif /* CONFIG_PHYLIB */
-
 #endif /*_CONFIG_PHYLIB_ALL_H */
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 1a34b95..abecf90 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -586,9 +586,6 @@
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_PHYLIB_10G
-#define CONFIG_PHY_VITESSE
-#define CONFIG_PHY_TERANETICS
 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 20684dc..e61c978 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -288,8 +288,6 @@
   #define FETH3_RST		0x80
 #endif					/* CONFIG_ETHER_INDEX */
 
-#define CONFIG_BITBANGMII		/* bit-bang MII PHY management */
-
 /*
  * GPIO pins used for bit-banged MII communications
  */
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
index 1818b4b..8ed351c 100644
--- a/include/configs/P1023RDB.h
+++ b/include/configs/P1023RDB.h
@@ -277,10 +277,6 @@
 /* For FM */
 #define CONFIG_SYS_DPAA_FMAN
 
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_PHY_ATHEROS
-#endif
-
 /* Default address of microcode for the Linux Fman driver */
 /* QE microcode/firmware address */
 #define CONFIG_SYS_FMAN_FW_ADDR	0xEFF00000
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index f6472b9..0dcba7d 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -418,12 +418,6 @@
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_PHYLIB_10G
-#define CONFIG_PHY_VITESSE
-#define CONFIG_PHY_TERANETICS
-#endif
-
 #ifdef CONFIG_PCI
 #if !defined(CONFIG_DM_PCI)
 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
index 8ac260c..20c0534 100644
--- a/include/configs/T102xQDS.h
+++ b/include/configs/T102xQDS.h
@@ -653,10 +653,6 @@
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_PHYLIB_10G
-#define CONFIG_PHY_VITESSE
-#define CONFIG_PHY_REALTEK
-#define CONFIG_PHY_TERANETICS
 #define RGMII_PHY1_ADDR		0x1
 #define RGMII_PHY2_ADDR		0x2
 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 43897a7..094795c 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -610,7 +610,6 @@
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_PHY_REALTEK
 #if defined(CONFIG_TARGET_T1024RDB)
 #define RGMII_PHY1_ADDR		0x2
 #define RGMII_PHY2_ADDR		0x6
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index aa2a8b0..cda8251 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -540,10 +540,6 @@
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_PHYLIB_10G
-#define CONFIG_PHY_VITESSE
-#define CONFIG_PHY_REALTEK
-#define CONFIG_PHY_TERANETICS
 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 50b37ac..bc65118 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -654,11 +654,6 @@
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 #endif /* CONFIG_NOBQFMAN */
 
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_PHY_VITESSE
-#define CONFIG_PHY_REALTEK
-#endif
-
 #ifdef CONFIG_FMAN_ENET
 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x03
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index be5a658..96801e5 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -587,9 +587,6 @@
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_PHY_VITESSE
-#define CONFIG_PHY_REALTEK
-#define CONFIG_PHY_TERANETICS
 #define RGMII_PHY1_ADDR	0x1
 #define RGMII_PHY2_ADDR	0x2
 #define FM1_10GEC1_PHY_ADDR	  0x3
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 68de90f..a90ea11 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -536,7 +536,6 @@
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_PHY_REALTEK
 #define CONFIG_CORTINA_FW_LENGTH	0x40000
 #define RGMII_PHY1_ADDR		0x01  /* RealTek RTL8211E */
 #define RGMII_PHY2_ADDR		0x02
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index 94e0ddb..91a7c70 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -404,9 +404,6 @@
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_PHYLIB_10G
-#define CONFIG_PHY_VITESSE
-#define CONFIG_PHY_TERANETICS
 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 042757c..31cb1cf 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -546,11 +546,8 @@
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_PHYLIB_10G
-#define CONFIG_PHY_VITESSE
 #define CONFIG_CORTINA_FW_ADDR		0xefe00000
 #define CONFIG_CORTINA_FW_LENGTH	0x40000
-#define CONFIG_PHY_TERANETICS
 #define SGMII_PHY_ADDR1 0x0
 #define SGMII_PHY_ADDR2 0x1
 #define SGMII_PHY_ADDR3 0x2
diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h
index a115676..deb4374 100644
--- a/include/configs/advantech_dms-ba16.h
+++ b/include/configs/advantech_dms-ba16.h
@@ -55,7 +55,6 @@
 #define CONFIG_FEC_XCV_TYPE		RGMII
 #define CONFIG_ETHPRIME		"FEC"
 #define CONFIG_FEC_MXC_PHYADDR		4
-#define CONFIG_PHY_ATHEROS
 
 /* Serial Flash */
 
diff --git a/include/configs/alt.h b/include/configs/alt.h
index bb52675..8456a6b 100644
--- a/include/configs/alt.h
+++ b/include/configs/alt.h
@@ -31,7 +31,6 @@
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
 #define CONFIG_SH_ETHER_ALIGNE_SIZE	64
-#define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 
 /* Board Clock */
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index f2f1004..6de463e 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -285,9 +285,7 @@
 /* SPI flash. */
 
 /* Network. */
-#define CONFIG_PHY_SMSC
 /* Enable Atheros phy driver */
-#define CONFIG_PHY_ATHEROS
 
 /*
  * NOR Size = 16 MiB
diff --git a/include/configs/am335x_igep003x.h b/include/configs/am335x_igep003x.h
index 5b5e160..95ba949 100644
--- a/include/configs/am335x_igep003x.h
+++ b/include/configs/am335x_igep003x.h
@@ -101,7 +101,6 @@
 #define CONFIG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
 
 /* Ethernet support */
-#define CONFIG_PHY_SMSC
 
 /* NAND support */
 #define CONFIG_SYS_NAND_ONFI_DETECTION	1
diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h
index eabf19d..6e1a40c 100644
--- a/include/configs/am335x_shc.h
+++ b/include/configs/am335x_shc.h
@@ -246,7 +246,6 @@
 #define CONFIG_BOOTP_DNS2
 #define CONFIG_BOOTP_SEND_HOSTNAME
 #define CONFIG_NET_RETRY_COUNT         10
-#define CONFIG_PHY_SMSC
 
 /* I2C configuration */
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h
index 0453cb2..9087e04 100644
--- a/include/configs/am335x_sl50.h
+++ b/include/configs/am335x_sl50.h
@@ -81,6 +81,5 @@
 #endif
 
 /* Network. */
-#define CONFIG_PHY_SMSC
 
 #endif	/* ! __CONFIG_AM335X_SL50_H */
diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h
index e9f1eb2..e569296 100644
--- a/include/configs/armadillo-800eva.h
+++ b/include/configs/armadillo-800eva.h
@@ -77,8 +77,6 @@
 #define CONFIG_SH_ETHER_BASE_ADDR	0xe9a00000
 #define CONFIG_SH_ETHER_SH7734_MII	(0x01)
 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
-#define CONFIG_PHY_SMSC
-#define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 
 /* Board Clock */
diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h
index 297800e..c51b850 100644
--- a/include/configs/bav335x.h
+++ b/include/configs/bav335x.h
@@ -449,7 +449,6 @@
 /* SPI flash. */
 
 /* Network. */
-#define CONFIG_PHY_SMSC
 
 /*
  * NOR Size = 16 MiB
diff --git a/include/configs/bmips_bcm6318.h b/include/configs/bmips_bcm6318.h
index c7e7119..45eb931 100644
--- a/include/configs/bmips_bcm6318.h
+++ b/include/configs/bmips_bcm6318.h
@@ -19,7 +19,9 @@
 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#if defined(CONFIG_USB_OHCI_HCD)
 #define CONFIG_USB_OHCI_NEW
+#endif /* CONFIG_USB_OHCI_HCD */
 
 /* U-Boot */
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + SZ_1M
diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h
index 45f26bb..eed321e 100644
--- a/include/configs/bmips_bcm63268.h
+++ b/include/configs/bmips_bcm63268.h
@@ -19,7 +19,9 @@
 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#if defined(CONFIG_USB_OHCI_HCD)
 #define CONFIG_USB_OHCI_NEW
+#endif /* CONFIG_USB_OHCI_HCD */
 
 /* U-Boot */
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + SZ_1M
diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h
index 8d59438..c78099a 100644
--- a/include/configs/bmips_bcm6328.h
+++ b/include/configs/bmips_bcm6328.h
@@ -19,7 +19,9 @@
 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#if defined(CONFIG_USB_OHCI_HCD)
 #define CONFIG_USB_OHCI_NEW
+#endif /* CONFIG_USB_OHCI_HCD */
 
 /* U-Boot */
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + SZ_1M
diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h
index 061d6b2..547cf85 100644
--- a/include/configs/bmips_bcm6348.h
+++ b/include/configs/bmips_bcm6348.h
@@ -17,7 +17,9 @@
 /* USB */
 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#if defined(CONFIG_USB_OHCI_HCD)
 #define CONFIG_USB_OHCI_NEW
+#endif /* CONFIG_USB_OHCI_HCD */
 
 /* U-Boot */
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + SZ_1M
diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h
index 583217d..116e970 100644
--- a/include/configs/bmips_bcm6358.h
+++ b/include/configs/bmips_bcm6358.h
@@ -19,7 +19,9 @@
 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#if defined(CONFIG_USB_OHCI_HCD)
 #define CONFIG_USB_OHCI_NEW
+#endif /* CONFIG_USB_OHCI_HCD */
 
 /* U-Boot */
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + SZ_1M
diff --git a/include/configs/bmips_bcm6362.h b/include/configs/bmips_bcm6362.h
index 570bc3b..e5e8b15 100644
--- a/include/configs/bmips_bcm6362.h
+++ b/include/configs/bmips_bcm6362.h
@@ -19,7 +19,9 @@
 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#if defined(CONFIG_USB_OHCI_HCD)
 #define CONFIG_USB_OHCI_NEW
+#endif /* CONFIG_USB_OHCI_HCD */
 
 /* U-Boot */
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + SZ_1M
diff --git a/include/configs/bmips_bcm6368.h b/include/configs/bmips_bcm6368.h
index ab5bdac..4d4403f 100644
--- a/include/configs/bmips_bcm6368.h
+++ b/include/configs/bmips_bcm6368.h
@@ -19,7 +19,9 @@
 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#if defined(CONFIG_USB_OHCI_HCD)
 #define CONFIG_USB_OHCI_NEW
+#endif /* CONFIG_USB_OHCI_HCD */
 
 /* U-Boot */
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + SZ_1M
diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h
index befa06f..797fcb1 100644
--- a/include/configs/cgtqmx6eval.h
+++ b/include/configs/cgtqmx6eval.h
@@ -79,7 +79,6 @@
 #define CONFIG_FEC_XCV_TYPE		RGMII
 #define CONFIG_ETHPRIME			"FEC"
 #define CONFIG_FEC_MXC_PHYADDR		6
-#define CONFIG_PHY_ATHEROS
 
 /* Command definition */
 
diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h
index ca7ce31..f4dcc54 100644
--- a/include/configs/chiliboard.h
+++ b/include/configs/chiliboard.h
@@ -167,6 +167,5 @@
 #endif
 
 /* Network. */
-#define CONFIG_PHY_SMSC
 
 #endif	/* ! __CONFIG_CHILIBOARD_H */
diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h
index f9ffb4d..d47bdd2 100644
--- a/include/configs/cl-som-imx7.h
+++ b/include/configs/cl-som-imx7.h
@@ -23,8 +23,6 @@
 #define CONFIG_ETHPRIME                 "FEC"
 #define CONFIG_FEC_MXC_PHYADDR          0
 
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_ATHEROS
 /* ENET1 */
 #define IMX_FEC_BASE			ENET_IPS_BASE_ADDR
 
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index 53ae5f0..e62130f 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -165,7 +165,6 @@
 #define CONFIG_FEC_MXC_PHYADDR		0
 #define CONFIG_FEC_XCV_TYPE		RGMII
 #define IMX_FEC_BASE			ENET_BASE_ADDR
-#define CONFIG_PHY_ATHEROS
 #define CONFIG_ETHPRIME			"FEC0"
 #define CONFIG_ARP_TIMEOUT		200UL
 #define CONFIG_NET_RETRY_COUNT		5
diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h
index e0fc7fc..342cc7f 100644
--- a/include/configs/cm_t335.h
+++ b/include/configs/cm_t335.h
@@ -90,7 +90,6 @@
 /* SPL */
 
 /* Network. */
-#define CONFIG_PHY_ATHEROS
 
 /* NAND support */
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
index 1314cf9..55d9f53 100644
--- a/include/configs/cm_t43.h
+++ b/include/configs/cm_t43.h
@@ -45,7 +45,6 @@
 /* CPSW Ethernet support */
 #define CONFIG_BOOTP_DEFAULT
 #define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_PHY_ATHEROS
 #define CONFIG_SYS_RX_ETH_BUFFER	64
 
 /* USB support */
diff --git a/include/configs/condor.h b/include/configs/condor.h
index c286dbb..36466f0 100644
--- a/include/configs/condor.h
+++ b/include/configs/condor.h
@@ -12,7 +12,6 @@
 #include "rcar-gen3-common.h"
 
 /* Ethernet RAVB */
-#define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 
 /* Environment compatibility */
@@ -24,7 +23,6 @@
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
 #define CONFIG_SH_ETHER_ALIGNE_SIZE	64
-#define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 
 /* Board Clock */
diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h
index 1f6d0c5..a326a1c 100644
--- a/include/configs/controlcenterdc.h
+++ b/include/configs/controlcenterdc.h
@@ -54,7 +54,6 @@
 /*
  * Software (bit-bang) MII driver configuration
  */
-#define CONFIG_BITBANGMII		/* bit-bang MII PHY management */
 #define CONFIG_BITBANGMII_MULTI
 
 /* SPL */
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index bafedcb..b2c86ff 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -431,12 +431,6 @@
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_PHYLIB_10G
-#define CONFIG_PHY_VITESSE
-#define CONFIG_PHY_TERANETICS
-#endif
-
 #ifdef CONFIG_PCI
 #if !defined(CONFIG_DM_PCI)
 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
index 911ab9a..4c0229e 100644
--- a/include/configs/devkit3250.h
+++ b/include/configs/devkit3250.h
@@ -65,7 +65,6 @@
  * Ethernet
  */
 #define CONFIG_RMII
-#define CONFIG_PHY_SMSC
 #define CONFIG_LPC32XX_ETH
 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 
diff --git a/include/configs/draak.h b/include/configs/draak.h
index 78ec444..3248320 100644
--- a/include/configs/draak.h
+++ b/include/configs/draak.h
@@ -12,7 +12,6 @@
 #include "rcar-gen3-common.h"
 
 /* Ethernet RAVB */
-#define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 
 /* Generic Timer Definitions (use in assembler source) */
diff --git a/include/configs/draco.h b/include/configs/draco.h
index 016532f..396eb7d 100644
--- a/include/configs/draco.h
+++ b/include/configs/draco.h
@@ -36,8 +36,6 @@
 #define EEPROM_ADDR_DDR3 0x90
 #define EEPROM_ADDR_CHIP 0x120
 
-#define CONFIG_PHY_SMSC
-
 #define CONFIG_FACTORYSET
 
 /* Define own nand partitions */
diff --git a/include/configs/eagle.h b/include/configs/eagle.h
index b567caa..ee53504 100644
--- a/include/configs/eagle.h
+++ b/include/configs/eagle.h
@@ -12,7 +12,6 @@
 #include "rcar-gen3-common.h"
 
 /* Ethernet RAVB */
-#define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 
 /* Environment compatibility */
diff --git a/include/configs/ebisu.h b/include/configs/ebisu.h
index 0e24662..521a348 100644
--- a/include/configs/ebisu.h
+++ b/include/configs/ebisu.h
@@ -15,7 +15,6 @@
 
 /* Ethernet RAVB */
 #define CONFIG_NET_MULTI
-#define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 
 /* Generic Timer Definitions (use in assembler source) */
diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h
index 481066b..6256111 100644
--- a/include/configs/embestmx6boards.h
+++ b/include/configs/embestmx6boards.h
@@ -47,8 +47,6 @@
 #define CONFIG_ETHPRIME			"FEC"
 #define CONFIG_FEC_MXC_PHYADDR		4
 
-#define CONFIG_PHY_ATHEROS
-
 #define CONFIG_ARP_TIMEOUT     200UL
 
 #define CONFIG_SYS_MEMTEST_START       0x10000000
diff --git a/include/configs/etamin.h b/include/configs/etamin.h
index 4ce8f93..880149f 100644
--- a/include/configs/etamin.h
+++ b/include/configs/etamin.h
@@ -93,8 +93,6 @@
 #define EEPROM_ADDR_DDR3 0x90
 #define EEPROM_ADDR_CHIP 0x120
 
-#define CONFIG_PHY_SMSC
-
 #define CONFIG_FACTORYSET
 
 /* use both define to compile a SPL compliance test  */
diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h
index 59c6074..6412efc 100644
--- a/include/configs/gardena-smart-gateway-mt7688.h
+++ b/include/configs/gardena-smart-gateway-mt7688.h
@@ -16,10 +16,29 @@
 
 #define CONFIG_SYS_INIT_SP_OFFSET	0x400000
 
-#ifdef CONFIG_BOOT_RAM
+/* SPL */
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #endif
 
+#define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SPL_BSS_START_ADDR	0x80010000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x10000
+#define CONFIG_SPL_MAX_SIZE		0x10000
+#define CONFIG_SPL_PAD_TO		0
+
+/* Dummy value */
+#define CONFIG_SYS_UBOOT_BASE		0
+
+/* Serial SPL */
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT)
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_CLK		40000000
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_COM1		0xb0000c00
+#define CONFIG_CONS_INDEX		1
+#endif
+
 /* UART */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
 					  230400, 460800, 921600 }
diff --git a/include/configs/gose.h b/include/configs/gose.h
index fcb9f17..60a89e00 100644
--- a/include/configs/gose.h
+++ b/include/configs/gose.h
@@ -27,7 +27,6 @@
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
 #define CONFIG_SH_ETHER_ALIGNE_SIZE	64
-#define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 
 /* Board Clock */
diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h
index b875f9b..001e9d3 100644
--- a/include/configs/grpeach.h
+++ b/include/configs/grpeach.h
@@ -16,7 +16,6 @@
 
 /* Miscellaneous */
 #define CONFIG_SYS_PBSIZE	256
-#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
 #define CONFIG_CMDLINE_TAG
 
 /* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
@@ -43,7 +42,6 @@
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
 #define CONFIG_SH_ETHER_ALIGNE_SIZE	64
-#define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 
 #endif	/* __GRPEACH_H */
diff --git a/include/configs/helios4.h b/include/configs/helios4.h
index af595bc..f0ca8e2 100644
--- a/include/configs/helios4.h
+++ b/include/configs/helios4.h
@@ -52,7 +52,6 @@
 /* stay within first 1M */
 #endif
 
-#define CONFIG_PHY_MARVELL		/* there is a marvell phy */
 #define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
 
 /* Keep device tree and initrd in lower memory so the kernel can access them */
diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h
index 43c31e6..5d85092 100644
--- a/include/configs/hrcon.h
+++ b/include/configs/hrcon.h
@@ -293,7 +293,6 @@
 /*
  * Software (bit-bang) MII driver configuration
  */
-#define CONFIG_BITBANGMII		/* bit-bang MII PHY management */
 #define CONFIG_BITBANGMII_MULTI
 
 /*
diff --git a/include/configs/hsdk-4xd.h b/include/configs/hsdk-4xd.h
new file mode 100644
index 0000000..4628108
--- /dev/null
+++ b/include/configs/hsdk-4xd.h
@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ */
+
+#ifndef _CONFIG_HSDK_H_
+#define _CONFIG_HSDK_H_
+
+#include <linux/sizes.h>
+
+/*
+ *  CPU configuration
+ */
+#define NR_CPUS				4
+#define ARC_PERIPHERAL_BASE		0xF0000000
+#define ARC_DWMMC_BASE			(ARC_PERIPHERAL_BASE + 0xA000)
+#define ARC_DWGMAC_BASE			(ARC_PERIPHERAL_BASE + 0x18000)
+
+/*
+ * Memory configuration
+ */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE		SZ_1G
+
+#define CONFIG_SYS_INIT_SP_ADDR		\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN		SZ_2M
+#define CONFIG_SYS_BOOTM_LEN		SZ_128M
+#define CONFIG_SYS_LOAD_ADDR		0x82000000
+
+/*
+ * UART configuration
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_CLK		33330000
+#define CONFIG_SYS_NS16550_MEM32
+
+/*
+ * Ethernet PHY configuration
+ */
+
+/*
+ * USB 1.1 configuration
+ */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
+
+/*
+ * Environment settings
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"upgrade=if mmc rescan && " \
+		"fatload mmc 0:1 ${loadaddr} u-boot-update.scr && " \
+		"iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \
+		"\"Fail to upgrade.\n" \
+		"Do you have u-boot-update.scr and u-boot.head on first (FAT) SD card partition?\"" \
+		"; fi\0" \
+	"core_mask=0xF\0" \
+	"hsdk_hs45d=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
+setenv l2_cache_ena 0x0; setenv icache_ena 0x0; setenv csm_location 0x10; \
+setenv dcache_ena 0x0; setenv core_iccm_1 0x7; \
+setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
+	"hsdk_hs47d=setenv core_mask 0x1; setenv haps_apb_location 0x1; \
+setenv l2_cache_ena 0x0; setenv icache_ena 0x1; setenv csm_location 0x10; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF;\0" \
+	"hsdk_hs47d_ccm=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
+setenv l2_cache_ena 0x0; setenv icache_ena 0x1; setenv csm_location 0x10; \
+setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
+setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
+	"hsdk_hs48=setenv core_mask 0x1; setenv haps_apb_location 0x1; \
+setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF;\0" \
+	"hsdk_hs48_ccm=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
+setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
+setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
+setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
+	"hsdk_hs48x2=run hsdk_hs47dx2;\0" \
+	"hsdk_hs47dx2=setenv core_mask 0x3; setenv haps_apb_location 0x1; \
+setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \
+setenv core_iccm_1 0x6; setenv core_dccm_1 0x6;\0" \
+	"hsdk_hs48x3=run hsdk_hs47dx3;\0" \
+	"hsdk_hs47dx3=setenv core_mask 0x7; setenv haps_apb_location 0x1; \
+setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \
+setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
+setenv core_iccm_2 0x10; setenv core_dccm_2 0x10;\0" \
+	"hsdk_hs48x4=run hsdk_hs47dx4;\0" \
+	"hsdk_hs47dx4=setenv core_mask 0xF; setenv haps_apb_location 0x1; \
+setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \
+setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
+setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \
+setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0"
+
+/*
+ * Environment configuration
+ */
+#define CONFIG_BOOTFILE			"uImage"
+#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
+
+/* Cli configuration */
+#define CONFIG_SYS_CBSIZE		SZ_2K
+
+/*
+ * Callback configuration
+ */
+#define CONFIG_BOARD_LATE_INIT
+
+#endif /* _CONFIG_HSDK_H_ */
diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
index 5d9ef70..ecf4c2e 100644
--- a/include/configs/imx8mq_evk.h
+++ b/include/configs/imx8mq_evk.h
@@ -82,9 +82,6 @@
 
 #define CONFIG_PHY_GIGE
 #define IMX_FEC_BASE			0x30BE0000
-
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_ATHEROS
 #endif
 
 #define CONFIG_MFG_ENV_SETTINGS \
diff --git a/include/configs/kmp204x.h b/include/configs/kmp204x.h
index 0224ac4..e43b2f7 100644
--- a/include/configs/kmp204x.h
+++ b/include/configs/kmp204x.h
@@ -318,8 +318,6 @@
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 
-#define CONFIG_PHYLIB_10G
-
 #define CONFIG_PCI_INDIRECT_BRIDGE
 
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h
index 140076a..65a38c5 100644
--- a/include/configs/koelsch.h
+++ b/include/configs/koelsch.h
@@ -27,7 +27,6 @@
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
 #define CONFIG_SH_ETHER_ALIGNE_SIZE	64
-#define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 
 /* Board Clock */
diff --git a/include/configs/lager.h b/include/configs/lager.h
index db1dbc0..c5001e3 100644
--- a/include/configs/lager.h
+++ b/include/configs/lager.h
@@ -28,7 +28,6 @@
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
 #define CONFIG_SH_ETHER_ALIGNE_SIZE	64
-#define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 
 /* Board Clock */
diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h
index ca5b693..4276e95 100644
--- a/include/configs/linkit-smart-7688.h
+++ b/include/configs/linkit-smart-7688.h
@@ -16,10 +16,30 @@
 
 #define CONFIG_SYS_INIT_SP_OFFSET	0x400000
 
-#ifdef CONFIG_BOOT_RAM
+/* SPL */
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #endif
 
+#define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SPL_BSS_START_ADDR	0x80010000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x10000
+#define CONFIG_SPL_MAX_SIZE		0x10000
+#define CONFIG_SPL_PAD_TO		0
+
+/* Dummy value */
+#define CONFIG_SYS_UBOOT_BASE		0
+
+/* Serial SPL */
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT)
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_CLK		40000000
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_COM3		0xb0000e00
+#define CONFIG_CONS_INDEX		3
+
+#endif
+
 /* UART */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
 					  230400, 460800, 921600 }
diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h
index 14008fe..6aba6a6 100644
--- a/include/configs/liteboard.h
+++ b/include/configs/liteboard.h
@@ -143,8 +143,6 @@
 #define CONFIG_FEC_MXC_PHYADDR		0x0
 #define CONFIG_FEC_XCV_TYPE		RMII
 #define CONFIG_ETHPRIME			"FEC"
-
-#define CONFIG_PHY_SMSC
 #endif
 
 #define CONFIG_IMX_THERMAL
diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h
index 6143e97..4d4c1a0 100644
--- a/include/configs/ls1012afrwy.h
+++ b/include/configs/ls1012afrwy.h
@@ -33,7 +33,8 @@
 #undef BOOT_TARGET_DEVICES
 #define BOOT_TARGET_DEVICES(func) \
 	func(MMC, mmc, 0) \
-	func(USB, usb, 0)
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
 #endif
 
 #undef FSL_QSPI_FLASH_SIZE
@@ -102,15 +103,6 @@
 			"env exists secureboot "	\
 			"&& esbc_validate ${scripthdraddr};"    \
 		"source ${scriptaddr}\0"	  \
-	"installer=load mmc 0:2 $load_addr "	\
-		   "/flex_installer_arm64.itb; "	\
-		   "bootm $load_addr#$BOARD\0"	\
-	"qspi_bootcmd=pfe stop; echo Trying load from qspi..;"	\
-		"sf probe && sf read $load_addr "	\
-		"$kernel_addr $kernel_size; env exists secureboot "	\
-		"&& sf read $kernelheader_addr_r $kernelheader_addr "	\
-		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
-		"bootm $load_addr#$BOARD\0"	\
 	"sd_bootcmd=pfe stop; echo Trying load from sd card..;"		\
 		"mmcinfo; mmc read $load_addr "			\
 		"$kernel_addr_sd $kernel_size_sd ;"		\
diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h
index 7821e98..912345b 100644
--- a/include/configs/ls1021aiot.h
+++ b/include/configs/ls1021aiot.h
@@ -174,8 +174,6 @@
 
 #define CONFIG_ETHPRIME			"eTSEC2"
 
-#define CONFIG_PHY_ATHEROS
-
 #define CONFIG_HAS_ETH0
 #define CONFIG_HAS_ETH1
 #define CONFIG_HAS_ETH2
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 5a2bd75..0e1eff7 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -419,8 +419,6 @@
 
 #define CONFIG_ETHPRIME			"eTSEC1"
 
-#define CONFIG_PHY_REALTEK
-
 #define CONFIG_HAS_ETH0
 #define CONFIG_HAS_ETH1
 #define CONFIG_HAS_ETH2
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index a628985..45ce460 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -297,7 +297,8 @@
 
 #ifdef CONFIG_LPUART
 #define CONFIG_EXTRA_ENV_SETTINGS       \
-	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200 $othbootargs\0" \
+	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200 "	\
+		"cma=64M@0x0-0xb0000000\0" \
 	"initrd_high=0xffffffff\0"      \
 	"fdt_addr=0x64f00000\0"		\
 	"kernel_addr=0x65000000\0"	\
@@ -353,7 +354,8 @@
 		"$kernel_size && bootm $load_addr#$board\0"
 #else
 #define CONFIG_EXTRA_ENV_SETTINGS	\
-	"bootargs=root=/dev/ram0 rw console=ttyS0,115200 $othbootargs\0" \
+	"bootargs=root=/dev/ram0 rw console=ttyS0,115200 "	\
+		"cma=64M@0x0-0xb0000000\0" \
 	"initrd_high=0xffffffff\0"      \
 	"fdt_addr=0x64f00000\0"		\
 	"kernel_addr=0x61000000\0"	\
diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h
index 818b994..b910169 100644
--- a/include/configs/ls1028aqds.h
+++ b/include/configs/ls1028aqds.h
@@ -66,6 +66,13 @@
 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 #endif
 
+/* LPUART */
+#ifdef CONFIG_LPUART
+#define CONFIG_LPUART_32B_REG
+#define CFG_LPUART_MUX_MASK	0xf0
+#define CFG_LPUART_EN		0xf0
+#endif
+
 /* SATA */
 #define CONFIG_SCSI_AHCI_PLAT
 
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 3708062..5769dc4 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -35,9 +35,6 @@
 #endif
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_PHY_VITESSE
-#define CONFIG_PHY_REALTEK
-#define CONFIG_PHYLIB_10G
 #define RGMII_PHY1_ADDR		0x1
 #define RGMII_PHY2_ADDR		0x2
 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index f7b110c..4ad51f1 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -258,11 +258,6 @@
 #ifndef SPL_NO_FMAN
 #define AQR105_IRQ_MASK			0x40000000
 
-#ifdef CONFIG_NET
-#define CONFIG_PHY_VITESSE
-#define CONFIG_PHY_REALTEK
-#endif
-
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define RGMII_PHY1_ADDR			0x1
 #define RGMII_PHY2_ADDR			0x2
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index e80c299..24db23b 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -217,6 +217,10 @@
 #define LS1046A_BOOT_SRC_AND_HDR\
 	"boot_scripts=ls1046afrwy_boot.scr\0"	\
 	"boot_script_hdr=hdr_ls1046afrwy_bs.out\0"
+#elif defined(CONFIG_TARGET_LS1046AQDS)
+#define LS1046A_BOOT_SRC_AND_HDR\
+	"boot_scripts=ls1046aqds_boot.scr\0"	\
+	"boot_script_hdr=hdr_ls1046aqds_bs.out\0"
 #else
 #define LS1046A_BOOT_SRC_AND_HDR\
 	"boot_scripts=ls1046ardb_boot.scr\0"	\
@@ -230,7 +234,7 @@
 	"ramdisk_size=0x2000000\0"		\
 	"bootm_size=0x10000000\0"		\
 	"fdt_addr=0x64f00000\0"                 \
-	"kernel_addr=0x65000000\0"              \
+	"kernel_addr=0x61000000\0"              \
 	"scriptaddr=0x80000000\0"               \
 	"scripthdraddr=0x80080000\0"		\
 	"fdtheader_addr_r=0x80100000\0"         \
@@ -277,6 +281,18 @@
 		"&& sf read $kernelheader_addr_r $kernelheader_start "	\
 		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 		"bootm $load_addr#$board\0"		\
+	"nand_bootcmd=echo Trying load from nand..;"      \
+		"nand info; nand read $load_addr "         \
+		"$kernel_start $kernel_size; env exists secureboot "	\
+		"&& nand read $kernelheader_addr_r $kernelheader_start " \
+		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
+		"bootm $load_addr#$board\0"		\
+	"nor_bootcmd=echo Trying load from nor..;"	\
+		"cp.b $kernel_addr $load_addr "		\
+		"$kernel_size; env exists secureboot "	\
+		"&& cp.b $kernelheader_addr $kernelheader_addr_r "	\
+		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
+		"bootm $load_addr#$board\0"	\
 	"sd_bootcmd=echo Trying load from SD ..;"	\
 		"mmcinfo; mmc read $load_addr "		\
 		"$kernel_addr_sd $kernel_size_sd && "	\
diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index 0b17b1e..9ff248c 100644
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -52,9 +52,6 @@
 #endif
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_PHY_VITESSE
-#define CONFIG_PHY_REALTEK
-#define CONFIG_PHYLIB_10G
 #define RGMII_PHY1_ADDR		0x1
 #define RGMII_PHY2_ADDR		0x2
 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
@@ -440,19 +437,27 @@
 
 #undef CONFIG_BOOTCOMMAND
 #ifdef CONFIG_TFABOOT
-#define QSPI_NOR_BOOTCOMMAND		"sf probe && sf read $kernel_load "    \
-					"e0000 f00000 && bootm $kernel_load"
-#define IFC_NOR_BOOTCOMMAND		"cp.b $kernel_start $kernel_load "     \
-					"$kernel_size && bootm $kernel_load"
-#define SD_BOOTCOMMAND		"mmc info; mmc read $kernel_load"     \
-					"$kernel_addr_sd $kernel_size_sd && bootm $kernel_load"
+#define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; "	\
+			   "env exists secureboot && esbc_halt;;"
+#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd"	\
+			   "env exists secureboot && esbc_halt;;"
+#define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "	\
+			   "env exists secureboot && esbc_halt;;"
+#define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "	\
+			   "env exists secureboot && esbc_halt;;"
 #else
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_BOOTCOMMAND		"sf probe && sf read $kernel_load "    \
-					"e0000 f00000 && bootm $kernel_load"
+#if defined(CONFIG_QSPI_BOOT)
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "	\
+			   "env exists secureboot && esbc_halt;;"
+#elif defined(CONFIG_NAND_BOOT)
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; "	\
+			   "env exists secureboot && esbc_halt;;"
+#elif defined(CONFIG_SD_BOOT)
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "	\
+			   "env exists secureboot && esbc_halt;;"
 #else
-#define CONFIG_BOOTCOMMAND		"cp.b $kernel_start $kernel_load "     \
-					"$kernel_size && bootm $kernel_load"
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "	\
+			   "env exists secureboot && esbc_halt;;"
 #endif
 #endif
 
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
index efedfd5..1093761 100644
--- a/include/configs/ls1046ardb.h
+++ b/include/configs/ls1046ardb.h
@@ -170,11 +170,6 @@
 #define AQR105_IRQ_MASK			0x80000000
 /* FMan */
 #ifndef SPL_NO_FMAN
-
-#ifdef CONFIG_NET
-#define CONFIG_PHY_REALTEK
-#endif
-
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define RGMII_PHY1_ADDR			0x1
 #define RGMII_PHY2_ADDR			0x2
diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h
index 4ac4a8d..301945f 100644
--- a/include/configs/ls1088aqds.h
+++ b/include/configs/ls1088aqds.h
@@ -549,11 +549,6 @@
 
 #ifdef CONFIG_FSL_MC_ENET
 #define CONFIG_FSL_MEMAC
-#define	CONFIG_PHYLIB
-#define CONFIG_PHYLIB_10G
-#define CONFIG_PHY_VITESSE
-#define CONFIG_PHY_REALTEK
-#define CONFIG_PHY_TERANETICS
 #define RGMII_PHY1_ADDR		0x1
 #define RGMII_PHY2_ADDR		0x2
 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h
index b48efcc..7cb0704 100644
--- a/include/configs/ls1088ardb.h
+++ b/include/configs/ls1088ardb.h
@@ -522,9 +522,6 @@
 
 /* MAC/PHY configuration */
 #ifdef CONFIG_FSL_MC_ENET
-#define CONFIG_PHYLIB
-
-#define CONFIG_PHY_VITESSE
 #define AQ_PHY_ADDR1			0x00
 #define AQR105_IRQ_MASK			0x00000004
 
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index e93faab..8ab892b 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -479,10 +479,6 @@
 
 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 #define CONFIG_FSL_MEMAC
-#define CONFIG_PHYLIB_10G
-#define CONFIG_PHY_VITESSE
-#define CONFIG_PHY_REALTEK
-#define CONFIG_PHY_TERANETICS
 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index d47abf6..5ab9244 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -207,6 +207,16 @@
 	"esbc_validate 0x80680000 ;"		\
 	"fsl_mc start mc 0x80a00000 0x80e00000\0"
 
+#define SD2_MC_INIT_CMD				\
+	"mmc dev 1; mmc read 0x80a00000 0x5000 0x1200;"	\
+	"mmc read 0x80e00000 0x7000 0x800;"	\
+	"env exists secureboot && "		\
+	"mmc read 0x80640000 0x3200 0x20 && "	\
+	"mmc read 0x80680000 0x3400 0x20 && "	\
+	"esbc_validate 0x80640000 && "		\
+	"esbc_validate 0x80680000 ;"		\
+	"fsl_mc start mc 0x80a00000 0x80e00000\0"
+
 #define EXTRA_ENV_SETTINGS			\
 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
 	"ramdisk_addr=0x800000\0"		\
@@ -274,11 +284,11 @@
 		"env exists secureboot && esbc_halt;"
 
 #define SD2_BOOTCOMMAND						\
-		"env exists mcinitcmd && mmcinfo; "		\
+		"mmc dev 1; env exists mcinitcmd && mmcinfo; "	\
 		"mmc read 0x80d00000 0x6800 0x800; "		\
 		"env exists mcinitcmd && env exists secureboot "	\
-		" && mmc read 0x80780000 0x3C00 0x20 "		\
-		"&& esbc_validate 0x80780000;env exists mcinitcmd "	\
+		" && mmc read 0x806C0000 0x3600 0x20 "		\
+		"&& esbc_validate 0x806C0000;env exists mcinitcmd "	\
 		"&& fsl_mc lazyapply dpl 0x80d00000;"		\
 		"run distro_bootcmd;run sd2_bootcmd;"		\
 		"env exists secureboot && esbc_halt;"
diff --git a/include/configs/malta.h b/include/configs/malta.h
index bb8a444..d41b80c 100644
--- a/include/configs/malta.h
+++ b/include/configs/malta.h
@@ -16,7 +16,6 @@
 #define CONFIG_PCI_GT64120
 #define CONFIG_PCI_MSC01
 #define CONFIG_PCNET
-#define CONFIG_PCNET_79C973
 #define PCNET_HAS_PROM
 
 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS	0
diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h
index faab091..fe436cc 100644
--- a/include/configs/mt7623.h
+++ b/include/configs/mt7623.h
@@ -45,11 +45,13 @@
 #define CONFIG_SYS_SDRAM_BASE		0x80000000
 
 /* This is needed for kernel booting */
-#define FDT_HIGH			"fdt_high=0xac000000\0"
+#define FDT_HIGH			"0xac000000"
 
-/* Extra environment variables */
-#define CONFIG_EXTRA_ENV_SETTINGS	\
-	FDT_HIGH
+#define ENV_MEM_LAYOUT_SETTINGS				\
+	"fdt_high=" FDT_HIGH "\0"			\
+	"kernel_addr_r=0x84000000\0"			\
+	"fdt_addr_r=" FDT_HIGH "\0"			\
+	"fdtfile=mt7623n-bananapi-bpi-r2.dtb" "\0"
 
 /* Ethernet */
 #define CONFIG_IPADDR			192.168.1.1
@@ -57,4 +59,18 @@
 
 #define CONFIG_SYS_MMC_ENV_DEV		0
 
+#ifdef CONFIG_DISTRO_DEFAULTS
+
+#define BOOT_TARGET_DEVICES(func)	\
+		func(MMC, mmc, 1)
+
+#include <config_distro_bootcmd.h>
+
+/* Extra environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	ENV_MEM_LAYOUT_SETTINGS		\
+	BOOTENV
+
+#endif /* ifdef CONFIG_DISTRO_DEFAULTS*/
+
 #endif
diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h
new file mode 100644
index 0000000..9b9218d
--- /dev/null
+++ b/include/configs/mt7628.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#ifndef __CONFIG_MT7628_H
+#define __CONFIG_MT7628_H
+
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_MIPS_TIMER_FREQ	290000000
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_MALLOC_LEN		0x100000
+#define CONFIG_SYS_BOOTPARAMS_LEN	0x20000
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_LOAD_ADDR		0x80010000
+
+#define CONFIG_SYS_INIT_SP_OFFSET	0x80000
+
+#define CONFIG_SYS_BOOTM_LEN		0x1000000
+
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_CBSIZE		1024
+
+/* Serial SPL */
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT)
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_CLK		40000000
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_COM1		0xb0000c00
+#define CONFIG_CONS_INDEX		1
+#endif
+
+/* Serial common */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+					  230400, 460800, 921600 }
+
+/* SPL */
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SPL_BSS_START_ADDR	0x80010000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x10000
+#define CONFIG_SPL_MAX_SIZE		0x10000
+#define CONFIG_SPL_PAD_TO		0
+
+/* Dummy value */
+#define CONFIG_SYS_UBOOT_BASE		0
+
+#endif /* __CONFIG_MT7628_H */
diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
index a669036..e10e768 100644
--- a/include/configs/mx6cuboxi.h
+++ b/include/configs/mx6cuboxi.h
@@ -32,7 +32,6 @@
 #define IMX_FEC_BASE			ENET_BASE_ADDR
 #define CONFIG_FEC_XCV_TYPE		RGMII
 #define CONFIG_FEC_MXC_PHYADDR		0
-#define CONFIG_PHY_ATHEROS
 
 /* Framebuffer */
 #define CONFIG_VIDEO_BMP_RLE8
diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h
index 0bcf031..984cf61 100644
--- a/include/configs/mx6sxsabreauto.h
+++ b/include/configs/mx6sxsabreauto.h
@@ -134,8 +134,6 @@
 #define CONFIG_FEC_XCV_TYPE             RGMII
 #define CONFIG_ETHPRIME                 "FEC"
 
-#define CONFIG_PHY_ATHEROS
-
 #ifdef CONFIG_CMD_USB
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 55aace1..86007a2 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -157,8 +157,6 @@
 #define CONFIG_FEC_XCV_TYPE             RGMII
 #define CONFIG_ETHPRIME                 "FEC"
 
-#define CONFIG_PHY_ATHEROS
-
 #ifdef CONFIG_CMD_USB
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h
index c8ebe3e..3a1ea0f 100644
--- a/include/configs/ot1200.h
+++ b/include/configs/ot1200.h
@@ -66,7 +66,6 @@
 #define CONFIG_FEC_XCV_TYPE             MII100
 #define CONFIG_ETHPRIME                 "FEC"
 #define CONFIG_FEC_MXC_PHYADDR          0x5
-#define CONFIG_PHY_SMSC
 
 #ifndef CONFIG_SPL
 #define CONFIG_ENV_EEPROM_IS_ON_I2C
diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h
index 3ff7566..6dc5039 100644
--- a/include/configs/p1_twr.h
+++ b/include/configs/p1_twr.h
@@ -11,7 +11,6 @@
 
 #if defined(CONFIG_TWR_P1025)
 #define CONFIG_BOARDNAME "TWR-P1025"
-#define CONFIG_PHY_ATHEROS
 #define CONFIG_SYS_LBC_LBCR	0x00080000	/* Conversion of LBC addr */
 #define CONFIG_SYS_LBC_LCRR	0x80000002	/* LB clock ratio reg */
 #endif
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
index fdbc075..290e652 100644
--- a/include/configs/pcm051.h
+++ b/include/configs/pcm051.h
@@ -128,6 +128,4 @@
 #define CONFIG_AM335X_USB1
 #define CONFIG_AM335X_USB1_MODE MUSB_HOST
 
-#define CONFIG_PHY_SMSC
-
 #endif	/* ! __CONFIG_PCM051_H */
diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h
index 8a05069..17d1981 100644
--- a/include/configs/pengwyn.h
+++ b/include/configs/pengwyn.h
@@ -162,7 +162,5 @@
 
 /* Network */
 #define CONFIG_PHY_RESET	1
-#define CONFIG_PHY_NATSEMI
-#define CONFIG_PHY_REALTEK
 
 #endif	/* ! __CONFIG_PENGWYN_H */
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 2f641d3..1a89c56 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -57,7 +57,6 @@
 /*-----------------------------------------------------------------------
  * Networking Configuration
  */
-#define CONFIG_PHY_SMSC
 #define CONFIG_SYS_RX_ETH_BUFFER	8
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_ARP_TIMEOUT		500 /* millisec */
diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h
index 376370b..7cc55cb 100644
--- a/include/configs/pico-imx6.h
+++ b/include/configs/pico-imx6.h
@@ -146,8 +146,6 @@
 #define CONFIG_FEC_XCV_TYPE		RGMII
 #define CONFIG_ETHPRIME			"FEC"
 #define CONFIG_FEC_MXC_PHYADDR		1
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_ATHEROS
 
 /* Framebuffer */
 #define CONFIG_VIDEO_BMP_RLE8
diff --git a/include/configs/porter.h b/include/configs/porter.h
index db42176..7ffcf5f 100644
--- a/include/configs/porter.h
+++ b/include/configs/porter.h
@@ -32,7 +32,6 @@
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
 #define CONFIG_SH_ETHER_ALIGNE_SIZE	64
-#define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 
 /* Board Clock */
diff --git a/include/configs/pxa-common.h b/include/configs/pxa-common.h
index e25800a..2632d48 100644
--- a/include/configs/pxa-common.h
+++ b/include/configs/pxa-common.h
@@ -8,8 +8,6 @@
 #ifndef	__CONFIG_PXA_COMMON_H__
 #define	__CONFIG_PXA_COMMON_H__
 
-#define	CONFIG_SYS_ARM_CACHE_WRITETHROUGH
-
 /*
  * KGDB
  */
diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h
index 543eb2d..ab9c116 100644
--- a/include/configs/pxm2.h
+++ b/include/configs/pxm2.h
@@ -36,8 +36,6 @@
 #define CONFIG_SYS_I2C_SPEED		400000
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
 
-#define CONFIG_PHY_ATHEROS
-
 #define CONFIG_FACTORYSET
 
 #ifndef CONFIG_SPL_BUILD
diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h
index bd5e00e..7f12844 100644
--- a/include/configs/rastaban.h
+++ b/include/configs/rastaban.h
@@ -41,8 +41,6 @@
 #define EEPROM_ADDR_DDR3 0x90
 #define EEPROM_ADDR_CHIP 0x120
 
-#define CONFIG_PHY_SMSC
-
 #define CONFIG_FACTORYSET
 
 /* Define own nand partitions */
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index 89a8a44..f0ae6e6 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -48,6 +48,8 @@
 
 #define ENV_MEM_LAYOUT_SETTINGS \
 	"scriptaddr=0x00500000\0" \
+	"script_offset_f=0xffe000\0" \
+	"script_size_f=0x2000\0" \
 	"pxefile_addr_r=0x00600000\0" \
 	"fdt_addr_r=0x01f00000\0" \
 	"kernel_addr_r=0x02080000\0" \
@@ -58,6 +60,7 @@
 #endif
 
 #include <config_distro_bootcmd.h>
+#include <environment/distro/sf.h>
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	ENV_MEM_LAYOUT_SETTINGS \
 	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h
index b55e09a..bf8c60d 100644
--- a/include/configs/rockchip-common.h
+++ b/include/configs/rockchip-common.h
@@ -41,11 +41,26 @@
 	#define BOOT_TARGET_DHCP(func)
 #endif
 
+#if CONFIG_IS_ENABLED(CMD_SF)
+	#define BOOT_TARGET_SF(func)	func(SF, sf, 0)
+#else
+	#define BOOT_TARGET_SF(func)
+#endif
+
+#ifdef CONFIG_ROCKCHIP_RK3399
 #define BOOT_TARGET_DEVICES(func) \
 	BOOT_TARGET_MMC(func) \
 	BOOT_TARGET_USB(func) \
 	BOOT_TARGET_PXE(func) \
+	BOOT_TARGET_DHCP(func) \
+	BOOT_TARGET_SF(func)
+#else
+#define BOOT_TARGET_DEVICES(func) \
+	BOOT_TARGET_MMC(func) \
+	BOOT_TARGET_USB(func) \
+	BOOT_TARGET_PXE(func) \
 	BOOT_TARGET_DHCP(func)
+#endif
 
 #ifdef CONFIG_ARM64
 #define ROOT_UUID "B921B045-1DF0-41C3-AF44-4C6F280D3FAE;\0"
diff --git a/include/configs/rut.h b/include/configs/rut.h
index 296bdc2..0dcdb10 100644
--- a/include/configs/rut.h
+++ b/include/configs/rut.h
@@ -31,8 +31,6 @@
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6       /* 64 byte pages */
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* take up to 10 msec */
 
-#define CONFIG_PHY_NATSEMI
-
 #define CONFIG_FACTORYSET
 
 /* Watchdog */
diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h
index 669602e..84c6ca9 100644
--- a/include/configs/salvator-x.h
+++ b/include/configs/salvator-x.h
@@ -12,7 +12,6 @@
 #include "rcar-gen3-common.h"
 
 /* Ethernet RAVB */
-#define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 
 /* Generic Timer Definitions (use in assembler source) */
diff --git a/include/configs/sc_sps_1.h b/include/configs/sc_sps_1.h
index 8db2772..3484bfe 100644
--- a/include/configs/sc_sps_1.h
+++ b/include/configs/sc_sps_1.h
@@ -28,7 +28,6 @@
 /* FEC Ethernet on SoC */
 #ifdef CONFIG_CMD_NET
 #define CONFIG_FEC_MXC
-#define CONFIG_PHY_SMSC
 #endif
 
 /* USB */
diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h
index 3a1f1ac..c45b33a 100644
--- a/include/configs/sh7752evb.h
+++ b/include/configs/sh7752evb.h
@@ -43,10 +43,8 @@
 #define CONFIG_SH_ETHER_PHY_ADDR	18
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK	1
 #define CONFIG_SH_ETHER_USE_GETHER	1
-#define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
-#define CONFIG_PHY_VITESSE
 
 #define SH7752EVB_ETHERNET_MAC_BASE_SPI	0x00090000
 #define SH7752EVB_SPI_SECTOR_SIZE	(64 * 1024)
diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h
index 5253a5b..70e7fb9 100644
--- a/include/configs/sh7753evb.h
+++ b/include/configs/sh7753evb.h
@@ -43,10 +43,8 @@
 #define CONFIG_SH_ETHER_PHY_ADDR	18
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK	1
 #define CONFIG_SH_ETHER_USE_GETHER	1
-#define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
-#define CONFIG_PHY_VITESSE
 
 #define SH7753EVB_ETHERNET_MAC_BASE_SPI	0x00090000
 #define SH7753EVB_SPI_SECTOR_SIZE	(64 * 1024)
diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h
index d46aaad..6a34dc7 100644
--- a/include/configs/sh7757lcr.h
+++ b/include/configs/sh7757lcr.h
@@ -45,7 +45,6 @@
 #define CONFIG_SH_ETHER_USE_PORT	0
 #define CONFIG_SH_ETHER_PHY_ADDR	1
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK	1
-#define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
 
diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h
index 2e79fea0..5122c8b 100644
--- a/include/configs/sh7763rdp.h
+++ b/include/configs/sh7763rdp.h
@@ -64,7 +64,6 @@
 /* Ether */
 #define CONFIG_SH_ETHER_USE_PORT (1)
 #define CONFIG_SH_ETHER_PHY_ADDR (0x01)
-#define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
 
diff --git a/include/configs/silk.h b/include/configs/silk.h
index a78da46..eee60fd 100644
--- a/include/configs/silk.h
+++ b/include/configs/silk.h
@@ -32,7 +32,6 @@
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
 #define CONFIG_SH_ETHER_ALIGNE_SIZE	64
-#define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 
 /* Board Clock */
diff --git a/include/configs/spear6xx_evb.h b/include/configs/spear6xx_evb.h
index cfadfc8..4fedc9e 100644
--- a/include/configs/spear6xx_evb.h
+++ b/include/configs/spear6xx_evb.h
@@ -29,7 +29,6 @@
 #define CONFIG_SYS_NAND_BASE			0xD2000000
 
 /* Ethernet PHY configuration */
-#define CONFIG_PHY_NATSEMI
 
 /* Environment Settings */
 #define CONFIG_EXTRA_ENV_SETTINGS              CONFIG_EXTRA_ENV_USBTTY
diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h
index 45343d2..529152f 100644
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h
@@ -33,7 +33,6 @@
 
 #define CONFIG_DW_GMAC_DEFAULT_DMA_PBL	(8)
 #define CONFIG_DW_ALTDESCRIPTOR
-#define CONFIG_PHY_SMSC
 
 #define CONFIG_SYS_HZ_CLOCK		1000000	/* Timer is clocked at 1MHz */
 
diff --git a/include/configs/stout.h b/include/configs/stout.h
index 6734595..a1e7e86 100644
--- a/include/configs/stout.h
+++ b/include/configs/stout.h
@@ -36,7 +36,6 @@
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
 #define CONFIG_SH_ETHER_ALIGNE_SIZE	64
-#define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 
 /* Board Clock */
diff --git a/include/configs/strider.h b/include/configs/strider.h
index ac9fce8..06a86bb 100644
--- a/include/configs/strider.h
+++ b/include/configs/strider.h
@@ -326,7 +326,6 @@
 /*
  * Software (bit-bang) MII driver configuration
  */
-#define CONFIG_BITBANGMII		/* bit-bang MII PHY management */
 #define CONFIG_BITBANGMII_MULTI
 
 /*
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 0ef289f..5b0bec0 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -272,10 +272,6 @@
 
 /* Ethernet support */
 
-#ifdef CONFIG_SUN7I_GMAC
-#define CONFIG_PHY_REALTEK
-#endif
-
 #ifdef CONFIG_USB_EHCI_HCD
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
diff --git a/include/configs/tb100.h b/include/configs/tb100.h
index a761c37..ae54520 100644
--- a/include/configs/tb100.h
+++ b/include/configs/tb100.h
@@ -38,7 +38,6 @@
  * Until Realtek PHY driver is fixed fall back to generic PHY driver
  * which implements all required functionality and behaves much more stable.
  *
- * #define CONFIG_PHY_REALTEK
  *
  */
 
diff --git a/include/configs/thuban.h b/include/configs/thuban.h
index d909be9..15a8469 100644
--- a/include/configs/thuban.h
+++ b/include/configs/thuban.h
@@ -34,8 +34,6 @@
 #define EEPROM_ADDR_DDR3 0x90
 #define EEPROM_ADDR_CHIP 0x120
 
-#define CONFIG_PHY_SMSC
-
 #define CONFIG_FACTORYSET
 
 /* Define own nand partitions */
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
index 46b1b41..cc32729 100644
--- a/include/configs/ti814x_evm.h
+++ b/include/configs/ti814x_evm.h
@@ -152,7 +152,6 @@
 #define CONFIG_BOOTP_DNS2
 #define CONFIG_BOOTP_SEND_HOSTNAME
 #define CONFIG_NET_RETRY_COUNT         10
-#define CONFIG_PHY_ET1011C
 #define CONFIG_PHY_ET1011C_TX_CLK_FIX
 
 #endif	/* ! __CONFIG_TI814X_EVM_H */
diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h
index 13b87e9..4c4a1a0 100644
--- a/include/configs/tqma6_wru4.h
+++ b/include/configs/tqma6_wru4.h
@@ -10,7 +10,6 @@
 #define CONFIG_FEC_XCV_TYPE		RMII
 #define CONFIG_ETHPRIME			"FEC"
 #define CONFIG_FEC_MXC_PHYADDR		0x01
-#define CONFIG_PHY_SMSC
 
 /* UART */
 #define CONFIG_MXC_UART_BASE		UART4_BASE
diff --git a/include/configs/ts4800.h b/include/configs/ts4800.h
index bd50d3b..e563f3f 100644
--- a/include/configs/ts4800.h
+++ b/include/configs/ts4800.h
@@ -50,7 +50,6 @@
 /*
  * Eth Configs
  */
-#define CONFIG_PHY_SMSC
 
 #define CONFIG_FEC_MXC
 #define IMX_FEC_BASE	        FEC_BASE_ADDR
diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h
index 9409344..e414f90 100644
--- a/include/configs/turris_mox.h
+++ b/include/configs/turris_mox.h
@@ -69,7 +69,6 @@
 #define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
 #define CONFIG_ARP_TIMEOUT	200
 #define CONFIG_NET_RETRY_COUNT	50
-#define CONFIG_PHY_MARVELL
 
 #define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3)
 
diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h
index 1d99dca..e006ad2 100644
--- a/include/configs/ulcb.h
+++ b/include/configs/ulcb.h
@@ -12,7 +12,6 @@
 #include "rcar-gen3-common.h"
 
 /* Ethernet RAVB */
-#define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 
 /* Generic Timer Definitions (use in assembler source) */
diff --git a/include/configs/vinco.h b/include/configs/vinco.h
index a709502..83ec78d 100644
--- a/include/configs/vinco.h
+++ b/include/configs/vinco.h
@@ -54,7 +54,6 @@
 /* USB device */
 
 /* Ethernet Hardware */
-#define CONFIG_PHY_SMSC
 #define CONFIG_MACB
 #define CONFIG_RMII
 #define CONFIG_NET_RETRY_COUNT		20
diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h
index 61d9c62..7120aa6 100644
--- a/include/configs/vining_2000.h
+++ b/include/configs/vining_2000.h
@@ -64,8 +64,6 @@
 #define CONFIG_FEC_XCV_TYPE             RMII
 #define CONFIG_ETHPRIME                 "FEC"
 
-#define CONFIG_PHY_ATHEROS
-
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS   0
diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h
new file mode 100644
index 0000000..8100e4d
--- /dev/null
+++ b/include/configs/vocore2.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Mauro Condarelli <mc5686@mclink.it>
+ */
+
+#ifndef __VOCORE2_CONFIG_H__
+#define __VOCORE2_CONFIG_H__
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	290000000
+
+/* RAM */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+
+/* SPL */
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SPL_BSS_START_ADDR	0x80010000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x10000
+#define CONFIG_SPL_MAX_SIZE		0x10000
+
+/* Dummy value */
+#define CONFIG_SYS_UBOOT_BASE		0
+
+/* Serial SPL */
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_CLK		40000000
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_COM3		0xb0000e00
+#define CONFIG_CONS_INDEX		3
+
+/* RAM */
+#define CONFIG_SYS_MEMTEST_START	0x80100000
+#define CONFIG_SYS_MEMTEST_END		0x80400000
+
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(128 * 1024)
+#define CONFIG_SYS_CBSIZE		512
+
+/* U-Boot */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+/* Environment settings */
+
+#endif //__VOCORE2_CONFIG_H__
diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h
index f73946b..54d211a 100644
--- a/include/configs/work_92105.h
+++ b/include/configs/work_92105.h
@@ -46,7 +46,6 @@
  * Ethernet Driver
  */
 
-#define CONFIG_PHY_SMSC
 #define CONFIG_LPC32XX_ETH
 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 /* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */
diff --git a/include/configs/x530.h b/include/configs/x530.h
index b6bff22..290e13d 100644
--- a/include/configs/x530.h
+++ b/include/configs/x530.h
@@ -60,7 +60,6 @@
 
 /* Environment in SPI NOR flash */
 
-#define CONFIG_PHY_MARVELL		/* there is a marvell phy */
 #define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
 
 /* PCIe support */
diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h
index dec5001..0c259a1 100644
--- a/include/configs/xilinx_versal.h
+++ b/include/configs/xilinx_versal.h
@@ -109,7 +109,8 @@
 #define BOOTENV_DEV_XSPI(devtypeu, devtypel, instance) \
 	"bootcmd_xspi0=sf probe 0 0 0 && " \
 	"sf read $scriptaddr $script_offset_f $script_size_f && " \
-	"source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0"
+	"echo XSPI: Trying to boot script at ${scriptaddr} && " \
+	"source ${scriptaddr}; echo XSPI: SCRIPT FAILED: continuing...;\0"
 
 #define BOOTENV_DEV_NAME_XSPI(devtypeu, devtypel, instance) \
 	"xspi "
@@ -117,7 +118,8 @@
 #define BOOT_TARGET_DEVICES_JTAG(func)	func(JTAG, jtag, na)
 
 #define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \
-	"bootcmd_jtag=source $scriptaddr; echo SCRIPT FAILED: continuing...;\0"
+	"bootcmd_jtag=echo JTAG: Trying to boot script at ${scriptaddr} && " \
+		"source ${scriptaddr}; echo JTAG: SCRIPT FAILED: continuing...;\0"
 
 #define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \
 	"jtag "
@@ -126,8 +128,10 @@
 
 #define BOOTENV_DEV_DFU_USB(devtypeu, devtypel, instance) \
 	"bootcmd_dfu_usb=setenv dfu_alt_info boot.scr ram $scriptaddr " \
-	"$script_size_f; dfu 0 ram 0 && source $scriptaddr; " \
-	"echo SCRIPT FAILED: continuing...;\0"
+	"$script_size_f; dfu 0 ram 0 && " \
+	"echo DFU: Trying to boot script at ${scriptaddr} && " \
+	"source ${scriptaddr}; " \
+	"echo DFU: SCRIPT FAILED: continuing...;\0"
 
 #define BOOTENV_DEV_NAME_DFU_USB(devtypeu, devtypel, instance) \
 	"dfu_usb "
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 0107383..eddc2b4 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -160,7 +160,8 @@
 #define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \
 	"bootcmd_" #devtypel #instance "=sf probe " #instance " 0 0 && " \
 		       "sf read $scriptaddr $script_offset_f $script_size_f && " \
-		       "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0"
+		       "echo QSPI: Trying to boot script at ${scriptaddr} && " \
+		       "source ${scriptaddr}; echo QSPI: SCRIPT FAILED: continuing...;\0"
 
 #define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \
 	#devtypel #instance " "
@@ -168,7 +169,8 @@
 #define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
 	"bootcmd_" #devtypel #instance "= nand info && " \
 		       "nand read $scriptaddr $script_offset_f $script_size_f && " \
-		       "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0"
+		       "echo NAND: Trying to boot script at ${scriptaddr} && " \
+		       "source ${scriptaddr}; echo NAND: SCRIPT FAILED: continuing...;\0"
 
 #define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
 	#devtypel #instance " "
@@ -176,7 +178,8 @@
 #define BOOT_TARGET_DEVICES_JTAG(func)	func(JTAG, jtag, na)
 
 #define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \
-	"bootcmd_jtag=source $scriptaddr; echo SCRIPT FAILED: continuing...;\0"
+	"bootcmd_jtag=echo JTAG: Trying to boot script at ${scriptaddr} && " \
+		"source ${scriptaddr}; echo JTAG: SCRIPT FAILED: continuing...;\0"
 
 #define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \
 	"jtag "
diff --git a/include/configs/xpress.h b/include/configs/xpress.h
index dbdd812..1bc46f6 100644
--- a/include/configs/xpress.h
+++ b/include/configs/xpress.h
@@ -67,7 +67,6 @@
 #define CONFIG_FEC_MXC_PHYADDR          0x0
 #define CONFIG_FEC_XCV_TYPE             RMII
 #define CONFIG_ETHPRIME			"FEC"
-#define CONFIG_PHY_SMSC
 
 #define CONFIG_IMX_THERMAL
 
diff --git a/include/configs/zc5202.h b/include/configs/zc5202.h
index 77ff047..7246b9e 100644
--- a/include/configs/zc5202.h
+++ b/include/configs/zc5202.h
@@ -20,7 +20,6 @@
 #define CONFIG_FEC_XCV_TYPE			MII100
 #define CONFIG_ETHPRIME				"FEC"
 #define CONFIG_FEC_MXC_PHYADDR			0
-#define CONFIG_MV88E6352_SWITCH
 
 #define CONFIG_PCI_SCAN_SHOW
 #define CONFIG_PCIE_IMX
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 1eaf65b..a93172b 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -152,7 +152,8 @@
 #define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \
 	"bootcmd_qspi=sf probe 0 0 0 && " \
 		      "sf read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \
-		      "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0"
+		      "echo QSPI: Trying to boot script at ${scriptaddr} && " \
+		      "source ${scriptaddr}; echo QSPI: SCRIPT FAILED: continuing...;\0"
 
 #define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \
 	"qspi "
@@ -160,7 +161,8 @@
 #define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
 	"bootcmd_nand=nand info && " \
 		      "nand read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \
-		      "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0"
+		      "echo NAND: Trying to boot script at ${scriptaddr} && " \
+		      "source ${scriptaddr}; echo NAND: SCRIPT FAILED: continuing...;\0"
 
 #define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
 	"nand "
@@ -168,7 +170,8 @@
 #define BOOTENV_DEV_NOR(devtypeu, devtypel, instance) \
 	"script_offset_nor=0xE2FC0000\0"        \
 	"bootcmd_nor=cp.b ${script_offset_nor} ${scriptaddr} ${script_size_f} && " \
-		     "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0"
+		     "echo NOR: Trying to boot script at ${scriptaddr} && " \
+		     "source ${scriptaddr}; echo NOR: SCRIPT FAILED: continuing...;\0"
 
 #define BOOTENV_DEV_NAME_NOR(devtypeu, devtypel, instance) \
 	"nor "
@@ -176,7 +179,8 @@
 #define BOOT_TARGET_DEVICES_JTAG(func)  func(JTAG, jtag, na)
 
 #define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \
-	"bootcmd_jtag=source $scriptaddr; echo SCRIPT FAILED: continuing...;\0"
+	"bootcmd_jtag=echo JTAG: Trying to boot script at ${scriptaddr} && " \
+		"source ${scriptaddr}; echo JTAG: SCRIPT FAILED: continuing...;\0"
 
 #define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \
 	"jtag "
@@ -198,7 +202,6 @@
 #ifndef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS	\
 	"fdt_high=0x20000000\0"		\
-	"initrd_high=0x20000000\0"	\
 	"scriptaddr=0x20000\0"	\
 	"script_size_f=0x40000\0"	\
 	"fdt_addr_r=0x1f00000\0"        \
diff --git a/include/dm/acpi.h b/include/dm/acpi.h
index 4925791..7563a4c 100644
--- a/include/dm/acpi.h
+++ b/include/dm/acpi.h
@@ -25,6 +25,24 @@
 #if !defined(__ACPI__)
 
 /**
+ * struct acpi_ctx - Context used for writing ACPI tables
+ *
+ * This contains a few useful pieces of information used when writing
+ *
+ * @current: Current address for writing
+ * @rsdp: Pointer to the Root System Description Pointer, typically used when
+ *	adding a new table. The RSDP holds pointers to the RSDT and XSDT.
+ * @rsdt: Pointer to the Root System Description Table
+ * @xsdt: Pointer to the Extended System Description Table
+ */
+struct acpi_ctx {
+	void *current;
+	struct acpi_rsdp *rsdp;
+	struct acpi_rsdt *rsdt;
+	struct acpi_xsdt *xsdt;
+};
+
+/**
  * struct acpi_ops - ACPI operations supported by driver model
  */
 struct acpi_ops {
@@ -38,6 +56,15 @@
 	 *	other error
 	 */
 	int (*get_name)(const struct udevice *dev, char *out_name);
+
+	/**
+	 * write_tables() - Write out any tables required by this device
+	 *
+	 * @dev: Device to write
+	 * @ctx: ACPI context to use
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*write_tables)(const struct udevice *dev, struct acpi_ctx *ctx);
 };
 
 #define device_get_acpi_ops(dev)	((dev)->driver->acpi_ops)
@@ -72,6 +99,16 @@
  */
 int acpi_copy_name(char *out_name, const char *name);
 
+/**
+ * acpi_write_dev_tables() - Write ACPI tables required by devices
+ *
+ * This scans through all devices and tells them to write any tables they want
+ * to write.
+ *
+ * @return 0 if OK, -ve if any device returned an error
+ */
+int acpi_write_dev_tables(struct acpi_ctx *ctx);
+
 #endif /* __ACPI__ */
 
 #endif
diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h
index 0837c1a..b0d65d7 100644
--- a/include/dt-bindings/clock/g12a-clkc.h
+++ b/include/dt-bindings/clock/g12a-clkc.h
@@ -143,5 +143,7 @@
 #define CLKID_CPU1_CLK				253
 #define CLKID_CPU2_CLK				254
 #define CLKID_CPU3_CLK				255
+#define CLKID_SPICC0_SCLK			258
+#define CLKID_SPICC1_SCLK			261
 
 #endif /* __G12A_CLKC_H */
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index db0763e..4073eb7 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -146,5 +146,6 @@
 #define CLKID_CTS_VDAC		201
 #define CLKID_HDMI_TX		202
 #define CLKID_HDMI		205
+#define CLKID_ACODEC		206
 
 #endif /* __GXBB_CLKC_H */
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
index 20641fa..c92ff1e 100644
--- a/include/dt-bindings/clock/r8a7790-clock.h
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -1,10 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
 /*
  * Copyright 2013 Ideas On Board SPRL
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
  */
 
 #ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h
index ef69213..bb4f18b 100644
--- a/include/dt-bindings/clock/r8a7791-clock.h
+++ b/include/dt-bindings/clock/r8a7791-clock.h
@@ -1,10 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
 /*
  * Copyright 2013 Ideas On Board SPRL
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
  */
 
 #ifndef __DT_BINDINGS_CLOCK_R8A7791_H__
diff --git a/include/dt-bindings/clock/r8a7792-clock.h b/include/dt-bindings/clock/r8a7792-clock.h
index 5be90bc..2948d9ce 100644
--- a/include/dt-bindings/clock/r8a7792-clock.h
+++ b/include/dt-bindings/clock/r8a7792-clock.h
@@ -1,10 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
 /*
  * Copyright (C) 2016 Cogent Embedded, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
  */
 
 #ifndef __DT_BINDINGS_CLOCK_R8A7792_H__
diff --git a/include/dt-bindings/clock/snps,hsdk-cgu.h b/include/dt-bindings/clock/snps,hsdk-cgu.h
index 2cfe34e..1ce7661 100644
--- a/include/dt-bindings/clock/snps,hsdk-cgu.h
+++ b/include/dt-bindings/clock/snps,hsdk-cgu.h
@@ -36,7 +36,8 @@
 #define CLK_TUN_TUN		21
 #define CLK_TUN_ROM		22
 #define CLK_TUN_PWM		23
-#define CLK_HDMI_PLL		24
-#define CLK_HDMI		25
+#define CLK_TUN_TIMER		24
+#define CLK_HDMI_PLL		25
+#define CLK_HDMI		26
 
 #endif /* __DT_BINDINGS_CLK_HSDK_CGU_H_ */
diff --git a/include/dt-bindings/power/r8a7790-sysc.h b/include/dt-bindings/power/r8a7790-sysc.h
index 6af4e99..bcb4905 100644
--- a/include/dt-bindings/power/r8a7790-sysc.h
+++ b/include/dt-bindings/power/r8a7790-sysc.h
@@ -1,9 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (C) 2016 Glider bvba
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
  */
 #ifndef __DT_BINDINGS_POWER_R8A7790_SYSC_H__
 #define __DT_BINDINGS_POWER_R8A7790_SYSC_H__
diff --git a/include/dt-bindings/power/r8a7791-sysc.h b/include/dt-bindings/power/r8a7791-sysc.h
index 1403baa..1d20fae 100644
--- a/include/dt-bindings/power/r8a7791-sysc.h
+++ b/include/dt-bindings/power/r8a7791-sysc.h
@@ -1,9 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (C) 2016 Glider bvba
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
  */
 #ifndef __DT_BINDINGS_POWER_R8A7791_SYSC_H__
 #define __DT_BINDINGS_POWER_R8A7791_SYSC_H__
diff --git a/include/dt-bindings/power/r8a7792-sysc.h b/include/dt-bindings/power/r8a7792-sysc.h
index 74f4a78..dd3a466 100644
--- a/include/dt-bindings/power/r8a7792-sysc.h
+++ b/include/dt-bindings/power/r8a7792-sysc.h
@@ -1,9 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (C) 2016 Cogent Embedded Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
  */
 #ifndef __DT_BINDINGS_POWER_R8A7792_SYSC_H__
 #define __DT_BINDINGS_POWER_R8A7792_SYSC_H__
diff --git a/include/dt-bindings/power/r8a7793-sysc.h b/include/dt-bindings/power/r8a7793-sysc.h
index b5693df3..056998c 100644
--- a/include/dt-bindings/power/r8a7793-sysc.h
+++ b/include/dt-bindings/power/r8a7793-sysc.h
@@ -1,9 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (C) 2016 Glider bvba
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
  */
 #ifndef __DT_BINDINGS_POWER_R8A7793_SYSC_H__
 #define __DT_BINDINGS_POWER_R8A7793_SYSC_H__
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 0ba9a1f..f92bfe5 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -11,6 +11,7 @@
 #include <common.h>
 #include <part_efi.h>
 #include <efi_api.h>
+#include <image.h>
 #include <pe.h>
 
 static inline int guidcmp(const void *g1, const void *g2)
@@ -47,6 +48,13 @@
 /* Root node */
 extern efi_handle_t efi_root;
 
+/* EFI system partition */
+extern struct efi_system_partition {
+	enum if_type if_type;
+	int devnum;
+	u8 part;
+} efi_system_partition;
+
 int __efi_entry_check(void);
 int __efi_exit_check(void);
 const char *__efi_nesting(void);
@@ -695,9 +703,6 @@
 unsigned long efi_serialize_load_option(struct efi_load_option *lo, u8 **data);
 efi_status_t efi_bootmgr_load(efi_handle_t *handle);
 
-#ifdef CONFIG_EFI_SECURE_BOOT
-#include <image.h>
-
 /**
  * efi_image_regions - A list of memory regions
  *
@@ -767,7 +772,6 @@
 
 bool efi_image_parse(void *efi, size_t len, struct efi_image_regions **regp,
 		     WIN_CERTIFICATE **auth, size_t *auth_len);
-#endif /* CONFIG_EFI_SECURE_BOOT */
 
 #else /* CONFIG_IS_ENABLED(EFI_LOADER) */
 
diff --git a/include/environment/distro/sf.h b/include/environment/distro/sf.h
new file mode 100644
index 0000000..e793be0
--- /dev/null
+++ b/include/environment/distro/sf.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Amarula Solutions(India)
+ *
+ * SF distro configurations.
+ */
+
+#ifndef __DISTRO_SF_CONFIG_H
+#define __DISTRO_SF_CONFIG_H
+
+#if CONFIG_IS_ENABLED(CMD_SF)
+#define BOOTENV_SHARED_SF(devtypel)				\
+	#devtypel "_boot=" 					\
+	"if " #devtypel " probe ${busnum}; then "		\
+		"devtype=" #devtypel "; "	  		\
+		"run scan_sf_for_scripts; "	  		\
+	"fi\0"
+#define BOOTENV_DEV_SF(devtypeu, devtypel, instance) 		\
+	"bootcmd_" #devtypel #instance "=" 			\
+		"busnum=" #instance "; " 			\
+		"run " #devtypel "_boot\0"
+#define BOOTENV_DEV_NAME_SF(devtypeu, devtypel, instance) 	\
+	#devtypel #instance " "
+#else
+#define BOOTENV_SHARED_SF(devtypel)
+#define BOOTENV_DEV_SF \
+	BOOT_TARGET_DEVICES_references_SF_without_CONFIG_CMD_SF
+#define BOOTENV_DEV_NAME_SF \
+	BOOT_TARGET_DEVICES_references_SF_without_CONFIG_CMD_SF
+
+#endif /* CONFIG_CMD_SF */
+
+#define BOOTENV_SF \
+	BOOTENV_SHARED_SF(sf) \
+	"scan_sf_for_scripts="					\
+		"${devtype} read ${scriptaddr} "		\
+			"${script_offset_f} ${script_size_f}; "	\
+		"source ${scriptaddr}; "			\
+		"echo SCRIPT FAILED: continuing...\0"
+
+#endif /* __DISTRO_SF_CONFIG_H */
diff --git a/include/fdt_region.h b/include/fdt_region.h
new file mode 100644
index 0000000..ff7a1cc
--- /dev/null
+++ b/include/fdt_region.h
@@ -0,0 +1,304 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef _FDT_REGION_H
+#define _FDT_REGION_H
+
+#ifndef SWIG /* Not available in Python */
+struct fdt_region {
+	int offset;
+	int size;
+};
+
+/*
+ * Flags for fdt_find_regions()
+ *
+ * Add a region for the string table (always the last region)
+ */
+#define FDT_REG_ADD_STRING_TAB		(1 << 0)
+
+/*
+ * Add all supernodes of a matching node/property, useful for creating a
+ * valid subset tree
+ */
+#define FDT_REG_SUPERNODES		(1 << 1)
+
+/* Add the FDT_BEGIN_NODE tags of subnodes, including their names */
+#define FDT_REG_DIRECT_SUBNODES	(1 << 2)
+
+/* Add all subnodes of a matching node */
+#define FDT_REG_ALL_SUBNODES		(1 << 3)
+
+/* Add a region for the mem_rsvmap table (always the first region) */
+#define FDT_REG_ADD_MEM_RSVMAP		(1 << 4)
+
+/* Indicates what an fdt part is (node, property, value) */
+#define FDT_IS_NODE			(1 << 0)
+#define FDT_IS_PROP			(1 << 1)
+#define FDT_IS_VALUE			(1 << 2)	/* not supported */
+#define FDT_IS_COMPAT			(1 << 3)	/* used internally */
+#define FDT_NODE_HAS_PROP		(1 << 4)	/* node contains prop */
+
+#define FDT_ANY_GLOBAL		(FDT_IS_NODE | FDT_IS_PROP | FDT_IS_VALUE | \
+					FDT_IS_COMPAT)
+#define FDT_IS_ANY			0x1f		/* all the above */
+
+/* We set a reasonable limit on the number of nested nodes */
+#define FDT_MAX_DEPTH			32
+
+/* Decribes what we want to include from the current tag */
+enum want_t {
+	WANT_NOTHING,
+	WANT_NODES_ONLY,		/* No properties */
+	WANT_NODES_AND_PROPS,		/* Everything for one level */
+	WANT_ALL_NODES_AND_PROPS	/* Everything for all levels */
+};
+
+/* Keeps track of the state at parent nodes */
+struct fdt_subnode_stack {
+	int offset;		/* Offset of node */
+	enum want_t want;	/* The 'want' value here */
+	int included;		/* 1 if we included this node, 0 if not */
+};
+
+struct fdt_region_ptrs {
+	int depth;			/* Current tree depth */
+	int done;			/* What we have completed scanning */
+	enum want_t want;		/* What we are currently including */
+	char *end;			/* Pointer to end of full node path */
+	int nextoffset;			/* Next node offset to check */
+};
+
+/* The state of our finding algortihm */
+struct fdt_region_state {
+	struct fdt_subnode_stack stack[FDT_MAX_DEPTH];	/* node stack */
+	struct fdt_region *region;	/* Contains list of regions found */
+	int count;			/* Numnber of regions found */
+	const void *fdt;		/* FDT blob */
+	int max_regions;		/* Maximum regions to find */
+	int can_merge;		/* 1 if we can merge with previous region */
+	int start;			/* Start position of current region */
+	struct fdt_region_ptrs ptrs;	/* Pointers for what we are up to */
+};
+
+/**
+ * fdt_find_regions() - find regions in device tree
+ *
+ * Given a list of nodes to include and properties to exclude, find
+ * the regions of the device tree which describe those included parts.
+ *
+ * The intent is to get a list of regions which will be invariant provided
+ * those parts are invariant. For example, if you request a list of regions
+ * for all nodes but exclude the property "data", then you will get the
+ * same region contents regardless of any change to "data" properties.
+ *
+ * This function can be used to produce a byte-stream to send to a hashing
+ * function to verify that critical parts of the FDT have not changed.
+ *
+ * Nodes which are given in 'inc' are included in the region list, as
+ * are the names of the immediate subnodes nodes (but not the properties
+ * or subnodes of those subnodes).
+ *
+ * For eaxample "/" means to include the root node, all root properties
+ * and the FDT_BEGIN_NODE and FDT_END_NODE of all subnodes of /. The latter
+ * ensures that we capture the names of the subnodes. In a hashing situation
+ * it prevents the root node from changing at all Any change to non-excluded
+ * properties, names of subnodes or number of subnodes would be detected.
+ *
+ * When used with FITs this provides the ability to hash and sign parts of
+ * the FIT based on different configurations in the FIT. Then it is
+ * impossible to change anything about that configuration (include images
+ * attached to the configuration), but it may be possible to add new
+ * configurations, new images or new signatures within the existing
+ * framework.
+ *
+ * Adding new properties to a device tree may result in the string table
+ * being extended (if the new property names are different from those
+ * already added). This function can optionally include a region for
+ * the string table so that this can be part of the hash too.
+ *
+ * The device tree header is not included in the list.
+ *
+ * @fdt:	Device tree to check
+ * @inc:	List of node paths to included
+ * @inc_count:	Number of node paths in list
+ * @exc_prop:	List of properties names to exclude
+ * @exc_prop_count:	Number of properties in exclude list
+ * @region:	Returns list of regions
+ * @max_region:	Maximum length of region list
+ * @path:	Pointer to a temporary string for the function to use for
+ *		building path names
+ * @path_len:	Length of path, must be large enough to hold the longest
+ *		path in the tree
+ * @add_string_tab:	1 to add a region for the string table
+ * @return number of regions in list. If this is >max_regions then the
+ * region array was exhausted. You should increase max_regions and try
+ * the call again.
+ */
+int fdt_find_regions(const void *fdt, char * const inc[], int inc_count,
+		     char * const exc_prop[], int exc_prop_count,
+		     struct fdt_region region[], int max_regions,
+		     char *path, int path_len, int add_string_tab);
+
+/**
+ * fdt_first_region() - find regions in device tree
+ *
+ * Given a nodes and properties to include and properties to exclude, find
+ * the regions of the device tree which describe those included parts.
+ *
+ * The use for this function is twofold. Firstly it provides a convenient
+ * way of performing a structure-aware grep of the tree. For example it is
+ * possible to grep for a node and get all the properties associated with
+ * that node. Trees can be subsetted easily, by specifying the nodes that
+ * are required, and then writing out the regions returned by this function.
+ * This is useful for small resource-constrained systems, such as boot
+ * loaders, which want to use an FDT but do not need to know about all of
+ * it.
+ *
+ * Secondly it makes it easy to hash parts of the tree and detect changes.
+ * The intent is to get a list of regions which will be invariant provided
+ * those parts are invariant. For example, if you request a list of regions
+ * for all nodes but exclude the property "data", then you will get the
+ * same region contents regardless of any change to "data" properties.
+ *
+ * This function can be used to produce a byte-stream to send to a hashing
+ * function to verify that critical parts of the FDT have not changed.
+ * Note that semantically null changes in order could still cause false
+ * hash misses. Such reordering might happen if the tree is regenerated
+ * from source, and nodes are reordered (the bytes-stream will be emitted
+ * in a different order and many hash functions will detect this). However
+ * if an existing tree is modified using libfdt functions, such as
+ * fdt_add_subnode() and fdt_setprop(), then this problem is avoided.
+ *
+ * The nodes/properties to include/exclude are defined by a function
+ * provided by the caller. This function is called for each node and
+ * property, and must return:
+ *
+ *    0 - to exclude this part
+ *    1 - to include this part
+ *   -1 - for FDT_IS_PROP only: no information is available, so include
+ *		if its containing node is included
+ *
+ * The last case is only used to deal with properties. Often a property is
+ * included if its containing node is included - this is the case where
+ * -1 is returned.. However if the property is specifically required to be
+ * included/excluded, then 0 or 1 can be returned. Note that including a
+ * property when the FDT_REG_SUPERNODES flag is given will force its
+ * containing node to be included since it is not valid to have a property
+ * that is not in a node.
+ *
+ * Using the information provided, the inclusion of a node can be controlled
+ * either by a node name or its compatible string, or any other property
+ * that the function can determine.
+ *
+ * As an example, including node "/" means to include the root node and all
+ * root properties. A flag provides a way of also including supernodes (of
+ * which there is none for the root node), and another flag includes
+ * immediate subnodes, so in this case we would get the FDT_BEGIN_NODE and
+ * FDT_END_NODE of all subnodes of /.
+ *
+ * The subnode feature helps in a hashing situation since it prevents the
+ * root node from changing at all. Any change to non-excluded properties,
+ * names of subnodes or number of subnodes would be detected.
+ *
+ * When used with FITs this provides the ability to hash and sign parts of
+ * the FIT based on different configurations in the FIT. Then it is
+ * impossible to change anything about that configuration (include images
+ * attached to the configuration), but it may be possible to add new
+ * configurations, new images or new signatures within the existing
+ * framework.
+ *
+ * Adding new properties to a device tree may result in the string table
+ * being extended (if the new property names are different from those
+ * already added). This function can optionally include a region for
+ * the string table so that this can be part of the hash too. This is always
+ * the last region.
+ *
+ * The FDT also has a mem_rsvmap table which can also be included, and is
+ * always the first region if so.
+ *
+ * The device tree header is not included in the region list. Since the
+ * contents of the FDT are changing (shrinking, often), the caller will need
+ * to regenerate the header anyway.
+ *
+ * @fdt:	Device tree to check
+ * @h_include:	Function to call to determine whether to include a part or
+ *		not:
+ *
+ *		@priv: Private pointer as passed to fdt_find_regions()
+ *		@fdt: Pointer to FDT blob
+ *		@offset: Offset of this node / property
+ *		@type: Type of this part, FDT_IS_...
+ *		@data: Pointer to data (node name, property name, compatible
+ *			string, value (not yet supported)
+ *		@size: Size of data, or 0 if none
+ *		@return 0 to exclude, 1 to include, -1 if no information is
+ *		available
+ * @priv:	Private pointer passed to h_include
+ * @region:	Returns list of regions, sorted by offset
+ * @max_regions: Maximum length of region list
+ * @path:	Pointer to a temporary string for the function to use for
+ *		building path names
+ * @path_len:	Length of path, must be large enough to hold the longest
+ *		path in the tree
+ * @flags:	Various flags that control the region algortihm, see
+ *		FDT_REG_...
+ * @return number of regions in list. If this is >max_regions then the
+ * region array was exhausted. You should increase max_regions and try
+ * the call again. Only the first max_regions elements are available in the
+ * array.
+ *
+ * On error a -ve value is return, which can be:
+ *
+ *	-FDT_ERR_BADSTRUCTURE (too deep or more END tags than BEGIN tags
+ *	-FDT_ERR_BADLAYOUT
+ *	-FDT_ERR_NOSPACE (path area is too small)
+ */
+int fdt_first_region(const void *fdt,
+		     int (*h_include)(void *priv, const void *fdt, int offset,
+				      int type, const char *data, int size),
+		     void *priv, struct fdt_region *region,
+		     char *path, int path_len, int flags,
+		     struct fdt_region_state *info);
+
+/** fdt_next_region() - find next region
+ *
+ * See fdt_first_region() for full description. This function finds the
+ * next region according to the provided parameters, which must be the same
+ * as passed to fdt_first_region().
+ *
+ * This function can additionally return -FDT_ERR_NOTFOUND when there are no
+ * more regions
+ */
+int fdt_next_region(const void *fdt,
+		    int (*h_include)(void *priv, const void *fdt, int offset,
+				     int type, const char *data, int size),
+		    void *priv, struct fdt_region *region,
+		    char *path, int path_len, int flags,
+		    struct fdt_region_state *info);
+
+/**
+ * fdt_add_alias_regions() - find aliases that point to existing regions
+ *
+ * Once a device tree grep is complete some of the nodes will be present
+ * and some will have been dropped. This function checks all the alias nodes
+ * to figure out which points point to nodes which are still present. These
+ * aliases need to be kept, along with the nodes they reference.
+ *
+ * Given a list of regions function finds the aliases that still apply and
+ * adds more regions to the list for these. This function is called after
+ * fdt_next_region() has finished returning regions and requires the same
+ * state.
+ *
+ * @fdt:	Device tree file to reference
+ * @region:	List of regions that will be kept
+ * @count:	Number of regions
+ * @max_regions: Number of entries that can fit in @region
+ * @info:	Region state as returned from fdt_next_region()
+ * @return new number of regions in @region (i.e. count + the number added)
+ * or -FDT_ERR_NOSPACE if there was not enough space.
+ */
+int fdt_add_alias_regions(const void *fdt, struct fdt_region *region, int count,
+			  int max_regions, struct fdt_region_state *info);
+#endif /* SWIG */
+
+#endif /* _FDT_REGION_H */
diff --git a/include/fsl_mdio.h b/include/fsl_mdio.h
index b87346c..8857d50 100644
--- a/include/fsl_mdio.h
+++ b/include/fsl_mdio.h
@@ -53,6 +53,7 @@
 		int regnum, u16 value);
 int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
 		int regnum);
+int memac_mdio_reset(struct mii_dev *bus);
 
 struct fsl_pq_mdio_info {
 	struct tsec_mii_mng __iomem *regs;
diff --git a/include/init.h b/include/init.h
index 9ef88c9..b5a167b 100644
--- a/include/init.h
+++ b/include/init.h
@@ -20,7 +20,7 @@
 #ifdef CONFIG_EFI_STUB
 #define ll_boot_init()	false
 #else
-#define ll_boot_init()	true
+#define ll_boot_init()	(!(gd->flags & GD_FLG_SKIP_LL_INIT))
 #endif
 
 /*
diff --git a/include/linux/libfdt.h b/include/linux/libfdt.h
index eeb2344..39dbc88 100644
--- a/include/linux/libfdt.h
+++ b/include/linux/libfdt.h
@@ -8,305 +8,6 @@
 #include "../../scripts/dtc/libfdt/libfdt.h"
 
 /* U-Boot local hacks */
-
-#ifndef SWIG /* Not available in Python */
-struct fdt_region {
-	int offset;
-	int size;
-};
-
-/*
- * Flags for fdt_find_regions()
- *
- * Add a region for the string table (always the last region)
- */
-#define FDT_REG_ADD_STRING_TAB		(1 << 0)
-
-/*
- * Add all supernodes of a matching node/property, useful for creating a
- * valid subset tree
- */
-#define FDT_REG_SUPERNODES		(1 << 1)
-
-/* Add the FDT_BEGIN_NODE tags of subnodes, including their names */
-#define FDT_REG_DIRECT_SUBNODES	(1 << 2)
-
-/* Add all subnodes of a matching node */
-#define FDT_REG_ALL_SUBNODES		(1 << 3)
-
-/* Add a region for the mem_rsvmap table (always the first region) */
-#define FDT_REG_ADD_MEM_RSVMAP		(1 << 4)
-
-/* Indicates what an fdt part is (node, property, value) */
-#define FDT_IS_NODE			(1 << 0)
-#define FDT_IS_PROP			(1 << 1)
-#define FDT_IS_VALUE			(1 << 2)	/* not supported */
-#define FDT_IS_COMPAT			(1 << 3)	/* used internally */
-#define FDT_NODE_HAS_PROP		(1 << 4)	/* node contains prop */
-
-#define FDT_ANY_GLOBAL		(FDT_IS_NODE | FDT_IS_PROP | FDT_IS_VALUE | \
-					FDT_IS_COMPAT)
-#define FDT_IS_ANY			0x1f		/* all the above */
-
-/* We set a reasonable limit on the number of nested nodes */
-#define FDT_MAX_DEPTH			32
-
-/* Decribes what we want to include from the current tag */
-enum want_t {
-	WANT_NOTHING,
-	WANT_NODES_ONLY,		/* No properties */
-	WANT_NODES_AND_PROPS,		/* Everything for one level */
-	WANT_ALL_NODES_AND_PROPS	/* Everything for all levels */
-};
-
-/* Keeps track of the state at parent nodes */
-struct fdt_subnode_stack {
-	int offset;		/* Offset of node */
-	enum want_t want;	/* The 'want' value here */
-	int included;		/* 1 if we included this node, 0 if not */
-};
-
-struct fdt_region_ptrs {
-	int depth;			/* Current tree depth */
-	int done;			/* What we have completed scanning */
-	enum want_t want;		/* What we are currently including */
-	char *end;			/* Pointer to end of full node path */
-	int nextoffset;			/* Next node offset to check */
-};
-
-/* The state of our finding algortihm */
-struct fdt_region_state {
-	struct fdt_subnode_stack stack[FDT_MAX_DEPTH];	/* node stack */
-	struct fdt_region *region;	/* Contains list of regions found */
-	int count;			/* Numnber of regions found */
-	const void *fdt;		/* FDT blob */
-	int max_regions;		/* Maximum regions to find */
-	int can_merge;		/* 1 if we can merge with previous region */
-	int start;			/* Start position of current region */
-	struct fdt_region_ptrs ptrs;	/* Pointers for what we are up to */
-};
-
-/**
- * fdt_find_regions() - find regions in device tree
- *
- * Given a list of nodes to include and properties to exclude, find
- * the regions of the device tree which describe those included parts.
- *
- * The intent is to get a list of regions which will be invariant provided
- * those parts are invariant. For example, if you request a list of regions
- * for all nodes but exclude the property "data", then you will get the
- * same region contents regardless of any change to "data" properties.
- *
- * This function can be used to produce a byte-stream to send to a hashing
- * function to verify that critical parts of the FDT have not changed.
- *
- * Nodes which are given in 'inc' are included in the region list, as
- * are the names of the immediate subnodes nodes (but not the properties
- * or subnodes of those subnodes).
- *
- * For eaxample "/" means to include the root node, all root properties
- * and the FDT_BEGIN_NODE and FDT_END_NODE of all subnodes of /. The latter
- * ensures that we capture the names of the subnodes. In a hashing situation
- * it prevents the root node from changing at all Any change to non-excluded
- * properties, names of subnodes or number of subnodes would be detected.
- *
- * When used with FITs this provides the ability to hash and sign parts of
- * the FIT based on different configurations in the FIT. Then it is
- * impossible to change anything about that configuration (include images
- * attached to the configuration), but it may be possible to add new
- * configurations, new images or new signatures within the existing
- * framework.
- *
- * Adding new properties to a device tree may result in the string table
- * being extended (if the new property names are different from those
- * already added). This function can optionally include a region for
- * the string table so that this can be part of the hash too.
- *
- * The device tree header is not included in the list.
- *
- * @fdt:	Device tree to check
- * @inc:	List of node paths to included
- * @inc_count:	Number of node paths in list
- * @exc_prop:	List of properties names to exclude
- * @exc_prop_count:	Number of properties in exclude list
- * @region:	Returns list of regions
- * @max_region:	Maximum length of region list
- * @path:	Pointer to a temporary string for the function to use for
- *		building path names
- * @path_len:	Length of path, must be large enough to hold the longest
- *		path in the tree
- * @add_string_tab:	1 to add a region for the string table
- * @return number of regions in list. If this is >max_regions then the
- * region array was exhausted. You should increase max_regions and try
- * the call again.
- */
-int fdt_find_regions(const void *fdt, char * const inc[], int inc_count,
-		     char * const exc_prop[], int exc_prop_count,
-		     struct fdt_region region[], int max_regions,
-		     char *path, int path_len, int add_string_tab);
-
-/**
- * fdt_first_region() - find regions in device tree
- *
- * Given a nodes and properties to include and properties to exclude, find
- * the regions of the device tree which describe those included parts.
- *
- * The use for this function is twofold. Firstly it provides a convenient
- * way of performing a structure-aware grep of the tree. For example it is
- * possible to grep for a node and get all the properties associated with
- * that node. Trees can be subsetted easily, by specifying the nodes that
- * are required, and then writing out the regions returned by this function.
- * This is useful for small resource-constrained systems, such as boot
- * loaders, which want to use an FDT but do not need to know about all of
- * it.
- *
- * Secondly it makes it easy to hash parts of the tree and detect changes.
- * The intent is to get a list of regions which will be invariant provided
- * those parts are invariant. For example, if you request a list of regions
- * for all nodes but exclude the property "data", then you will get the
- * same region contents regardless of any change to "data" properties.
- *
- * This function can be used to produce a byte-stream to send to a hashing
- * function to verify that critical parts of the FDT have not changed.
- * Note that semantically null changes in order could still cause false
- * hash misses. Such reordering might happen if the tree is regenerated
- * from source, and nodes are reordered (the bytes-stream will be emitted
- * in a different order and many hash functions will detect this). However
- * if an existing tree is modified using libfdt functions, such as
- * fdt_add_subnode() and fdt_setprop(), then this problem is avoided.
- *
- * The nodes/properties to include/exclude are defined by a function
- * provided by the caller. This function is called for each node and
- * property, and must return:
- *
- *    0 - to exclude this part
- *    1 - to include this part
- *   -1 - for FDT_IS_PROP only: no information is available, so include
- *		if its containing node is included
- *
- * The last case is only used to deal with properties. Often a property is
- * included if its containing node is included - this is the case where
- * -1 is returned.. However if the property is specifically required to be
- * included/excluded, then 0 or 1 can be returned. Note that including a
- * property when the FDT_REG_SUPERNODES flag is given will force its
- * containing node to be included since it is not valid to have a property
- * that is not in a node.
- *
- * Using the information provided, the inclusion of a node can be controlled
- * either by a node name or its compatible string, or any other property
- * that the function can determine.
- *
- * As an example, including node "/" means to include the root node and all
- * root properties. A flag provides a way of also including supernodes (of
- * which there is none for the root node), and another flag includes
- * immediate subnodes, so in this case we would get the FDT_BEGIN_NODE and
- * FDT_END_NODE of all subnodes of /.
- *
- * The subnode feature helps in a hashing situation since it prevents the
- * root node from changing at all. Any change to non-excluded properties,
- * names of subnodes or number of subnodes would be detected.
- *
- * When used with FITs this provides the ability to hash and sign parts of
- * the FIT based on different configurations in the FIT. Then it is
- * impossible to change anything about that configuration (include images
- * attached to the configuration), but it may be possible to add new
- * configurations, new images or new signatures within the existing
- * framework.
- *
- * Adding new properties to a device tree may result in the string table
- * being extended (if the new property names are different from those
- * already added). This function can optionally include a region for
- * the string table so that this can be part of the hash too. This is always
- * the last region.
- *
- * The FDT also has a mem_rsvmap table which can also be included, and is
- * always the first region if so.
- *
- * The device tree header is not included in the region list. Since the
- * contents of the FDT are changing (shrinking, often), the caller will need
- * to regenerate the header anyway.
- *
- * @fdt:	Device tree to check
- * @h_include:	Function to call to determine whether to include a part or
- *		not:
- *
- *		@priv: Private pointer as passed to fdt_find_regions()
- *		@fdt: Pointer to FDT blob
- *		@offset: Offset of this node / property
- *		@type: Type of this part, FDT_IS_...
- *		@data: Pointer to data (node name, property name, compatible
- *			string, value (not yet supported)
- *		@size: Size of data, or 0 if none
- *		@return 0 to exclude, 1 to include, -1 if no information is
- *		available
- * @priv:	Private pointer passed to h_include
- * @region:	Returns list of regions, sorted by offset
- * @max_regions: Maximum length of region list
- * @path:	Pointer to a temporary string for the function to use for
- *		building path names
- * @path_len:	Length of path, must be large enough to hold the longest
- *		path in the tree
- * @flags:	Various flags that control the region algortihm, see
- *		FDT_REG_...
- * @return number of regions in list. If this is >max_regions then the
- * region array was exhausted. You should increase max_regions and try
- * the call again. Only the first max_regions elements are available in the
- * array.
- *
- * On error a -ve value is return, which can be:
- *
- *	-FDT_ERR_BADSTRUCTURE (too deep or more END tags than BEGIN tags
- *	-FDT_ERR_BADLAYOUT
- *	-FDT_ERR_NOSPACE (path area is too small)
- */
-int fdt_first_region(const void *fdt,
-		     int (*h_include)(void *priv, const void *fdt, int offset,
-				      int type, const char *data, int size),
-		     void *priv, struct fdt_region *region,
-		     char *path, int path_len, int flags,
-		     struct fdt_region_state *info);
-
-/** fdt_next_region() - find next region
- *
- * See fdt_first_region() for full description. This function finds the
- * next region according to the provided parameters, which must be the same
- * as passed to fdt_first_region().
- *
- * This function can additionally return -FDT_ERR_NOTFOUND when there are no
- * more regions
- */
-int fdt_next_region(const void *fdt,
-		    int (*h_include)(void *priv, const void *fdt, int offset,
-				     int type, const char *data, int size),
-		    void *priv, struct fdt_region *region,
-		    char *path, int path_len, int flags,
-		    struct fdt_region_state *info);
-
-/**
- * fdt_add_alias_regions() - find aliases that point to existing regions
- *
- * Once a device tree grep is complete some of the nodes will be present
- * and some will have been dropped. This function checks all the alias nodes
- * to figure out which points point to nodes which are still present. These
- * aliases need to be kept, along with the nodes they reference.
- *
- * Given a list of regions function finds the aliases that still apply and
- * adds more regions to the list for these. This function is called after
- * fdt_next_region() has finished returning regions and requires the same
- * state.
- *
- * @fdt:	Device tree file to reference
- * @region:	List of regions that will be kept
- * @count:	Number of regions
- * @max_regions: Number of entries that can fit in @region
- * @info:	Region state as returned from fdt_next_region()
- * @return new number of regions in @region (i.e. count + the number added)
- * or -FDT_ERR_NOSPACE if there was not enough space.
- */
-int fdt_add_alias_regions(const void *fdt, struct fdt_region *region, int count,
-			  int max_regions, struct fdt_region_state *info);
-#endif /* SWIG */
-
 extern struct fdt_header *working_fdt;  /* Pointer to the working fdt */
 
 #endif /* _INCLUDE_LIBFDT_H_ */
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index ec144a0..233fdc3 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -22,6 +22,7 @@
 #define SNOR_MFR_INTEL		CFI_MFR_INTEL
 #define SNOR_MFR_ST		CFI_MFR_ST /* ST Micro <--> Micron */
 #define SNOR_MFR_MICRON		CFI_MFR_MICRON /* ST Micro <--> Micron */
+#define SNOR_MFR_ISSI		CFI_MFR_PMC
 #define SNOR_MFR_MACRONIX	CFI_MFR_MACRONIX
 #define SNOR_MFR_SPANSION	CFI_MFR_AMD
 #define SNOR_MFR_SST		CFI_MFR_SST
diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
index be01e1e..83eafb1 100644
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -204,6 +204,7 @@
 extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
 extern const struct spinand_manufacturer macronix_spinand_manufacturer;
 extern const struct spinand_manufacturer micron_spinand_manufacturer;
+extern const struct spinand_manufacturer toshiba_spinand_manufacturer;
 extern const struct spinand_manufacturer winbond_spinand_manufacturer;
 
 /**
diff --git a/include/netdev.h b/include/netdev.h
index 68a3fce..f2d21c4 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -125,6 +125,7 @@
 /*
  * Allow FEC to fine-tune MII configuration on boards which require this.
  */
+struct eth_device;
 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int));
 #endif
 
diff --git a/include/part.h b/include/part.h
index 0b5cf3d..3693527 100644
--- a/include/part.h
+++ b/include/part.h
@@ -51,13 +51,22 @@
 #define PART_TYPE_LEN 32
 #define MAX_SEARCH_PARTITIONS 64
 
+#define PART_BOOTABLE			((int)BIT(0))
+#define PART_EFI_SYSTEM_PARTITION	((int)BIT(1))
+
 typedef struct disk_partition {
 	lbaint_t	start;	/* # of first block in partition	*/
 	lbaint_t	size;	/* number of blocks in partition	*/
 	ulong	blksz;		/* block size in bytes			*/
 	uchar	name[PART_NAME_LEN];	/* partition name			*/
 	uchar	type[PART_TYPE_LEN];	/* string type description		*/
-	int	bootable;	/* Active/Bootable flag is set		*/
+	/*
+	 * The bootable is a bitmask with the following fields:
+	 *
+	 * PART_BOOTABLE		the MBR bootable flag is set
+	 * PART_EFI_SYSTEM_PARTITION	the partition is an EFI system partition
+	 */
+	int	bootable;
 #if CONFIG_IS_ENABLED(PARTITION_UUIDS)
 	char	uuid[UUID_STR_LEN + 1];	/* filesystem UUID as string, if exists	*/
 #endif
diff --git a/include/sdhci.h b/include/sdhci.h
index aa4378f..0ef8c2e 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -243,7 +243,6 @@
 #define SDHCI_QUIRK_BROKEN_HISPD_MODE	BIT(5)
 #define SDHCI_QUIRK_WAIT_SEND_CMD	(1 << 6)
 #define SDHCI_QUIRK_USE_WIDE8		(1 << 8)
-#define SDHCI_QUIRK_NO_1_8_V		(1 << 9)
 
 /* to make gcc happy */
 struct sdhci_host;
diff --git a/include/spi-mem.h b/include/spi-mem.h
index 36814ef..893f7bd 100644
--- a/include/spi-mem.h
+++ b/include/spi-mem.h
@@ -60,10 +60,12 @@
 /**
  * enum spi_mem_data_dir - describes the direction of a SPI memory data
  *			   transfer from the controller perspective
+ * @SPI_MEM_NO_DATA: no data transferred
  * @SPI_MEM_DATA_IN: data coming from the SPI memory
  * @SPI_MEM_DATA_OUT: data sent the SPI memory
  */
 enum spi_mem_data_dir {
+	SPI_MEM_NO_DATA,
 	SPI_MEM_DATA_IN,
 	SPI_MEM_DATA_OUT,
 };
diff --git a/include/spl.h b/include/spl.h
index 8b15cd4..6bf9fd8 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -224,6 +224,19 @@
 #define SPL_FIT_FOUND		2
 
 /**
+ * spl_load_legacy_img() - Loads a legacy image from a device.
+ * @spl_image:	Image description to set up
+ * @load:	Structure containing the information required to load data.
+ * @header:	Pointer to image header (including appended image)
+ *
+ * Reads an legacy image from the device. Loads u-boot image to
+ * specified load address.
+ * Returns 0 on success.
+ */
+int spl_load_legacy_img(struct spl_image_info *spl_image,
+			struct spl_load_info *load, ulong header);
+
+/**
  * spl_load_imx_container() - Loads a imx container image from a device.
  * @spl_image:	Image description to set up
  * @info:	Structure containing the information required to load data.
diff --git a/lib/Kconfig b/lib/Kconfig
index 144a54d..868de3b 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -434,6 +434,11 @@
 	  fast compression and decompression speed. It belongs to the LZ77
 	  family of byte-oriented compression schemes.
 
+config SPL_LZMA
+	bool "Enable LZMA decompression support for SPL build"
+	help
+	  This enables support for LZMA compression altorithm for SPL boot.
+
 config SPL_LZO
 	bool "Enable LZO decompression support in SPL"
 	help
diff --git a/lib/Makefile b/lib/Makefile
index ded9a93..c6f862b 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -67,6 +67,7 @@
 obj-$(CONFIG_$(SPL_)ZSTD) += zstd/
 obj-$(CONFIG_$(SPL_)GZIP) += gunzip.o
 obj-$(CONFIG_$(SPL_)LZO) += lzo/
+obj-$(CONFIG_$(SPL_)LZMA) += lzma/
 obj-$(CONFIG_$(SPL_)LZ4) += lz4_wrapper.o
 
 obj-$(CONFIG_LIBAVB) += libavb/
diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c
index 4633dcb..1c253af 100644
--- a/lib/acpi/acpi_table.c
+++ b/lib/acpi/acpi_table.c
@@ -6,12 +6,14 @@
  */
 
 #include <common.h>
-#include <acpi/acpi_table.h>
 #include <dm.h>
 #include <cpu.h>
+#include <mapmem.h>
+#include <tables_csum.h>
+#include <version.h>
+#include <acpi/acpi_table.h>
+#include <dm/acpi.h>
 
-/* Temporary change to ensure bisectability */
-#ifndef CONFIG_SANDBOX
 int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags)
 {
 	struct acpi_table_header *header = &dmar->header;
@@ -37,7 +39,6 @@
 
 	return 0;
 }
-#endif
 
 int acpi_get_table_revision(enum acpi_tables table)
 {
@@ -91,3 +92,173 @@
 		return -EINVAL;
 	}
 }
+
+void acpi_fill_header(struct acpi_table_header *header, char *signature)
+{
+	memcpy(header->signature, signature, 4);
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
+	header->oem_revision = U_BOOT_BUILD_DATE;
+	memcpy(header->aslc_id, ASLC_ID, 4);
+}
+
+void acpi_align(struct acpi_ctx *ctx)
+{
+	ctx->current = (void *)ALIGN((ulong)ctx->current, 16);
+}
+
+void acpi_align64(struct acpi_ctx *ctx)
+{
+	ctx->current = (void *)ALIGN((ulong)ctx->current, 64);
+}
+
+void acpi_inc(struct acpi_ctx *ctx, uint amount)
+{
+	ctx->current += amount;
+}
+
+void acpi_inc_align(struct acpi_ctx *ctx, uint amount)
+{
+	ctx->current += amount;
+	acpi_align(ctx);
+}
+
+/**
+ * Add an ACPI table to the RSDT (and XSDT) structure, recalculate length
+ * and checksum.
+ */
+int acpi_add_table(struct acpi_ctx *ctx, void *table)
+{
+	int i, entries_num;
+	struct acpi_rsdt *rsdt;
+	struct acpi_xsdt *xsdt;
+
+	/* The RSDT is mandatory while the XSDT is not */
+	rsdt = ctx->rsdt;
+
+	/* This should always be MAX_ACPI_TABLES */
+	entries_num = ARRAY_SIZE(rsdt->entry);
+
+	for (i = 0; i < entries_num; i++) {
+		if (rsdt->entry[i] == 0)
+			break;
+	}
+
+	if (i >= entries_num) {
+		log_err("ACPI: Error: too many tables\n");
+		return -E2BIG;
+	}
+
+	/* Add table to the RSDT */
+	rsdt->entry[i] = map_to_sysmem(table);
+
+	/* Fix RSDT length or the kernel will assume invalid entries */
+	rsdt->header.length = sizeof(struct acpi_table_header) +
+				(sizeof(u32) * (i + 1));
+
+	/* Re-calculate checksum */
+	rsdt->header.checksum = 0;
+	rsdt->header.checksum = table_compute_checksum((u8 *)rsdt,
+						       rsdt->header.length);
+
+	/*
+	 * And now the same thing for the XSDT. We use the same index as for
+	 * now we want the XSDT and RSDT to always be in sync in U-Boot
+	 */
+	xsdt = ctx->xsdt;
+
+	/* Add table to the XSDT */
+	xsdt->entry[i] = map_to_sysmem(table);
+
+	/* Fix XSDT length */
+	xsdt->header.length = sizeof(struct acpi_table_header) +
+				(sizeof(u64) * (i + 1));
+
+	/* Re-calculate checksum */
+	xsdt->header.checksum = 0;
+	xsdt->header.checksum = table_compute_checksum((u8 *)xsdt,
+						       xsdt->header.length);
+
+	return 0;
+}
+
+static void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt,
+			    struct acpi_xsdt *xsdt)
+{
+	memset(rsdp, 0, sizeof(struct acpi_rsdp));
+
+	memcpy(rsdp->signature, RSDP_SIG, 8);
+	memcpy(rsdp->oem_id, OEM_ID, 6);
+
+	rsdp->length = sizeof(struct acpi_rsdp);
+	rsdp->rsdt_address = map_to_sysmem(rsdt);
+
+	rsdp->xsdt_address = map_to_sysmem(xsdt);
+	rsdp->revision = ACPI_RSDP_REV_ACPI_2_0;
+
+	/* Calculate checksums */
+	rsdp->checksum = table_compute_checksum(rsdp, 20);
+	rsdp->ext_checksum = table_compute_checksum(rsdp,
+						    sizeof(struct acpi_rsdp));
+}
+
+static void acpi_write_rsdt(struct acpi_rsdt *rsdt)
+{
+	struct acpi_table_header *header = &rsdt->header;
+
+	/* Fill out header fields */
+	acpi_fill_header(header, "RSDT");
+	header->length = sizeof(struct acpi_rsdt);
+	header->revision = 1;
+
+	/* Entries are filled in later, we come with an empty set */
+
+	/* Fix checksum */
+	header->checksum = table_compute_checksum(rsdt,
+						  sizeof(struct acpi_rsdt));
+}
+
+static void acpi_write_xsdt(struct acpi_xsdt *xsdt)
+{
+	struct acpi_table_header *header = &xsdt->header;
+
+	/* Fill out header fields */
+	acpi_fill_header(header, "XSDT");
+	header->length = sizeof(struct acpi_xsdt);
+	header->revision = 1;
+
+	/* Entries are filled in later, we come with an empty set */
+
+	/* Fix checksum */
+	header->checksum = table_compute_checksum(xsdt,
+						  sizeof(struct acpi_xsdt));
+}
+
+void acpi_setup_base_tables(struct acpi_ctx *ctx, void *start)
+{
+	ctx->current = start;
+
+	/* Align ACPI tables to 16 byte */
+	acpi_align(ctx);
+	gd->arch.acpi_start = map_to_sysmem(ctx->current);
+
+	/* We need at least an RSDP and an RSDT Table */
+	ctx->rsdp = ctx->current;
+	acpi_inc_align(ctx, sizeof(struct acpi_rsdp));
+	ctx->rsdt = ctx->current;
+	acpi_inc_align(ctx, sizeof(struct acpi_rsdt));
+	ctx->xsdt = ctx->current;
+	acpi_inc_align(ctx, sizeof(struct acpi_xsdt));
+
+	/* clear all table memory */
+	memset((void *)start, '\0', ctx->current - start);
+
+	acpi_write_rsdp(ctx->rsdp, ctx->rsdt, ctx->xsdt);
+	acpi_write_rsdt(ctx->rsdt);
+	acpi_write_xsdt(ctx->xsdt);
+	/*
+	 * Per ACPI spec, the FACS table address must be aligned to a 64 byte
+	 * boundary (Windows checks this, but Linux does not).
+	 */
+	acpi_align64(ctx);
+}
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index fd8fe17..fd3df80 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -13,6 +13,8 @@
 #include <part.h>
 #include <malloc.h>
 
+struct efi_system_partition efi_system_partition;
+
 const efi_guid_t efi_block_io_guid = EFI_BLOCK_IO_PROTOCOL_GUID;
 
 /**
@@ -418,6 +420,24 @@
 	diskobj->ops.media = &diskobj->media;
 	if (disk)
 		*disk = diskobj;
+
+	/* Store first EFI system partition */
+	if (part && !efi_system_partition.if_type) {
+		int r;
+		disk_partition_t info;
+
+		r = part_get_info(desc, part, &info);
+		if (r)
+			return EFI_DEVICE_ERROR;
+		if (info.bootable & PART_EFI_SYSTEM_PARTITION) {
+			efi_system_partition.if_type = desc->if_type;
+			efi_system_partition.devnum = desc->devnum;
+			efi_system_partition.part = part;
+			EFI_PRINT("EFI system partition: %s %d:%d\n",
+				  blk_get_if_type_name(desc->if_type),
+				  desc->devnum, part);
+		}
+	}
 	return EFI_SUCCESS;
 }
 
diff --git a/lib/libfdt/Makefile b/lib/libfdt/Makefile
index 5d3ae4e..1fe50ec 100644
--- a/lib/libfdt/Makefile
+++ b/lib/libfdt/Makefile
@@ -3,9 +3,9 @@
 # (C) Copyright 2000-2007
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
-# Use upstream code.
 obj-y += \
 	fdt.o \
+	fdt_ro.o \
 	fdt_wip.o \
 	fdt_strerror.o \
 	fdt_sw.o \
@@ -15,12 +15,5 @@
 
 obj-$(CONFIG_OF_LIBFDT_OVERLAY) += fdt_overlay.o
 
-# Locally modified for U-Boot.
-# TODO: split out the local modifiction.
-obj-y += fdt_ro.o
-
-# U-Boot own file
-obj-y += fdt_region.o
-
 ccflags-y := -I$(srctree)/scripts/dtc/libfdt \
 	-DFDT_ASSUME_MASK=$(CONFIG_$(SPL_TPL_)OF_LIBFDT_ASSUME_MASK)
diff --git a/lib/libfdt/fdt_ro.c b/lib/libfdt/fdt_ro.c
index be03aea..7ede074 100644
--- a/lib/libfdt/fdt_ro.c
+++ b/lib/libfdt/fdt_ro.c
@@ -1,925 +1,2 @@
-// SPDX-License-Identifier: GPL-2.0+ OR BSD-2-Clause
-/*
- * libfdt - Flat Device Tree manipulation
- * Copyright (C) 2006 David Gibson, IBM Corporation.
- */
 #include <linux/libfdt_env.h>
-
-#ifndef USE_HOSTCC
-#include <fdt.h>
-#include <linux/libfdt.h>
-#else
-#include "fdt_host.h"
-#endif
-
-#include "libfdt_internal.h"
-
-static int fdt_nodename_eq_(const void *fdt, int offset,
-			    const char *s, int len)
-{
-	int olen;
-	const char *p = fdt_get_name(fdt, offset, &olen);
-
-	if (!p || (fdt_chk_extra() && olen < len))
-		/* short match */
-		return 0;
-
-	if (memcmp(p, s, len) != 0)
-		return 0;
-
-	if (p[len] == '\0')
-		return 1;
-	else if (!memchr(s, '@', len) && (p[len] == '@'))
-		return 1;
-	else
-		return 0;
-}
-
-const char *fdt_get_string(const void *fdt, int stroffset, int *lenp)
-{
-	int32_t totalsize;
-	uint32_t absoffset;
-	size_t len;
-	int err;
-	const char *s, *n;
-
-	if (!fdt_chk_extra()) {
-		s = (const char *)fdt + fdt_off_dt_strings(fdt) + stroffset;
-
-		if (lenp)
-			*lenp = strlen(s);
-		return s;
-	}
-	totalsize = fdt_ro_probe_(fdt);
-	err = totalsize;
-	if (totalsize < 0)
-		goto fail;
-
-	err = -FDT_ERR_BADOFFSET;
-	absoffset = stroffset + fdt_off_dt_strings(fdt);
-	if (absoffset >= totalsize)
-		goto fail;
-	len = totalsize - absoffset;
-
-	if (fdt_magic(fdt) == FDT_MAGIC) {
-		if (stroffset < 0)
-			goto fail;
-		if (!fdt_chk_version() || fdt_version(fdt) >= 17) {
-			if (stroffset >= fdt_size_dt_strings(fdt))
-				goto fail;
-			if ((fdt_size_dt_strings(fdt) - stroffset) < len)
-				len = fdt_size_dt_strings(fdt) - stroffset;
-		}
-	} else if (fdt_magic(fdt) == FDT_SW_MAGIC) {
-		if ((stroffset >= 0)
-		    || (stroffset < -fdt_size_dt_strings(fdt)))
-			goto fail;
-		if ((-stroffset) < len)
-			len = -stroffset;
-	} else {
-		err = -FDT_ERR_INTERNAL;
-		goto fail;
-	}
-
-	s = (const char *)fdt + absoffset;
-	n = memchr(s, '\0', len);
-	if (!n) {
-		/* missing terminating NULL */
-		err = -FDT_ERR_TRUNCATED;
-		goto fail;
-	}
-
-	if (lenp)
-		*lenp = n - s;
-	return s;
-
-fail:
-	if (lenp)
-		*lenp = err;
-	return NULL;
-}
-
-const char *fdt_string(const void *fdt, int stroffset)
-{
-	return fdt_get_string(fdt, stroffset, NULL);
-}
-
-static int fdt_string_eq_(const void *fdt, int stroffset,
-			  const char *s, int len)
-{
-	int slen;
-	const char *p = fdt_get_string(fdt, stroffset, &slen);
-
-	return p && (slen == len) && (memcmp(p, s, len) == 0);
-}
-
-int fdt_find_max_phandle(const void *fdt, uint32_t *phandle)
-{
-	uint32_t max = 0;
-	int offset = -1;
-
-	while (true) {
-		uint32_t value;
-
-		offset = fdt_next_node(fdt, offset, NULL);
-		if (offset < 0) {
-			if (offset == -FDT_ERR_NOTFOUND)
-				break;
-
-			return offset;
-		}
-
-		value = fdt_get_phandle(fdt, offset);
-
-		if (value > max)
-			max = value;
-	}
-
-	if (phandle)
-		*phandle = max;
-
-	return 0;
-}
-
-int fdt_generate_phandle(const void *fdt, uint32_t *phandle)
-{
-	uint32_t max;
-	int err;
-
-	err = fdt_find_max_phandle(fdt, &max);
-	if (err < 0)
-		return err;
-
-	if (max == FDT_MAX_PHANDLE)
-		return -FDT_ERR_NOPHANDLES;
-
-	if (phandle)
-		*phandle = max + 1;
-
-	return 0;
-}
-
-static const struct fdt_reserve_entry *fdt_mem_rsv(const void *fdt, int n)
-{
-	int offset = n * sizeof(struct fdt_reserve_entry);
-	int absoffset = fdt_off_mem_rsvmap(fdt) + offset;
-
-	if (fdt_chk_extra()) {
-		if (absoffset < fdt_off_mem_rsvmap(fdt))
-			return NULL;
-		if (absoffset > fdt_totalsize(fdt) -
-		    sizeof(struct fdt_reserve_entry))
-			return NULL;
-	}
-	return fdt_mem_rsv_(fdt, n);
-}
-
-int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size)
-{
-	const struct fdt_reserve_entry *re;
-
-	FDT_RO_PROBE(fdt);
-	re = fdt_mem_rsv(fdt, n);
-	if (fdt_chk_extra() && !re)
-		return -FDT_ERR_BADOFFSET;
-
-	*address = fdt64_to_cpu(re->address);
-	*size = fdt64_to_cpu(re->size);
-	return 0;
-}
-
-int fdt_num_mem_rsv(const void *fdt)
-{
-	int i;
-	const struct fdt_reserve_entry *re;
-
-	for (i = 0; (re = fdt_mem_rsv(fdt, i)) != NULL; i++) {
-		if (fdt64_to_cpu(re->size) == 0)
-			return i;
-	}
-	return -FDT_ERR_TRUNCATED;
-}
-
-static int nextprop_(const void *fdt, int offset)
-{
-	uint32_t tag;
-	int nextoffset;
-
-	do {
-		tag = fdt_next_tag(fdt, offset, &nextoffset);
-
-		switch (tag) {
-		case FDT_END:
-			if (nextoffset >= 0)
-				return -FDT_ERR_BADSTRUCTURE;
-			else
-				return nextoffset;
-
-		case FDT_PROP:
-			return offset;
-		}
-		offset = nextoffset;
-	} while (tag == FDT_NOP);
-
-	return -FDT_ERR_NOTFOUND;
-}
-
-int fdt_subnode_offset_namelen(const void *fdt, int offset,
-			       const char *name, int namelen)
-{
-	int depth;
-
-	FDT_RO_PROBE(fdt);
-
-	for (depth = 0;
-	     (offset >= 0) && (depth >= 0);
-	     offset = fdt_next_node(fdt, offset, &depth))
-		if ((depth == 1)
-		    && fdt_nodename_eq_(fdt, offset, name, namelen))
-			return offset;
-
-	if (depth < 0)
-		return -FDT_ERR_NOTFOUND;
-	return offset; /* error */
-}
-
-int fdt_subnode_offset(const void *fdt, int parentoffset,
-		       const char *name)
-{
-	return fdt_subnode_offset_namelen(fdt, parentoffset, name, strlen(name));
-}
-
-int fdt_path_offset_namelen(const void *fdt, const char *path, int namelen)
-{
-	const char *end = path + namelen;
-	const char *p = path;
-	int offset = 0;
-
-	FDT_RO_PROBE(fdt);
-
-	/* see if we have an alias */
-	if (*path != '/') {
-		const char *q = memchr(path, '/', end - p);
-
-		if (!q)
-			q = end;
-
-		p = fdt_get_alias_namelen(fdt, p, q - p);
-		if (!p)
-			return -FDT_ERR_BADPATH;
-		offset = fdt_path_offset(fdt, p);
-
-		p = q;
-	}
-
-	while (p < end) {
-		const char *q;
-
-		while (*p == '/') {
-			p++;
-			if (p == end)
-				return offset;
-		}
-		q = memchr(p, '/', end - p);
-		if (! q)
-			q = end;
-
-		offset = fdt_subnode_offset_namelen(fdt, offset, p, q-p);
-		if (offset < 0)
-			return offset;
-
-		p = q;
-	}
-
-	return offset;
-}
-
-int fdt_path_offset(const void *fdt, const char *path)
-{
-	return fdt_path_offset_namelen(fdt, path, strlen(path));
-}
-
-const char *fdt_get_name(const void *fdt, int nodeoffset, int *len)
-{
-	const struct fdt_node_header *nh = fdt_offset_ptr_(fdt, nodeoffset);
-	const char *nameptr;
-	int err;
-
-	if (fdt_chk_extra() &&
-	    (((err = fdt_ro_probe_(fdt)) < 0)
-	     || ((err = fdt_check_node_offset_(fdt, nodeoffset)) < 0)))
-		goto fail;
-
-	nameptr = nh->name;
-
-	if (fdt_chk_version() && fdt_version(fdt) < 0x10) {
-		/*
-		 * For old FDT versions, match the naming conventions of V16:
-		 * give only the leaf name (after all /). The actual tree
-		 * contents are loosely checked.
-		 */
-		const char *leaf;
-		leaf = strrchr(nameptr, '/');
-		if (leaf == NULL) {
-			err = -FDT_ERR_BADSTRUCTURE;
-			goto fail;
-		}
-		nameptr = leaf+1;
-	}
-
-	if (len)
-		*len = strlen(nameptr);
-
-	return nameptr;
-
- fail:
-	if (len)
-		*len = err;
-	return NULL;
-}
-
-int fdt_first_property_offset(const void *fdt, int nodeoffset)
-{
-	int offset;
-
-	if ((offset = fdt_check_node_offset_(fdt, nodeoffset)) < 0)
-		return offset;
-
-	return nextprop_(fdt, offset);
-}
-
-int fdt_next_property_offset(const void *fdt, int offset)
-{
-	if ((offset = fdt_check_prop_offset_(fdt, offset)) < 0)
-		return offset;
-
-	return nextprop_(fdt, offset);
-}
-
-static const struct fdt_property *fdt_get_property_by_offset_(const void *fdt,
-						              int offset,
-						              int *lenp)
-{
-	int err;
-	const struct fdt_property *prop;
-
-	if (fdt_chk_basic() && (err = fdt_check_prop_offset_(fdt, offset)) < 0) {
-		if (lenp)
-			*lenp = err;
-		return NULL;
-	}
-
-	prop = fdt_offset_ptr_(fdt, offset);
-
-	if (lenp)
-		*lenp = fdt32_to_cpu(prop->len);
-
-	return prop;
-}
-
-const struct fdt_property *fdt_get_property_by_offset(const void *fdt,
-						      int offset,
-						      int *lenp)
-{
-	/* Prior to version 16, properties may need realignment
-	 * and this API does not work. fdt_getprop_*() will, however. */
-
-	if (fdt_chk_version() && fdt_version(fdt) < 0x10) {
-		if (lenp)
-			*lenp = -FDT_ERR_BADVERSION;
-		return NULL;
-	}
-
-	return fdt_get_property_by_offset_(fdt, offset, lenp);
-}
-
-static const struct fdt_property *fdt_get_property_namelen_(const void *fdt,
-						            int offset,
-						            const char *name,
-						            int namelen,
-							    int *lenp,
-							    int *poffset)
-{
-	for (offset = fdt_first_property_offset(fdt, offset);
-	     (offset >= 0);
-	     (offset = fdt_next_property_offset(fdt, offset))) {
-		const struct fdt_property *prop;
-
-		prop = fdt_get_property_by_offset_(fdt, offset, lenp);
-		if (fdt_chk_extra() && !prop) {
-			offset = -FDT_ERR_INTERNAL;
-			break;
-		}
-		if (fdt_string_eq_(fdt, fdt32_to_cpu(prop->nameoff),
-				   name, namelen)) {
-			if (poffset)
-				*poffset = offset;
-			return prop;
-		}
-	}
-
-	if (lenp)
-		*lenp = offset;
-	return NULL;
-}
-
-
-const struct fdt_property *fdt_get_property_namelen(const void *fdt,
-						    int offset,
-						    const char *name,
-						    int namelen, int *lenp)
-{
-	/* Prior to version 16, properties may need realignment
-	 * and this API does not work. fdt_getprop_*() will, however. */
-	if (fdt_chk_version() && fdt_version(fdt) < 0x10) {
-		if (lenp)
-			*lenp = -FDT_ERR_BADVERSION;
-		return NULL;
-	}
-
-	return fdt_get_property_namelen_(fdt, offset, name, namelen, lenp,
-					 NULL);
-}
-
-
-const struct fdt_property *fdt_get_property(const void *fdt,
-					    int nodeoffset,
-					    const char *name, int *lenp)
-{
-	return fdt_get_property_namelen(fdt, nodeoffset, name,
-					strlen(name), lenp);
-}
-
-const void *fdt_getprop_namelen(const void *fdt, int nodeoffset,
-				const char *name, int namelen, int *lenp)
-{
-	int poffset;
-	const struct fdt_property *prop;
-
-	prop = fdt_get_property_namelen_(fdt, nodeoffset, name, namelen, lenp,
-					 &poffset);
-	if (!prop)
-		return NULL;
-
-	/* Handle realignment */
-	if (fdt_chk_version() && fdt_version(fdt) < 0x10 &&
-	    (poffset + sizeof(*prop)) % 8 && fdt32_to_cpu(prop->len) >= 8)
-		return prop->data + 4;
-	return prop->data;
-}
-
-const void *fdt_getprop_by_offset(const void *fdt, int offset,
-				  const char **namep, int *lenp)
-{
-	const struct fdt_property *prop;
-
-	prop = fdt_get_property_by_offset_(fdt, offset, lenp);
-	if (!prop)
-		return NULL;
-	if (namep) {
-		const char *name;
-		int namelen;
-
-		if (fdt_chk_extra()) {
-			name = fdt_get_string(fdt, fdt32_to_cpu(prop->nameoff),
-					      &namelen);
-			if (!name) {
-				if (lenp)
-					*lenp = namelen;
-				return NULL;
-			}
-			*namep = name;
-		} else {
-			*namep = fdt_string(fdt, fdt32_to_cpu(prop->nameoff));
-		}
-	}
-
-	/* Handle realignment */
-	if (fdt_chk_version() && fdt_version(fdt) < 0x10 &&
-	    (offset + sizeof(*prop)) % 8 && fdt32_to_cpu(prop->len) >= 8)
-		return prop->data + 4;
-	return prop->data;
-}
-
-const void *fdt_getprop(const void *fdt, int nodeoffset,
-			const char *name, int *lenp)
-{
-	return fdt_getprop_namelen(fdt, nodeoffset, name, strlen(name), lenp);
-}
-
-uint32_t fdt_get_phandle(const void *fdt, int nodeoffset)
-{
-	const fdt32_t *php;
-	int len;
-
-	/* FIXME: This is a bit sub-optimal, since we potentially scan
-	 * over all the properties twice. */
-	php = fdt_getprop(fdt, nodeoffset, "phandle", &len);
-	if (!php || (len != sizeof(*php))) {
-		php = fdt_getprop(fdt, nodeoffset, "linux,phandle", &len);
-		if (!php || (len != sizeof(*php)))
-			return 0;
-	}
-
-	return fdt32_to_cpu(*php);
-}
-
-const char *fdt_get_alias_namelen(const void *fdt,
-				  const char *name, int namelen)
-{
-	int aliasoffset;
-
-	aliasoffset = fdt_path_offset(fdt, "/aliases");
-	if (aliasoffset < 0)
-		return NULL;
-
-	return fdt_getprop_namelen(fdt, aliasoffset, name, namelen, NULL);
-}
-
-const char *fdt_get_alias(const void *fdt, const char *name)
-{
-	return fdt_get_alias_namelen(fdt, name, strlen(name));
-}
-
-int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen)
-{
-	int pdepth = 0, p = 0;
-	int offset, depth, namelen;
-	const char *name;
-
-	FDT_RO_PROBE(fdt);
-
-	if (buflen < 2)
-		return -FDT_ERR_NOSPACE;
-
-	for (offset = 0, depth = 0;
-	     (offset >= 0) && (offset <= nodeoffset);
-	     offset = fdt_next_node(fdt, offset, &depth)) {
-		while (pdepth > depth) {
-			do {
-				p--;
-			} while (buf[p-1] != '/');
-			pdepth--;
-		}
-
-		if (pdepth >= depth) {
-			name = fdt_get_name(fdt, offset, &namelen);
-			if (!name)
-				return namelen;
-			if ((p + namelen + 1) <= buflen) {
-				memcpy(buf + p, name, namelen);
-				p += namelen;
-				buf[p++] = '/';
-				pdepth++;
-			}
-		}
-
-		if (offset == nodeoffset) {
-			if (pdepth < (depth + 1))
-				return -FDT_ERR_NOSPACE;
-
-			if (p > 1) /* special case so that root path is "/", not "" */
-				p--;
-			buf[p] = '\0';
-			return 0;
-		}
-	}
-
-	if ((offset == -FDT_ERR_NOTFOUND) || (offset >= 0))
-		return -FDT_ERR_BADOFFSET;
-	else if (offset == -FDT_ERR_BADOFFSET)
-		return -FDT_ERR_BADSTRUCTURE;
-
-	return offset; /* error from fdt_next_node() */
-}
-
-int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset,
-				 int supernodedepth, int *nodedepth)
-{
-	int offset, depth;
-	int supernodeoffset = -FDT_ERR_INTERNAL;
-
-	FDT_RO_PROBE(fdt);
-
-	if (supernodedepth < 0)
-		return -FDT_ERR_NOTFOUND;
-
-	for (offset = 0, depth = 0;
-	     (offset >= 0) && (offset <= nodeoffset);
-	     offset = fdt_next_node(fdt, offset, &depth)) {
-		if (depth == supernodedepth)
-			supernodeoffset = offset;
-
-		if (offset == nodeoffset) {
-			if (nodedepth)
-				*nodedepth = depth;
-
-			if (supernodedepth > depth)
-				return -FDT_ERR_NOTFOUND;
-			else
-				return supernodeoffset;
-		}
-	}
-
-	if (fdt_chk_extra()) {
-		if ((offset == -FDT_ERR_NOTFOUND) || (offset >= 0))
-			return -FDT_ERR_BADOFFSET;
-		else if (offset == -FDT_ERR_BADOFFSET)
-			return -FDT_ERR_BADSTRUCTURE;
-	}
-
-	return offset; /* error from fdt_next_node() */
-}
-
-int fdt_node_depth(const void *fdt, int nodeoffset)
-{
-	int nodedepth;
-	int err;
-
-	err = fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, &nodedepth);
-	if (err)
-		return (!fdt_chk_extra() || err < 0) ? err : -FDT_ERR_INTERNAL;
-	return nodedepth;
-}
-
-int fdt_parent_offset(const void *fdt, int nodeoffset)
-{
-	int nodedepth = fdt_node_depth(fdt, nodeoffset);
-
-	if (nodedepth < 0)
-		return nodedepth;
-	return fdt_supernode_atdepth_offset(fdt, nodeoffset,
-					    nodedepth - 1, NULL);
-}
-
-int fdt_node_offset_by_prop_value(const void *fdt, int startoffset,
-				  const char *propname,
-				  const void *propval, int proplen)
-{
-	int offset;
-	const void *val;
-	int len;
-
-	FDT_RO_PROBE(fdt);
-
-	/* FIXME: The algorithm here is pretty horrible: we scan each
-	 * property of a node in fdt_getprop(), then if that didn't
-	 * find what we want, we scan over them again making our way
-	 * to the next node.  Still it's the easiest to implement
-	 * approach; performance can come later. */
-	for (offset = fdt_next_node(fdt, startoffset, NULL);
-	     offset >= 0;
-	     offset = fdt_next_node(fdt, offset, NULL)) {
-		val = fdt_getprop(fdt, offset, propname, &len);
-		if (val && (len == proplen)
-		    && (memcmp(val, propval, len) == 0))
-			return offset;
-	}
-
-	return offset; /* error from fdt_next_node() */
-}
-
-int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle)
-{
-	int offset;
-
-	if ((phandle == 0) || (phandle == -1))
-		return -FDT_ERR_BADPHANDLE;
-
-	FDT_RO_PROBE(fdt);
-
-	/* FIXME: The algorithm here is pretty horrible: we
-	 * potentially scan each property of a node in
-	 * fdt_get_phandle(), then if that didn't find what
-	 * we want, we scan over them again making our way to the next
-	 * node.  Still it's the easiest to implement approach;
-	 * performance can come later. */
-	for (offset = fdt_next_node(fdt, -1, NULL);
-	     offset >= 0;
-	     offset = fdt_next_node(fdt, offset, NULL)) {
-		if (fdt_get_phandle(fdt, offset) == phandle)
-			return offset;
-	}
-
-	return offset; /* error from fdt_next_node() */
-}
-
-int fdt_stringlist_contains(const char *strlist, int listlen, const char *str)
-{
-	int len = strlen(str);
-	const char *p;
-
-	while (listlen >= len) {
-		if (memcmp(str, strlist, len+1) == 0)
-			return 1;
-		p = memchr(strlist, '\0', listlen);
-		if (!p)
-			return 0; /* malformed strlist.. */
-		listlen -= (p-strlist) + 1;
-		strlist = p + 1;
-	}
-	return 0;
-}
-
-int fdt_stringlist_count(const void *fdt, int nodeoffset, const char *property)
-{
-	const char *list, *end;
-	int length, count = 0;
-
-	list = fdt_getprop(fdt, nodeoffset, property, &length);
-	if (!list)
-		return length;
-
-	end = list + length;
-
-	while (list < end) {
-		length = strnlen(list, end - list) + 1;
-
-		/* Abort if the last string isn't properly NUL-terminated. */
-		if (list + length > end)
-			return -FDT_ERR_BADVALUE;
-
-		list += length;
-		count++;
-	}
-
-	return count;
-}
-
-int fdt_stringlist_search(const void *fdt, int nodeoffset, const char *property,
-			  const char *string)
-{
-	int length, len, idx = 0;
-	const char *list, *end;
-
-	list = fdt_getprop(fdt, nodeoffset, property, &length);
-	if (!list)
-		return length;
-
-	len = strlen(string) + 1;
-	end = list + length;
-
-	while (list < end) {
-		length = strnlen(list, end - list) + 1;
-
-		/* Abort if the last string isn't properly NUL-terminated. */
-		if (list + length > end)
-			return -FDT_ERR_BADVALUE;
-
-		if (length == len && memcmp(list, string, length) == 0)
-			return idx;
-
-		list += length;
-		idx++;
-	}
-
-	return -FDT_ERR_NOTFOUND;
-}
-
-const char *fdt_stringlist_get(const void *fdt, int nodeoffset,
-			       const char *property, int idx,
-			       int *lenp)
-{
-	const char *list, *end;
-	int length;
-
-	list = fdt_getprop(fdt, nodeoffset, property, &length);
-	if (!list) {
-		if (lenp)
-			*lenp = length;
-
-		return NULL;
-	}
-
-	end = list + length;
-
-	while (list < end) {
-		length = strnlen(list, end - list) + 1;
-
-		/* Abort if the last string isn't properly NUL-terminated. */
-		if (list + length > end) {
-			if (lenp)
-				*lenp = -FDT_ERR_BADVALUE;
-
-			return NULL;
-		}
-
-		if (idx == 0) {
-			if (lenp)
-				*lenp = length - 1;
-
-			return list;
-		}
-
-		list += length;
-		idx--;
-	}
-
-	if (lenp)
-		*lenp = -FDT_ERR_NOTFOUND;
-
-	return NULL;
-}
-
-int fdt_node_check_compatible(const void *fdt, int nodeoffset,
-			      const char *compatible)
-{
-	const void *prop;
-	int len;
-
-	prop = fdt_getprop(fdt, nodeoffset, "compatible", &len);
-	if (!prop)
-		return len;
-
-	return !fdt_stringlist_contains(prop, len, compatible);
-}
-
-int fdt_node_offset_by_compatible(const void *fdt, int startoffset,
-				  const char *compatible)
-{
-	int offset, err;
-
-	FDT_RO_PROBE(fdt);
-
-	/* FIXME: The algorithm here is pretty horrible: we scan each
-	 * property of a node in fdt_node_check_compatible(), then if
-	 * that didn't find what we want, we scan over them again
-	 * making our way to the next node.  Still it's the easiest to
-	 * implement approach; performance can come later. */
-	for (offset = fdt_next_node(fdt, startoffset, NULL);
-	     offset >= 0;
-	     offset = fdt_next_node(fdt, offset, NULL)) {
-		err = fdt_node_check_compatible(fdt, offset, compatible);
-		if ((err < 0) && (err != -FDT_ERR_NOTFOUND))
-			return err;
-		else if (err == 0)
-			return offset;
-	}
-
-	return offset; /* error from fdt_next_node() */
-}
-
-#if !defined(CHECK_LEVEL) || CHECK_LEVEL > 0
-int fdt_check_full(const void *fdt, size_t bufsize)
-{
-	int err;
-	int num_memrsv;
-	int offset, nextoffset = 0;
-	uint32_t tag;
-	unsigned depth = 0;
-	const void *prop;
-	const char *propname;
-
-	if (bufsize < FDT_V1_SIZE)
-		return -FDT_ERR_TRUNCATED;
-	err = fdt_check_header(fdt);
-	if (err != 0)
-		return err;
-	if (bufsize < fdt_totalsize(fdt))
-		return -FDT_ERR_TRUNCATED;
-
-	num_memrsv = fdt_num_mem_rsv(fdt);
-	if (num_memrsv < 0)
-		return num_memrsv;
-
-	while (1) {
-		offset = nextoffset;
-		tag = fdt_next_tag(fdt, offset, &nextoffset);
-
-		if (nextoffset < 0)
-			return nextoffset;
-
-		switch (tag) {
-		case FDT_NOP:
-			break;
-
-		case FDT_END:
-			if (depth != 0)
-				return -FDT_ERR_BADSTRUCTURE;
-			return 0;
-
-		case FDT_BEGIN_NODE:
-			depth++;
-			if (depth > INT_MAX)
-				return -FDT_ERR_BADSTRUCTURE;
-			break;
-
-		case FDT_END_NODE:
-			if (depth == 0)
-				return -FDT_ERR_BADSTRUCTURE;
-			depth--;
-			break;
-
-		case FDT_PROP:
-			prop = fdt_getprop_by_offset(fdt, offset, &propname,
-						     &err);
-			if (!prop)
-				return err;
-			break;
-
-		default:
-			return -FDT_ERR_INTERNAL;
-		}
-	}
-}
-#endif
+#include "../../scripts/dtc/libfdt/fdt_ro.c"
diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
index 1138c70..8fc7e48 100644
--- a/lib/tiny-printf.c
+++ b/lib/tiny-printf.c
@@ -242,6 +242,7 @@
 				goto abort;
 			case 'u':
 			case 'd':
+			case 'i':
 				div = 1000000000;
 				if (islong) {
 					num = va_arg(va, unsigned long);
@@ -251,7 +252,7 @@
 					num = va_arg(va, unsigned int);
 				}
 
-				if (ch == 'd') {
+				if (ch != 'u') {
 					if (islong && (long)num < 0) {
 						num = -(long)num;
 						out(info, '-');
diff --git a/lib/zlib/trees.c b/lib/zlib/trees.c
index a0078d0..3e09517 100644
--- a/lib/zlib/trees.c
+++ b/lib/zlib/trees.c
@@ -7,27 +7,28 @@
 /*
  *  ALGORITHM
  *
- *      The "deflation" process uses several Huffman trees. The more
- *      common source values are represented by shorter bit sequences.
+ *	The "deflation" process uses several Huffman trees. The more
+ *	common source values are represented by shorter bit sequences.
  *
- *      Each code tree is stored in a compressed form which is itself
- * a Huffman encoding of the lengths of all the code strings (in
- * ascending order by source values).  The actual code strings are
- * reconstructed from the lengths in the inflate process, as described
- * in the deflate specification.
+ *	Each code tree is stored in a compressed form which is itself
+ *	a Huffman encoding of the lengths of all the code strings (in
+ *	ascending order by source values). The actual code strings are
+ *	reconstructed from the lengths in the inflate process, as
+ *	described in the deflate specification.
  *
  *  REFERENCES
  *
- *      Deutsch, L.P.,"'Deflate' Compressed Data Format Specification".
- *      Available in ftp.uu.net:/pub/archiving/zip/doc/deflate-1.1.doc
+ *	Deutsch, P.
+ *	    RFC 1951, DEFLATE Compressed Data Format Specification version 1.3
+ *	    https://tools.ietf.org/html/rfc1951, 1996
  *
- *      Storer, James A.
- *          Data Compression:  Methods and Theory, pp. 49-50.
- *          Computer Science Press, 1988.  ISBN 0-7167-8156-5.
+ *	Storer, James A.
+ *	    Data Compression:  Methods and Theory, pp. 49-50.
+ *	    Computer Science Press, 1988.  ISBN 0-7167-8156-5.
  *
- *      Sedgewick, R.
- *          Algorithms, p290.
- *          Addison-Wesley, 1983. ISBN 0-201-06672-6.
+ *	Sedgewick, R.
+ *	    Algorithms, p290.
+ *	    Addison-Wesley, 1983. ISBN 0-201-06672-6.
  */
 
 /* @(#) $Id$ */
diff --git a/net/Kconfig b/net/Kconfig
index 96bbce1..ac6d0cf 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -44,5 +44,9 @@
 	default 1468
 	help
 	  Default TFTP block size.
+	  The MTU is typically 1500 for ethernet, so a TFTP block of
+	  1468 (MTU minus eth.hdrs) provides a good throughput with
+	  almost-MTU block sizes.
+	  You can also activate CONFIG_IP_DEFRAG to set a larger block.
 
 endif   # if NET
diff --git a/net/tftp.c b/net/tftp.c
index 585eb6e..be24e63 100644
--- a/net/tftp.c
+++ b/net/tftp.c
@@ -133,14 +133,9 @@
  * almost-MTU block sizes.  At least try... fall back to 512 if need be.
  * (but those using CONFIG_IP_DEFRAG may want to set a larger block in cfg file)
  */
-#ifdef CONFIG_TFTP_BLOCKSIZE
-#define TFTP_MTU_BLOCKSIZE CONFIG_TFTP_BLOCKSIZE
-#else
-#define TFTP_MTU_BLOCKSIZE 1468
-#endif
 
 static unsigned short tftp_block_size = TFTP_BLOCK_SIZE;
-static unsigned short tftp_block_size_option = TFTP_MTU_BLOCKSIZE;
+static unsigned short tftp_block_size_option = CONFIG_TFTP_BLOCKSIZE;
 
 static inline int store_block(int block, uchar *src, unsigned int len)
 {
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 4c2c056..6741ef9 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -22,6 +22,8 @@
 -include include/config/auto.conf
 -include $(obj)/include/autoconf.mk
 
+UBOOTINCLUDE := -I$(obj)/include $(UBOOTINCLUDE)
+
 KBUILD_CPPFLAGS += -DCONFIG_SPL_BUILD
 ifeq ($(CONFIG_TPL_BUILD),y)
 KBUILD_CPPFLAGS += -DCONFIG_TPL_BUILD
@@ -311,7 +313,7 @@
 
 targets += $(obj)/dts/dt-platdata.o
 $(obj)/dts/dt-platdata.o: $(obj)/dts/dt-platdata.c \
-		include/generated/dt-structs-gen.h FORCE
+		include/generated/dt-structs-gen.h prepare FORCE
 	$(call if_changed,plat)
 
 PHONY += dts_dir
@@ -422,9 +424,13 @@
 $(sort $(u-boot-spl-init) $(u-boot-spl-main)): $(u-boot-spl-dirs) ;
 
 PHONY += $(u-boot-spl-dirs)
-$(u-boot-spl-dirs): $(u-boot-spl-platdata)
+$(u-boot-spl-dirs): $(u-boot-spl-platdata) prepare
 	$(Q)$(MAKE) $(build)=$@
 
+PHONY += prepare
+prepare:
+	$(Q)$(MAKE) $(build)=$(obj)/.
+
 quiet_cmd_cpp_lds = LDS     $@
 cmd_cpp_lds = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) -ansi \
 		-D__ASSEMBLY__ -x assembler-with-cpp -std=c99 -P -o $@ $<
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 6908431..19c9218 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -22,7 +22,6 @@
 CONFIG_ALTERA_SPI_IDLE_VAL
 CONFIG_ALTIVEC
 CONFIG_ALU
-CONFIG_AM335X_LCD
 CONFIG_AM335X_USB0
 CONFIG_AM335X_USB0_MODE
 CONFIG_AM335X_USB1
@@ -165,7 +164,6 @@
 CONFIG_BUFNO_AUTO_INCR_BIT
 CONFIG_BUILD_ENVCRC
 CONFIG_BUS_WIDTH
-CONFIG_BZIP2
 CONFIG_CALXEDA_XGMAC
 CONFIG_CDP_APPLIANCE_VLAN_TYPE
 CONFIG_CDP_CAPABILITIES
@@ -1190,7 +1188,6 @@
 CONFIG_NAND_KMETER1
 CONFIG_NAND_LPC32XX_MLC
 CONFIG_NAND_MODE_REG
-CONFIG_NAND_MXC_V1_1
 CONFIG_NAND_OMAP_ECCSCHEME
 CONFIG_NAND_OMAP_GPMC_WSCFG
 CONFIG_NAND_SECBOOT
@@ -1295,8 +1292,6 @@
 CONFIG_PCI_SYS_PHYS
 CONFIG_PCI_SYS_SIZE
 CONFIG_PCNET
-CONFIG_PCNET_79C973
-CONFIG_PCNET_79C975
 CONFIG_PEN_ADDR_BIG_ENDIAN
 CONFIG_PERIF1_FREQ
 CONFIG_PERIF2_FREQ
@@ -1773,7 +1768,6 @@
 CONFIG_SYS_AMASK5
 CONFIG_SYS_AMASK6
 CONFIG_SYS_AMASK7
-CONFIG_SYS_ARM_CACHE_WRITETHROUGH
 CONFIG_SYS_AT91_CPU_NAME
 CONFIG_SYS_AT91_MAIN_CLOCK
 CONFIG_SYS_AT91_PLLA
@@ -4081,9 +4075,6 @@
 CONFIG_TSEC_TBI
 CONFIG_TSEC_TBICR_SETTINGS
 CONFIG_TULIP
-CONFIG_TULIP_FIX_DAVICOM
-CONFIG_TULIP_SELECT_MEDIA
-CONFIG_TULIP_USE_IO
 CONFIG_TWL6030_INPUT
 CONFIG_TWL6030_POWER
 CONFIG_TWR
diff --git a/test/dm/acpi.c b/test/dm/acpi.c
index e7b8abd..176d207 100644
--- a/test/dm/acpi.c
+++ b/test/dm/acpi.c
@@ -7,13 +7,36 @@
  */
 
 #include <common.h>
+#include <console.h>
 #include <dm.h>
+#include <malloc.h>
+#include <mapmem.h>
+#include <version.h>
+#include <tables_csum.h>
+#include <version.h>
 #include <acpi/acpi_table.h>
 #include <dm/acpi.h>
 #include <dm/test.h>
 #include <test/ut.h>
 
 #define ACPI_TEST_DEV_NAME	"ABCD"
+#define BUF_SIZE		4096
+
+static int testacpi_write_tables(const struct udevice *dev,
+				 struct acpi_ctx *ctx)
+{
+	struct acpi_dmar *dmar;
+	int ret;
+
+	dmar = (struct acpi_dmar *)ctx->current;
+	acpi_create_dmar(dmar, DMAR_INTR_REMAP);
+	ctx->current += sizeof(struct acpi_dmar);
+	ret = acpi_add_table(ctx, dmar);
+	if (ret)
+		return log_msg_ret("add", ret);
+
+	return 0;
+}
 
 static int testacpi_get_name(const struct udevice *dev, char *out_name)
 {
@@ -22,6 +45,7 @@
 
 struct acpi_ops testacpi_ops = {
 	.get_name	= testacpi_get_name,
+	.write_tables	= testacpi_write_tables,
 };
 
 static const struct udevice_id testacpi_ids[] = {
@@ -68,8 +92,6 @@
 DM_TEST(dm_test_acpi_get_table_revision,
 	DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
 
-/* Temporary change to ensure bisectability */
-#ifndef CONFIG_SANDBOX
 /* Test acpi_create_dmar() */
 static int dm_test_acpi_create_dmar(struct unit_test_state *uts)
 {
@@ -82,4 +104,214 @@
 	return 0;
 }
 DM_TEST(dm_test_acpi_create_dmar, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
-#endif
+
+/* Test acpi_fill_header() */
+static int dm_test_acpi_fill_header(struct unit_test_state *uts)
+{
+	struct acpi_table_header hdr;
+
+	/* Make sure these 5 fields are not changed */
+	hdr.length = 0x11;
+	hdr.revision = 0x22;
+	hdr.checksum = 0x33;
+	hdr.aslc_revision = 0x44;
+	acpi_fill_header(&hdr, "ABCD");
+
+	ut_asserteq_mem("ABCD", hdr.signature, sizeof(hdr.signature));
+	ut_asserteq(0x11, hdr.length);
+	ut_asserteq(0x22, hdr.revision);
+	ut_asserteq(0x33, hdr.checksum);
+	ut_asserteq_mem(OEM_ID, hdr.oem_id, sizeof(hdr.oem_id));
+	ut_asserteq_mem(OEM_TABLE_ID, hdr.oem_table_id,
+			sizeof(hdr.oem_table_id));
+	ut_asserteq(U_BOOT_BUILD_DATE, hdr.oem_revision);
+	ut_asserteq_mem(ASLC_ID, hdr.aslc_id, sizeof(hdr.aslc_id));
+	ut_asserteq(0x44, hdr.aslc_revision);
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_fill_header, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test ACPI write_tables() */
+static int dm_test_acpi_write_tables(struct unit_test_state *uts)
+{
+	struct acpi_dmar *dmar;
+	struct acpi_ctx ctx;
+	void *buf;
+
+	buf = malloc(BUF_SIZE);
+	ut_assertnonnull(buf);
+
+	acpi_setup_base_tables(&ctx, buf);
+	dmar = ctx.current;
+	ut_assertok(acpi_write_dev_tables(&ctx));
+
+	/*
+	 * We should have two dmar tables, one for each "denx,u-boot-acpi-test"
+	 * device
+	 */
+	ut_asserteq_ptr(dmar + 2, ctx.current);
+	ut_asserteq(DMAR_INTR_REMAP, dmar->flags);
+	ut_asserteq(32 - 1, dmar->host_address_width);
+
+	ut_asserteq(DMAR_INTR_REMAP, dmar[1].flags);
+	ut_asserteq(32 - 1, dmar[1].host_address_width);
+
+	/* Check that the pointers were added correctly */
+	ut_asserteq(map_to_sysmem(dmar), ctx.rsdt->entry[0]);
+	ut_asserteq(map_to_sysmem(dmar + 1), ctx.rsdt->entry[1]);
+	ut_asserteq(0, ctx.rsdt->entry[2]);
+
+	ut_asserteq(map_to_sysmem(dmar), ctx.xsdt->entry[0]);
+	ut_asserteq(map_to_sysmem(dmar + 1), ctx.xsdt->entry[1]);
+	ut_asserteq(0, ctx.xsdt->entry[2]);
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_write_tables, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test basic ACPI functions */
+static int dm_test_acpi_basic(struct unit_test_state *uts)
+{
+	struct acpi_ctx ctx;
+
+	/* Check align works */
+	ctx.current = (void *)5;
+	acpi_align(&ctx);
+	ut_asserteq_ptr((void *)16, ctx.current);
+
+	/* Check that align does nothing if already aligned */
+	acpi_align(&ctx);
+	ut_asserteq_ptr((void *)16, ctx.current);
+	acpi_align64(&ctx);
+	ut_asserteq_ptr((void *)64, ctx.current);
+	acpi_align64(&ctx);
+	ut_asserteq_ptr((void *)64, ctx.current);
+
+	/* Check incrementing */
+	acpi_inc(&ctx, 3);
+	ut_asserteq_ptr((void *)67, ctx.current);
+	acpi_inc_align(&ctx, 3);
+	ut_asserteq_ptr((void *)80, ctx.current);
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_basic, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test acpi_setup_base_tables */
+static int dm_test_acpi_setup_base_tables(struct unit_test_state *uts)
+{
+	struct acpi_rsdp *rsdp;
+	struct acpi_rsdt *rsdt;
+	struct acpi_xsdt *xsdt;
+	struct acpi_ctx ctx;
+	void *buf, *end;
+
+	/*
+	 * Use an unaligned address deliberately, by allocating an aligned
+	 * address and then adding 4 to it
+	 */
+	buf = memalign(64, BUF_SIZE);
+	ut_assertnonnull(buf);
+	acpi_setup_base_tables(&ctx, buf + 4);
+	ut_asserteq(map_to_sysmem(PTR_ALIGN(buf + 4, 16)), gd->arch.acpi_start);
+
+	rsdp = buf + 16;
+	ut_asserteq_ptr(rsdp, ctx.rsdp);
+	ut_assertok(memcmp(RSDP_SIG, rsdp->signature, sizeof(rsdp->signature)));
+	ut_asserteq(sizeof(*rsdp), rsdp->length);
+	ut_assertok(table_compute_checksum(rsdp, 20));
+	ut_assertok(table_compute_checksum(rsdp, sizeof(*rsdp)));
+
+	rsdt = PTR_ALIGN((void *)rsdp + sizeof(*rsdp), 16);
+	ut_asserteq_ptr(rsdt, ctx.rsdt);
+	ut_assertok(memcmp("RSDT", rsdt->header.signature, ACPI_NAME_LEN));
+	ut_asserteq(sizeof(*rsdt), rsdt->header.length);
+	ut_assertok(table_compute_checksum(rsdt, sizeof(*rsdt)));
+
+	xsdt = PTR_ALIGN((void *)rsdt + sizeof(*rsdt), 16);
+	ut_asserteq_ptr(xsdt, ctx.xsdt);
+	ut_assertok(memcmp("XSDT", xsdt->header.signature, ACPI_NAME_LEN));
+	ut_asserteq(sizeof(*xsdt), xsdt->header.length);
+	ut_assertok(table_compute_checksum(xsdt, sizeof(*xsdt)));
+
+	end = PTR_ALIGN((void *)xsdt + sizeof(*xsdt), 64);
+	ut_asserteq_ptr(end, ctx.current);
+
+	ut_asserteq(map_to_sysmem(rsdt), rsdp->rsdt_address);
+	ut_asserteq(map_to_sysmem(xsdt), rsdp->xsdt_address);
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_setup_base_tables,
+	DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test 'acpi list' command */
+static int dm_test_acpi_cmd_list(struct unit_test_state *uts)
+{
+	struct acpi_ctx ctx;
+	ulong addr;
+	void *buf;
+
+	buf = memalign(16, BUF_SIZE);
+	ut_assertnonnull(buf);
+	acpi_setup_base_tables(&ctx, buf);
+
+	ut_assertok(acpi_write_dev_tables(&ctx));
+
+	console_record_reset();
+	run_command("acpi list", 0);
+	addr = (ulong)map_to_sysmem(buf);
+	ut_assert_nextline("ACPI tables start at %lx", addr);
+	ut_assert_nextline("RSDP %08lx %06lx (v02 U-BOOT)", addr,
+			   sizeof(struct acpi_rsdp));
+	addr = ALIGN(addr + sizeof(struct acpi_rsdp), 16);
+	ut_assert_nextline("RSDT %08lx %06lx (v01 U-BOOT U-BOOTBL %u INTL 0)",
+			   addr, sizeof(struct acpi_table_header) +
+			   2 * sizeof(u32), U_BOOT_BUILD_DATE);
+	addr = ALIGN(addr + sizeof(struct acpi_rsdt), 16);
+	ut_assert_nextline("XSDT %08lx %06lx (v01 U-BOOT U-BOOTBL %u INTL 0)",
+			   addr, sizeof(struct acpi_table_header) +
+			   2 * sizeof(u64), U_BOOT_BUILD_DATE);
+	addr = ALIGN(addr + sizeof(struct acpi_xsdt), 64);
+	ut_assert_nextline("DMAR %08lx %06lx (v01 U-BOOT U-BOOTBL %u INTL 0)",
+			   addr, sizeof(struct acpi_dmar), U_BOOT_BUILD_DATE);
+	addr = ALIGN(addr + sizeof(struct acpi_dmar), 16);
+	ut_assert_nextline("DMAR %08lx %06lx (v01 U-BOOT U-BOOTBL %u INTL 0)",
+			   addr, sizeof(struct acpi_dmar), U_BOOT_BUILD_DATE);
+	ut_assert_console_end();
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_cmd_list, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test 'acpi dump' command */
+static int dm_test_acpi_cmd_dump(struct unit_test_state *uts)
+{
+	struct acpi_ctx ctx;
+	ulong addr;
+	void *buf;
+
+	buf = memalign(16, BUF_SIZE);
+	ut_assertnonnull(buf);
+	acpi_setup_base_tables(&ctx, buf);
+
+	ut_assertok(acpi_write_dev_tables(&ctx));
+
+	/* First search for a non-existent table */
+	console_record_reset();
+	run_command("acpi dump rdst", 0);
+	ut_assert_nextline("Table 'RDST' not found");
+	ut_assert_console_end();
+
+	/* Now a real table */
+	console_record_reset();
+	run_command("acpi dump dmar", 0);
+	addr = ALIGN(map_to_sysmem(ctx.xsdt) + sizeof(struct acpi_xsdt), 64);
+	ut_assert_nextline("DMAR @ %08lx", addr);
+	ut_assert_nextlines_are_dump(0x30);
+	ut_assert_console_end();
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_cmd_dump, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
diff --git a/test/py/tests/test_efi_secboot/conftest.py b/test/py/tests/test_efi_secboot/conftest.py
index e542fef..5d99b8b 100644
--- a/test/py/tests/test_efi_secboot/conftest.py
+++ b/test/py/tests/test_efi_secboot/conftest.py
@@ -43,7 +43,8 @@
         HELLO_PATH = u_boot_config.build_dir + '/lib/efi_loader/helloworld.efi'
 
     try:
-        non_root = tool_is_in_path('udisksctl')
+        mnt_point = u_boot_config.persistent_data_dir + '/mnt_efisecure'
+        check_call('mkdir -p {}'.format(mnt_point), shell=True)
 
         # create a disk/partition
         check_call('dd if=/dev/zero of=%s bs=1MiB count=%d'
@@ -57,25 +58,11 @@
         check_call('dd if=%s.tmp of=%s bs=1MiB seek=1 count=%d conv=notrunc'
                             % (image_path, image_path, 1), shell=True)
         check_call('rm %s.tmp' % image_path, shell=True)
-        if non_root:
-            out_data = check_output('udisksctl loop-setup -f %s -o %d'
-                                % (image_path, 1048576), shell=True).decode()
-            m = re.search('(?<= as )(.*)\.', out_data)
-            loop_dev = m.group(1)
-            # print 'loop device is: %s' % loop_dev
-            out_data = check_output('udisksctl info -b %s'
-                                % loop_dev, shell=True).decode()
-            m = re.search('MountPoints:[ \t]+(.*)', out_data)
-            mnt_point = m.group(1)
-        else:
-            loop_dev = check_output('sudo losetup -o 1MiB --sizelimit %dMiB --show -f %s | tr -d "\n"'
+        loop_dev = check_output('sudo losetup -o 1MiB --sizelimit %dMiB --show -f %s | tr -d "\n"'
                                 % (part_size, image_path), shell=True).decode()
-            mnt_point = '/mnt'
-            check_output('sudo mount -t %s -o umask=000 %s %s'
+        check_output('sudo mount -t %s -o umask=000 %s %s'
                                 % (fs_type, loop_dev, mnt_point), shell=True)
 
-        # print 'mount point is: %s' % mnt_point
-
         # suffix
         # *.key: RSA private key in PEM
         # *.crt: X509 certificate (self-signed) in PEM
@@ -134,13 +121,8 @@
                             % (mnt_point, EFITOOLS_PATH, EFITOOLS_PATH),
                             shell=True)
 
-        if non_root:
-            check_call('udisksctl unmount -b %s' % loop_dev, shell=True)
-            # not needed
-            # check_call('udisksctl loop-delete -b %s' % loop_dev, shell=True)
-        else:
-            check_call('sudo umount %s' % loop_dev, shell=True)
-            check_call('sudo losetup -d %s' % loop_dev, shell=True)
+        check_call('sudo umount %s' % loop_dev, shell=True)
+        check_call('sudo losetup -d %s' % loop_dev, shell=True)
 
     except CalledProcessError as e:
         pytest.skip('Setup failed: %s' % e.cmd)
diff --git a/test/py/tests/test_fs/conftest.py b/test/py/tests/test_fs/conftest.py
index 1949f91..ee82169 100644
--- a/test/py/tests/test_fs/conftest.py
+++ b/test/py/tests/test_fs/conftest.py
@@ -335,8 +335,9 @@
         md5val.append(out.split()[0])
 
         umount_fs(mount_dir)
-    except CalledProcessError:
-        pytest.skip('Setup failed for filesystem: ' + fs_type)
+    except CalledProcessError as err:
+        pytest.skip('Setup failed for filesystem: ' + fs_type + \
+            '. {}'.format(err))
         return
     else:
         yield [fs_ubtype, fs_img, md5val]
diff --git a/test/py/tests/test_vboot.py b/test/py/tests/test_vboot.py
index e67f2b3..6b998cf 100644
--- a/test/py/tests/test_vboot.py
+++ b/test/py/tests/test_vboot.py
@@ -30,11 +30,16 @@
 import vboot_forge
 
 TESTDATA = [
-    ['sha1', '', False],
-    ['sha1', '-pss', False],
-    ['sha256', '', False],
-    ['sha256', '-pss', False],
-    ['sha256', '-pss', True],
+    ['sha1', '', None, False],
+    ['sha1', '', '-E -p 0x10000', False],
+    ['sha1', '-pss', None, False],
+    ['sha1', '-pss', '-E -p 0x10000', False],
+    ['sha256', '', None, False],
+    ['sha256', '', '-E -p 0x10000', False],
+    ['sha256', '-pss', None, False],
+    ['sha256', '-pss', '-E -p 0x10000', False],
+    ['sha256', '-pss', None, True],
+    ['sha256', '-pss', '-E -p 0x10000', True],
 ]
 
 @pytest.mark.boardspec('sandbox')
@@ -43,8 +48,8 @@
 @pytest.mark.requiredtool('fdtget')
 @pytest.mark.requiredtool('fdtput')
 @pytest.mark.requiredtool('openssl')
-@pytest.mark.parametrize("sha_algo,padding,required", TESTDATA)
-def test_vboot(u_boot_console, sha_algo, padding, required):
+@pytest.mark.parametrize("sha_algo,padding,sign_options,required", TESTDATA)
+def test_vboot(u_boot_console, sha_algo, padding, sign_options, required):
     """Test verified boot signing with mkimage and verification with 'bootm'.
 
     This works using sandbox only as it needs to update the device tree used
@@ -104,7 +109,7 @@
         util.run_and_log(cons, [mkimage, '-D', dtc_args, '-f',
                                 '%s%s' % (datadir, its), fit])
 
-    def sign_fit(sha_algo):
+    def sign_fit(sha_algo, options):
         """Sign the FIT
 
         Signs the FIT and writes the signature into it. It also writes the
@@ -113,10 +118,13 @@
         Args:
             sha_algo: Either 'sha1' or 'sha256', to select the algorithm to
                     use.
+            options: Options to provide to mkimage.
         """
+        args = [mkimage, '-F', '-k', tmpdir, '-K', dtb, '-r', fit]
+        if options:
+            args += options.split(' ')
         cons.log.action('%s: Sign images' % sha_algo)
-        util.run_and_log(cons, [mkimage, '-F', '-k', tmpdir, '-K', dtb,
-                                '-r', fit])
+        util.run_and_log(cons, args)
 
     def replace_fit_totalsize(size):
         """Replace FIT header's totalsize with something greater.
@@ -154,7 +162,7 @@
         util.run_and_log(cons, 'openssl req -batch -new -x509 -key %s%s.key '
                          '-out %s%s.crt' % (tmpdir, name, tmpdir, name))
 
-    def test_with_algo(sha_algo, padding):
+    def test_with_algo(sha_algo, padding, sign_options):
         """Test verified boot with the given hash algorithm.
 
         This is the main part of the test code. The same procedure is followed
@@ -163,6 +171,9 @@
         Args:
             sha_algo: Either 'sha1' or 'sha256', to select the algorithm to
                     use.
+            padding: Either '' or '-pss', to select the padding to use for the
+                    rsa signature algorithm.
+            sign_options: Options to mkimage when signing a fit image.
         """
         # Compile our device tree files for kernel and U-Boot. These are
         # regenerated here since mkimage will modify them (by adding a
@@ -176,7 +187,7 @@
         run_bootm(sha_algo, 'unsigned images', 'dev-', True)
 
         # Sign images with our dev keys
-        sign_fit(sha_algo)
+        sign_fit(sha_algo, sign_options)
         run_bootm(sha_algo, 'signed images', 'dev+', True)
 
         # Create a fresh .dtb without the public keys
@@ -187,7 +198,7 @@
         run_bootm(sha_algo, 'unsigned config', '%s+ OK' % sha_algo, True)
 
         # Sign images with our dev keys
-        sign_fit(sha_algo)
+        sign_fit(sha_algo, sign_options)
         run_bootm(sha_algo, 'signed config', 'dev+', True)
 
         cons.log.action('%s: Check signed config on the host' % sha_algo)
@@ -209,7 +220,7 @@
 
         # Create a new properly signed fit and replace header bytes
         make_fit('sign-configs-%s%s.its' % (sha_algo, padding))
-        sign_fit(sha_algo)
+        sign_fit(sha_algo, sign_options)
         bcfg = u_boot_console.config.buildconfig
         max_size = int(bcfg.get('config_fit_signature_max_size', 0x10000000), 0)
         existing_size = replace_fit_totalsize(max_size + 1)
@@ -240,7 +251,7 @@
             cons, [fit_check_sign, '-f', fit, '-k', dtb],
             1, 'Failed to verify required signature')
 
-    def test_required_key(sha_algo, padding):
+    def test_required_key(sha_algo, padding, sign_options):
         """Test verified boot with the given hash algorithm.
 
         This function tests if U-Boot rejects an image when a required key isn't
@@ -248,6 +259,9 @@
 
         Args:
             sha_algo: Either 'sha1' or 'sha256', to select the algorithm to use
+            padding: Either '' or '-pss', to select the padding to use for the
+                    rsa signature algorithm.
+            sign_options: Options to mkimage when signing a fit image.
         """
         # Compile our device tree files for kernel and U-Boot. These are
         # regenerated here since mkimage will modify them (by adding a
@@ -260,12 +274,12 @@
         # Build the FIT with prod key (keys required) and sign it. This puts the
         # signature into sandbox-u-boot.dtb, marked 'required'
         make_fit('sign-configs-%s%s-prod.its' % (sha_algo, padding))
-        sign_fit(sha_algo)
+        sign_fit(sha_algo, sign_options)
 
         # Build the FIT with dev key (keys NOT required). This adds the
         # signature into sandbox-u-boot.dtb, NOT marked 'required'.
         make_fit('sign-configs-%s%s.its' % (sha_algo, padding))
-        sign_fit(sha_algo)
+        sign_fit(sha_algo, sign_options)
 
         # So now sandbox-u-boot.dtb two signatures, for the prod and dev keys.
         # Only the prod key is set as 'required'. But FIT we just built has
@@ -297,9 +311,9 @@
         old_dtb = cons.config.dtb
         cons.config.dtb = dtb
         if required:
-            test_required_key(sha_algo, padding)
+            test_required_key(sha_algo, padding, sign_options)
         else:
-            test_with_algo(sha_algo, padding)
+            test_with_algo(sha_algo, padding, sign_options)
     finally:
         # Go back to the original U-Boot with the correct dtb.
         cons.config.dtb = old_dtb
diff --git a/test/run b/test/run
index d635622..27331a8 100755
--- a/test/run
+++ b/test/run
@@ -15,22 +15,29 @@
 
 # SKip slow tests if requested
 [ "$1" == "quick" ] && mark_expr="not slow"
+[ "$1" == "quick" ] && skip=--skip-net-tests
+[ "$1" == "tools" ] && tools_only=y
 
 failures=0
 
-# Run all tests that the standard sandbox build can support
-run_test "sandbox" ./test/py/test.py --bd sandbox --build -m "${mark_expr}"
+if [ -z "$tools_only" ]; then
+	# Run all tests that the standard sandbox build can support
+	run_test "sandbox" ./test/py/test.py --bd sandbox --build \
+		-m "${mark_expr}"
+fi
 
 # Run tests which require sandbox_spl
 run_test "sandbox_spl" ./test/py/test.py --bd sandbox_spl --build \
-	-k 'test_ofplatdata or test_handoff'
+		-k 'test_ofplatdata or test_handoff'
 
-# Run tests for the flat-device-tree version of sandbox. This is a special
-# build which does not enable CONFIG_OF_LIVE for the live device tree, so we can
-# check that functionality is the same. The standard sandbox build (above) uses
-# CONFIG_OF_LIVE.
-run_test "sandbox_flattree" ./test/py/test.py --bd sandbox_flattree --build \
-	-k test_ut
+if [ -z "$tools_only" ]; then
+	# Run tests for the flat-device-tree version of sandbox. This is a special
+	# build which does not enable CONFIG_OF_LIVE for the live device tree, so we can
+	# check that functionality is the same. The standard sandbox build (above) uses
+	# CONFIG_OF_LIVE.
+	run_test "sandbox_flattree" ./test/py/test.py --bd sandbox_flattree \
+		--build -k test_ut
+fi
 
 # Set up a path to dtc (device-tree compiler) and libfdt.py, a library it
 # provides and which is built by the sandbox_spl config. Also set up the path
@@ -43,7 +50,6 @@
 run_test "binman" ./tools/binman/binman --toolpath ${TOOLS_DIR} test
 run_test "patman" ./tools/patman/patman --test
 
-[ "$1" == "quick" ] && skip=--skip-net-tests
 run_test "buildman" ./tools/buildman/buildman -t ${skip}
 run_test "fdt" ./tools/dtoc/test_fdt -t
 run_test "dtoc" ./tools/dtoc/dtoc -t
diff --git a/tools/Makefile b/tools/Makefile
index c2b2634..1f9144f 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -63,14 +63,8 @@
 
 # The following files are synced with upstream DTC.
 # Use synced versions from scripts/dtc/libfdt/.
-LIBFDT_SRCS_SYNCED := fdt.c fdt_wip.c fdt_sw.c fdt_rw.c \
-		fdt_strerror.c fdt_empty_tree.c fdt_addresses.c fdt_overlay.c
-# The following files are locally modified for U-Boot (unfotunately).
-# Use U-Boot own versions from lib/libfdt/.
-LIBFDT_SRCS_UNSYNCED := fdt_ro.c fdt_region.c
-
-LIBFDT_OBJS := $(addprefix libfdt/, $(patsubst %.c, %.o, $(LIBFDT_SRCS_SYNCED))) \
-	       $(addprefix lib/libfdt/, $(patsubst %.c, %.o, $(LIBFDT_SRCS_UNSYNCED)))
+LIBFDT_OBJS := $(addprefix libfdt/, fdt.o fdt_ro.o fdt_wip.o fdt_sw.o fdt_rw.o \
+		fdt_strerror.o fdt_empty_tree.o fdt_addresses.o fdt_overlay.o)
 
 RSA_OBJS-$(CONFIG_FIT_SIGNATURE) := $(addprefix lib/rsa/, \
 					rsa-sign.o rsa-verify.o rsa-checksum.o \
@@ -87,6 +81,7 @@
 			$(FIT_OBJS-y) \
 			$(FIT_SIG_OBJS-y) \
 			$(FIT_CIPHER_OBJS-y) \
+			common/fdt_region.o \
 			common/bootm.o \
 			lib/crc32.o \
 			default_image.o \
@@ -211,7 +206,7 @@
 hostprogs-$(CONFIG_RISCV) += prelink-riscv
 
 hostprogs-y += fdtgrep
-fdtgrep-objs += $(LIBFDT_OBJS) fdtgrep.o
+fdtgrep-objs += $(LIBFDT_OBJS) common/fdt_region.o fdtgrep.o
 
 ifneq ($(TOOLS_ONLY),y)
 hostprogs-y += spl_size_limit
diff --git a/tools/binman/binman b/tools/binman/binman
index 979b7e4..11a5d8e 120000
--- a/tools/binman/binman
+++ b/tools/binman/binman
@@ -1 +1 @@
-binman.py
\ No newline at end of file
+main.py
\ No newline at end of file
diff --git a/tools/binman/binman.py b/tools/binman/binman.py
deleted file mode 100755
index 9e6fd72..0000000
--- a/tools/binman/binman.py
+++ /dev/null
@@ -1,202 +0,0 @@
-#!/usr/bin/env python3
-# SPDX-License-Identifier: GPL-2.0+
-
-# Copyright (c) 2016 Google, Inc
-# Written by Simon Glass <sjg@chromium.org>
-#
-# Creates binary images from input files controlled by a description
-#
-
-"""See README for more information"""
-
-from __future__ import print_function
-
-from distutils.sysconfig import get_python_lib
-import glob
-import multiprocessing
-import os
-import site
-import sys
-import traceback
-import unittest
-
-# Bring in the patman and dtoc libraries (but don't override the first path
-# in PYTHONPATH)
-our_path = os.path.dirname(os.path.realpath(__file__))
-for dirname in ['../patman', '../dtoc', '..', '../concurrencytest']:
-    sys.path.insert(2, os.path.join(our_path, dirname))
-
-# Bring in the libfdt module
-sys.path.insert(2, 'scripts/dtc/pylibfdt')
-sys.path.insert(2, os.path.join(our_path,
-                '../../build-sandbox_spl/scripts/dtc/pylibfdt'))
-
-# When running under python-coverage on Ubuntu 16.04, the dist-packages
-# directories are dropped from the python path. Add them in so that we can find
-# the elffile module. We could use site.getsitepackages() here but unfortunately
-# that is not available in a virtualenv.
-sys.path.append(get_python_lib())
-
-import cmdline
-import command
-use_concurrent = True
-try:
-    from concurrencytest import ConcurrentTestSuite, fork_for_tests
-except:
-    use_concurrent = False
-import control
-import test_util
-
-def RunTests(debug, verbosity, processes, test_preserve_dirs, args, toolpath):
-    """Run the functional tests and any embedded doctests
-
-    Args:
-        debug: True to enable debugging, which shows a full stack trace on error
-        verbosity: Verbosity level to use
-        test_preserve_dirs: True to preserve the input directory used by tests
-            so that it can be examined afterwards (only useful for debugging
-            tests). If a single test is selected (in args[0]) it also preserves
-            the output directory for this test. Both directories are displayed
-            on the command line.
-        processes: Number of processes to use to run tests (None=same as #CPUs)
-        args: List of positional args provided to binman. This can hold a test
-            name to execute (as in 'binman test testSections', for example)
-        toolpath: List of paths to use for tools
-    """
-    import cbfs_util_test
-    import elf_test
-    import entry_test
-    import fdt_test
-    import ftest
-    import image_test
-    import test
-    import doctest
-
-    result = unittest.TestResult()
-    for module in []:
-        suite = doctest.DocTestSuite(module)
-        suite.run(result)
-
-    sys.argv = [sys.argv[0]]
-    if debug:
-        sys.argv.append('-D')
-    if verbosity:
-        sys.argv.append('-v%d' % verbosity)
-    if toolpath:
-        for path in toolpath:
-            sys.argv += ['--toolpath', path]
-
-    # Run the entry tests first ,since these need to be the first to import the
-    # 'entry' module.
-    test_name = args and args[0] or None
-    suite = unittest.TestSuite()
-    loader = unittest.TestLoader()
-    for module in (entry_test.TestEntry, ftest.TestFunctional, fdt_test.TestFdt,
-                   elf_test.TestElf, image_test.TestImage,
-                   cbfs_util_test.TestCbfs):
-        # Test the test module about our arguments, if it is interested
-        if hasattr(module, 'setup_test_args'):
-            setup_test_args = getattr(module, 'setup_test_args')
-            setup_test_args(preserve_indir=test_preserve_dirs,
-                preserve_outdirs=test_preserve_dirs and test_name is not None,
-                toolpath=toolpath, verbosity=verbosity)
-        if test_name:
-            try:
-                suite.addTests(loader.loadTestsFromName(test_name, module))
-            except AttributeError:
-                continue
-        else:
-            suite.addTests(loader.loadTestsFromTestCase(module))
-    if use_concurrent and processes != 1:
-        concurrent_suite = ConcurrentTestSuite(suite,
-                fork_for_tests(processes or multiprocessing.cpu_count()))
-        concurrent_suite.run(result)
-    else:
-        suite.run(result)
-
-    # Remove errors which just indicate a missing test. Since Python v3.5 If an
-    # ImportError or AttributeError occurs while traversing name then a
-    # synthetic test that raises that error when run will be returned. These
-    # errors are included in the errors accumulated by result.errors.
-    if test_name:
-        errors = []
-        for test, err in result.errors:
-            if ("has no attribute '%s'" % test_name) not in err:
-                errors.append((test, err))
-            result.testsRun -= 1
-        result.errors = errors
-
-    print(result)
-    for test, err in result.errors:
-        print(test.id(), err)
-    for test, err in result.failures:
-        print(err, result.failures)
-    if result.skipped:
-        print('%d binman test%s SKIPPED:' %
-              (len(result.skipped), 's' if len(result.skipped) > 1 else ''))
-        for skip_info in result.skipped:
-            print('%s: %s' % (skip_info[0], skip_info[1]))
-    if result.errors or result.failures:
-        print('binman tests FAILED')
-        return 1
-    return 0
-
-def GetEntryModules(include_testing=True):
-    """Get a set of entry class implementations
-
-    Returns:
-        Set of paths to entry class filenames
-    """
-    glob_list = glob.glob(os.path.join(our_path, 'etype/*.py'))
-    return set([os.path.splitext(os.path.basename(item))[0]
-                for item in glob_list
-                if include_testing or '_testing' not in item])
-
-def RunTestCoverage():
-    """Run the tests and check that we get 100% coverage"""
-    glob_list = GetEntryModules(False)
-    all_set = set([os.path.splitext(os.path.basename(item))[0]
-                   for item in glob_list if '_testing' not in item])
-    test_util.RunTestCoverage('tools/binman/binman.py', None,
-            ['*test*', '*binman.py', 'tools/patman/*', 'tools/dtoc/*'],
-            args.build_dir, all_set)
-
-def RunBinman(args):
-    """Main entry point to binman once arguments are parsed
-
-    Args:
-        args: Command line arguments Namespace object
-    """
-    ret_code = 0
-
-    if not args.debug:
-        sys.tracebacklimit = 0
-
-    if args.cmd == 'test':
-        if args.test_coverage:
-            RunTestCoverage()
-        else:
-            ret_code = RunTests(args.debug, args.verbosity, args.processes,
-                                args.test_preserve_dirs, args.tests,
-                                args.toolpath)
-
-    elif args.cmd == 'entry-docs':
-        control.WriteEntryDocs(GetEntryModules())
-
-    else:
-        try:
-            ret_code = control.Binman(args)
-        except Exception as e:
-            print('binman: %s' % e)
-            if args.debug:
-                print()
-                traceback.print_exc()
-            ret_code = 1
-    return ret_code
-
-
-if __name__ == "__main__":
-    args = cmdline.ParseArgs(sys.argv[1:])
-
-    ret_code = RunBinman(args)
-    sys.exit(ret_code)
diff --git a/tools/binman/cbfs_util.py b/tools/binman/cbfs_util.py
index 99d7787..3997337 100644
--- a/tools/binman/cbfs_util.py
+++ b/tools/binman/cbfs_util.py
@@ -15,16 +15,14 @@
     with empty files, fixed-offset files
 """
 
-from __future__ import print_function
-
 from collections import OrderedDict
 import io
 import struct
 import sys
 
-import command
-import elf
-import tools
+from binman import elf
+from patman import command
+from patman import tools
 
 # Set to True to enable printing output while working
 DEBUG = False
diff --git a/tools/binman/cbfs_util_test.py b/tools/binman/cbfs_util_test.py
index ddc2e09..2c62c8a 100755
--- a/tools/binman/cbfs_util_test.py
+++ b/tools/binman/cbfs_util_test.py
@@ -9,8 +9,6 @@
 values and with cbfstool
 """
 
-from __future__ import print_function
-
 import io
 import os
 import shutil
@@ -18,11 +16,11 @@
 import tempfile
 import unittest
 
-import cbfs_util
-from cbfs_util import CbfsWriter
-import elf
-import test_util
-import tools
+from binman import cbfs_util
+from binman.cbfs_util import CbfsWriter
+from binman import elf
+from patman import test_util
+from patman import tools
 
 U_BOOT_DATA           = b'1234'
 U_BOOT_DTB_DATA       = b'udtb'
diff --git a/tools/binman/control.py b/tools/binman/control.py
index 68ad5fc..dc1dd2a 100644
--- a/tools/binman/control.py
+++ b/tools/binman/control.py
@@ -5,17 +5,15 @@
 # Creates binary images from input files controlled by a description
 #
 
-from __future__ import print_function
-
 from collections import OrderedDict
 import os
 import sys
-import tools
+from patman import tools
 
-import cbfs_util
-import command
-import elf
-import tout
+from binman import cbfs_util
+from binman import elf
+from patman import command
+from patman import tout
 
 # List of images we plan to create
 # Make this global so that it can be referenced from tests
@@ -62,7 +60,7 @@
             to show as missing even if it is present. Should be set to None in
             normal use.
     """
-    from entry import Entry
+    from binman.entry import Entry
     Entry.WriteDocs(modules, test_missing)
 
 
@@ -336,8 +334,8 @@
     """
     # Import these here in case libfdt.py is not available, in which case
     # the above help option still works.
-    import fdt
-    import fdt_util
+    from dtoc import fdt
+    from dtoc import fdt_util
     global images
 
     # Get the device tree ready by compiling it and copying the compiled
@@ -475,7 +473,7 @@
 
     # Put these here so that we can import this module without libfdt
     from image import Image
-    import state
+    from binman import state
 
     if args.cmd in ['ls', 'extract', 'replace']:
         try:
diff --git a/tools/binman/elf.py b/tools/binman/elf.py
index de1ce73..f88031c 100644
--- a/tools/binman/elf.py
+++ b/tools/binman/elf.py
@@ -5,10 +5,7 @@
 # Handle various things related to ELF images
 #
 
-from __future__ import print_function
-
 from collections import namedtuple, OrderedDict
-import command
 import io
 import os
 import re
@@ -16,8 +13,9 @@
 import struct
 import tempfile
 
-import tools
-import tout
+from patman import command
+from patman import tools
+from patman import tout
 
 ELF_TOOLS = True
 try:
diff --git a/tools/binman/elf_test.py b/tools/binman/elf_test.py
index ac26fd5..37e1b42 100644
--- a/tools/binman/elf_test.py
+++ b/tools/binman/elf_test.py
@@ -10,11 +10,11 @@
 import tempfile
 import unittest
 
-import command
-import elf
-import test_util
-import tools
-import tout
+from binman import elf
+from patman import command
+from patman import test_util
+from patman import tools
+from patman import tout
 
 binman_dir = os.path.dirname(os.path.realpath(sys.argv[0]))
 
diff --git a/tools/binman/entry.py b/tools/binman/entry.py
index b6f1b2c..90ffd27 100644
--- a/tools/binman/entry.py
+++ b/tools/binman/entry.py
@@ -4,17 +4,15 @@
 # Base class for all entries
 #
 
-from __future__ import print_function
-
 from collections import namedtuple
 import importlib
 import os
 import sys
 
-import fdt_util
-import tools
-from tools import ToHex, ToHexSize
-import tout
+from dtoc import fdt_util
+from patman import tools
+from patman.tools import ToHex, ToHexSize
+from patman import tout
 
 modules = {}
 
@@ -65,7 +63,7 @@
     def __init__(self, section, etype, node, name_prefix=''):
         # Put this here to allow entry-docs and help to work without libfdt
         global state
-        import state
+        from binman import state
 
         self.section = section
         self.etype = etype
@@ -110,15 +108,11 @@
 
         # Import the module if we have not already done so.
         if not module:
-            old_path = sys.path
-            sys.path.insert(0, os.path.join(our_path, 'etype'))
             try:
-                module = importlib.import_module(module_name)
+                module = importlib.import_module('binman.etype.' + module_name)
             except ImportError as e:
                 raise ValueError("Unknown entry type '%s' in node '%s' (expected etype/%s.py, error '%s'" %
                                  (etype, node_path, module_name, e))
-            finally:
-                sys.path = old_path
             modules[module_name] = module
 
         # Look up the expected class name
@@ -592,9 +586,7 @@
             modules.remove('_testing')
         missing = []
         for name in modules:
-            if name.startswith('__'):
-                continue
-            module = Entry.Lookup(name, name)
+            module = Entry.Lookup('WriteDocs', name)
             docs = getattr(module, '__doc__')
             if test_missing == name:
                 docs = None
diff --git a/tools/binman/entry_test.py b/tools/binman/entry_test.py
index 277e10b..80802f3 100644
--- a/tools/binman/entry_test.py
+++ b/tools/binman/entry_test.py
@@ -9,10 +9,10 @@
 import sys
 import unittest
 
-import entry
-import fdt
-import fdt_util
-import tools
+from binman import entry
+from dtoc import fdt
+from dtoc import fdt_util
+from patman import tools
 
 class TestEntry(unittest.TestCase):
     def setUp(self):
@@ -37,11 +37,11 @@
             else:
                 reload(entry)
         else:
-            import entry
+            from binman import entry
 
     def testEntryContents(self):
         """Test the Entry bass class"""
-        import entry
+        from binman import entry
         base_entry = entry.Entry(None, None, None)
         self.assertEqual(True, base_entry.ObtainContents())
 
diff --git a/tools/binman/etype/__init__.py b/tools/binman/etype/__init__.py
deleted file mode 100644
index e69de29..0000000
--- a/tools/binman/etype/__init__.py
+++ /dev/null
diff --git a/tools/binman/etype/_testing.py b/tools/binman/etype/_testing.py
index 25a6206..ed718ee 100644
--- a/tools/binman/etype/_testing.py
+++ b/tools/binman/etype/_testing.py
@@ -7,9 +7,9 @@
 
 from collections import OrderedDict
 
-from entry import Entry, EntryArg
-import fdt_util
-import tools
+from binman.entry import Entry, EntryArg
+from dtoc import fdt_util
+from patman import tools
 
 
 class Entry__testing(Entry):
diff --git a/tools/binman/etype/blob.py b/tools/binman/etype/blob.py
index d34c7b5..ede7a7a 100644
--- a/tools/binman/etype/blob.py
+++ b/tools/binman/etype/blob.py
@@ -5,10 +5,10 @@
 # Entry-type module for blobs, which are binary objects read from files
 #
 
-from entry import Entry
-import fdt_util
-import tools
-import tout
+from binman.entry import Entry
+from dtoc import fdt_util
+from patman import tools
+from patman import tout
 
 class Entry_blob(Entry):
     """Entry containing an arbitrary binary blob
diff --git a/tools/binman/etype/blob_dtb.py b/tools/binman/etype/blob_dtb.py
index b2afa06..6c06943 100644
--- a/tools/binman/etype/blob_dtb.py
+++ b/tools/binman/etype/blob_dtb.py
@@ -5,8 +5,8 @@
 # Entry-type module for U-Boot device tree files
 #
 
-from entry import Entry
-from blob import Entry_blob
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
 
 class Entry_blob_dtb(Entry_blob):
     """A blob that holds a device tree
@@ -18,7 +18,7 @@
     def __init__(self, section, etype, node):
         # Put this here to allow entry-docs and help to work without libfdt
         global state
-        import state
+        from binman import state
 
         Entry_blob.__init__(self, section, etype, node)
 
diff --git a/tools/binman/etype/blob_named_by_arg.py b/tools/binman/etype/blob_named_by_arg.py
index 344112b..3b4593f 100644
--- a/tools/binman/etype/blob_named_by_arg.py
+++ b/tools/binman/etype/blob_named_by_arg.py
@@ -8,8 +8,8 @@
 
 from collections import OrderedDict
 
-from blob import Entry_blob
-from entry import EntryArg
+from binman.etype.blob import Entry_blob
+from binman.entry import EntryArg
 
 
 class Entry_blob_named_by_arg(Entry_blob):
diff --git a/tools/binman/etype/cbfs.py b/tools/binman/etype/cbfs.py
index 35b7837..e9aed83 100644
--- a/tools/binman/etype/cbfs.py
+++ b/tools/binman/etype/cbfs.py
@@ -7,10 +7,10 @@
 
 from collections import OrderedDict
 
-import cbfs_util
-from cbfs_util import CbfsWriter
-from entry import Entry
-import fdt_util
+from binman import cbfs_util
+from binman.cbfs_util import CbfsWriter
+from binman.entry import Entry
+from dtoc import fdt_util
 
 class Entry_cbfs(Entry):
     """Entry containing a Coreboot Filesystem (CBFS)
@@ -165,7 +165,7 @@
     def __init__(self, section, etype, node):
         # Put this here to allow entry-docs and help to work without libfdt
         global state
-        import state
+        from binman import state
 
         Entry.__init__(self, section, etype, node)
         self._cbfs_arg = fdt_util.GetString(node, 'cbfs-arch', 'x86')
diff --git a/tools/binman/etype/cros_ec_rw.py b/tools/binman/etype/cros_ec_rw.py
index 261f865..0dbe14b 100644
--- a/tools/binman/etype/cros_ec_rw.py
+++ b/tools/binman/etype/cros_ec_rw.py
@@ -5,7 +5,7 @@
 # Entry-type module for a Chromium OS EC image (read-write section)
 #
 
-from blob_named_by_arg import Entry_blob_named_by_arg
+from binman.etype.blob_named_by_arg import Entry_blob_named_by_arg
 
 
 class Entry_cros_ec_rw(Entry_blob_named_by_arg):
diff --git a/tools/binman/etype/fdtmap.py b/tools/binman/etype/fdtmap.py
index 5dc08b8..aa88079 100644
--- a/tools/binman/etype/fdtmap.py
+++ b/tools/binman/etype/fdtmap.py
@@ -8,9 +8,9 @@
 image.
 """
 
-from entry import Entry
-import tools
-import tout
+from binman.entry import Entry
+from patman import tools
+from patman import tout
 
 FDTMAP_MAGIC   = b'_FDTMAP_'
 FDTMAP_HDR_LEN = 16
@@ -82,8 +82,8 @@
         global Fdt
 
         import libfdt
-        import state
-        from fdt import Fdt
+        from binman import state
+        from dtoc.fdt import Fdt
 
         Entry.__init__(self, section, etype, node)
 
diff --git a/tools/binman/etype/files.py b/tools/binman/etype/files.py
index 3473a2b..10ab585 100644
--- a/tools/binman/etype/files.py
+++ b/tools/binman/etype/files.py
@@ -9,9 +9,9 @@
 import glob
 import os
 
-from section import Entry_section
-import fdt_util
-import tools
+from binman.etype.section import Entry_section
+from dtoc import fdt_util
+from patman import tools
 
 
 class Entry_files(Entry_section):
@@ -30,7 +30,7 @@
     def __init__(self, section, etype, node):
         # Put this here to allow entry-docs and help to work without libfdt
         global state
-        import state
+        from binman import state
 
         Entry_section.__init__(self, section, etype, node)
         self._pattern = fdt_util.GetString(self._node, 'pattern')
diff --git a/tools/binman/etype/fill.py b/tools/binman/etype/fill.py
index 623b7f4..860410e 100644
--- a/tools/binman/etype/fill.py
+++ b/tools/binman/etype/fill.py
@@ -3,9 +3,9 @@
 # Written by Simon Glass <sjg@chromium.org>
 #
 
-from entry import Entry
-import fdt_util
-import tools
+from binman.entry import Entry
+from dtoc import fdt_util
+from patman import tools
 
 class Entry_fill(Entry):
     """An entry which is filled to a particular byte value
diff --git a/tools/binman/etype/fmap.py b/tools/binman/etype/fmap.py
index 835ba50..a43fac3 100644
--- a/tools/binman/etype/fmap.py
+++ b/tools/binman/etype/fmap.py
@@ -5,11 +5,11 @@
 # Entry-type module for a Flash map, as used by the flashrom SPI flash tool
 #
 
-from entry import Entry
-import fmap_util
-import tools
-from tools import ToHexSize
-import tout
+from binman.entry import Entry
+from binman import fmap_util
+from patman import tools
+from patman.tools import ToHexSize
+from patman import tout
 
 
 class Entry_fmap(Entry):
diff --git a/tools/binman/etype/gbb.py b/tools/binman/etype/gbb.py
index a94c0fc..dd10599 100644
--- a/tools/binman/etype/gbb.py
+++ b/tools/binman/etype/gbb.py
@@ -8,11 +8,11 @@
 
 from collections import OrderedDict
 
-import command
-from entry import Entry, EntryArg
+from patman import command
+from binman.entry import Entry, EntryArg
 
-import fdt_util
-import tools
+from dtoc import fdt_util
+from patman import tools
 
 # Build GBB flags.
 # (src/platform/vboot_reference/firmware/include/gbb_header.h)
diff --git a/tools/binman/etype/image_header.py b/tools/binman/etype/image_header.py
index b9327dd..176bdeb 100644
--- a/tools/binman/etype/image_header.py
+++ b/tools/binman/etype/image_header.py
@@ -11,8 +11,8 @@
 
 import struct
 
-from entry import Entry
-import fdt_util
+from binman.entry import Entry
+from dtoc import fdt_util
 
 IMAGE_HEADER_MAGIC = b'BinM'
 IMAGE_HEADER_LEN   = 8
diff --git a/tools/binman/etype/intel_cmc.py b/tools/binman/etype/intel_cmc.py
index fa6f779..5e6edbe 100644
--- a/tools/binman/etype/intel_cmc.py
+++ b/tools/binman/etype/intel_cmc.py
@@ -5,8 +5,8 @@
 # Entry-type module for Intel Chip Microcode binary blob
 #
 
-from entry import Entry
-from blob import Entry_blob
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
 
 class Entry_intel_cmc(Entry_blob):
     """Entry containing an Intel Chipset Micro Code (CMC) file
diff --git a/tools/binman/etype/intel_descriptor.py b/tools/binman/etype/intel_descriptor.py
index b647793..d4d7a26 100644
--- a/tools/binman/etype/intel_descriptor.py
+++ b/tools/binman/etype/intel_descriptor.py
@@ -7,8 +7,8 @@
 
 import struct
 
-from entry import Entry
-from blob import Entry_blob
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
 
 FD_SIGNATURE   = struct.pack('<L', 0x0ff0a55a)
 MAX_REGIONS    = 5
diff --git a/tools/binman/etype/intel_fit.py b/tools/binman/etype/intel_fit.py
index 2a34a05..ea482a6 100644
--- a/tools/binman/etype/intel_fit.py
+++ b/tools/binman/etype/intel_fit.py
@@ -7,7 +7,7 @@
 
 import struct
 
-from blob import Entry_blob
+from binman.etype.blob import Entry_blob
 
 class Entry_intel_fit(Entry_blob):
     """Intel Firmware Image Table (FIT)
diff --git a/tools/binman/etype/intel_fit_ptr.py b/tools/binman/etype/intel_fit_ptr.py
index 148b206..df118a6 100644
--- a/tools/binman/etype/intel_fit_ptr.py
+++ b/tools/binman/etype/intel_fit_ptr.py
@@ -7,7 +7,7 @@
 
 import struct
 
-from blob import Entry_blob
+from binman.etype.blob import Entry_blob
 
 class Entry_intel_fit_ptr(Entry_blob):
     """Intel Firmware Image Table (FIT) pointer
diff --git a/tools/binman/etype/intel_fsp.py b/tools/binman/etype/intel_fsp.py
index 00a78e7..7db3d96 100644
--- a/tools/binman/etype/intel_fsp.py
+++ b/tools/binman/etype/intel_fsp.py
@@ -5,8 +5,8 @@
 # Entry-type module for Intel Firmware Support Package binary blob
 #
 
-from entry import Entry
-from blob import Entry_blob
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
 
 class Entry_intel_fsp(Entry_blob):
     """Entry containing an Intel Firmware Support Package (FSP) file
diff --git a/tools/binman/etype/intel_fsp_m.py b/tools/binman/etype/intel_fsp_m.py
index bb1de73..51b4e7e 100644
--- a/tools/binman/etype/intel_fsp_m.py
+++ b/tools/binman/etype/intel_fsp_m.py
@@ -5,8 +5,8 @@
 # Entry-type module for Intel Firmware Support Package binary blob (M section)
 #
 
-from entry import Entry
-from blob import Entry_blob
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
 
 class Entry_intel_fsp_m(Entry_blob):
     """Entry containing Intel Firmware Support Package (FSP) memory init
diff --git a/tools/binman/etype/intel_fsp_s.py b/tools/binman/etype/intel_fsp_s.py
index 3d6900d..b3683e4 100644
--- a/tools/binman/etype/intel_fsp_s.py
+++ b/tools/binman/etype/intel_fsp_s.py
@@ -5,8 +5,8 @@
 # Entry-type module for Intel Firmware Support Package binary blob (S section)
 #
 
-from entry import Entry
-from blob import Entry_blob
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
 
 class Entry_intel_fsp_s(Entry_blob):
     """Entry containing Intel Firmware Support Package (FSP) silicon init
diff --git a/tools/binman/etype/intel_fsp_t.py b/tools/binman/etype/intel_fsp_t.py
index 813a81f..0f196f0 100644
--- a/tools/binman/etype/intel_fsp_t.py
+++ b/tools/binman/etype/intel_fsp_t.py
@@ -5,8 +5,8 @@
 # Entry-type module for Intel Firmware Support Package binary blob (T section)
 #
 
-from entry import Entry
-from blob import Entry_blob
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
 
 class Entry_intel_fsp_t(Entry_blob):
     """Entry containing Intel Firmware Support Package (FSP) temp ram init
diff --git a/tools/binman/etype/intel_ifwi.py b/tools/binman/etype/intel_ifwi.py
index 36aadc2..6a96f6b 100644
--- a/tools/binman/etype/intel_ifwi.py
+++ b/tools/binman/etype/intel_ifwi.py
@@ -7,10 +7,10 @@
 
 from collections import OrderedDict
 
-from entry import Entry
-from blob import Entry_blob
-import fdt_util
-import tools
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
+from dtoc import fdt_util
+from patman import tools
 
 class Entry_intel_ifwi(Entry_blob):
     """Entry containing an Intel Integrated Firmware Image (IFWI) file
diff --git a/tools/binman/etype/intel_me.py b/tools/binman/etype/intel_me.py
index c932ec5..41c9c6b 100644
--- a/tools/binman/etype/intel_me.py
+++ b/tools/binman/etype/intel_me.py
@@ -5,8 +5,8 @@
 # Entry-type module for Intel Management Engine binary blob
 #
 
-from entry import Entry
-from blob import Entry_blob
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
 
 class Entry_intel_me(Entry_blob):
     """Entry containing an Intel Management Engine (ME) file
diff --git a/tools/binman/etype/intel_mrc.py b/tools/binman/etype/intel_mrc.py
index 4dbc99a..854a4dd 100644
--- a/tools/binman/etype/intel_mrc.py
+++ b/tools/binman/etype/intel_mrc.py
@@ -5,8 +5,8 @@
 # Entry-type module for Intel Memory Reference Code binary blob
 #
 
-from entry import Entry
-from blob import Entry_blob
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
 
 class Entry_intel_mrc(Entry_blob):
     """Entry containing an Intel Memory Reference Code (MRC) file
diff --git a/tools/binman/etype/intel_refcode.py b/tools/binman/etype/intel_refcode.py
index 045db58..a1059f7 100644
--- a/tools/binman/etype/intel_refcode.py
+++ b/tools/binman/etype/intel_refcode.py
@@ -5,8 +5,8 @@
 # Entry-type module for Intel Memory Reference Code binary blob
 #
 
-from entry import Entry
-from blob import Entry_blob
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
 
 class Entry_intel_refcode(Entry_blob):
     """Entry containing an Intel Reference Code file
diff --git a/tools/binman/etype/intel_vbt.py b/tools/binman/etype/intel_vbt.py
index d93dd19..4d465ad 100644
--- a/tools/binman/etype/intel_vbt.py
+++ b/tools/binman/etype/intel_vbt.py
@@ -4,8 +4,8 @@
 # Entry-type module for Intel Video BIOS Table binary blob
 #
 
-from entry import Entry
-from blob import Entry_blob
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
 
 class Entry_intel_vbt(Entry_blob):
     """Entry containing an Intel Video BIOS Table (VBT) file
diff --git a/tools/binman/etype/intel_vga.py b/tools/binman/etype/intel_vga.py
index 40982c8..04cd72f 100644
--- a/tools/binman/etype/intel_vga.py
+++ b/tools/binman/etype/intel_vga.py
@@ -5,8 +5,8 @@
 # Entry-type module for x86 VGA ROM binary blob
 #
 
-from entry import Entry
-from blob import Entry_blob
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
 
 class Entry_intel_vga(Entry_blob):
     """Entry containing an Intel Video Graphics Adaptor (VGA) file
diff --git a/tools/binman/etype/powerpc_mpc85xx_bootpg_resetvec.py b/tools/binman/etype/powerpc_mpc85xx_bootpg_resetvec.py
index 59fedd2..cefd425 100644
--- a/tools/binman/etype/powerpc_mpc85xx_bootpg_resetvec.py
+++ b/tools/binman/etype/powerpc_mpc85xx_bootpg_resetvec.py
@@ -4,8 +4,8 @@
 # Entry-type module for the PowerPC mpc85xx bootpg and resetvec code for U-Boot
 #
 
-from entry import Entry
-from blob import Entry_blob
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
 
 class Entry_powerpc_mpc85xx_bootpg_resetvec(Entry_blob):
     """PowerPC mpc85xx bootpg + resetvec code for U-Boot
diff --git a/tools/binman/etype/section.py b/tools/binman/etype/section.py
index 89b7bf6..91b8e0c 100644
--- a/tools/binman/etype/section.py
+++ b/tools/binman/etype/section.py
@@ -8,16 +8,14 @@
 images to be created.
 """
 
-from __future__ import print_function
-
 from collections import OrderedDict
 import re
 import sys
 
-from entry import Entry
-import fdt_util
-import tools
-import tout
+from binman.entry import Entry
+from dtoc import fdt_util
+from patman import tools
+from patman import tout
 
 
 class Entry_section(Entry):
diff --git a/tools/binman/etype/text.py b/tools/binman/etype/text.py
index da1813a..3577135 100644
--- a/tools/binman/etype/text.py
+++ b/tools/binman/etype/text.py
@@ -5,9 +5,9 @@
 
 from collections import OrderedDict
 
-from entry import Entry, EntryArg
-import fdt_util
-import tools
+from binman.entry import Entry, EntryArg
+from dtoc import fdt_util
+from patman import tools
 
 
 class Entry_text(Entry):
diff --git a/tools/binman/etype/u_boot.py b/tools/binman/etype/u_boot.py
index 23dd12c..ab1019b 100644
--- a/tools/binman/etype/u_boot.py
+++ b/tools/binman/etype/u_boot.py
@@ -5,8 +5,8 @@
 # Entry-type module for U-Boot binary
 #
 
-from entry import Entry
-from blob import Entry_blob
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
 
 class Entry_u_boot(Entry_blob):
     """U-Boot flat binary
diff --git a/tools/binman/etype/u_boot_dtb.py b/tools/binman/etype/u_boot_dtb.py
index 6c805a6..e983500 100644
--- a/tools/binman/etype/u_boot_dtb.py
+++ b/tools/binman/etype/u_boot_dtb.py
@@ -5,8 +5,8 @@
 # Entry-type module for U-Boot device tree
 #
 
-from entry import Entry
-from blob_dtb import Entry_blob_dtb
+from binman.entry import Entry
+from binman.etype.blob_dtb import Entry_blob_dtb
 
 class Entry_u_boot_dtb(Entry_blob_dtb):
     """U-Boot device tree
diff --git a/tools/binman/etype/u_boot_dtb_with_ucode.py b/tools/binman/etype/u_boot_dtb_with_ucode.py
index 6efd24a..aec1455 100644
--- a/tools/binman/etype/u_boot_dtb_with_ucode.py
+++ b/tools/binman/etype/u_boot_dtb_with_ucode.py
@@ -5,9 +5,9 @@
 # Entry-type module for U-Boot device tree with the microcode removed
 #
 
-from entry import Entry
-from blob_dtb import Entry_blob_dtb
-import tools
+from binman.entry import Entry
+from binman.etype.blob_dtb import Entry_blob_dtb
+from patman import tools
 
 class Entry_u_boot_dtb_with_ucode(Entry_blob_dtb):
     """A U-Boot device tree file, with the microcode removed
@@ -26,7 +26,7 @@
     def __init__(self, section, etype, node):
         # Put this here to allow entry-docs and help to work without libfdt
         global state
-        import state
+        from binman import state
 
         Entry_blob_dtb.__init__(self, section, etype, node)
         self.ucode_data = b''
@@ -44,7 +44,7 @@
 
     def ProcessFdt(self, fdt):
         # So the module can be loaded without it
-        import fdt
+        from dtoc import fdt
 
         # If the section does not need microcode, there is nothing to do
         ucode_dest_entry = self.section.FindEntryType(
diff --git a/tools/binman/etype/u_boot_elf.py b/tools/binman/etype/u_boot_elf.py
index f83860d..5f906e5 100644
--- a/tools/binman/etype/u_boot_elf.py
+++ b/tools/binman/etype/u_boot_elf.py
@@ -5,11 +5,11 @@
 # Entry-type module for U-Boot ELF image
 #
 
-from entry import Entry
-from blob import Entry_blob
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
 
-import fdt_util
-import tools
+from dtoc import fdt_util
+from patman import tools
 
 class Entry_u_boot_elf(Entry_blob):
     """U-Boot ELF image
diff --git a/tools/binman/etype/u_boot_img.py b/tools/binman/etype/u_boot_img.py
index 1ec0757..50cc71d 100644
--- a/tools/binman/etype/u_boot_img.py
+++ b/tools/binman/etype/u_boot_img.py
@@ -5,8 +5,8 @@
 # Entry-type module for U-Boot binary
 #
 
-from entry import Entry
-from blob import Entry_blob
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
 
 class Entry_u_boot_img(Entry_blob):
     """U-Boot legacy image
diff --git a/tools/binman/etype/u_boot_nodtb.py b/tools/binman/etype/u_boot_nodtb.py
index a4b95a4..e8c0e1a 100644
--- a/tools/binman/etype/u_boot_nodtb.py
+++ b/tools/binman/etype/u_boot_nodtb.py
@@ -5,8 +5,8 @@
 # Entry-type module for 'u-boot-nodtb.bin'
 #
 
-from entry import Entry
-from blob import Entry_blob
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
 
 class Entry_u_boot_nodtb(Entry_blob):
     """U-Boot flat binary without device tree appended
diff --git a/tools/binman/etype/u_boot_spl.py b/tools/binman/etype/u_boot_spl.py
index 7fedd00..a6fddbe 100644
--- a/tools/binman/etype/u_boot_spl.py
+++ b/tools/binman/etype/u_boot_spl.py
@@ -5,10 +5,9 @@
 # Entry-type module for spl/u-boot-spl.bin
 #
 
-import elf
-
-from entry import Entry
-from blob import Entry_blob
+from binman import elf
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
 
 class Entry_u_boot_spl(Entry_blob):
     """U-Boot SPL binary
diff --git a/tools/binman/etype/u_boot_spl_bss_pad.py b/tools/binman/etype/u_boot_spl_bss_pad.py
index 66a296a..a6a177a 100644
--- a/tools/binman/etype/u_boot_spl_bss_pad.py
+++ b/tools/binman/etype/u_boot_spl_bss_pad.py
@@ -7,11 +7,11 @@
 # to it will appear to SPL to be at the end of BSS rather than the start.
 #
 
-import command
-import elf
-from entry import Entry
-from blob import Entry_blob
-import tools
+from binman import elf
+from binman.entry import Entry
+from patman import command
+from binman.etype.blob import Entry_blob
+from patman import tools
 
 class Entry_u_boot_spl_bss_pad(Entry_blob):
     """U-Boot SPL binary padded with a BSS region
diff --git a/tools/binman/etype/u_boot_spl_dtb.py b/tools/binman/etype/u_boot_spl_dtb.py
index 1bcd449..a0761ee 100644
--- a/tools/binman/etype/u_boot_spl_dtb.py
+++ b/tools/binman/etype/u_boot_spl_dtb.py
@@ -5,8 +5,8 @@
 # Entry-type module for U-Boot device tree in SPL (Secondary Program Loader)
 #
 
-from entry import Entry
-from blob_dtb import Entry_blob_dtb
+from binman.entry import Entry
+from binman.etype.blob_dtb import Entry_blob_dtb
 
 class Entry_u_boot_spl_dtb(Entry_blob_dtb):
     """U-Boot SPL device tree
diff --git a/tools/binman/etype/u_boot_spl_elf.py b/tools/binman/etype/u_boot_spl_elf.py
index 24ee772..f99f74a 100644
--- a/tools/binman/etype/u_boot_spl_elf.py
+++ b/tools/binman/etype/u_boot_spl_elf.py
@@ -5,8 +5,8 @@
 # Entry-type module for U-Boot SPL ELF image
 #
 
-from entry import Entry
-from blob import Entry_blob
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
 
 class Entry_u_boot_spl_elf(Entry_blob):
     """U-Boot SPL ELF image
diff --git a/tools/binman/etype/u_boot_spl_nodtb.py b/tools/binman/etype/u_boot_spl_nodtb.py
index 41c1736..072b915 100644
--- a/tools/binman/etype/u_boot_spl_nodtb.py
+++ b/tools/binman/etype/u_boot_spl_nodtb.py
@@ -5,8 +5,8 @@
 # Entry-type module for 'u-boot-nodtb.bin'
 #
 
-from entry import Entry
-from blob import Entry_blob
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
 
 class Entry_u_boot_spl_nodtb(Entry_blob):
     """SPL binary without device tree appended
diff --git a/tools/binman/etype/u_boot_spl_with_ucode_ptr.py b/tools/binman/etype/u_boot_spl_with_ucode_ptr.py
index b650cf0..b1543a5 100644
--- a/tools/binman/etype/u_boot_spl_with_ucode_ptr.py
+++ b/tools/binman/etype/u_boot_spl_with_ucode_ptr.py
@@ -7,11 +7,7 @@
 
 import struct
 
-import command
-from entry import Entry
-from blob import Entry_blob
-from u_boot_with_ucode_ptr import Entry_u_boot_with_ucode_ptr
-import tools
+from binman.etype.u_boot_with_ucode_ptr import Entry_u_boot_with_ucode_ptr
 
 class Entry_u_boot_spl_with_ucode_ptr(Entry_u_boot_with_ucode_ptr):
     """U-Boot SPL with embedded microcode pointer
diff --git a/tools/binman/etype/u_boot_tpl.py b/tools/binman/etype/u_boot_tpl.py
index 1b69c4f..6562457 100644
--- a/tools/binman/etype/u_boot_tpl.py
+++ b/tools/binman/etype/u_boot_tpl.py
@@ -5,10 +5,9 @@
 # Entry-type module for tpl/u-boot-tpl.bin
 #
 
-import elf
-
-from entry import Entry
-from blob import Entry_blob
+from binman import elf
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
 
 class Entry_u_boot_tpl(Entry_blob):
     """U-Boot TPL binary
diff --git a/tools/binman/etype/u_boot_tpl_dtb.py b/tools/binman/etype/u_boot_tpl_dtb.py
index 81a3970..890155f 100644
--- a/tools/binman/etype/u_boot_tpl_dtb.py
+++ b/tools/binman/etype/u_boot_tpl_dtb.py
@@ -5,8 +5,8 @@
 # Entry-type module for U-Boot device tree in TPL (Tertiary Program Loader)
 #
 
-from entry import Entry
-from blob_dtb import Entry_blob_dtb
+from binman.entry import Entry
+from binman.etype.blob_dtb import Entry_blob_dtb
 
 class Entry_u_boot_tpl_dtb(Entry_blob_dtb):
     """U-Boot TPL device tree
diff --git a/tools/binman/etype/u_boot_tpl_dtb_with_ucode.py b/tools/binman/etype/u_boot_tpl_dtb_with_ucode.py
index ce19a49..ca1bf85 100644
--- a/tools/binman/etype/u_boot_tpl_dtb_with_ucode.py
+++ b/tools/binman/etype/u_boot_tpl_dtb_with_ucode.py
@@ -5,10 +5,7 @@
 # Entry-type module for U-Boot device tree with the microcode removed
 #
 
-import control
-from entry import Entry
-from u_boot_dtb_with_ucode import Entry_u_boot_dtb_with_ucode
-import tools
+from binman.etype.u_boot_dtb_with_ucode import Entry_u_boot_dtb_with_ucode
 
 class Entry_u_boot_tpl_dtb_with_ucode(Entry_u_boot_dtb_with_ucode):
     """U-Boot TPL with embedded microcode pointer
diff --git a/tools/binman/etype/u_boot_tpl_elf.py b/tools/binman/etype/u_boot_tpl_elf.py
index 9cc1cc2..7fa8e96 100644
--- a/tools/binman/etype/u_boot_tpl_elf.py
+++ b/tools/binman/etype/u_boot_tpl_elf.py
@@ -5,8 +5,8 @@
 # Entry-type module for U-Boot TPL ELF image
 #
 
-from entry import Entry
-from blob import Entry_blob
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
 
 class Entry_u_boot_tpl_elf(Entry_blob):
     """U-Boot TPL ELF image
diff --git a/tools/binman/etype/u_boot_tpl_with_ucode_ptr.py b/tools/binman/etype/u_boot_tpl_with_ucode_ptr.py
index 8d94dde..7f7fab7 100644
--- a/tools/binman/etype/u_boot_tpl_with_ucode_ptr.py
+++ b/tools/binman/etype/u_boot_tpl_with_ucode_ptr.py
@@ -7,11 +7,11 @@
 
 import struct
 
-import command
-from entry import Entry
-from blob import Entry_blob
-from u_boot_with_ucode_ptr import Entry_u_boot_with_ucode_ptr
-import tools
+from patman import command
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
+from binman.etype.u_boot_with_ucode_ptr import Entry_u_boot_with_ucode_ptr
+from patman import tools
 
 class Entry_u_boot_tpl_with_ucode_ptr(Entry_u_boot_with_ucode_ptr):
     """U-Boot TPL with embedded microcode pointer
diff --git a/tools/binman/etype/u_boot_ucode.py b/tools/binman/etype/u_boot_ucode.py
index dee8848..d9e1a60 100644
--- a/tools/binman/etype/u_boot_ucode.py
+++ b/tools/binman/etype/u_boot_ucode.py
@@ -5,9 +5,9 @@
 # Entry-type module for a U-Boot binary with an embedded microcode pointer
 #
 
-from entry import Entry
-from blob import Entry_blob
-import tools
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
+from patman import tools
 
 class Entry_u_boot_ucode(Entry_blob):
     """U-Boot microcode block
diff --git a/tools/binman/etype/u_boot_with_ucode_ptr.py b/tools/binman/etype/u_boot_with_ucode_ptr.py
index 960a5ef..06047b6 100644
--- a/tools/binman/etype/u_boot_with_ucode_ptr.py
+++ b/tools/binman/etype/u_boot_with_ucode_ptr.py
@@ -7,12 +7,12 @@
 
 import struct
 
-import command
-import elf
-from entry import Entry
-from blob import Entry_blob
-import fdt_util
-import tools
+from binman import elf
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
+from dtoc import fdt_util
+from patman import tools
+from patman import command
 
 class Entry_u_boot_with_ucode_ptr(Entry_blob):
     """U-Boot with embedded microcode pointer
diff --git a/tools/binman/etype/vblock.py b/tools/binman/etype/vblock.py
index 91fa2f7..5753de7 100644
--- a/tools/binman/etype/vblock.py
+++ b/tools/binman/etype/vblock.py
@@ -9,10 +9,10 @@
 from collections import OrderedDict
 import os
 
-from entry import Entry, EntryArg
+from binman.entry import Entry, EntryArg
 
-import fdt_util
-import tools
+from dtoc import fdt_util
+from patman import tools
 
 class Entry_vblock(Entry):
     """An entry which contains a Chromium OS verified boot block
diff --git a/tools/binman/etype/x86_reset16.py b/tools/binman/etype/x86_reset16.py
index 54eb814..ad864e5 100644
--- a/tools/binman/etype/x86_reset16.py
+++ b/tools/binman/etype/x86_reset16.py
@@ -5,8 +5,8 @@
 # Entry-type module for the 16-bit x86 reset code for U-Boot
 #
 
-from entry import Entry
-from blob import Entry_blob
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
 
 class Entry_x86_reset16(Entry_blob):
     """x86 16-bit reset code for U-Boot
diff --git a/tools/binman/etype/x86_reset16_spl.py b/tools/binman/etype/x86_reset16_spl.py
index 699a0c6..9a663f0 100644
--- a/tools/binman/etype/x86_reset16_spl.py
+++ b/tools/binman/etype/x86_reset16_spl.py
@@ -5,8 +5,8 @@
 # Entry-type module for the 16-bit x86 reset code for U-Boot
 #
 
-from entry import Entry
-from blob import Entry_blob
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
 
 class Entry_x86_reset16_spl(Entry_blob):
     """x86 16-bit reset code for U-Boot
diff --git a/tools/binman/etype/x86_reset16_tpl.py b/tools/binman/etype/x86_reset16_tpl.py
index 4eedb8d..864508f 100644
--- a/tools/binman/etype/x86_reset16_tpl.py
+++ b/tools/binman/etype/x86_reset16_tpl.py
@@ -5,8 +5,8 @@
 # Entry-type module for the 16-bit x86 reset code for U-Boot
 #
 
-from entry import Entry
-from blob import Entry_blob
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
 
 class Entry_x86_reset16_tpl(Entry_blob):
     """x86 16-bit reset code for U-Boot
diff --git a/tools/binman/etype/x86_start16.py b/tools/binman/etype/x86_start16.py
index 6736b69..d8345f6 100644
--- a/tools/binman/etype/x86_start16.py
+++ b/tools/binman/etype/x86_start16.py
@@ -5,8 +5,8 @@
 # Entry-type module for the 16-bit x86 start-up code for U-Boot
 #
 
-from entry import Entry
-from blob import Entry_blob
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
 
 class Entry_x86_start16(Entry_blob):
     """x86 16-bit start-up code for U-Boot
diff --git a/tools/binman/etype/x86_start16_spl.py b/tools/binman/etype/x86_start16_spl.py
index c8c7063..ad520d3 100644
--- a/tools/binman/etype/x86_start16_spl.py
+++ b/tools/binman/etype/x86_start16_spl.py
@@ -5,8 +5,8 @@
 # Entry-type module for the 16-bit x86 start-up code for U-Boot SPL
 #
 
-from entry import Entry
-from blob import Entry_blob
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
 
 class Entry_x86_start16_spl(Entry_blob):
     """x86 16-bit start-up code for SPL
diff --git a/tools/binman/etype/x86_start16_tpl.py b/tools/binman/etype/x86_start16_tpl.py
index 5261a8a..ccc8727 100644
--- a/tools/binman/etype/x86_start16_tpl.py
+++ b/tools/binman/etype/x86_start16_tpl.py
@@ -5,8 +5,8 @@
 # Entry-type module for the 16-bit x86 start-up code for U-Boot TPL
 #
 
-from entry import Entry
-from blob import Entry_blob
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
 
 class Entry_x86_start16_tpl(Entry_blob):
     """x86 16-bit start-up code for TPL
diff --git a/tools/binman/fdt_test.py b/tools/binman/fdt_test.py
index ac6f910..c491d40 100644
--- a/tools/binman/fdt_test.py
+++ b/tools/binman/fdt_test.py
@@ -9,10 +9,10 @@
 import tempfile
 import unittest
 
-import fdt
-from fdt import FdtScan
-import fdt_util
-import tools
+from dtoc import fdt
+from dtoc import fdt_util
+from dtoc.fdt import FdtScan
+from patman import tools
 
 class TestFdt(unittest.TestCase):
     @classmethod
diff --git a/tools/binman/fmap_util.py b/tools/binman/fmap_util.py
index d0f956b..25fe60a 100644
--- a/tools/binman/fmap_util.py
+++ b/tools/binman/fmap_util.py
@@ -10,7 +10,7 @@
 import struct
 import sys
 
-import tools
+from patman import tools
 
 # constants imported from lib/fmap.h
 FMAP_SIGNATURE = b'__FMAP__'
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index 872b855..5e24920 100644
--- a/tools/binman/ftest.py
+++ b/tools/binman/ftest.py
@@ -6,8 +6,7 @@
 #
 #    python -m unittest func_test.TestFunctional.testHelp
 
-from __future__ import print_function
-
+import gzip
 import hashlib
 from optparse import OptionParser
 import os
@@ -17,24 +16,23 @@
 import tempfile
 import unittest
 
-import binman
-import cbfs_util
-import cmdline
-import command
-import control
-import elf
-import elf_test
-import fdt
-from etype import fdtmap
-from etype import image_header
-import fdt_util
-import fmap_util
-import test_util
-import gzip
+from binman import cbfs_util
+from binman import cmdline
+from binman import control
+from binman import elf
+from binman import elf_test
+from binman import fmap_util
+from binman import main
+from binman import state
+from dtoc import fdt
+from dtoc import fdt_util
+from binman.etype import fdtmap
+from binman.etype import image_header
 from image import Image
-import state
-import tools
-import tout
+from patman import command
+from patman import test_util
+from patman import tools
+from patman import tout
 
 # Contents of test files, corresponding to different entry types
 U_BOOT_DATA           = b'1234'
@@ -103,7 +101,7 @@
     @classmethod
     def setUpClass(cls):
         global entry
-        import entry
+        from binman import entry
 
         # Handle the case where argv[0] is 'python'
         cls._binman_dir = os.path.dirname(os.path.realpath(sys.argv[0]))
@@ -1290,8 +1288,8 @@
         with self.assertRaises(ValueError) as e:
             self._DoReadFile('057_unknown_contents.dts', True)
         self.assertIn("Image '/binman': Internal error: Could not complete "
-                "processing of contents: remaining [<_testing.Entry__testing ",
-                str(e.exception))
+                "processing of contents: remaining ["
+                "<binman.etype._testing.Entry__testing ", str(e.exception))
 
     def testBadChangeSize(self):
         """Test that trying to change the size of an entry fails"""
@@ -1338,7 +1336,8 @@
         with self.assertRaises(ValueError) as e:
             self._DoReadFileDtb('061_fdt_update_bad.dts', update_dtb=True)
         self.assertIn('Could not complete processing of Fdt: remaining '
-                      '[<_testing.Entry__testing', str(e.exception))
+                      '[<binman.etype._testing.Entry__testing',
+                        str(e.exception))
 
     def testEntryArgs(self):
         """Test passing arguments to entries from the command line"""
@@ -1430,14 +1429,14 @@
     def testEntryDocs(self):
         """Test for creation of entry documentation"""
         with test_util.capture_sys_output() as (stdout, stderr):
-            control.WriteEntryDocs(binman.GetEntryModules())
+            control.WriteEntryDocs(main.GetEntryModules())
         self.assertTrue(len(stdout.getvalue()) > 0)
 
     def testEntryDocsMissing(self):
         """Test handling of missing entry documentation"""
         with self.assertRaises(ValueError) as e:
             with test_util.capture_sys_output() as (stdout, stderr):
-                control.WriteEntryDocs(binman.GetEntryModules(), 'u_boot')
+                control.WriteEntryDocs(main.GetEntryModules(), 'u_boot')
         self.assertIn('Documentation is missing for modules: u_boot',
                       str(e.exception))
 
diff --git a/tools/binman/image.py b/tools/binman/image.py
index 2beab7f..523b274 100644
--- a/tools/binman/image.py
+++ b/tools/binman/image.py
@@ -5,8 +5,6 @@
 # Class for an image, the output of binman
 #
 
-from __future__ import print_function
-
 from collections import OrderedDict
 import fnmatch
 from operator import attrgetter
@@ -14,14 +12,14 @@
 import re
 import sys
 
-from entry import Entry
-from etype import fdtmap
-from etype import image_header
-from etype import section
-import fdt
-import fdt_util
-import tools
-import tout
+from binman.entry import Entry
+from binman.etype import fdtmap
+from binman.etype import image_header
+from binman.etype import section
+from dtoc import fdt
+from dtoc import fdt_util
+from patman import tools
+from patman import tout
 
 class Image(section.Entry_section):
     """A Image, representing an output from binman
diff --git a/tools/binman/image_test.py b/tools/binman/image_test.py
index 10f85d1..f85c3c5 100644
--- a/tools/binman/image_test.py
+++ b/tools/binman/image_test.py
@@ -7,7 +7,7 @@
 import unittest
 
 from image import Image
-from test_util import capture_sys_output
+from patman.test_util import capture_sys_output
 
 class TestImage(unittest.TestCase):
     def testInvalidFormat(self):
diff --git a/tools/binman/main.py b/tools/binman/main.py
new file mode 100755
index 0000000..efa7fa8
--- /dev/null
+++ b/tools/binman/main.py
@@ -0,0 +1,138 @@
+#!/usr/bin/env python3
+# SPDX-License-Identifier: GPL-2.0+
+
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# Creates binary images from input files controlled by a description
+#
+
+"""See README for more information"""
+
+from distutils.sysconfig import get_python_lib
+import glob
+import os
+import site
+import sys
+import traceback
+import unittest
+
+# Bring in the patman and dtoc libraries (but don't override the first path
+# in PYTHONPATH)
+our_path = os.path.dirname(os.path.realpath(__file__))
+sys.path.insert(2, os.path.join(our_path, '..'))
+
+from patman import test_util
+
+# Bring in the libfdt module
+sys.path.insert(2, 'scripts/dtc/pylibfdt')
+sys.path.insert(2, os.path.join(our_path,
+                '../../build-sandbox_spl/scripts/dtc/pylibfdt'))
+
+# When running under python-coverage on Ubuntu 16.04, the dist-packages
+# directories are dropped from the python path. Add them in so that we can find
+# the elffile module. We could use site.getsitepackages() here but unfortunately
+# that is not available in a virtualenv.
+sys.path.append(get_python_lib())
+
+from binman import cmdline
+from binman import control
+from patman import test_util
+
+def RunTests(debug, verbosity, processes, test_preserve_dirs, args, toolpath):
+    """Run the functional tests and any embedded doctests
+
+    Args:
+        debug: True to enable debugging, which shows a full stack trace on error
+        verbosity: Verbosity level to use
+        test_preserve_dirs: True to preserve the input directory used by tests
+            so that it can be examined afterwards (only useful for debugging
+            tests). If a single test is selected (in args[0]) it also preserves
+            the output directory for this test. Both directories are displayed
+            on the command line.
+        processes: Number of processes to use to run tests (None=same as #CPUs)
+        args: List of positional args provided to binman. This can hold a test
+            name to execute (as in 'binman test testSections', for example)
+        toolpath: List of paths to use for tools
+    """
+    from binman import cbfs_util_test
+    from binman import elf_test
+    from binman import entry_test
+    from binman import fdt_test
+    from binman import ftest
+    from binman import image_test
+    from binman import test
+    import doctest
+
+    result = unittest.TestResult()
+    test_name = args and args[0] or None
+
+    # Run the entry tests first ,since these need to be the first to import the
+    # 'entry' module.
+    test_util.RunTestSuites(
+        result, debug, verbosity, test_preserve_dirs, processes, test_name,
+        toolpath,
+        [entry_test.TestEntry, ftest.TestFunctional, fdt_test.TestFdt,
+         elf_test.TestElf, image_test.TestImage, cbfs_util_test.TestCbfs])
+
+    return test_util.ReportResult('binman', test_name, result)
+
+def GetEntryModules(include_testing=True):
+    """Get a set of entry class implementations
+
+    Returns:
+        Set of paths to entry class filenames
+    """
+    glob_list = glob.glob(os.path.join(our_path, 'etype/*.py'))
+    return set([os.path.splitext(os.path.basename(item))[0]
+                for item in glob_list
+                if include_testing or '_testing' not in item])
+
+def RunTestCoverage():
+    """Run the tests and check that we get 100% coverage"""
+    glob_list = GetEntryModules(False)
+    all_set = set([os.path.splitext(os.path.basename(item))[0]
+                   for item in glob_list if '_testing' not in item])
+    test_util.RunTestCoverage('tools/binman/binman', None,
+            ['*test*', '*main.py', 'tools/patman/*', 'tools/dtoc/*'],
+            args.build_dir, all_set)
+
+def RunBinman(args):
+    """Main entry point to binman once arguments are parsed
+
+    Args:
+        args: Command line arguments Namespace object
+    """
+    ret_code = 0
+
+    if not args.debug:
+        sys.tracebacklimit = 0
+
+    if args.cmd == 'test':
+        if args.test_coverage:
+            RunTestCoverage()
+        else:
+            ret_code = RunTests(args.debug, args.verbosity, args.processes,
+                                args.test_preserve_dirs, args.tests,
+                                args.toolpath)
+
+    elif args.cmd == 'entry-docs':
+        control.WriteEntryDocs(GetEntryModules())
+
+    else:
+        try:
+            ret_code = control.Binman(args)
+        except Exception as e:
+            print('binman: %s' % e)
+            if args.debug:
+                print()
+                traceback.print_exc()
+            ret_code = 1
+    return ret_code
+
+
+if __name__ == "__main__":
+    args = cmdline.ParseArgs(sys.argv[1:])
+
+    ret_code = RunBinman(args)
+    sys.exit(ret_code)
diff --git a/tools/binman/state.py b/tools/binman/state.py
index d704ed2..36bc513 100644
--- a/tools/binman/state.py
+++ b/tools/binman/state.py
@@ -8,10 +8,10 @@
 import hashlib
 import re
 
-import fdt
+from dtoc import fdt
 import os
-import tools
-import tout
+from patman import tools
+from patman import tout
 
 # Records the device-tree files known to binman, keyed by entry type (e.g.
 # 'u-boot-spl-dtb'). These are the output FDT files, which can be updated by
@@ -167,8 +167,8 @@
     global output_fdt_info, main_dtb, fdt_path_prefix
     # Import these here in case libfdt.py is not available, in which case
     # the above help option still works.
-    import fdt
-    import fdt_util
+    from dtoc import fdt
+    from dtoc import fdt_util
 
     # If we are updating the DTBs we need to put these updated versions
     # where Entry_blob_dtb can find them. We can ignore 'u-boot.dtb'
diff --git a/tools/buildman/README b/tools/buildman/README
index f3a0dc7..b2f983c 100644
--- a/tools/buildman/README
+++ b/tools/buildman/README
@@ -1091,7 +1091,8 @@
 
    buildman -o /tmp/build --board sandbox -w
 
-This will write the full build into /tmp/build including object files.
+This will write the full build into /tmp/build including object files. You must
+specify the output directory with -o when using -w.
 
 
 Other options
diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py
index 30ebe1d..f8e71de 100644
--- a/tools/buildman/builder.py
+++ b/tools/buildman/builder.py
@@ -17,12 +17,12 @@
 import threading
 import time
 
-import builderthread
-import command
-import gitutil
-import terminal
-from terminal import Print
-import toolchain
+from buildman import builderthread
+from buildman import toolchain
+from patman import command
+from patman import gitutil
+from patman import terminal
+from patman.terminal import Print
 
 """
 Theory of Operation
@@ -479,6 +479,9 @@
         Args:
             commit_upto: Commit number to use (0..self.count-1)
         """
+        if self.work_in_output:
+            return self._working_dir
+
         commit_dir = None
         if self.commits:
             commit = self.commits[commit_upto]
@@ -502,6 +505,8 @@
             target: Target name
         """
         output_dir = self._GetOutputDir(commit_upto)
+        if self.work_in_output:
+            return output_dir
         return os.path.join(output_dir, target)
 
     def GetDoneFile(self, commit_upto, target):
diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py
index fc6e1ab..48fcd6c 100644
--- a/tools/buildman/builderthread.py
+++ b/tools/buildman/builderthread.py
@@ -9,8 +9,8 @@
 import sys
 import threading
 
-import command
-import gitutil
+from patman import command
+from patman import gitutil
 
 RETURN_CODE_RETRY = -1
 
@@ -280,8 +280,6 @@
             work_in_output: Use the output directory as the work directory and
                 don't write to a separate output directory.
         """
-        if work_in_output:
-            return
         # Fatal error
         if result.return_code < 0:
             return
@@ -333,7 +331,7 @@
 
             # Write out the image and function size information and an objdump
             env = result.toolchain.MakeEnvironment(self.builder.full_path)
-            with open(os.path.join(build_dir, 'env'), 'w') as fd:
+            with open(os.path.join(build_dir, 'out-env'), 'w') as fd:
                 for var in sorted(env.keys()):
                     print('%s="%s"' % (var, env[var]), file=fd)
             lines = []
@@ -379,7 +377,8 @@
                             capture_stderr=True, cwd=result.out_dir,
                             raise_on_error=False, env=env)
             ubootenv = os.path.join(result.out_dir, 'uboot.env')
-            self.CopyFiles(result.out_dir, build_dir, '', ['uboot.env'])
+            if not work_in_output:
+                self.CopyFiles(result.out_dir, build_dir, '', ['uboot.env'])
 
             # Write out the image sizes file. This is similar to the output
             # of binutil's 'size' utility, but it omits the header line and
@@ -391,17 +390,21 @@
                 with open(sizes, 'w') as fd:
                     print('\n'.join(lines), file=fd)
 
-        # Write out the configuration files, with a special case for SPL
-        for dirname in ['', 'spl', 'tpl']:
-            self.CopyFiles(result.out_dir, build_dir, dirname, ['u-boot.cfg',
-                'spl/u-boot-spl.cfg', 'tpl/u-boot-tpl.cfg', '.config',
-                'include/autoconf.mk', 'include/generated/autoconf.h'])
+        if not work_in_output:
+            # Write out the configuration files, with a special case for SPL
+            for dirname in ['', 'spl', 'tpl']:
+                self.CopyFiles(
+                    result.out_dir, build_dir, dirname,
+                    ['u-boot.cfg', 'spl/u-boot-spl.cfg', 'tpl/u-boot-tpl.cfg',
+                     '.config', 'include/autoconf.mk',
+                     'include/generated/autoconf.h'])
 
-        # Now write the actual build output
-        if keep_outputs:
-            self.CopyFiles(result.out_dir, build_dir, '', ['u-boot*', '*.bin',
-                '*.map', '*.img', 'MLO', 'SPL', 'include/autoconf.mk',
-                'spl/u-boot-spl*'])
+            # Now write the actual build output
+            if keep_outputs:
+                self.CopyFiles(
+                    result.out_dir, build_dir, '',
+                    ['u-boot*', '*.bin', '*.map', '*.img', 'MLO', 'SPL',
+                     'include/autoconf.mk', 'spl/u-boot-spl*'])
 
     def CopyFiles(self, out_dir, build_dir, dirname, patterns):
         """Copy files from the build directory to the output.
diff --git a/tools/buildman/buildman b/tools/buildman/buildman
index e4fba2d..11a5d8e 120000
--- a/tools/buildman/buildman
+++ b/tools/buildman/buildman
@@ -1 +1 @@
-buildman.py
\ No newline at end of file
+main.py
\ No newline at end of file
diff --git a/tools/buildman/cmdline.py b/tools/buildman/cmdline.py
index 1377b9d..680c072 100644
--- a/tools/buildman/cmdline.py
+++ b/tools/buildman/cmdline.py
@@ -76,8 +76,7 @@
           default=False, help="Do a dry run (describe actions, but do nothing)")
     parser.add_option('-N', '--no-subdirs', action='store_true', dest='no_subdirs',
           default=False, help="Don't create subdirectories when building current source for a single board")
-    parser.add_option('-o', '--output-dir', type='string',
-          dest='output_dir', default='..',
+    parser.add_option('-o', '--output-dir', type='string', dest='output_dir',
           help='Directory where all builds happen and buildman has its workspace (default is ../)')
     parser.add_option('-O', '--override-toolchain', type='string',
           help="Override host toochain to use for sandbox (e.g. 'clang-7')")
diff --git a/tools/buildman/control.py b/tools/buildman/control.py
index 30c030f..071c261 100644
--- a/tools/buildman/control.py
+++ b/tools/buildman/control.py
@@ -5,18 +5,18 @@
 import multiprocessing
 import os
 import shutil
+import subprocess
 import sys
 
-import board
-import bsettings
-from builder import Builder
-import gitutil
-import patchstream
-import terminal
-from terminal import Print
-import toolchain
-import command
-import subprocess
+from buildman import board
+from buildman import bsettings
+from buildman import toolchain
+from buildman.builder import Builder
+from patman import command
+from patman import gitutil
+from patman import patchstream
+from patman import terminal
+from patman.terminal import Print
 
 def GetPlural(count):
     """Returns a plural 's' if count is not 1"""
@@ -175,6 +175,10 @@
     if options.incremental:
         print(col.Color(col.RED,
                         'Warning: -I has been removed. See documentation'))
+    if not options.output_dir:
+        if options.work_in_output:
+            sys.exit(col.Color(col.RED, '-w requires that you specify -o'))
+        options.output_dir = '..'
 
     # Work out what subset of the boards we are building
     if not boards:
@@ -207,7 +211,7 @@
         sys.exit(col.Color(col.RED, 'No matching boards found'))
 
     if options.print_prefix:
-        err = ShowToolchainInfo(boards, toolchains)
+        err = ShowToolchainPrefix(boards, toolchains)
         if err:
             sys.exit(col.Color(col.RED, err))
         return 0
diff --git a/tools/buildman/func_test.py b/tools/buildman/func_test.py
index 1fbc6f6..418677f 100644
--- a/tools/buildman/func_test.py
+++ b/tools/buildman/func_test.py
@@ -8,15 +8,15 @@
 import tempfile
 import unittest
 
-import board
-import bsettings
-import cmdline
-import command
-import control
-import gitutil
-import terminal
-import toolchain
-import tools
+from buildman import board
+from buildman import bsettings
+from buildman import cmdline
+from buildman import control
+from buildman import toolchain
+from patman import command
+from patman import gitutil
+from patman import terminal
+from patman import tools
 
 settings_data = '''
 # Buildman settings file
@@ -546,6 +546,13 @@
         self.assertEqual(self._builder.count, self._total_builds)
         self.assertEqual(self._builder.fail, 0)
 
+    def testEnvironment(self):
+        """Test that the done and environment files are written to out-env"""
+        self._RunControl('-o', self._output_dir)
+        board0_dir = os.path.join(self._output_dir, 'current', 'board0')
+        self.assertTrue(os.path.exists(os.path.join(board0_dir, 'done')))
+        self.assertTrue(os.path.exists(os.path.join(board0_dir, 'out-env')))
+
     def testWorkInOutput(self):
         """Test the -w option which should write directly to the output dir"""
         board_list = board.Boards()
@@ -554,6 +561,10 @@
                          boards=board_list)
         self.assertTrue(
             os.path.exists(os.path.join(self._output_dir, 'u-boot')))
+        self.assertTrue(
+            os.path.exists(os.path.join(self._output_dir, 'done')))
+        self.assertTrue(
+            os.path.exists(os.path.join(self._output_dir, 'out-env')))
 
     def testWorkInOutputFail(self):
         """Test the -w option failures"""
@@ -569,3 +580,9 @@
             self._RunControl('-b', self._test_branch, '-o', self._output_dir,
                              '-w', clean_dir=False, boards=board_list)
         self.assertIn("single commit", str(e.exception))
+
+        board_list = board.Boards()
+        board_list.AddBoard(board.Board(*boards[0]))
+        with self.assertRaises(SystemExit) as e:
+            self._RunControl('-w', clean_dir=False)
+        self.assertIn("specify -o", str(e.exception))
diff --git a/tools/buildman/buildman.py b/tools/buildman/main.py
similarity index 76%
rename from tools/buildman/buildman.py
rename to tools/buildman/main.py
index 30a8690..2b71473 100755
--- a/tools/buildman/buildman.py
+++ b/tools/buildman/main.py
@@ -6,8 +6,7 @@
 
 """See README for more information"""
 
-from __future__ import print_function
-
+import doctest
 import multiprocessing
 import os
 import re
@@ -16,20 +15,18 @@
 
 # Bring in the patman libraries
 our_path = os.path.dirname(os.path.realpath(__file__))
-sys.path.insert(1, os.path.join(our_path, '../patman'))
+sys.path.insert(1, os.path.join(our_path, '..'))
 
 # Our modules
-import board
-import bsettings
-import builder
-import checkpatch
-import cmdline
-import control
-import doctest
-import gitutil
-import patchstream
-import terminal
-import toolchain
+from buildman import board
+from buildman import bsettings
+from buildman import builder
+from buildman import cmdline
+from buildman import control
+from buildman import toolchain
+from patman import patchstream
+from patman import gitutil
+from patman import terminal
 
 def RunTests(skip_net_tests):
     import func_test
@@ -37,7 +34,7 @@
     import doctest
 
     result = unittest.TestResult()
-    for module in ['toolchain', 'gitutil']:
+    for module in ['buildman.toolchain', 'patman.gitutil']:
         suite = doctest.DocTestSuite(module)
         suite.run(result)
 
diff --git a/tools/buildman/test.py b/tools/buildman/test.py
index d32b226..40811ba 100644
--- a/tools/buildman/test.py
+++ b/tools/buildman/test.py
@@ -11,18 +11,17 @@
 
 # Bring in the patman libraries
 our_path = os.path.dirname(os.path.realpath(__file__))
-sys.path.append(os.path.join(our_path, '../patman'))
 
-import board
-import bsettings
-import builder
-import control
-import command
-import commit
-import terminal
-import test_util
-import toolchain
-import tools
+from buildman import board
+from buildman import bsettings
+from buildman import builder
+from buildman import control
+from buildman import toolchain
+from patman import commit
+from patman import command
+from patman import terminal
+from patman import test_util
+from patman import tools
 
 use_network = True
 
@@ -583,7 +582,7 @@
                 url = self.toolchains.LocateArchUrl('arm')
             self.assertRegexpMatches(url, 'https://www.kernel.org/pub/tools/'
                     'crosstool/files/bin/x86_64/.*/'
-                    'x86_64-gcc-.*-nolibc_arm-.*linux-gnueabi.tar.xz')
+                    'x86_64-gcc-.*-nolibc[-_]arm-.*linux-gnueabi.tar.xz')
 
     def testGetEnvArgs(self):
         """Test the GetEnvArgs() function"""
diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py
index 4456a80..acb5a29 100644
--- a/tools/buildman/toolchain.py
+++ b/tools/buildman/toolchain.py
@@ -10,10 +10,10 @@
 import tempfile
 import urllib.request, urllib.error, urllib.parse
 
-import bsettings
-import command
-import terminal
-import tools
+from buildman import bsettings
+from patman import command
+from patman import terminal
+from patman import tools
 
 (PRIORITY_FULL_PREFIX, PRIORITY_PREFIX_GCC, PRIORITY_PREFIX_GCC_PATH,
     PRIORITY_CALC) = list(range(4))
diff --git a/tools/dtoc/dtb_platdata.py b/tools/dtoc/dtb_platdata.py
index 90a9e1a..ecfe062 100644
--- a/tools/dtoc/dtb_platdata.py
+++ b/tools/dtoc/dtb_platdata.py
@@ -15,9 +15,9 @@
 import copy
 import sys
 
-import fdt
-import fdt_util
-import tools
+from dtoc import fdt
+from dtoc import fdt_util
+from patman import tools
 
 # When we see these properties we ignore them - i.e. do not create a structure member
 PROP_IGNORE_LIST = [
diff --git a/tools/dtoc/dtoc b/tools/dtoc/dtoc
index 896ca44..11a5d8e 120000
--- a/tools/dtoc/dtoc
+++ b/tools/dtoc/dtoc
@@ -1 +1 @@
-dtoc.py
\ No newline at end of file
+main.py
\ No newline at end of file
diff --git a/tools/dtoc/fdt.py b/tools/dtoc/fdt.py
index 1b7b730..188490b 100644
--- a/tools/dtoc/fdt.py
+++ b/tools/dtoc/fdt.py
@@ -8,10 +8,10 @@
 import struct
 import sys
 
-import fdt_util
+from dtoc import fdt_util
 import libfdt
 from libfdt import QUIET_NOTFOUND
-import tools
+from patman import tools
 
 # This deals with a device tree, presenting it as an assortment of Node and
 # Prop objects, representing nodes and properties, respectively. This file
diff --git a/tools/dtoc/fdt_util.py b/tools/dtoc/fdt_util.py
index b105fae..b040793 100644
--- a/tools/dtoc/fdt_util.py
+++ b/tools/dtoc/fdt_util.py
@@ -13,8 +13,8 @@
 import sys
 import tempfile
 
-import command
-import tools
+from patman import command
+from patman import tools
 
 def fdt32_to_cpu(val):
     """Convert a device tree cell to an integer
diff --git a/tools/dtoc/dtoc.py b/tools/dtoc/main.py
similarity index 94%
rename from tools/dtoc/dtoc.py
rename to tools/dtoc/main.py
index f31cba9..b94d9c3 100755
--- a/tools/dtoc/dtoc.py
+++ b/tools/dtoc/main.py
@@ -25,8 +25,6 @@
 see doc/driver-model/of-plat.rst
 """
 
-from __future__ import print_function
-
 from optparse import OptionParser
 import os
 import sys
@@ -34,15 +32,15 @@
 
 # Bring in the patman libraries
 our_path = os.path.dirname(os.path.realpath(__file__))
-sys.path.append(os.path.join(our_path, '../patman'))
+sys.path.append(os.path.join(our_path, '..'))
 
 # Bring in the libfdt module
 sys.path.insert(0, 'scripts/dtc/pylibfdt')
 sys.path.insert(0, os.path.join(our_path,
                 '../../build-sandbox_spl/scripts/dtc/pylibfdt'))
 
-import dtb_platdata
-import test_util
+from dtoc import dtb_platdata
+from patman import test_util
 
 def run_tests(args):
     """Run all the test we have for dtoc
@@ -79,7 +77,7 @@
 def RunTestCoverage():
     """Run the tests and check that we get 100% coverage"""
     sys.argv = [sys.argv[0]]
-    test_util.RunTestCoverage('tools/dtoc/dtoc.py', '/dtoc.py',
+    test_util.RunTestCoverage('tools/dtoc/dtoc', '/main.py',
             ['tools/patman/*.py', '*/fdt*', '*test*'], options.build_dir)
 
 
diff --git a/tools/dtoc/test_dtoc.py b/tools/dtoc/test_dtoc.py
index d733b70..8498e83 100755
--- a/tools/dtoc/test_dtoc.py
+++ b/tools/dtoc/test_dtoc.py
@@ -9,22 +9,20 @@
 tool.
 """
 
-from __future__ import print_function
-
 import collections
 import os
 import struct
 import unittest
 
-import dtb_platdata
+from dtoc import dtb_platdata
 from dtb_platdata import conv_name_to_c
 from dtb_platdata import get_compat_name
 from dtb_platdata import get_value
 from dtb_platdata import tab_to
-import fdt
-import fdt_util
-import test_util
-import tools
+from dtoc import fdt
+from dtoc import fdt_util
+from patman import test_util
+from patman import tools
 
 our_path = os.path.dirname(os.path.realpath(__file__))
 
diff --git a/tools/dtoc/test_fdt.py b/tools/dtoc/test_fdt.py
index 3316757..375e906 100755
--- a/tools/dtoc/test_fdt.py
+++ b/tools/dtoc/test_fdt.py
@@ -4,8 +4,6 @@
 # Written by Simon Glass <sjg@chromium.org>
 #
 
-from __future__ import print_function
-
 from optparse import OptionParser
 import glob
 import os
@@ -16,17 +14,16 @@
 
 # Bring in the patman libraries
 our_path = os.path.dirname(os.path.realpath(__file__))
-for dirname in ['../patman', '..']:
-    sys.path.insert(0, os.path.join(our_path, dirname))
+sys.path.insert(1, os.path.join(our_path, '..'))
 
-import command
-import fdt
+from dtoc import fdt
+from dtoc import fdt_util
+from dtoc.fdt_util import fdt32_to_cpu
 from fdt import TYPE_BYTE, TYPE_INT, TYPE_STRING, TYPE_BOOL, BytesToValue
-import fdt_util
-from fdt_util import fdt32_to_cpu
 import libfdt
-import test_util
-import tools
+from patman import command
+from patman import test_util
+from patman import tools
 
 def _GetPropertyValue(dtb, node, prop_name):
     """Low-level function to get the property value based on its offset
diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index 381739d..8734663 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -1647,6 +1647,9 @@
 			goto err;
 		}
 		DEVTYPE(dev) = mtdinfo.type;
+		if (DEVESIZE(dev) == 0 && ENVSECTORS(dev) == 0 &&
+		    mtdinfo.type == MTD_NORFLASH)
+			DEVESIZE(dev) = mtdinfo.erasesize;
 		if (DEVESIZE(dev) == 0)
 			/* Assume the erase size is the same as the env-size */
 			DEVESIZE(dev) = ENVSIZE(dev);
diff --git a/tools/fdtgrep.c b/tools/fdtgrep.c
index 2a8058f..7e168a1 100644
--- a/tools/fdtgrep.c
+++ b/tools/fdtgrep.c
@@ -17,6 +17,7 @@
 #include <stdlib.h>
 #include <string.h>
 #include <unistd.h>
+#include <fdt_region.h>
 
 #include "fdt_host.h"
 #include "libfdt_internal.h"
diff --git a/tools/fit_image.c b/tools/fit_image.c
index 4aeabbc..1e0f1e9 100644
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -17,6 +17,7 @@
 #include "fit_common.h"
 #include "mkimage.h"
 #include <image.h>
+#include <string.h>
 #include <stdarg.h>
 #include <version.h>
 #include <u-boot/crc.h>
@@ -434,7 +435,7 @@
 	int image_number;
 	int align_size;
 
-	align_size = params->bl_len ? params->bl_len : 4;
+	align_size = params->bl_len ? params->bl_len : 1;
 	fd = mmap_fdt(params->cmdname, fname, 0, &fdt, &sbuf, false, false);
 	if (fd < 0)
 		return -EIO;
@@ -492,7 +493,6 @@
 	fdt_pack(fdt);
 
 	new_size = fdt_totalsize(fdt);
-	new_size = ALIGN(new_size, align_size);
 	fdt_set_totalsize(fdt, new_size);
 	debug("Size reduced from %x to %x\n", fit_size, fdt_totalsize(fdt));
 	debug("External data size %x\n", buf_ptr);
@@ -744,6 +744,9 @@
 		snprintf(cmd, sizeof(cmd), "cp \"%s\" \"%s\"",
 			 params->imagefile, tmpfile);
 	}
+	if (strlen(cmd) >= MKIMAGE_MAX_DTC_CMDLINE_LEN - 1) {
+		fprintf(stderr, "WARNING: command-line for FIT creation might be truncated and will probably fail.\n");
+	}
 
 	if (*cmd && system(cmd) == -1) {
 		fprintf (stderr, "%s: system(%s) failed: %s\n",
diff --git a/tools/genboardscfg.py b/tools/genboardscfg.py
index 4f6382b..4ee7aa1 100755
--- a/tools/genboardscfg.py
+++ b/tools/genboardscfg.py
@@ -22,8 +22,7 @@
 import tempfile
 import time
 
-sys.path.insert(1, os.path.join(os.path.dirname(__file__), 'buildman'))
-import kconfiglib
+from buildman import kconfiglib
 
 ### constant variables ###
 OUTPUT_FILE = 'boards.cfg'
diff --git a/tools/image-host.c b/tools/image-host.c
index 5bb6896..9a83b7f 100644
--- a/tools/image-host.c
+++ b/tools/image-host.c
@@ -10,6 +10,7 @@
 
 #include "mkimage.h"
 #include <bootm.h>
+#include <fdt_region.h>
 #include <image.h>
 #include <version.h>
 
diff --git a/tools/libfdt/fdt_ro.c b/tools/libfdt/fdt_ro.c
new file mode 100644
index 0000000..8a9735a
--- /dev/null
+++ b/tools/libfdt/fdt_ro.c
@@ -0,0 +1,2 @@
+#include "fdt_host.h"
+#include "../scripts/dtc/libfdt/fdt_ro.c"
diff --git a/tools/mkimage.h b/tools/mkimage.h
index 0254af5..5b096a5 100644
--- a/tools/mkimage.h
+++ b/tools/mkimage.h
@@ -42,6 +42,6 @@
 #define MKIMAGE_TMPFILE_SUFFIX		".tmp"
 #define MKIMAGE_MAX_TMPFILE_LEN		256
 #define MKIMAGE_DEFAULT_DTC_OPTIONS	"-I dts -O dtb -p 500"
-#define MKIMAGE_MAX_DTC_CMDLINE_LEN	512
+#define MKIMAGE_MAX_DTC_CMDLINE_LEN	2 * MKIMAGE_MAX_TMPFILE_LEN + 35
 
 #endif /* _MKIIMAGE_H_ */
diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index d8bf7fd..36361f9 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -314,11 +314,9 @@
 import threading
 import time
 
-sys.path.append(os.path.join(os.path.dirname(__file__), 'buildman'))
-sys.path.append(os.path.join(os.path.dirname(__file__), 'patman'))
-import bsettings
-import kconfiglib
-import toolchain
+from buildman import bsettings
+from buildman import kconfiglib
+from buildman import toolchain
 
 SHOW_GNU_MAKE = 'scripts/show-gnu-make'
 SLEEP_TIME=0.03
diff --git a/tools/patman/checkpatch.py b/tools/patman/checkpatch.py
index d47ea43..795b519 100644
--- a/tools/patman/checkpatch.py
+++ b/tools/patman/checkpatch.py
@@ -3,12 +3,14 @@
 #
 
 import collections
-import command
-import gitutil
 import os
 import re
 import sys
-import terminal
+
+from patman import command
+from patman import gitutil
+from patman import terminal
+from patman import tools
 
 def FindCheckPatch():
     top_level = gitutil.GetTopLevel()
diff --git a/tools/patman/command.py b/tools/patman/command.py
index 5fbd2c4..e67ac15 100644
--- a/tools/patman/command.py
+++ b/tools/patman/command.py
@@ -3,8 +3,9 @@
 #
 
 import os
-import cros_subprocess
-import tools
+
+from patman import cros_subprocess
+from patman import tools
 
 """Shell command ease-ups for Python."""
 
diff --git a/tools/patman/func_test.py b/tools/patman/func_test.py
index 76319ff..b7e2825 100644
--- a/tools/patman/func_test.py
+++ b/tools/patman/func_test.py
@@ -12,15 +12,12 @@
 import tempfile
 import unittest
 
-try:
-    from StringIO import StringIO
-except ImportError:
-    from io import StringIO
+from io import StringIO
 
-import gitutil
-import patchstream
-import settings
-import tools
+from patman import gitutil
+from patman import patchstream
+from patman import settings
+from patman import tools
 
 
 @contextlib.contextmanager
diff --git a/tools/patman/get_maintainer.py b/tools/patman/get_maintainer.py
index 0ffb55a..473f0fe 100644
--- a/tools/patman/get_maintainer.py
+++ b/tools/patman/get_maintainer.py
@@ -2,10 +2,11 @@
 # Copyright (c) 2012 The Chromium OS Authors.
 #
 
-import command
-import gitutil
 import os
 
+from patman import command
+from patman import gitutil
+
 def FindGetMaintainer():
     """Look for the get_maintainer.pl script.
 
diff --git a/tools/patman/gitutil.py b/tools/patman/gitutil.py
index a2a225c..770a051 100644
--- a/tools/patman/gitutil.py
+++ b/tools/patman/gitutil.py
@@ -2,17 +2,17 @@
 # Copyright (c) 2011 The Chromium OS Authors.
 #
 
-import command
 import re
 import os
-import series
 import subprocess
 import sys
-import terminal
 
-import checkpatch
-import settings
-import tools
+from patman import checkpatch
+from patman import command
+from patman import series
+from patman import settings
+from patman import terminal
+from patman import tools
 
 # True to use --no-decorate - we check this in Setup()
 use_no_decorate = True
diff --git a/tools/patman/patman.py b/tools/patman/main.py
similarity index 93%
rename from tools/patman/patman.py
rename to tools/patman/main.py
index 7f4ac9a..f3d9c0c 100755
--- a/tools/patman/patman.py
+++ b/tools/patman/main.py
@@ -12,19 +12,20 @@
 import sys
 import unittest
 
+if __name__ == "__main__":
+    # Allow 'from patman import xxx to work'
+    our_path = os.path.dirname(os.path.realpath(__file__))
+    sys.path.append(os.path.join(our_path, '..'))
+
 # Our modules
-try:
-    from patman import checkpatch, command, gitutil, patchstream, \
-        project, settings, terminal, test
-except ImportError:
-    import checkpatch
-    import command
-    import gitutil
-    import patchstream
-    import project
-    import settings
-    import terminal
-    import test
+from patman import checkpatch
+from patman import command
+from patman import gitutil
+from patman import patchstream
+from patman import project
+from patman import settings
+from patman import terminal
+from patman import test
 
 
 parser = OptionParser()
@@ -85,7 +86,7 @@
 # Run our meagre tests
 elif options.test:
     import doctest
-    import func_test
+    from patman import func_test
 
     sys.argv = [sys.argv[0]]
     result = unittest.TestResult()
diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py
index df3eb74..4052975 100644
--- a/tools/patman/patchstream.py
+++ b/tools/patman/patchstream.py
@@ -9,10 +9,10 @@
 import shutil
 import tempfile
 
-import command
-import commit
-import gitutil
-from series import Series
+from patman import command
+from patman import commit
+from patman import gitutil
+from patman.series import Series
 
 # Tags that we detect and remove
 re_remove = re.compile('^BUG=|^TEST=|^BRANCH=|^Review URL:'
diff --git a/tools/patman/patman b/tools/patman/patman
index 6cc3d7a..11a5d8e 120000
--- a/tools/patman/patman
+++ b/tools/patman/patman
@@ -1 +1 @@
-patman.py
\ No newline at end of file
+main.py
\ No newline at end of file
diff --git a/tools/patman/project.py b/tools/patman/project.py
index 1d9cfc0..2dfc303 100644
--- a/tools/patman/project.py
+++ b/tools/patman/project.py
@@ -4,7 +4,7 @@
 
 import os.path
 
-import gitutil
+from patman import gitutil
 
 def DetectProject():
     """Autodetect the name of the current project.
diff --git a/tools/patman/series.py b/tools/patman/series.py
index 6d9d48b..e5e28ce 100644
--- a/tools/patman/series.py
+++ b/tools/patman/series.py
@@ -2,16 +2,14 @@
 # Copyright (c) 2011 The Chromium OS Authors.
 #
 
-from __future__ import print_function
-
 import itertools
 import os
 
-import get_maintainer
-import gitutil
-import settings
-import terminal
-import tools
+from patman import get_maintainer
+from patman import gitutil
+from patman import settings
+from patman import terminal
+from patman import tools
 
 # Series-xxx tags that we understand
 valid_series = ['to', 'cc', 'version', 'changes', 'prefix', 'notes', 'name',
diff --git a/tools/patman/settings.py b/tools/patman/settings.py
index 5dc83a8..ca74fc6 100644
--- a/tools/patman/settings.py
+++ b/tools/patman/settings.py
@@ -2,8 +2,6 @@
 # Copyright (c) 2011 The Chromium OS Authors.
 #
 
-from __future__ import print_function
-
 try:
     import configparser as ConfigParser
 except:
@@ -12,9 +10,9 @@
 import os
 import re
 
-import command
-import gitutil
-import tools
+from patman import command
+from patman import gitutil
+from patman import tools
 
 """Default settings per-project.
 
@@ -36,10 +34,7 @@
     - Merge general default settings/aliases with project-specific ones.
 
     # Sample config used for tests below...
-    >>> try:
-    ...     from StringIO import StringIO
-    ... except ImportError:
-    ...     from io import StringIO
+    >>> from io import StringIO
     >>> sample_config = '''
     ... [alias]
     ... me: Peter P. <likesspiders@example.com>
diff --git a/tools/patman/terminal.py b/tools/patman/terminal.py
index 5c9e3ee..c709438 100644
--- a/tools/patman/terminal.py
+++ b/tools/patman/terminal.py
@@ -7,8 +7,6 @@
 This module handles terminal interaction including ANSI color codes.
 """
 
-from __future__ import print_function
-
 import os
 import re
 import shutil
diff --git a/tools/patman/test.py b/tools/patman/test.py
index 889e186..e7f709e 100644
--- a/tools/patman/test.py
+++ b/tools/patman/test.py
@@ -8,11 +8,11 @@
 import tempfile
 import unittest
 
-import checkpatch
-import gitutil
-import patchstream
-import series
-import commit
+from patman import checkpatch
+from patman import gitutil
+from patman import patchstream
+from patman import series
+from patman import commit
 
 
 class TestPatch(unittest.TestCase):
diff --git a/tools/patman/test_util.py b/tools/patman/test_util.py
index 09f258c..4d28d9f 100644
--- a/tools/patman/test_util.py
+++ b/tools/patman/test_util.py
@@ -3,21 +3,23 @@
 # Copyright (c) 2016 Google, Inc
 #
 
-from __future__ import print_function
-
 from contextlib import contextmanager
 import glob
+import multiprocessing
 import os
 import sys
+import unittest
 
-import command
+from patman import command
+from patman import test_util
 
-try:
-  from StringIO import StringIO
-except ImportError:
-  from io import StringIO
+from io import StringIO
 
-PYTHON = 'python%d' % sys.version_info[0]
+use_concurrent = True
+try:
+    from concurrencytest import ConcurrentTestSuite, fork_for_tests
+except:
+    use_concurrent = False
 
 
 def RunTestCoverage(prog, filter_fname, exclude_list, build_dir, required=None):
@@ -46,12 +48,15 @@
         glob_list = []
     glob_list += exclude_list
     glob_list += ['*libfdt.py', '*site-packages*', '*dist-packages*']
-    test_cmd = 'test' if 'binman.py' in prog else '-t'
-    cmd = ('PYTHONPATH=$PYTHONPATH:%s/sandbox_spl/tools %s-coverage run '
-           '--omit "%s" %s %s -P1' % (build_dir, PYTHON, ','.join(glob_list),
+    test_cmd = 'test' if 'binman' in prog else '-t'
+    prefix = ''
+    if build_dir:
+        prefix = 'PYTHONPATH=$PYTHONPATH:%s/sandbox_spl/tools ' % build_dir
+    cmd = ('%spython3-coverage run '
+           '--omit "%s" %s %s -P1' % (prefix, ','.join(glob_list),
                                       prog, test_cmd))
     os.system(cmd)
-    stdout = command.Output('%s-coverage' % PYTHON, 'report')
+    stdout = command.Output('python3-coverage', 'report')
     lines = stdout.splitlines()
     if required:
         # Convert '/path/to/name.py' just the module name 'name'
@@ -70,8 +75,8 @@
     print(coverage)
     if coverage != '100%':
         print(stdout)
-        print("Type '%s-coverage html' to get a report in "
-              'htmlcov/index.html' % PYTHON)
+        print("Type 'python3-coverage html' to get a report in "
+              'htmlcov/index.html')
         print('Coverage error: %s, but should be 100%%' % coverage)
         ok = False
     if not ok:
@@ -90,3 +95,95 @@
         yield capture_out, capture_err
     finally:
         sys.stdout, sys.stderr = old_out, old_err
+
+
+def ReportResult(toolname:str, test_name: str, result: unittest.TestResult):
+    """Report the results from a suite of tests
+
+    Args:
+        toolname: Name of the tool that ran the tests
+        test_name: Name of test that was run, or None for all
+        result: A unittest.TestResult object containing the results
+    """
+    # Remove errors which just indicate a missing test. Since Python v3.5 If an
+    # ImportError or AttributeError occurs while traversing name then a
+    # synthetic test that raises that error when run will be returned. These
+    # errors are included in the errors accumulated by result.errors.
+    if test_name:
+        errors = []
+
+        for test, err in result.errors:
+            if ("has no attribute '%s'" % test_name) not in err:
+                errors.append((test, err))
+            result.testsRun -= 1
+        result.errors = errors
+
+    print(result)
+    for test, err in result.errors:
+        print(test.id(), err)
+    for test, err in result.failures:
+        print(err, result.failures)
+    if result.skipped:
+        print('%d binman test%s SKIPPED:' %
+              (len(result.skipped), 's' if len(result.skipped) > 1 else ''))
+        for skip_info in result.skipped:
+            print('%s: %s' % (skip_info[0], skip_info[1]))
+    if result.errors or result.failures:
+        print('binman tests FAILED')
+        return 1
+    return 0
+
+
+def RunTestSuites(result, debug, verbosity, test_preserve_dirs, processes,
+                  test_name, toolpath, test_class_list):
+    """Run a series of test suites and collect the results
+
+    Args:
+        result: A unittest.TestResult object to add the results to
+        debug: True to enable debugging, which shows a full stack trace on error
+        verbosity: Verbosity level to use (0-4)
+        test_preserve_dirs: True to preserve the input directory used by tests
+            so that it can be examined afterwards (only useful for debugging
+            tests). If a single test is selected (in args[0]) it also preserves
+            the output directory for this test. Both directories are displayed
+            on the command line.
+        processes: Number of processes to use to run tests (None=same as #CPUs)
+        test_name: Name of test to run, or None for all
+        toolpath: List of paths to use for tools
+        test_class_list: List of test classes to run
+    """
+    for module in []:
+        suite = doctest.DocTestSuite(module)
+        suite.run(result)
+
+    sys.argv = [sys.argv[0]]
+    if debug:
+        sys.argv.append('-D')
+    if verbosity:
+        sys.argv.append('-v%d' % verbosity)
+    if toolpath:
+        for path in toolpath:
+            sys.argv += ['--toolpath', path]
+
+    suite = unittest.TestSuite()
+    loader = unittest.TestLoader()
+    for module in test_class_list:
+        # Test the test module about our arguments, if it is interested
+        if hasattr(module, 'setup_test_args'):
+            setup_test_args = getattr(module, 'setup_test_args')
+            setup_test_args(preserve_indir=test_preserve_dirs,
+                preserve_outdirs=test_preserve_dirs and test_name is not None,
+                toolpath=toolpath, verbosity=verbosity)
+        if test_name:
+            try:
+                suite.addTests(loader.loadTestsFromName(test_name, module))
+            except AttributeError:
+                continue
+        else:
+            suite.addTests(loader.loadTestsFromTestCase(module))
+    if use_concurrent and processes != 1:
+        concurrent_suite = ConcurrentTestSuite(suite,
+                fork_for_tests(processes or multiprocessing.cpu_count()))
+        concurrent_suite.run(result)
+    else:
+        suite.run(result)
diff --git a/tools/patman/tools.py b/tools/patman/tools.py
index 3feddb2..b50370d 100644
--- a/tools/patman/tools.py
+++ b/tools/patman/tools.py
@@ -3,9 +3,6 @@
 # Copyright (c) 2016 Google, Inc
 #
 
-from __future__ import print_function
-
-import command
 import glob
 import os
 import shutil
@@ -13,7 +10,8 @@
 import sys
 import tempfile
 
-import tout
+from patman import command
+from patman import tout
 
 # Output directly (generally this is temporary)
 outdir = None
diff --git a/tools/patman/tout.py b/tools/patman/tout.py
index 2a38485..c7e3272 100644
--- a/tools/patman/tout.py
+++ b/tools/patman/tout.py
@@ -4,11 +4,9 @@
 # Terminal output logging.
 #
 
-from __future__ import print_function
-
 import sys
 
-import terminal
+from patman import terminal
 
 # Output verbosity levels that we support
 ERROR, WARNING, NOTICE, INFO, DETAIL, DEBUG = range(6)
diff --git a/tools/rmboard.py b/tools/rmboard.py
index df4f04b..06c3562 100755
--- a/tools/rmboard.py
+++ b/tools/rmboard.py
@@ -1,4 +1,4 @@
-#! /usr/bin/python
+#! /usr/bin/python3
 # SPDX-License-Identifier: GPL-2.0+
 # Copyright 2019 Google LLC
 #
@@ -23,8 +23,6 @@
 Search for ## to update the commit message manually.
 """
 
-from __future__ import print_function
-
 import glob
 import os
 import re
@@ -32,9 +30,8 @@
 
 # Bring in the patman libraries
 our_path = os.path.dirname(os.path.realpath(__file__))
-sys.path.append(os.path.join(our_path, '../tools/patman'))
 
-import command
+from patman import command
 
 def rm_kconfig_include(path):
     """Remove a path from Kconfig files