Merge branch 'master' of http://git.denx.de/u-boot-samsung
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index a82c8b9..4b2494e 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -223,6 +223,7 @@
__maybe_unused int rc;
#ifdef CONFIG_MACPWR
+ gpio_request(CONFIG_MACPWR, "macpwr");
gpio_direction_output(CONFIG_MACPWR, 1);
mdelay(200);
#endif
diff --git a/arch/arm/dts/tegra124-nyan-big.dts b/arch/arm/dts/tegra124-nyan-big.dts
index 5a39e93..8be6adb 100644
--- a/arch/arm/dts/tegra124-nyan-big.dts
+++ b/arch/arm/dts/tegra124-nyan-big.dts
@@ -163,12 +163,15 @@
spi@7000d400 {
status = "okay";
+ spi-deactivate-delay = <200>;
+ spi-max-frequency = <3000000>;
cros_ec: cros-ec@0 {
compatible = "google,cros-ec-spi";
spi-max-frequency = <3000000>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
+ ec-interrupt = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
reg = <0>;
google,cros-ec-spi-msg-delay = <2000>;
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h
index 04011ae..f9dd3c8 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -336,4 +336,12 @@
void tegra30_set_up_pllp(void);
+/**
+ * Enable output clock for external peripherals
+ *
+ * @param clk_id Clock ID to output (1, 2 or 3)
+ * @return 0 if OK. -ve on error
+ */
+int clock_external_output(int clk_id);
+
#endif /* _TEGRA_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/sys_proto.h b/arch/arm/include/asm/arch-tegra/sys_proto.h
index 83f9f47..b64f9d8 100644
--- a/arch/arm/include/asm/arch-tegra/sys_proto.h
+++ b/arch/arm/include/asm/arch-tegra/sys_proto.h
@@ -25,4 +25,11 @@
*/
int tegra_lcd_pmic_init(int board_id);
+/**
+ * nvidia_board_init() - perform any board-specific init
+ *
+ * @return 0 if OK, -ve on error
+ */
+int nvidia_board_init(void);
+
#endif
diff --git a/arch/arm/include/asm/arch-tegra124/clock-tables.h b/arch/arm/include/asm/arch-tegra124/clock-tables.h
index 7005855..3c67e72 100644
--- a/arch/arm/include/asm/arch-tegra124/clock-tables.h
+++ b/arch/arm/include/asm/arch-tegra124/clock-tables.h
@@ -285,12 +285,12 @@
/* 184 */
PERIPH_ID_GPU,
PERIPH_ID_AMX1,
- PERIPH_ID_X_RESERVED26,
- PERIPH_ID_X_RESERVED27,
- PERIPH_ID_X_RESERVED28,
- PERIPH_ID_X_RESERVED29,
- PERIPH_ID_X_RESERVED30,
- PERIPH_ID_X_RESERVED31,
+ PERIPH_ID_AFC5,
+ PERIPH_ID_AFC4,
+ PERIPH_ID_AFC3,
+ PERIPH_ID_AFC2,
+ PERIPH_ID_AFC1,
+ PERIPH_ID_AFC0,
PERIPH_ID_COUNT,
PERIPH_ID_NONE = -1,
diff --git a/arch/arm/include/asm/arch-tegra124/flow.h b/arch/arm/include/asm/arch-tegra124/flow.h
index d6f515f..7818b1b 100644
--- a/arch/arm/include/asm/arch-tegra124/flow.h
+++ b/arch/arm/include/asm/arch-tegra124/flow.h
@@ -26,6 +26,12 @@
u32 cpu_pwr_csr; /* offset 0x38 */
u32 mpid; /* offset 0x3c */
u32 ram_repair; /* offset 0x40 */
+ u32 flow_dbg_sel; /* offset 0x44 */
+ u32 flow_dbg_cnt0; /* offset 0x48 */
+ u32 flow_dbg_cnt1; /* offset 0x4c */
+ u32 flow_dbg_qual; /* offset 0x50 */
+ u32 flow_ctlr_spare; /* offset 0x54 */
+ u32 ram_repair_cluster1;/* offset 0x58 */
};
/* HALT_COP_EVENTS_0, 0x04 */
@@ -43,4 +49,10 @@
#define CSR_WAIT_WFI_SHIFT 8
#define CSR_PWR_OFF_STS (1 << 16)
+/* RAM_REPAIR, 0x40, 0x58 */
+enum {
+ RAM_REPAIR_REQ = 0x1 << 0,
+ RAM_REPAIR_STS = 0x1 << 1,
+};
+
#endif /* _TEGRA124_FLOW_H_ */
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 131802a..ebcee4e 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -107,6 +107,11 @@
return 0;
}
+__weak int nvidia_board_init(void)
+{
+ return 0;
+}
+
/*
* Routine: board_init
* Description: Early hardware init.
@@ -180,8 +185,7 @@
/* prepare the WB code to LP0 location */
warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
#endif
-
- return 0;
+ return nvidia_board_init();
}
#ifdef CONFIG_BOARD_EARLY_INIT_F
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index cdd5438..24047b8 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -17,11 +17,13 @@
/* Tegra SoC common clock control functions */
#include <common.h>
+#include <errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/ap.h>
#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
#include <asm/arch-tegra/timer.h>
#include <div64.h>
#include <fdtdec.h>
@@ -82,7 +84,7 @@
assert(clock_id_is_pll(clkid));
if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) {
- debug("%s: Invalid PLL\n", __func__);
+ debug("%s: Invalid PLL %d\n", __func__, clkid);
return NULL;
}
return &clkrst->crc_pll[clkid];
@@ -118,9 +120,12 @@
unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
u32 divp, u32 cpcon, u32 lfcon)
{
- struct clk_pll *pll = get_pll(clkid);
+ struct clk_pll *pll = NULL;
u32 misc_data, data;
+ if (clkid < (enum clock_id)TEGRA_CLK_PLLS)
+ pll = get_pll(clkid);
+
/*
* We cheat by treating all PLL (except PLLU) in the same fashion.
* This works only because:
@@ -702,3 +707,18 @@
set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4);
}
+
+int clock_external_output(int clk_id)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+ if (clk_id >= 1 && clk_id <= 3) {
+ setbits_le32(&pmc->pmc_clk_out_cntrl,
+ 1 << (2 + (clk_id - 1) * 8));
+ } else {
+ printf("%s: Unknown output clock id %d\n", __func__, clk_id);
+ return -EINVAL;
+ }
+
+ return 0;
+}
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index 6331cd4..30ae036 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -9,7 +9,7 @@
#include <asm/io.h>
#include <asm/types.h>
-
+#include <asm/arch/flow.h>
#include <asm/arch/powergate.h>
#include <asm/arch/tegra.h>
@@ -75,11 +75,29 @@
return 0;
}
+static void tegra_powergate_ram_repair(void)
+{
+#ifdef CONFIG_TEGRA124
+ struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+
+ /* Request RAM repair for cluster 0 and wait until complete */
+ setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ);
+ while (!(readl(&flow->ram_repair) & RAM_REPAIR_STS))
+ ;
+
+ /* Same for cluster 1 */
+ setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ);
+ while (!(readl(&flow->ram_repair_cluster1) & RAM_REPAIR_STS))
+ ;
+#endif
+}
+
int tegra_powergate_sequence_power_up(enum tegra_powergate id,
enum periph_id periph)
{
int err;
+ tegra_powergate_ram_repair();
reset_set_enable(periph, 1);
err = tegra_powergate_power_on(id);
diff --git a/arch/arm/mach-tegra/tegra124/Kconfig b/arch/arm/mach-tegra/tegra124/Kconfig
index 6579e3f..f3324ff 100644
--- a/arch/arm/mach-tegra/tegra124/Kconfig
+++ b/arch/arm/mach-tegra/tegra124/Kconfig
@@ -10,7 +10,7 @@
select CPU_V7_HAS_VIRT if !SPL_BUILD
config TARGET_NYAN_BIG
- bool "Google/NVIDIA Nyan-big Chrombook"
+ bool "Google/NVIDIA Nyan-big Chromebook"
help
Nyan Big is a Tegra124 clamshell board that is very similar
to venice2, but it has a different panel, the sdcard CD and WP
diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c
index 2d17550..b955848 100644
--- a/arch/arm/mach-tegra/tegra124/clock.c
+++ b/arch/arm/mach-tegra/tegra124/clock.c
@@ -475,7 +475,7 @@
PERIPHC_ACTMON,
/* 120 */
- NONE(EXTPERIPH1),
+ PERIPHC_EXTPERIPH1,
NONE(EXTPERIPH2),
NONE(EXTPERIPH3),
NONE(OOB),
diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
index c69654c..eb33774 100644
--- a/arch/avr32/Kconfig
+++ b/arch/avr32/Kconfig
@@ -17,35 +17,14 @@
config TARGET_ATSTK1002
bool "Support atstk1002"
-config TARGET_ATSTK1003
- bool "Support atstk1003"
-
-config TARGET_ATSTK1004
- bool "Support atstk1004"
-
-config TARGET_ATSTK1006
- bool "Support atstk1006"
-
-config TARGET_FAVR_32_EZKIT
- bool "Support favr-32-ezkit"
-
config TARGET_GRASSHOPPER
bool "Support grasshopper"
-config TARGET_MIMC200
- bool "Support mimc200"
-
-config TARGET_HAMMERHEAD
- bool "Support hammerhead"
-
endchoice
source "board/atmel/atngw100/Kconfig"
source "board/atmel/atngw100mkii/Kconfig"
source "board/atmel/atstk1000/Kconfig"
-source "board/earthlcd/favr-32-ezkit/Kconfig"
source "board/in-circuit/grasshopper/Kconfig"
-source "board/mimc/mimc200/Kconfig"
-source "board/miromico/hammerhead/Kconfig"
endmenu
diff --git a/arch/avr32/lib/Makefile b/arch/avr32/lib/Makefile
index 6750913..8108ae5 100644
--- a/arch/avr32/lib/Makefile
+++ b/arch/avr32/lib/Makefile
@@ -8,9 +8,6 @@
#
obj-y += memset.o
-ifndef CONFIG_SYS_GENERIC_BOARD
-obj-y += board.o
-endif
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-y += interrupts.o
obj-y += dram_init.o
diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c
deleted file mode 100644
index aacfcbf..0000000
--- a/arch/avr32/lib/board.c
+++ /dev/null
@@ -1,256 +0,0 @@
-/*
- * Copyright (C) 2004-2006 Atmel Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <stdio_dev.h>
-#include <version.h>
-#include <net.h>
-
-#ifdef CONFIG_BITBANGMII
-#include <miiphy.h>
-#endif
-
-#include <asm/sections.h>
-#include <asm/arch/mmu.h>
-#include <asm/arch/hardware.h>
-
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-#include <mmc.h>
-#endif
-DECLARE_GLOBAL_DATA_PTR;
-
-unsigned long monitor_flash_len;
-
-__weak void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = gd->ram_size;
-}
-
-/* Weak aliases for optional board functions */
-static int __do_nothing(void)
-{
- return 0;
-}
-int board_postclk_init(void) __attribute__((weak, alias("__do_nothing")));
-int board_early_init_r(void) __attribute__((weak, alias("__do_nothing")));
-
-static int init_baudrate(void)
-{
- gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
- return 0;
-}
-
-static int display_banner (void)
-{
- printf ("\n\n%s\n\n", version_string);
- printf ("U-Boot code: %08lx -> %08lx data: %08lx -> %08lx\n",
- (unsigned long)_text, (unsigned long)_etext,
- (unsigned long)_data, (unsigned long)(&__bss_end));
- return 0;
-}
-
-static int display_dram_config (void)
-{
- int i;
-
- puts ("DRAM Configuration:\n");
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- printf ("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
- print_size (gd->bd->bi_dram[i].size, "\n");
- }
-
- return 0;
-}
-
-static void display_flash_config (void)
-{
- puts ("Flash: ");
- print_size(gd->bd->bi_flashsize, " ");
- printf("at address 0x%08lx\n", gd->bd->bi_flashstart);
-}
-
-void board_init_f(ulong board_type)
-{
- gd_t gd_data;
- gd_t *new_gd;
- bd_t *bd;
- unsigned long *new_sp;
- unsigned long monitor_len;
- unsigned long monitor_addr;
- unsigned long addr;
-
- /* Initialize the global data pointer */
- memset(&gd_data, 0, sizeof(gd_data));
- gd = &gd_data;
-
- /* Perform initialization sequence */
- board_early_init_f();
- arch_cpu_init();
- board_postclk_init();
- env_init();
- init_baudrate();
- serial_init();
- console_init_f();
- display_banner();
- dram_init();
-
- /* If we have no SDRAM, we can't go on */
- if (gd->ram_size <= 0)
- panic("No working SDRAM available\n");
-
- /*
- * Now that we have DRAM mapped and working, we can
- * relocate the code and continue running from DRAM.
- *
- * Reserve memory at end of RAM for (top down in that order):
- * - u-boot image
- * - heap for malloc()
- * - board info struct
- * - global data struct
- * - stack
- */
- addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
- monitor_len = (char *)(&__bss_end) - _text;
-
- /*
- * Reserve memory for u-boot code, data and bss.
- * Round down to next 4 kB limit.
- */
- addr -= monitor_len;
- addr &= ~(4096UL - 1);
- monitor_addr = addr;
-
- /* Reserve memory for malloc() */
- addr -= CONFIG_SYS_MALLOC_LEN;
-
-#ifdef CONFIG_LCD
-#ifdef CONFIG_FB_ADDR
- printf("LCD: Frame buffer allocated at preset 0x%08x\n",
- CONFIG_FB_ADDR);
- gd->fb_base = CONFIG_FB_ADDR;
-#else
- addr = lcd_setmem(addr);
- printf("LCD: Frame buffer allocated at 0x%08lx\n", addr);
- gd->fb_base = addr;
-#endif /* CONFIG_FB_ADDR */
-#endif /* CONFIG_LCD */
-
- /* Allocate a Board Info struct on a word boundary */
- addr -= sizeof(bd_t);
- addr &= ~3UL;
- gd->bd = bd = (bd_t *)addr;
-
- /* Allocate a new global data copy on a 8-byte boundary. */
- addr -= sizeof(gd_t);
- addr &= ~7UL;
- new_gd = (gd_t *)addr;
-
- /* And finally, a new, bigger stack. */
- new_sp = (unsigned long *)addr;
- gd->start_addr_sp = addr;
- *(--new_sp) = 0;
- *(--new_sp) = 0;
-
- dram_init_banksize();
-
- memcpy(new_gd, gd, sizeof(gd_t));
-
- relocate_code((unsigned long)new_sp, new_gd, monitor_addr);
-}
-
-void board_init_r(gd_t *new_gd, ulong dest_addr)
-{
-#ifndef CONFIG_ENV_IS_NOWHERE
- extern char * env_name_spec;
-#endif
- bd_t *bd;
-
- gd = new_gd;
- bd = gd->bd;
-
- gd->flags |= GD_FLG_RELOC;
- gd->reloc_off = dest_addr - CONFIG_SYS_MONITOR_BASE;
-
- /* Enable the MMU so that we can keep u-boot simple */
- mmu_init_r(dest_addr);
-
- board_early_init_r();
-
- monitor_flash_len = _edata - _text;
-
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
- /*
- * We have to relocate the command table manually
- */
- fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
- ll_entry_count(cmd_tbl_t, cmd));
-#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
-
- /* there are some other pointer constants we must deal with */
-#ifndef CONFIG_ENV_IS_NOWHERE
- env_name_spec += gd->reloc_off;
-#endif
-
- timer_init();
-
- /* The malloc area is right below the monitor image in RAM */
- mem_malloc_init(CONFIG_SYS_MONITOR_BASE + gd->reloc_off -
- CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN);
-
- enable_interrupts();
-
- bd->bi_flashstart = 0;
- bd->bi_flashsize = 0;
- bd->bi_flashoffset = 0;
-
-#ifndef CONFIG_SYS_NO_FLASH
- bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
- bd->bi_flashsize = flash_init();
- bd->bi_flashoffset = (unsigned long)_edata - (unsigned long)_text;
-
- if (bd->bi_flashsize)
- display_flash_config();
-#endif
-
- if (bd->bi_dram[0].size)
- display_dram_config();
-
- gd->bd->bi_boot_params = malloc(CONFIG_SYS_BOOTPARAMS_LEN);
- if (!gd->bd->bi_boot_params)
- puts("WARNING: Cannot allocate space for boot parameters\n");
-
- /* initialize environment */
- env_relocate();
-
- stdio_init();
- jumptable_init();
- console_init_r();
-
- /* Initialize from environment */
- load_addr = getenv_ulong("loadaddr", 16, load_addr);
-
-#ifdef CONFIG_BITBANGMII
- bb_miiphy_init();
-#endif
-#if defined(CONFIG_CMD_NET)
- puts("Net: ");
- eth_initialize();
-#endif
-
-#ifdef CONFIG_GENERIC_ATMEL_MCI
- mmc_initialize(gd->bd);
-#endif
- for (;;) {
- main_loop();
- }
-}
diff --git a/board/atmel/atstk1000/Kconfig b/board/atmel/atstk1000/Kconfig
index 6d41514..b4fa9a2 100644
--- a/board/atmel/atstk1000/Kconfig
+++ b/board/atmel/atstk1000/Kconfig
@@ -13,51 +13,3 @@
default "atstk1002"
endif
-
-if TARGET_ATSTK1003
-
-config SYS_BOARD
- default "atstk1000"
-
-config SYS_VENDOR
- default "atmel"
-
-config SYS_SOC
- default "at32ap700x"
-
-config SYS_CONFIG_NAME
- default "atstk1003"
-
-endif
-
-if TARGET_ATSTK1004
-
-config SYS_BOARD
- default "atstk1000"
-
-config SYS_VENDOR
- default "atmel"
-
-config SYS_SOC
- default "at32ap700x"
-
-config SYS_CONFIG_NAME
- default "atstk1004"
-
-endif
-
-if TARGET_ATSTK1006
-
-config SYS_BOARD
- default "atstk1000"
-
-config SYS_VENDOR
- default "atmel"
-
-config SYS_SOC
- default "at32ap700x"
-
-config SYS_CONFIG_NAME
- default "atstk1006"
-
-endif
diff --git a/board/atmel/atstk1000/MAINTAINERS b/board/atmel/atstk1000/MAINTAINERS
index 378e1b3..1070f98 100644
--- a/board/atmel/atstk1000/MAINTAINERS
+++ b/board/atmel/atstk1000/MAINTAINERS
@@ -1,12 +1,6 @@
ATSTK1000 BOARD
-#M: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
-S: Orphan (since 2014-06)
+M: Andreas Bießmann <andreas.biessmann@corscience.de>
+S: Maintained
F: board/atmel/atstk1000/
F: include/configs/atstk1002.h
F: configs/atstk1002_defconfig
-F: include/configs/atstk1003.h
-F: configs/atstk1003_defconfig
-F: include/configs/atstk1004.h
-F: configs/atstk1004_defconfig
-F: include/configs/atstk1006.h
-F: configs/atstk1006_defconfig
diff --git a/board/atmel/atstk1000/atstk1000.c b/board/atmel/atstk1000/atstk1000.c
index fd4363b..679b674 100644
--- a/board/atmel/atstk1000/atstk1000.c
+++ b/board/atmel/atstk1000/atstk1000.c
@@ -30,32 +30,12 @@
};
static const struct sdram_config sdram_config = {
-#if defined(CONFIG_ATSTK1006)
- /* Dual MT48LC16M16A2-7E (64 MB) on daughterboard */
.data_bits = SDRAM_DATA_32BIT,
- .row_bits = 13,
- .col_bits = 9,
- .bank_bits = 2,
- .cas = 2,
- .twr = 2,
- .trc = 7,
- .trp = 2,
- .trcd = 2,
- .tras = 4,
- .txsr = 7,
- /* 7.81 us */
- .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
-#else
- /* MT48LC2M32B2P-5 (8 MB) on motherboard */
-#ifdef CONFIG_ATSTK1004
- .data_bits = SDRAM_DATA_16BIT,
-#else
- .data_bits = SDRAM_DATA_32BIT,
-#endif
#ifdef CONFIG_ATSTK1000_16MB_SDRAM
/* MT48LC4M32B2P-6 (16 MB) on mod'ed motherboard */
.row_bits = 12,
#else
+ /* MT48LC2M32B2P-5 (8 MB) on motherboard */
.row_bits = 11,
#endif
.col_bits = 8,
@@ -69,7 +49,6 @@
.txsr = 5,
/* 15.6 us */
.refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
-#endif
};
int board_early_init_f(void)
diff --git a/board/earthlcd/favr-32-ezkit/Kconfig b/board/earthlcd/favr-32-ezkit/Kconfig
deleted file mode 100644
index 50e29ec..0000000
--- a/board/earthlcd/favr-32-ezkit/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_FAVR_32_EZKIT
-
-config SYS_BOARD
- default "favr-32-ezkit"
-
-config SYS_VENDOR
- default "earthlcd"
-
-config SYS_SOC
- default "at32ap700x"
-
-config SYS_CONFIG_NAME
- default "favr-32-ezkit"
-
-endif
diff --git a/board/earthlcd/favr-32-ezkit/MAINTAINERS b/board/earthlcd/favr-32-ezkit/MAINTAINERS
deleted file mode 100644
index 89ba862..0000000
--- a/board/earthlcd/favr-32-ezkit/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-FAVR-32-EZKIT BOARD
-#M: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
-S: Orphan (since 2014-06)
-F: board/earthlcd/favr-32-ezkit/
-F: include/configs/favr-32-ezkit.h
-F: configs/favr-32-ezkit_defconfig
diff --git a/board/earthlcd/favr-32-ezkit/Makefile b/board/earthlcd/favr-32-ezkit/Makefile
deleted file mode 100644
index f712ab9..0000000
--- a/board/earthlcd/favr-32-ezkit/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2008 Atmel Corporation
-#
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y := favr-32-ezkit.o flash.o
diff --git a/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c b/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c
deleted file mode 100644
index f9ac330..0000000
--- a/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright (C) 2008 Atmel Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <netdev.h>
-
-#include <asm/io.h>
-#include <asm/sdram.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/hmatrix.h>
-#include <asm/arch/mmu.h>
-#include <asm/arch/portmux.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
- {
- .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
- .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
- .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
- | MMU_VMR_CACHE_NONE,
- }, {
- .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
- .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
- .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
- | MMU_VMR_CACHE_WRBACK,
- },
-};
-
-static const struct sdram_config sdram_config = {
- /* MT48LC4M32B2P-6 (16 MB) */
- .data_bits = SDRAM_DATA_32BIT,
- .row_bits = 12,
- .col_bits = 8,
- .bank_bits = 2,
- .cas = 3,
- .twr = 2,
- .trc = 7,
- .trp = 2,
- .trcd = 2,
- .tras = 5,
- .txsr = 5,
- /* 15.6 us */
- .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
-};
-
-int board_early_init_f(void)
-{
- /* Enable SDRAM in the EBI mux */
- hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
-
- portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
-
- sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
-
- portmux_enable_usart3(PORTMUX_DRIVE_MIN);
-#if defined(CONFIG_MACB)
- portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
-#endif
-#if defined(CONFIG_MMC)
- portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
-#endif
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
- gd->bd->bi_phy_id[0] = 0x01;
- return 0;
-}
-
-#if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET)
-int board_eth_init(bd_t *bi)
-{
- return macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0,
- bi->bi_phy_id[0]);
-}
-#endif
diff --git a/board/earthlcd/favr-32-ezkit/flash.c b/board/earthlcd/favr-32-ezkit/flash.c
deleted file mode 100644
index e45c6f4..0000000
--- a/board/earthlcd/favr-32-ezkit/flash.c
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * Copyright (C) 2008 Atmel Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-
-#ifdef CONFIG_FAVR32_EZKIT_EXT_FLASH
-#include <asm/arch/cacheflush.h>
-#include <asm/io.h>
-#include <asm/sections.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-flash_info_t flash_info[1];
-
-static void flash_identify(uint16_t *flash, flash_info_t *info)
-{
- unsigned long flags;
-
- flags = disable_interrupts();
-
- dcache_flush_unlocked();
-
- writew(0xaa, flash + 0x555);
- writew(0x55, flash + 0xaaa);
- writew(0x90, flash + 0x555);
- info->flash_id = readl(flash);
- writew(0xff, flash);
-
- readw(flash);
-
- if (flags)
- enable_interrupts();
-}
-
-unsigned long flash_init(void)
-{
- unsigned long addr;
- unsigned int i;
-
- flash_info[0].size = CONFIG_SYS_FLASH_SIZE;
- flash_info[0].sector_count = 135;
-
- flash_identify(uncached((void *)CONFIG_SYS_FLASH_BASE), &flash_info[0]);
-
- for (i = 0, addr = 0; i < 8; i++, addr += 0x2000)
- flash_info[0].start[i] = addr;
- for (; i < flash_info[0].sector_count; i++, addr += 0x10000)
- flash_info[0].start[i] = addr;
-
- return CONFIG_SYS_FLASH_SIZE;
-}
-
-void flash_print_info(flash_info_t *info)
-{
- printf("Flash: Vendor ID: 0x%02lx, Product ID: 0x%02lx\n",
- info->flash_id >> 16, info->flash_id & 0xffff);
- printf("Size: %ld MB in %d sectors\n",
- info->size >> 10, info->sector_count);
-}
-
-int flash_erase(flash_info_t *info, int s_first, int s_last)
-{
- unsigned long flags;
- unsigned long start_time;
- uint16_t *fb, *sb;
- unsigned int i;
- int ret;
- uint16_t status;
-
- if ((s_first < 0) || (s_first > s_last)
- || (s_last >= info->sector_count)) {
- puts("Error: first and/or last sector out of range\n");
- return ERR_INVAL;
- }
-
- for (i = s_first; i < s_last; i++)
- if (info->protect[i]) {
- printf("Error: sector %d is protected\n", i);
- return ERR_PROTECTED;
- }
-
- fb = (uint16_t *)uncached(info->start[0]);
-
- dcache_flush_unlocked();
-
- for (i = s_first; (i <= s_last) && !ctrlc(); i++) {
- printf("Erasing sector %3d...", i);
-
- sb = (uint16_t *)uncached(info->start[i]);
-
- flags = disable_interrupts();
-
- start_time = get_timer(0);
-
- /* Unlock sector */
- writew(0xaa, fb + 0x555);
- writew(0x70, sb);
-
- /* Erase sector */
- writew(0xaa, fb + 0x555);
- writew(0x55, fb + 0xaaa);
- writew(0x80, fb + 0x555);
- writew(0xaa, fb + 0x555);
- writew(0x55, fb + 0xaaa);
- writew(0x30, sb);
-
- /* Wait for completion */
- ret = ERR_OK;
- do {
- /* TODO: Timeout */
- status = readw(sb);
- } while ((status != 0xffff) && !(status & 0x28));
-
- writew(0xf0, fb);
-
- /*
- * Make sure the command actually makes it to the bus
- * before we re-enable interrupts.
- */
- readw(fb);
-
- if (flags)
- enable_interrupts();
-
- if (status != 0xffff) {
- printf("Flash erase error at address 0x%p: 0x%02x\n",
- sb, status);
- ret = ERR_PROG_ERROR;
- break;
- }
- }
-
- if (ctrlc())
- printf("User interrupt!\n");
-
- return ERR_OK;
-}
-
-int write_buff(flash_info_t *info, uchar *src,
- ulong addr, ulong count)
-{
- unsigned long flags;
- uint16_t *base, *p, *s, *end;
- uint16_t word, status, status1;
- int ret = ERR_OK;
-
- if (addr < info->start[0]
- || (addr + count) > (info->start[0] + info->size)
- || (addr + count) < addr) {
- puts("Error: invalid address range\n");
- return ERR_INVAL;
- }
-
- if (addr & 1 || count & 1 || (unsigned int)src & 1) {
- puts("Error: misaligned source, destination or count\n");
- return ERR_ALIGN;
- }
-
- base = (uint16_t *)uncached(info->start[0]);
- end = (uint16_t *)uncached(addr + count);
-
- flags = disable_interrupts();
-
- dcache_flush_unlocked();
- sync_write_buffer();
-
- for (p = (uint16_t *)uncached(addr), s = (uint16_t *)src;
- p < end && !ctrlc(); p++, s++) {
- word = *s;
-
- writew(0xaa, base + 0x555);
- writew(0x55, base + 0xaaa);
- writew(0xa0, base + 0x555);
- writew(word, p);
-
- sync_write_buffer();
-
- /* Wait for completion */
- status1 = readw(p);
- do {
- /* TODO: Timeout */
- status = status1;
- status1 = readw(p);
- } while (((status ^ status1) & 0x40) /* toggled */
- && !(status1 & 0x28)); /* error bits */
-
- /*
- * We'll need to check once again for toggle bit
- * because the toggle bit may stop toggling as I/O5
- * changes to "1" (ref at49bv642.pdf p9)
- */
- status1 = readw(p);
- status = readw(p);
- if ((status ^ status1) & 0x40) {
- printf("Flash write error at address 0x%p: "
- "0x%02x != 0x%02x\n",
- p, status,word);
- ret = ERR_PROG_ERROR;
- writew(0xf0, base);
- readw(base);
- break;
- }
-
- writew(0xf0, base);
- readw(base);
- }
-
- if (flags)
- enable_interrupts();
-
- return ret;
-}
-
-#endif /* CONFIG_FAVR32_EZKIT_EXT_FLASH */
diff --git a/board/mimc/mimc200/Kconfig b/board/mimc/mimc200/Kconfig
deleted file mode 100644
index 18736d7..0000000
--- a/board/mimc/mimc200/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_MIMC200
-
-config SYS_BOARD
- default "mimc200"
-
-config SYS_VENDOR
- default "mimc"
-
-config SYS_SOC
- default "at32ap700x"
-
-config SYS_CONFIG_NAME
- default "mimc200"
-
-endif
diff --git a/board/mimc/mimc200/MAINTAINERS b/board/mimc/mimc200/MAINTAINERS
deleted file mode 100644
index 6cb51dd..0000000
--- a/board/mimc/mimc200/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MIMC200 BOARD
-M: Mark Jackson <mpfj@mimc.co.uk>
-S: Maintained
-F: board/mimc/mimc200/
-F: include/configs/mimc200.h
-F: configs/mimc200_defconfig
diff --git a/board/mimc/mimc200/Makefile b/board/mimc/mimc200/Makefile
deleted file mode 100644
index 5c30c0d..0000000
--- a/board/mimc/mimc200/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Copyright (C) 2005-2006 Atmel Corporation
-#
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y := mimc200.o
diff --git a/board/mimc/mimc200/mimc200.c b/board/mimc/mimc200/mimc200.c
deleted file mode 100644
index f078295..0000000
--- a/board/mimc/mimc200/mimc200.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * Copyright (C) 2006 Atmel Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <netdev.h>
-
-#include <asm/io.h>
-#include <asm/sdram.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/hmatrix.h>
-#include <asm/arch/mmu.h>
-#include <asm/arch/portmux.h>
-#include <atmel_lcdc.h>
-#include <lcd.h>
-
-#include "../../../arch/avr32/cpu/hsmc3.h"
-
-struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
- {
- .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
- .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
- .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
- | MMU_VMR_CACHE_NONE,
- }, {
- .virt_pgno = EBI_SRAM_CS2_BASE >> MMU_PAGE_SHIFT,
- .nr_pages = EBI_SRAM_CS2_SIZE >> MMU_PAGE_SHIFT,
- .phys = (EBI_SRAM_CS2_BASE >> MMU_PAGE_SHIFT)
- | MMU_VMR_CACHE_NONE,
- }, {
- .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
- .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
- .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
- | MMU_VMR_CACHE_WRBACK,
- },
-};
-
-#if defined(CONFIG_LCD)
-/* 480x272x16 @ 72 Hz */
-vidinfo_t panel_info = {
- .vl_col = 480, /* Number of columns */
- .vl_row = 272, /* Number of rows */
- .vl_clk = 5000000, /* pixel clock in ps */
- .vl_sync = ATMEL_LCDC_INVCLK_INVERTED |
- ATMEL_LCDC_INVLINE_INVERTED |
- ATMEL_LCDC_INVFRAME_INVERTED,
- .vl_bpix = LCD_COLOR16, /* Bits per pixel, BPP = 2^n */
- .vl_tft = 1, /* 0 = passive, 1 = TFT */
- .vl_hsync_len = 42, /* Length of horizontal sync */
- .vl_left_margin = 1, /* Time from sync to picture */
- .vl_right_margin = 1, /* Time from picture to sync */
- .vl_vsync_len = 1, /* Length of vertical sync */
- .vl_upper_margin = 12, /* Time from sync to picture */
- .vl_lower_margin = 1, /* Time from picture to sync */
- .mmio = LCDC_BASE, /* Memory mapped registers */
-};
-
-void lcd_enable(void)
-{
-}
-
-void lcd_disable(void)
-{
-}
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static const struct sdram_config sdram_config = {
- .data_bits = SDRAM_DATA_16BIT,
- .row_bits = 13,
- .col_bits = 9,
- .bank_bits = 2,
- .cas = 3,
- .twr = 2,
- .trc = 6,
- .trp = 2,
- .trcd = 2,
- .tras = 6,
- .txsr = 6,
- /* 15.6 us */
- .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
-};
-
-int board_early_init_f(void)
-{
- /* Enable SDRAM in the EBI mux */
- hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
-
- /* Enable 26 address bits and NCS2 */
- portmux_enable_ebi(16, 26, PORTMUX_EBI_CS(2), PORTMUX_DRIVE_HIGH);
- sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
-
- portmux_enable_usart1(PORTMUX_DRIVE_MIN);
-
- /* de-assert "force sys reset" pin */
- portmux_select_gpio(PORTMUX_PORT_D, 1 << 15,
- PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
-
- /* init custom i/o */
- /* cpu type inputs */
- portmux_select_gpio(PORTMUX_PORT_E, (1 << 19) | (1 << 20) | (1 << 23),
- PORTMUX_DIR_INPUT);
- /* main board type inputs */
- portmux_select_gpio(PORTMUX_PORT_B, (1 << 19) | (1 << 29),
- PORTMUX_DIR_INPUT);
- /* DEBUG input (use weak pullup) */
- portmux_select_gpio(PORTMUX_PORT_E, 1 << 21,
- PORTMUX_DIR_INPUT | PORTMUX_PULL_UP);
-
- /* are we suppressing the console ? */
- if (gpio_get_value(GPIO_PIN_PE(21)) == 1)
- gd->flags |= (GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE);
-
- /* reset phys */
- portmux_select_gpio(PORTMUX_PORT_E, 1 << 24, PORTMUX_DIR_INPUT);
- portmux_select_gpio(PORTMUX_PORT_C, 1 << 18,
- PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
-
- udelay(5000);
-
- /* release phys reset */
- gpio_set_value(GPIO_PIN_PC(18), 0); /* PHY RESET (Release) */
-
- /* setup Data Flash chip select (NCS2) */
- hsmc3_writel(MODE2, 0x20121003);
- hsmc3_writel(CYCLE2, 0x000a0009);
- hsmc3_writel(PULSE2, 0x0a060806);
- hsmc3_writel(SETUP2, 0x00030102);
-
- /* setup FRAM chip select (NCS3) */
- hsmc3_writel(MODE3, 0x10120001);
- hsmc3_writel(CYCLE3, 0x001e001d);
- hsmc3_writel(PULSE3, 0x08040704);
- hsmc3_writel(SETUP3, 0x02050204);
-
-#if defined(CONFIG_MACB)
- /* init macb0 pins */
- portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
- portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
-#endif
-
-#if defined(CONFIG_MMC)
- portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
-#endif
-
-#if defined(CONFIG_LCD)
- portmux_enable_lcdc(1);
-#endif
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
- gd->bd->bi_phy_id[0] = 0x01;
- gd->bd->bi_phy_id[1] = 0x03;
- return 0;
-}
-
-int board_postclk_init(void)
-{
- /* Use GCLK0 as 10MHz output */
- gclk_enable_output(0, PORTMUX_DRIVE_LOW);
- gclk_set_rate(0, GCLK_PARENT_OSC0, 10000000);
- return 0;
-}
-
-/* SPI chip select control */
-#ifdef CONFIG_ATMEL_SPI
-#include <spi.h>
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return (bus == 0) && (cs == 0);
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-}
-#endif /* CONFIG_ATMEL_SPI */
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bi)
-{
- macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
- macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
-
- return 0;
-}
-#endif
diff --git a/board/miromico/hammerhead/Kconfig b/board/miromico/hammerhead/Kconfig
deleted file mode 100644
index 1f09ef7..0000000
--- a/board/miromico/hammerhead/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_HAMMERHEAD
-
-config SYS_BOARD
- default "hammerhead"
-
-config SYS_VENDOR
- default "miromico"
-
-config SYS_SOC
- default "at32ap700x"
-
-config SYS_CONFIG_NAME
- default "hammerhead"
-
-endif
diff --git a/board/miromico/hammerhead/MAINTAINERS b/board/miromico/hammerhead/MAINTAINERS
deleted file mode 100644
index a87ceee..0000000
--- a/board/miromico/hammerhead/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-HAMMERHEAD BOARD
-M: Alex Raimondi <alex.raimondi@miromico.ch>
-S: Maintained
-F: board/miromico/hammerhead/
-F: include/configs/hammerhead.h
-F: configs/hammerhead_defconfig
diff --git a/board/miromico/hammerhead/Makefile b/board/miromico/hammerhead/Makefile
deleted file mode 100644
index 638a9df..0000000
--- a/board/miromico/hammerhead/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Copyright (C) 2008 Miromico AG
-#
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y := hammerhead.o
diff --git a/board/miromico/hammerhead/hammerhead.c b/board/miromico/hammerhead/hammerhead.c
deleted file mode 100644
index a0c7d3b..0000000
--- a/board/miromico/hammerhead/hammerhead.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Copyright (C) 2008 Miromico AG
- *
- * Mostly copied form atmel ATNGW100 sources
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-
-#include <asm/io.h>
-#include <asm/sdram.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/hmatrix.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/mmu.h>
-#include <asm/arch/portmux.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
- {
- .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
- .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
- .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
- | MMU_VMR_CACHE_NONE,
- }, {
- .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
- .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
- .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
- | MMU_VMR_CACHE_WRBACK,
- },
-};
-
-static const struct sdram_config sdram_config = {
- .data_bits = SDRAM_DATA_32BIT,
- .row_bits = 13,
- .col_bits = 9,
- .bank_bits = 2,
- .cas = 3,
- .twr = 2,
- .trc = 7,
- .trp = 2,
- .trcd = 2,
- .tras = 5,
- .txsr = 5,
- /* 7.81 us */
- .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
-};
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- return macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0,
- bis->bi_phy_id[0]);
-}
-#endif
-
-int board_early_init_f(void)
-{
- /* Enable SDRAM in the EBI mux */
- hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
-
- portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
- sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
-
- portmux_enable_usart1(PORTMUX_DRIVE_MIN);
-
-#if defined(CONFIG_MACB)
- portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
-#endif
-#if defined(CONFIG_MMC)
- portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
-#endif
- return 0;
-}
-
-int board_early_init_r(void)
-{
- gd->bd->bi_phy_id[0] = 0x01;
- return 0;
-}
-
-int board_postclk_init(void)
-{
- /* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */
- gclk_enable_output(3, PORTMUX_DRIVE_LOW);
- gclk_set_rate(3, GCLK_PARENT_OSC0, 25000000);
- return 0;
-}
diff --git a/board/nvidia/nyan-big/MAINTAINERS b/board/nvidia/nyan-big/MAINTAINERS
index ff74627..7790777 100644
--- a/board/nvidia/nyan-big/MAINTAINERS
+++ b/board/nvidia/nyan-big/MAINTAINERS
@@ -1,4 +1,4 @@
-NORRIN BOARD
+NYAN-BIG BOARD
M: Allen Martin <amartin@nvidia.com>
S: Maintained
F: board/nvidia/nyan-big/
diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c
index ae8874b..ba96401 100644
--- a/board/nvidia/nyan-big/nyan-big.c
+++ b/board/nvidia/nyan-big/nyan-big.c
@@ -8,7 +8,12 @@
#include <common.h>
#include <errno.h>
#include <asm/gpio.h>
+#include <asm/io.h>
#include <asm/arch/pinmux.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mc.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
#include <power/as3722.h>
#include <power/pmic.h>
#include "pinmux-config-nyan-big.h"
@@ -57,3 +62,67 @@
return 0;
}
+
+/* Setup required information for Linux kernel */
+static void setup_kernel_info(void)
+{
+ struct mc_ctlr *mc = (void *)NV_PA_MC_BASE;
+
+ /* The kernel graphics driver needs this region locked down */
+ writel(0, &mc->mc_video_protect_bom);
+ writel(0, &mc->mc_video_protect_size_mb);
+ writel(1, &mc->mc_video_protect_reg_ctrl);
+}
+
+/*
+ * We need to take ALL audio devices conntected to AHUB (AUDIO, APBIF,
+ * I2S, DAM, AMX, ADX, SPDIF, AFC) out of reset and enable the clocks.
+ * Otherwise reading AHUB devices will hang when the kernel boots.
+ */
+static void enable_required_clocks(void)
+{
+ static enum periph_id ids[] = {
+ PERIPH_ID_I2S0,
+ PERIPH_ID_I2S1,
+ PERIPH_ID_I2S2,
+ PERIPH_ID_I2S3,
+ PERIPH_ID_I2S4,
+ PERIPH_ID_AUDIO,
+ PERIPH_ID_APBIF,
+ PERIPH_ID_DAM0,
+ PERIPH_ID_DAM1,
+ PERIPH_ID_DAM2,
+ PERIPH_ID_AMX0,
+ PERIPH_ID_AMX1,
+ PERIPH_ID_ADX0,
+ PERIPH_ID_ADX1,
+ PERIPH_ID_SPDIF,
+ PERIPH_ID_AFC0,
+ PERIPH_ID_AFC1,
+ PERIPH_ID_AFC2,
+ PERIPH_ID_AFC3,
+ PERIPH_ID_AFC4,
+ PERIPH_ID_AFC5,
+ PERIPH_ID_EXTPERIPH1
+ };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(ids); i++)
+ clock_enable(ids[i]);
+ udelay(2);
+ for (i = 0; i < ARRAY_SIZE(ids); i++)
+ reset_set_enable(ids[i], 0);
+}
+
+int nvidia_board_init(void)
+{
+ clock_start_periph_pll(PERIPH_ID_EXTPERIPH1, CLOCK_ID_OSC, 12000000);
+ clock_start_periph_pll(PERIPH_ID_I2S1, CLOCK_ID_OSC, 1500000);
+
+ /* For external MAX98090 audio codec */
+ clock_external_output(1);
+ setup_kernel_info();
+ enable_required_clocks();
+
+ return 0;
+}
diff --git a/configs/atstk1003_defconfig b/configs/atstk1003_defconfig
deleted file mode 100644
index bd6c93a..0000000
--- a/configs/atstk1003_defconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_AVR32=y
-CONFIG_TARGET_ATSTK1003=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/atstk1004_defconfig b/configs/atstk1004_defconfig
deleted file mode 100644
index 4d12160..0000000
--- a/configs/atstk1004_defconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_AVR32=y
-CONFIG_TARGET_ATSTK1004=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/atstk1006_defconfig b/configs/atstk1006_defconfig
deleted file mode 100644
index 6d1d045..0000000
--- a/configs/atstk1006_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_AVR32=y
-CONFIG_CMD_NET=y
-CONFIG_TARGET_ATSTK1006=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/favr-32-ezkit_defconfig b/configs/favr-32-ezkit_defconfig
deleted file mode 100644
index 3330530..0000000
--- a/configs/favr-32-ezkit_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_AVR32=y
-CONFIG_CMD_NET=y
-CONFIG_TARGET_FAVR_32_EZKIT=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/hammerhead_defconfig b/configs/hammerhead_defconfig
deleted file mode 100644
index 278c76a..0000000
--- a/configs/hammerhead_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_AVR32=y
-CONFIG_CMD_NET=y
-CONFIG_TARGET_HAMMERHEAD=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/mimc200_defconfig b/configs/mimc200_defconfig
deleted file mode 100644
index 85c646e..0000000
--- a/configs/mimc200_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_AVR32=y
-CONFIG_TARGET_MIMC200=y
-CONFIG_CMD_NET=y
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index 92acab2..81949e8 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -6,3 +6,8 @@
CONFIG_CMD_NET=y
CONFIG_DISPLAY_PORT=y
CONFIG_VIDEO_TEGRA124=y
+CONFIG_DM_CROS_EC=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_SPI=y
+CONFIG_CROS_EC_KEYB=y
+CONFIG_CMD_CROS_EC=y
diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c
index 4bec663..d7eecd5 100644
--- a/drivers/spi/tegra114_spi.c
+++ b/drivers/spi/tegra114_spi.c
@@ -143,24 +143,30 @@
{
struct tegra_spi_platdata *plat = dev_get_platdata(bus);
struct tegra114_spi_priv *priv = dev_get_priv(bus);
+ struct spi_regs *regs;
+ ulong rate;
priv->regs = (struct spi_regs *)plat->base;
+ regs = priv->regs;
priv->last_transaction_us = timer_get_us();
priv->freq = plat->frequency;
priv->periph_id = plat->periph_id;
- return 0;
-}
-
-static int tegra114_spi_claim_bus(struct udevice *dev)
-{
- struct udevice *bus = dev->parent;
- struct tegra114_spi_priv *priv = dev_get_priv(bus);
- struct spi_regs *regs = priv->regs;
-
- /* Change SPI clock to correct frequency, PLLP_OUT0 source */
- clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
+ /*
+ * Change SPI clock to correct frequency, PLLP_OUT0 source, falling
+ * back to the oscillator if that is too fast.
+ */
+ rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
+ priv->freq);
+ if (rate > priv->freq + 100000) {
+ rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_OSC,
+ priv->freq);
+ if (rate != priv->freq) {
+ printf("Warning: SPI '%s' requested clock %u, actual clock %lu\n",
+ bus->name, priv->freq, rate);
+ }
+ }
/* Clear stale status here */
setbits_le32(®s->fifo_status,
@@ -175,9 +181,8 @@
SPI_FIFO_STS_RX_FIFO_EMPTY);
debug("%s: FIFO STATUS = %08x\n", __func__, readl(®s->fifo_status));
- /* Set master mode and sw controlled CS */
- setbits_le32(®s->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW |
- (priv->mode << SPI_CMD1_MODE_SHIFT));
+ setbits_le32(&priv->regs->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW |
+ (priv->mode << SPI_CMD1_MODE_SHIFT) | SPI_CMD1_CS_SW_VAL);
debug("%s: COMMAND1 = %08x\n", __func__, readl(®s->command1));
return 0;
@@ -249,6 +254,9 @@
ret = 0;
+ if (flags & SPI_XFER_BEGIN)
+ spi_cs_activate(dev);
+
/* clear all error status bits */
reg = readl(®s->fifo_status);
writel(reg, ®s->fifo_status);
@@ -260,9 +268,6 @@
/* set xfer size to 1 block (32 bits) */
writel(0, ®s->dma_blk);
- if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(dev);
-
/* handle data in 32-bit chunks */
while (num_bytes > 0) {
int bytes;
@@ -385,7 +390,6 @@
}
static const struct dm_spi_ops tegra114_spi_ops = {
- .claim_bus = tegra114_spi_claim_bus,
.xfer = tegra114_spi_xfer,
.set_speed = tegra114_spi_set_speed,
.set_mode = tegra114_spi_set_mode,
diff --git a/drivers/video/tegra124/tegra124-lcd.c b/drivers/video/tegra124/tegra124-lcd.c
index 2733590..cfdc77f 100644
--- a/drivers/video/tegra124/tegra124-lcd.c
+++ b/drivers/video/tegra124/tegra124-lcd.c
@@ -51,15 +51,13 @@
int ret;
clock_set_up_plldp();
- clock_adjust_periph_pll_div(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH,
- 408000000, NULL);
+ clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, 408000000);
clock_enable(PERIPH_ID_HOST1X);
clock_enable(PERIPH_ID_DISP1);
clock_enable(PERIPH_ID_PWM);
clock_enable(PERIPH_ID_DPAUX);
clock_enable(PERIPH_ID_SOR0);
-
udelay(2);
reset_set_enable(PERIPH_ID_HOST1X, 0);
diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h
index 1202ec2..56bd7f8 100644
--- a/include/configs/atngw100.h
+++ b/include/configs/atngw100.h
@@ -14,6 +14,10 @@
#define CONFIG_AT32AP7000
#define CONFIG_ATNGW100
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+
/*
* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
* frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h
deleted file mode 100644
index 4126b66..0000000
--- a/include/configs/atstk1003.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * Copyright (C) 2007 Atmel Corporation
- *
- * Configuration settings for the ATSTK1003 CPU daughterboard
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/hardware.h>
-
-#define CONFIG_AT32AP
-#define CONFIG_AT32AP7001
-#define CONFIG_ATSTK1003
-#define CONFIG_ATSTK1000
-
-/*
- * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
- * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
- * PLL frequency.
- * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
- */
-#define CONFIG_PLL
-#define CONFIG_SYS_POWER_MANAGER
-#define CONFIG_SYS_OSC0_HZ 20000000
-#define CONFIG_SYS_PLL0_DIV 1
-#define CONFIG_SYS_PLL0_MUL 7
-#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
-/*
- * Set the CPU running at:
- * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
- */
-#define CONFIG_SYS_CLKDIV_CPU 0
-/*
- * Set the HSB running at:
- * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
- */
-#define CONFIG_SYS_CLKDIV_HSB 1
-/*
- * Set the PBA running at:
- * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
- */
-#define CONFIG_SYS_CLKDIV_PBA 2
-/*
- * Set the PBB running at:
- * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
- */
-#define CONFIG_SYS_CLKDIV_PBB 1
-
-/* Reserve VM regions for SDRAM and NOR flash */
-#define CONFIG_SYS_NR_VM_REGIONS 2
-
-/*
- * The PLLOPT register controls the PLL like this:
- * icp = PLLOPT<2>
- * ivco = PLLOPT<1:0>
- *
- * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
- */
-#define CONFIG_SYS_PLL0_OPT 0x04
-
-#define CONFIG_USART_BASE ATMEL_BASE_USART1
-#define CONFIG_USART_ID 1
-
-/* User serviceable stuff */
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#define CONFIG_STACKSIZE (2048)
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTARGS \
- "console=ttyS0 root=/dev/mmcblk0p1 rootwait"
-
-#define CONFIG_BOOTCOMMAND \
- "mmc rescan; ext2load mmc 0:1 0x10400000 /boot/uImage; bootm"
-
-#define CONFIG_BOOTDELAY 1
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MMC
-
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_SETGETDCR
-#undef CONFIG_CMD_XIMG
-
-#define CONFIG_ATMEL_USART
-#define CONFIG_PORTMUX_PIO
-#define CONFIG_SYS_HSDRAMC
-#define CONFIG_MMC
-#define CONFIG_GENERIC_ATMEL_MCI
-#define CONFIG_GENERIC_MMC
-
-#define CONFIG_SYS_DCACHE_LINESZ 32
-#define CONFIG_SYS_ICACHE_LINESZ 32
-
-#define CONFIG_NR_DRAM_BANKS 1
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-
-#define CONFIG_SYS_FLASH_BASE 0x00000000
-#define CONFIG_SYS_FLASH_SIZE 0x800000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 135
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_TEXT_BASE 0x00000000
-
-#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
-#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
-#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
-
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SIZE 65536
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
-
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
-
-#define CONFIG_SYS_MALLOC_LEN (256*1024)
-
-/* Allow 4MB for the kernel run-time image */
-#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
-#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
-
-/* Other configuration settings that shouldn't have to change all that often */
-#define CONFIG_SYS_PROMPT "U-Boot> "
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LONGHELP
-
-#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000)
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h
deleted file mode 100644
index 97a1d3e..0000000
--- a/include/configs/atstk1004.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * Copyright (C) 2007 Atmel Corporation
- *
- * Configuration settings for the ATSTK1003 CPU daughterboard
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/hardware.h>
-
-#define CONFIG_AT32AP
-#define CONFIG_AT32AP7002
-#define CONFIG_ATSTK1004
-#define CONFIG_ATSTK1000
-
-/*
- * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
- * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
- * PLL frequency.
- * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
- */
-#define CONFIG_PLL
-#define CONFIG_SYS_POWER_MANAGER
-#define CONFIG_SYS_OSC0_HZ 20000000
-#define CONFIG_SYS_PLL0_DIV 1
-#define CONFIG_SYS_PLL0_MUL 7
-#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
-/*
- * Set the CPU running at:
- * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
- */
-#define CONFIG_SYS_CLKDIV_CPU 0
-/*
- * Set the HSB running at:
- * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
- */
-#define CONFIG_SYS_CLKDIV_HSB 1
-/*
- * Set the PBA running at:
- * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
- */
-#define CONFIG_SYS_CLKDIV_PBA 2
-/*
- * Set the PBB running at:
- * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
- */
-#define CONFIG_SYS_CLKDIV_PBB 1
-
-/* Reserve VM regions for SDRAM and NOR flash */
-#define CONFIG_SYS_NR_VM_REGIONS 2
-
-/*
- * The PLLOPT register controls the PLL like this:
- * icp = PLLOPT<2>
- * ivco = PLLOPT<1:0>
- *
- * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
- */
-#define CONFIG_SYS_PLL0_OPT 0x04
-
-#define CONFIG_USART_BASE ATMEL_BASE_USART1
-#define CONFIG_USART_ID 1
-
-/* User serviceable stuff */
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#define CONFIG_STACKSIZE (2048)
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTARGS \
- "console=ttyS0 root=/dev/mmcblk0p1 rootwait"
-
-#define CONFIG_BOOTCOMMAND \
- "mmc rescan; ext2load mmc 0:1 0x10200000 /boot/uImage; bootm"
-
-#define CONFIG_BOOTDELAY 1
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MMC
-
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_SETGETDCR
-#undef CONFIG_CMD_XIMG
-
-#define CONFIG_ATMEL_USART
-#define CONFIG_PORTMUX_PIO
-#define CONFIG_SYS_HSDRAMC
-#define CONFIG_MMC
-#define CONFIG_GENERIC_ATMEL_MCI
-#define CONFIG_GENERIC_MMC
-
-#define CONFIG_SYS_DCACHE_LINESZ 32
-#define CONFIG_SYS_ICACHE_LINESZ 32
-
-#define CONFIG_NR_DRAM_BANKS 1
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-
-#define CONFIG_SYS_FLASH_BASE 0x00000000
-#define CONFIG_SYS_FLASH_SIZE 0x800000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 135
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_TEXT_BASE 0x00000000
-
-#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
-#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
-#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
-
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SIZE 65536
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
-
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
-
-#define CONFIG_SYS_MALLOC_LEN (256*1024)
-
-/* Allow 2MB for the kernel run-time image */
-#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00200000)
-#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
-
-/* Other configuration settings that shouldn't have to change all that often */
-#define CONFIG_SYS_PROMPT "U-Boot> "
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LONGHELP
-
-#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000)
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h
deleted file mode 100644
index cbf17db..0000000
--- a/include/configs/atstk1006.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * Copyright (C) 2005-2006 Atmel Corporation
- *
- * Configuration settings for the ATSTK1002 CPU daughterboard
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/hardware.h>
-
-#define CONFIG_AT32AP
-#define CONFIG_AT32AP7000
-#define CONFIG_ATSTK1006
-#define CONFIG_ATSTK1000
-
-
-/*
- * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
- * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
- * PLL frequency.
- * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
- */
-#define CONFIG_PLL
-#define CONFIG_SYS_POWER_MANAGER
-#define CONFIG_SYS_OSC0_HZ 20000000
-#define CONFIG_SYS_PLL0_DIV 1
-#define CONFIG_SYS_PLL0_MUL 7
-#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
-/*
- * Set the CPU running at:
- * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
- */
-#define CONFIG_SYS_CLKDIV_CPU 0
-/*
- * Set the HSB running at:
- * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
- */
-#define CONFIG_SYS_CLKDIV_HSB 1
-/*
- * Set the PBA running at:
- * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
- */
-#define CONFIG_SYS_CLKDIV_PBA 2
-/*
- * Set the PBB running at:
- * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
- */
-#define CONFIG_SYS_CLKDIV_PBB 1
-
-/* Reserve VM regions for SDRAM and NOR flash */
-#define CONFIG_SYS_NR_VM_REGIONS 2
-
-/*
- * The PLLOPT register controls the PLL like this:
- * icp = PLLOPT<2>
- * ivco = PLLOPT<1:0>
- *
- * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
- */
-#define CONFIG_SYS_PLL0_OPT 0x04
-
-#define CONFIG_USART_BASE ATMEL_BASE_USART1
-#define CONFIG_USART_ID 1
-
-/* User serviceable stuff */
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#define CONFIG_STACKSIZE (2048)
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTARGS \
- "console=ttyS0 root=mtd3 fbmem=2400k"
-
-#define CONFIG_BOOTCOMMAND \
- "fsload; bootm $(fileaddr)"
-
-#define CONFIG_BOOTDELAY 1
-
-/*
- * After booting the board for the first time, new ethernet addresses
- * should be generated and assigned to the environment variables
- * "ethaddr" and "eth1addr". This is normally done during production.
- */
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MMC
-
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
-#undef CONFIG_CMD_SOURCE
-#undef CONFIG_CMD_XIMG
-
-#define CONFIG_ATMEL_USART
-#define CONFIG_MACB
-#define CONFIG_PORTMUX_PIO
-#define CONFIG_SYS_NR_PIOS 5
-#define CONFIG_SYS_HSDRAMC
-#define CONFIG_MMC
-#define CONFIG_GENERIC_ATMEL_MCI
-#define CONFIG_GENERIC_MMC
-
-#define CONFIG_SYS_DCACHE_LINESZ 32
-#define CONFIG_SYS_ICACHE_LINESZ 32
-
-#define CONFIG_NR_DRAM_BANKS 1
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-
-#define CONFIG_SYS_FLASH_BASE 0x00000000
-#define CONFIG_SYS_FLASH_SIZE 0x800000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 135
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_TEXT_BASE 0x00000000
-
-#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
-#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
-#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
-
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SIZE 65536
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
-
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
-
-#define CONFIG_SYS_MALLOC_LEN (256*1024)
-
-/* Allow 4MB for the kernel run-time image */
-#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
-#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
-
-/* Other configuration settings that shouldn't have to change all that often */
-#define CONFIG_SYS_PROMPT "U-Boot> "
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LONGHELP
-
-#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x3f00000)
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/favr-32-ezkit.h b/include/configs/favr-32-ezkit.h
deleted file mode 100644
index 04f4124..0000000
--- a/include/configs/favr-32-ezkit.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * Copyright (C) 2008 Atmel Corporation
- *
- * Configuration settings for the Favr-32 EarthLCD LCD kit.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/hardware.h>
-
-#define CONFIG_AT32AP
-#define CONFIG_AT32AP7000
-#define CONFIG_FAVR32_EZKIT
-
-#define CONFIG_FAVR32_EZKIT_EXT_FLASH
-
-/*
- * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
- * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
- * PLL frequency.
- * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
- */
-#define CONFIG_PLL
-#define CONFIG_SYS_POWER_MANAGER
-#define CONFIG_SYS_OSC0_HZ 20000000
-#define CONFIG_SYS_PLL0_DIV 1
-#define CONFIG_SYS_PLL0_MUL 7
-#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
-/*
- * Set the CPU running at:
- * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
- */
-#define CONFIG_SYS_CLKDIV_CPU 0
-/*
- * Set the HSB running at:
- * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
- */
-#define CONFIG_SYS_CLKDIV_HSB 1
-/*
- * Set the PBA running at:
- * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
- */
-#define CONFIG_SYS_CLKDIV_PBA 2
-/*
- * Set the PBB running at:
- * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
- */
-#define CONFIG_SYS_CLKDIV_PBB 1
-
-/* Reserve VM regions for SDRAM and NOR flash */
-#define CONFIG_SYS_NR_VM_REGIONS 2
-
-/*
- * The PLLOPT register controls the PLL like this:
- * icp = PLLOPT<2>
- * ivco = PLLOPT<1:0>
- *
- * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
- */
-#define CONFIG_SYS_PLL0_OPT 0x04
-
-#define CONFIG_USART_BASE ATMEL_BASE_USART3
-#define CONFIG_USART_ID 3
-
-/* User serviceable stuff */
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#define CONFIG_STACKSIZE (2048)
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTARGS \
- "root=/dev/mtdblock1 rootfstype=jffs fbmem=1800k"
-
-#define CONFIG_BOOTCOMMAND \
- "fsload; bootm $(fileaddr)"
-
-#define CONFIG_BOOTDELAY 1
-
-/*
- * After booting the board for the first time, new ethernet addresses
- * should be generated and assigned to the environment variables
- * "ethaddr" and "eth1addr". This is normally done during production.
- */
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MMC
-
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
-#undef CONFIG_CMD_SOURCE
-#undef CONFIG_CMD_XIMG
-
-#define CONFIG_ATMEL_USART
-#define CONFIG_MACB
-#define CONFIG_PORTMUX_PIO
-#define CONFIG_SYS_NR_PIOS 5
-#define CONFIG_SYS_HSDRAMC
-#define CONFIG_MMC
-#define CONFIG_GENERIC_ATMEL_MCI
-#define CONFIG_GENERIC_MMC
-
-#define CONFIG_SYS_DCACHE_LINESZ 32
-#define CONFIG_SYS_ICACHE_LINESZ 32
-
-#define CONFIG_NR_DRAM_BANKS 1
-
-/* External flash on Favr-32 */
-#if 0
-#define CONFIG_SYS_FLASH_CFI 1
-#define CONFIG_FLASH_CFI_DRIVER 1
-#endif
-
-#define CONFIG_SYS_FLASH_BASE 0x00000000
-#define CONFIG_SYS_FLASH_SIZE 0x800000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 135
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_TEXT_BASE 0x00000000
-
-#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
-#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
-#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
-
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SIZE 65536
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
-
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
-
-#define CONFIG_SYS_MALLOC_LEN (256*1024)
-
-/* Allow 4MB for the kernel run-time image */
-#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
-#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
-
-/* Other configuration settings that shouldn't have to change all that often */
-#define CONFIG_SYS_PROMPT "U-Boot> "
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LONGHELP
-
-#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000)
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/hammerhead.h b/include/configs/hammerhead.h
deleted file mode 100644
index 274f2a8..0000000
--- a/include/configs/hammerhead.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * Copyright (C) 2008 Miromico AG
- *
- * Configuration settings for the Miromico Hammerhead AVR32 board
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_AT32AP
-#define CONFIG_AT32AP7000
-#define CONFIG_HAMMERHEAD
-
-/*
- * Set up the PLL to run at 125 MHz, the CPU to run at the PLL
- * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
- * and the PBA bus to run at 1/4 the PLL frequency.
- */
-#define CONFIG_PLL
-#define CONFIG_SYS_POWER_MANAGER
-#define CONFIG_SYS_OSC0_HZ 25000000
-#define CONFIG_SYS_PLL0_DIV 1
-#define CONFIG_SYS_PLL0_MUL 5
-#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
-#define CONFIG_SYS_CLKDIV_CPU 0
-#define CONFIG_SYS_CLKDIV_HSB 1
-#define CONFIG_SYS_CLKDIV_PBA 2
-#define CONFIG_SYS_CLKDIV_PBB 1
-
-/* Reserve VM regions for SDRAM and NOR flash */
-#define CONFIG_SYS_NR_VM_REGIONS 2
-
-/*
- * The PLLOPT register controls the PLL like this:
- * icp = PLLOPT<2>
- * ivco = PLLOPT<1:0>
- *
- * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
- */
-#define CONFIG_SYS_PLL0_OPT 0x04
-
-#define CONFIG_USART_BASE ATMEL_BASE_USART1
-#define CONFIG_USART_ID 1
-
-#define CONFIG_HOSTNAME hammerhead
-
-/* User serviceable stuff */
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#define CONFIG_STACKSIZE (2048)
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTARGS \
- "console=ttyS0 root=mtd1 rootfstype=jffs2"
-#define CONFIG_BOOTCOMMAND \
- "fsload; bootm"
-
-#define CONFIG_BOOTDELAY 1
-
-/*
- * After booting the board for the first time, new ethernet address
- * should be generated and assigned to the environment variables
- * "ethaddr". This is normally done during production.
- */
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-
-/*
- * BOOTP/DHCP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MMC
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
-
-#define CONFIG_ATMEL_USART
-#define CONFIG_MACB
-#define CONFIG_PORTMUX_PIO
-#define CONFIG_SYS_NR_PIOS 5
-#define CONFIG_SYS_HSDRAMC
-#define CONFIG_MMC
-#define CONFIG_GENERIC_ATMEL_MCI
-#define CONFIG_GENERIC_MMC
-
-#define CONFIG_SYS_DCACHE_LINESZ 32
-#define CONFIG_SYS_ICACHE_LINESZ 32
-
-#define CONFIG_NR_DRAM_BANKS 1
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-
-#define CONFIG_SYS_FLASH_BASE 0x00000000
-#define CONFIG_SYS_FLASH_SIZE 0x800000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 135
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_TEXT_BASE 0x00000000
-
-#define CONFIG_SYS_INTRAM_BASE 0x24000000
-#define CONFIG_SYS_INTRAM_SIZE 0x8000
-
-#define CONFIG_SYS_SDRAM_BASE 0x10000000
-
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SIZE 65536
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
-
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
-
-#define CONFIG_SYS_MALLOC_LEN (256*1024)
-
-
-/* Allow 4MB for the kernel run-time image */
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00400000)
-#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
-
-/* Other configuration settings that shouldn't have to change all that often */
-#define CONFIG_SYS_PROMPT "Hammerhead> "
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LONGHELP
-
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/mimc200.h b/include/configs/mimc200.h
deleted file mode 100644
index e8e5ae7..0000000
--- a/include/configs/mimc200.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * Copyright (C) 2006 Atmel Corporation
- *
- * Configuration settings for the AVR32 Network Gateway
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/hardware.h>
-
-#define CONFIG_AT32AP
-#define CONFIG_AT32AP7000
-#define CONFIG_MIMC200
-
-#define CONFIG_MIMC200_EXT_FLASH
-
-/*
- * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
- * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
- * and the PBA bus to run at 1/4 the PLL frequency.
- */
-#define CONFIG_PLL
-#define CONFIG_SYS_POWER_MANAGER
-#define CONFIG_SYS_OSC0_HZ 10000000
-#define CONFIG_SYS_PLL0_DIV 1
-#define CONFIG_SYS_PLL0_MUL 15
-#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
-#define CONFIG_SYS_CLKDIV_CPU 0
-#define CONFIG_SYS_CLKDIV_HSB 1
-#define CONFIG_SYS_CLKDIV_PBA 2
-#define CONFIG_SYS_CLKDIV_PBB 1
-
-/* Reserve VM regions for SDRAM, NOR flash and FRAM */
-#define CONFIG_SYS_NR_VM_REGIONS 3
-
-/*
- * The PLLOPT register controls the PLL like this:
- * icp = PLLOPT<2>
- * ivco = PLLOPT<1:0>
- *
- * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
- */
-#define CONFIG_SYS_PLL0_OPT 0x04
-
-#define CONFIG_USART_BASE ATMEL_BASE_USART1
-#define CONFIG_USART_ID 1
-
-#define CONFIG_MIMC200_DBGLINK 1
-
-/* User serviceable stuff */
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#define CONFIG_STACKSIZE (2048)
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTARGS \
- "root=/dev/mtdblock1 rootfstype=jffs2 fbmem=512k console=ttyS1"
-#define CONFIG_BOOTCOMMAND \
- "fsload boot/uImage; bootm"
-
-#define CONFIG_SILENT_CONSOLE /* enable silent startup */
-#define CONFIG_DISABLE_CONSOLE /* disable console */
-#define CONFIG_SYS_DEVICE_NULLDEV /* include nulldev device */
-
-#define CONFIG_LCD 1
-
-/*
- * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
- * data on the serial line may interrupt the boot sequence.
- */
-#define CONFIG_BOOTDELAY 0
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_AUTOBOOT
-
-/*
- * After booting the board for the first time, new ethernet addresses
- * should be generated and assigned to the environment variables
- * "ethaddr" and "eth1addr". This is normally done during production.
- */
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-
-/*
- * BOOTP/DHCP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MMC
-
-#define CONFIG_ATMEL_USART
-#define CONFIG_MACB
-#define CONFIG_PORTMUX_PIO
-#define CONFIG_SYS_NR_PIOS 5
-#define CONFIG_SYS_HSDRAMC
-#define CONFIG_MMC
-#define CONFIG_GENERIC_ATMEL_MCI
-#define CONFIG_GENERIC_MMC
-
-#if defined(CONFIG_LCD)
-#define CONFIG_CMD_BMP
-#define CONFIG_ATMEL_LCD 1
-#define LCD_BPP LCD_COLOR16
-#define CONFIG_BMP_16BPP 1
-#define CONFIG_FB_ADDR 0x10600000
-#define CONFIG_WHITE_ON_BLACK 1
-#define CONFIG_VIDEO_BMP_GZIP 1
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE 262144
-#define CONFIG_ATMEL_LCD_BGR555 1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
-#define CONFIG_SPLASH_SCREEN 1
-#endif
-
-#define CONFIG_SYS_DCACHE_LINESZ 32
-#define CONFIG_SYS_ICACHE_LINESZ 32
-
-#define CONFIG_NR_DRAM_BANKS 1
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-
-#define CONFIG_SYS_FLASH_BASE 0x00000000
-#define CONFIG_SYS_FLASH_SIZE 0x800000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 135
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_TEXT_BASE 0x00000000
-
-#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
-#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
-#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
-
-#define CONFIG_SYS_FRAM_BASE 0x08000000
-#define CONFIG_SYS_FRAM_SIZE 0x20000
-
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SIZE 65536
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
-
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
-
-#define CONFIG_SYS_MALLOC_LEN (1024*1024)
-
-/* Allow 4MB for the kernel run-time image */
-#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
-#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
-
-/* Other configuration settings that shouldn't have to change all that often */
-#define CONFIG_SYS_PROMPT "U-Boot> "
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LONGHELP
-
-#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h
index a92112f..b99d762 100644
--- a/include/configs/nyan-big.h
+++ b/include/configs/nyan-big.h
@@ -47,6 +47,7 @@
#define CONFIG_AS3722_POWER
#define LCD_BPP LCD_COLOR16
#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CMD_BMP
/* Align LCD to 1MB boundary */
#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
@@ -77,8 +78,14 @@
#define CONFIG_CMD_DHCP
#define CONFIG_FIT
+#define CONFIG_FIT_BEST_MATCH
#define CONFIG_OF_LIBFDT
+#define CONFIG_KEYBOARD
+
+#undef CONFIG_LOADADDR
+#define CONFIG_LOADADDR 0x82408000
+
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 07db736..063abd5 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -126,6 +126,7 @@
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SUNXI_AHCI
+#define CONFIG_SYS_64BIT_LBA
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h
index 0cea795..483222f 100644
--- a/include/configs/tegra-common-post.h
+++ b/include/configs/tegra-common-post.h
@@ -40,8 +40,14 @@
#define STDOUT_LCD ""
#endif
+#ifdef CONFIG_CROS_EC_KEYB
+#define STDOUT_CROS_EC ",cros-ec-keyb"
+#else
+#define STDOUT_CROS_EC ""
+#endif
+
#define TEGRA_DEVICE_SETTINGS \
- "stdin=serial" STDIN_KBD_KBC STDIN_KBD_USB "\0" \
+ "stdin=serial" STDIN_KBD_KBC STDIN_KBD_USB STDOUT_CROS_EC "\0" \
"stdout=serial" STDOUT_LCD "\0" \
"stderr=serial" STDOUT_LCD "\0" \
""
@@ -52,13 +58,18 @@
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#ifndef CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
+#define CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
+#endif
+
#define CONFIG_EXTRA_ENV_SETTINGS \
TEGRA_DEVICE_SETTINGS \
MEM_LAYOUT_ENV_SETTINGS \
"fdt_high=ffffffff\0" \
"initrd_high=ffffffff\0" \
BOOTENV \
- BOARD_EXTRA_ENV_SETTINGS
+ BOARD_EXTRA_ENV_SETTINGS \
+ CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
#if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI)
#define CONFIG_TEGRA_SPI
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index 0bac9ad..2d58422 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -104,7 +104,7 @@
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)