commit 1b2430042413faddbca33e15e4e3c35de1de0d78
author Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Thu Mar 20 10:13:24 2025 +0100
committer Michal Simek <michal.simek@amd.com> Wed Apr 16 13:42:06 2025 +0200
tree bc9ef54871690897dbd9cab6f5163795e6fa7f34
parent 0f502f88fd4a450ca76afaac96976b6def37c0b8

ufs: amd-versal2: Use raw read/write for SLCR/CACHE registers

Update the firmware driver UFS APIs zynqmp_pm_ufs_* to directly
read/write to the pmc_iou_slcr and efuse_cache registers. Replace
these raw reads/writes with the xilinx_pm_request() API with the
correct arguments once the PM related changes are done.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ee2d1ad2e07e96f1948ab6ffe8f3c50a3b8f9be9.1742462001.git.michal.simek@amd.com