EXYNOS: definitions of system resgister and power management registers.
This is definitions of system registers and power mananagement registers for EXYNOS SoC.
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
diff --git a/arch/arm/include/asm/arch-exynos/system.h b/arch/arm/include/asm/arch-exynos/system.h
new file mode 100644
index 0000000..c85f949
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/system.h
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_SYSTEM_H_
+#define __ASM_ARM_ARCH_SYSTEM_H_
+
+#ifndef __ASSEMBLY__
+struct exynos4_sysreg {
+ unsigned char res1[0x210];
+ unsigned int display_ctrl;
+ unsigned int display_ctrl2;
+ unsigned int camera_control;
+ unsigned int audio_endian;
+ unsigned int jtag_con;
+};
+
+struct exynos5_sysreg {
+ unsigned char res1[0x214];
+ unsigned int disp1blk_cfg;
+ unsigned int disp2blk_cfg;
+ unsigned int hdcp_e_fuse;
+ unsigned int gsclblk_cfg0;
+ unsigned int gsclblk_cfg1;
+ unsigned int reserved;
+ unsigned int ispblk_cfg;
+ unsigned int usb20phy_cfg;
+ unsigned int mipi_dphy;
+ unsigned int dptx_dphy;
+ unsigned int phyclk_sel;
+};
+#endif
+
+void set_system_display_ctrl(void);
+
+#endif /* _EXYNOS4_SYSTEM_H */