diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c
index bd2af94..d3305a6 100644
--- a/drivers/ddr/altera/sdram_arria10.c
+++ b/drivers/ddr/altera/sdram_arria10.c
@@ -645,7 +645,6 @@
 	writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable);
 	writel(0, &socfpga_noc_fw_ddr_l3_base->enable);
 
-
 	for (i = 0; i < ARRAY_SIZE(firewall_table); i++) {
 		sprintf(name, "%s", firewall_table[i].prop_name);
 		ret = fdtdec_get_int_array(blob, child, name,
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 7636e71..69937fc 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -689,7 +689,6 @@
 	}
 }
 
-
 /* apply and load delay on both DQS and OCT out1 */
 static void scc_mgr_apply_group_dqs_io_and_oct_out1(struct socfpga_sdrseq *seq,
 						    u32 write_group, u32 delay)
@@ -2580,7 +2579,6 @@
 			 &sticky_bit_chk,
 			 left_edge, right_edge, use_read_test);
 
-
 	/* Search for the right edge of the window for each bit */
 	ret = search_right_edge(seq, 0, rank_bgn, rw_group, rw_group,
 				start_dqs, start_dqs_en,
diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h
index 618ba00..96a6bac 100644
--- a/drivers/ddr/altera/sequencer.h
+++ b/drivers/ddr/altera/sequencer.h
@@ -164,7 +164,6 @@
 	u32	write_correct_mask_vg;
 };
 
-
 /* global variable holder */
 struct gbl_type {
 	uint32_t phy_debug_mode_flags;
diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c
index 9f9aea8..f1dcba4 100644
--- a/drivers/ddr/fsl/arm_ddr_gen3.c
+++ b/drivers/ddr/fsl/arm_ddr_gen3.c
@@ -19,7 +19,6 @@
 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
 #endif
 
-
 /*
  * regs has the to-be-set values for DDR controller registers
  * ctrl_num is the DDR controller number
diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c
index 94a5e44..52a2050 100644
--- a/drivers/ddr/fsl/interactive.c
+++ b/drivers/ddr/fsl/interactive.c
@@ -1209,7 +1209,6 @@
 	for (i = 0; i < 18; i++)
 		printf("%c", spd->mpart[i]);
 
-
 	printf("<<* 73 Manufacturer's Part Number *\n");
 
 	printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
@@ -1227,7 +1226,6 @@
 	for (i = 0; i < 27; i++)
 		printf("%02x", spd->mspec[i]);
 
-
 	printf("* 99 Manufacturer Specific Data *\n");
 }
 #endif
@@ -1946,7 +1944,6 @@
 		if (argc == 0)
 			continue;
 
-
 		if (strcmp(argv[0], "help") == 0) {
 			puts(usage);
 			continue;
@@ -2042,7 +2039,6 @@
 			debug("src_ctlr_num = %u, src_dimm_num = %u, dst_ctlr_num = %u, dst_dimm_num = %u, step_mask = %x\n",
 				src_ctlr_num, src_dimm_num, dst_ctlr_num, dst_dimm_num, step_mask);
 
-
 			switch (step_mask) {
 
 			case STEP_GET_SPD:
@@ -2117,7 +2113,6 @@
 			if (error)
 				continue;
 
-
 			/* Check arguments */
 
 			/* ERROR: If no steps were found */
diff --git a/drivers/ddr/fsl/lc_common_dimm_params.c b/drivers/ddr/fsl/lc_common_dimm_params.c
index aaf9800..cc12811 100644
--- a/drivers/ddr/fsl/lc_common_dimm_params.c
+++ b/drivers/ddr/fsl/lc_common_dimm_params.c
@@ -191,7 +191,6 @@
 	      lowest_good_caslat);
 	outpdimm->lowest_common_spd_caslat = lowest_good_caslat;
 
-
 	/*
 	 * Compute a common 'de-rated' CAS latency.
 	 *
diff --git a/drivers/ddr/imx/phy/ddrphy_train.c b/drivers/ddr/imx/phy/ddrphy_train.c
index ccc10df..2a2161d 100644
--- a/drivers/ddr/imx/phy/ddrphy_train.c
+++ b/drivers/ddr/imx/phy/ddrphy_train.c
@@ -78,7 +78,6 @@
 
 		dwc_ddrphy_apb_wr(0xd0000, 0x1);
 
-
 		fsp_msg++;
 	}
 
diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c b/drivers/ddr/marvell/a38x/ddr3_init.c
index 7c5147f..b28b2c7 100644
--- a/drivers/ddr/marvell/a38x/ddr3_init.c
+++ b/drivers/ddr/marvell/a38x/ddr3_init.c
@@ -75,7 +75,6 @@
 #endif
 	}
 
-
 	status = ddr3_silicon_post_init();
 	if (MV_OK != status) {
 		printf("DDR3 Post Init - FAILED 0x%x\n", status);
@@ -89,7 +88,6 @@
 		return status;
 	}
 
-
 	/* Post MC/PHY initializations */
 	mv_ddr_post_training_soc_config(ddr_type);
 
diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c
index 790b01d..5b8747c 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training.c
@@ -285,7 +285,6 @@
 	if (params->g_rtt_park != PARAM_UNDEFINED)
 		g_rtt_park = params->g_rtt_park;
 
-
 	DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
 			  ("DGL parameters: 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n",
 			   g_zpri_data, g_znri_data, g_zpri_ctrl, g_znri_ctrl, g_zpodt_data, g_znodt_data,
@@ -870,7 +869,6 @@
 	return (status == 1) ? MV_OK : MV_NOT_INITIALIZED;
 }
 
-
 int ddr3_pre_algo_config(void)
 {
 	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
@@ -1114,7 +1112,6 @@
 		mv_ddr_phy_write(phy_access, phy_id, phy_type, reg_addr, data_value, OPERATION_WRITE);
 }
 
-
 /*
  * Phy read-modify-write
  */
@@ -1406,7 +1403,6 @@
 			t2t = (cs_num == 1) ? 0 : 1;
 		}
 
-
 		if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_INTERLEAVE_WA) == 1) {
 			/* Use 1T mode if 1:1 ratio configured */
 			if (config_func_info[dev_num].tip_get_clock_ratio(frequency) == 1) {
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h b/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
index 8765df7c..bdd7836 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
@@ -82,7 +82,6 @@
 #define ADDR_SIZE_8GB			0x40000000
 #define ADDR_SIZE_16GB			0x80000000
 
-
 enum hws_edge_compare {
 	EDGE_PF,
 	EDGE_FP,
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_leveling.c b/drivers/ddr/marvell/a38x/ddr3_training_leveling.c
index 55abbad..bc58f55 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_leveling.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_leveling.c
@@ -1677,7 +1677,6 @@
 	u32 val, mask;
 	u8 cs_bitmask_inv;
 
-
 	if (dis_auto_refresh == 1) {
 		ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_CTRL_CTRL_REG,
 			  ODPG_CTRL_AUTO_REFRESH_DIS << ODPG_CTRL_AUTO_REFRESH_OFFS,
diff --git a/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h b/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h
index dff5633..e6b7cc5 100644
--- a/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h
+++ b/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h
@@ -79,7 +79,6 @@
 #define MV_DEBUG_WL_FULL
 #endif
 
-
 /* The following is a list of Marvell status */
 #define MV_ERROR	(-1)
 #define MV_OK		(0x00)	/* Operation succeeded                   */
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.c b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
index 8ec9fb0..fb69539 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
@@ -1144,7 +1144,6 @@
 	uint64_t cs_mem_size = 0;
 	uint64_t mem_total_size_c, cs_mem_size_c;
 
-
 #ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
 	u32 physical_mem_size;
 	u32 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE;
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.h b/drivers/ddr/marvell/a38x/mv_ddr_plat.h
index 01894f6..23f3dd6 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_plat.h
+++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.h
@@ -55,7 +55,6 @@
 
 #define MARVELL_BOARD				MARVELL_BOARD_ID_BASE
 
-
 #define REG_DEVICE_SAR1_ADDR			0xe4204
 #define RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET	17
 #define RST2_CPU_DDR_CLOCK_SELECT_IN_MASK	0x1f
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_regs.h b/drivers/ddr/marvell/a38x/mv_ddr_regs.h
index a19000d..6a8a921 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_regs.h
+++ b/drivers/ddr/marvell/a38x/mv_ddr_regs.h
@@ -520,5 +520,4 @@
 #define RESULT_PHY_RX_OFFS			5
 #define RESULT_PHY_TX_OFFS			0
 
-
 #endif /* _MV_DDR_REGS_H */